STD4NS25 W N-CHANNEL 250V - 0.9 - 4A DPAK/IPAK MESH OVERLAY™ MOSFET TYPE VDSS RDS(on) ID STD4NS25 250 V < 1.1 W 4 A n TYPICAL RDS(on) = 0.9 W ) n EXTREMELY HIGH dv/dt CAPABILITY 3 s 3 n 100% AVALANCHE TESTED t( 2 ADD SUFFIX “T4” FOR ORDERING IN TAPE & 1 c 1 n u REEL d DPAK o IPAK DESCRIPTION TO-252 P r TO-251 Using the latest high voltage MESH OVERLAY™ e process, STMicroelectronics has designed an ad- t vanced family of power MOSFETs with outstanding e performance. The new patented STrip layout cou- ol pled with the Company’s proprietary edge termina- s tion structure, makes it suitable in coverters for b INTERNAL SCHEMATIC DIAGRAM lighting applications. O - ) s APPLICATIONS ( t HIGH CURRENT, HIGH SPEED cSWITCHING n u SWITH MODE POWER SUPPLIES (SMPS) n d n DC-DC CONVERTERS oFOR TELECOM, INDUSTRIAL, AND LrIGHTING EQUIPMENT P e t e l o s ABSOLUTE MAXIMUM RATINGS b O Symbol Parameter Value Unit VDS Drain-source Voltage (VGS = 0) 250 V VDGR Drain-gate Voltage (RGS = 20 kW ) 250 V VGS Gate- source Voltage ± 20 V ID Drain Current (continuos) at TC = 25°C 4 A ID Drain Current (continuos) at TC = 100°C 2.5 A IDM (l) Drain Current (pulsed) 16 A PTOT Total Dissipation at TC = 25°C 50 W Derating Factor 0.4 W/°C dv/dt (1) Peak Diode Recovery voltage slope 5 V/ns Tstg Storage Temperature –65 to 150 °C Tj Max. Operating Junction Temperature 150 °C (•)Pulse width limited by safe operating area (1) ISD £ 4A, di/dt£ 300 A/m s, VDD£ V(BR)DSS, Tj£ TjMAX February 2001 1/9

STD4NS25 THERMAL DATA Rthj-case Thermal Resistance Junction-case Max 2.5 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 100 °C/W Rthc-sink Thermal Resistance Case-sink Typ 1.5 °C/W Tl Maximum Lead Temperature For Soldering Purpose 275 °C AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive 4 A (pulse width limited by Tj max) EAS Single Pulse Avalanche Energy 120 )mJ (starting Tj = 25 °C, ID = IAR, VDD = 50 V) s ( t c ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) u OFF d Symbol Parameter Test Conditions Min. oTyp. Max. Unit r V(BR)DSS Drain-source ID = 250 µA, VGS = 0 250P V Breakdown Voltage e IDSS Zero Gate Voltage VDS = Max Rating e t 1 µA Drain Current (VGS = 0) VDS = Max Rating, TC o= l125 °C 10 µA IGSS Gate-body Leakage VGS = ±20V s ±100 nA b Current (VDS = 0) O - ON (1) ) s Symbol Parameter ( Test Conditions Min. Typ. Max. Unit t VGS(th) Gate Threshold Voltage c VDS = VGS, ID = 250µA 2 3 4 V u RDS(on) Static Drain-sourced On VGS = 10V, ID = 2 A 0.9 1.1 W Resistance o r P ID(on) On State Drain Current VDS > ID(on) x RDS(on)max, 4 A e VGS=10V t e l DYNAMoIC s b Symbol Parameter Test Conditions Min. Typ. Max. Unit O gfs (1) Forward Transconductance VDS > ID(on) x RDS(on)max, 1 3.5 S ID=2A Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 355 pF Coss Output Capacitance 64 pF Reverse Transfer Crss Capacitance 29.5 pF 2/9

STD4NS25 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) Turn-on Delay Time VDD = 125 V, ID = 2 A 12 ns RG=4.7W VGS = 10 V tr Rise Time (see test circuit, Figure 3) 18 ns Qg Total Gate Charge VDD = 200V, ID = 4 A, 19 27 nC Qgs Gate-Source Charge VGS = 10V 3.2 nC Qgd Gate-Drain Charge 7.5 nC ) SWITCHING OFF s ( Symbol Parameter Test Conditions Min. Typ. Matx. Unit c td(Voff) Turn-off- Delay Time VDD = 125V, ID = 2 A, 70 u ns tf Fall Time RG=4.7W, VGS = 10V 10.5d ns o (see test circuit, Figure 3) r tr(Voff) Off-voltage Rise Time Vclamp = 200V, ID = 4 A, P 13 ns tf Fall Time RG=4.7W, VGS = 10V e 10 ns tc Cross-over Time (see test circuit, Figure 5) t 21.5 ns e l o SOURCE DRAIN DIODE s b Symbol Parameter Test Conditions Min. Typ. Max. Unit O ISD Source-drain Current 4 A - ISDM (2) Source-drain Current (pulsed) ) 16 A s VSD (1) Forward On Voltage ( ISD = 4 A, VGS = 0 1.5 V t trr Reverse Recovery Timec ISD = 4 A, di/dt = 100A/µs 124 ns u Qrr Reverse Recoveryd Charge VDD = 30V, Tj = 150°C 0.5 m C (see test circuit, Figure 5) o IRRM Reverse Rercovery Current 7.2 A P Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width elim ited by safe operating area. t Safe Opereating Area Thermal Impedance l o s b O 3/9

STD4NS25 Output Characteristics Transfer Characteristics ) s ( t c u d o r P Transconductance Static Drain-sou rce On Resistance e t e l o s b O - ) s ( t c u d o r P e t e l o s Gate Charge vs Gate-source Voltage Capacitance Variations b O 4/9

STD4NS25 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature ) s ( t c u d o r P Source-drain Diode Forward Characteristics e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 5/9

STD4NS25 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform ) s ( t c u d o r P Fig. 3: Switching Times Test Circuit For Fig. 4: Gate Charge test Circuit Resistive Load e t e l o s b O - ) s ( t c u d o r P e t e l o Fig. s5: Test Circuit For Inductive Load Switching Abnd Diode Recovery Times O 6/9

STD4NS25 TO-252 (DPAK) MECHANICAL DATA mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.20 2.40 0.087 0.094 A1 0.90 1.10 0.035 0.043 A2 0.03 0.23 0.001 0.009 s ) ( B 0.64 0.90 0.025 0t.035 c B2 5.20 5.40 0.204 u 0.213 d C 0.45 0.60 0.018 0.024 o C2 0.48 0.60 0.019 r 0.024 P D 6.00 6.20 0.236 0.244 e E 6.40 6.60 0.25t2 0.260 e G 4.40 4.60 ol0.173 0.181 s H 9.35 10.10 0.368 0.398 b L2 0.8 O 0.031 L4 0.60 - 1.00 0.024 0.039 V2 0o ) 8o 0o 0o s ( t c u d o r P e t e l o s b O P032P_B 7/9

STD4NS25 TO-251 (IPAK) MECHANICAL DATA mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 ) B 0.64 0.9 0.025 0.031 s ( B2 5.2 5.4 0.204 0.2t12 c B3 0.85 u 0.033 B5 0.3 0.012 d o B6 0.95 0.037 r C 0.45 0.6 0.017 P 0.023 C2 0.48 0.6 0.019 e 0.023 D 6 6.2 0.236t 0.244 e E 6.4 6.6 l0.252 0.260 o G 4.4 4.6 s 0.173 0.181 b H 15.9 16.3 0.626 0.641 O L 9 9.4 0.354 0.370 L1 0.8 - 1.2 0.031 0.047 ) L2 0.8 s 1 0.031 0.039 ( t c u d H o P r C e A t le C2 A3 o s 1 A b O L2 D L B3 B6 B B5 3 E = B2 = 2 G = = = = 1 L1 0068771-E 8/9

STD4NS25 ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics © 2000 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 9/9