New Product Si2304DDS Vishay Siliconix N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY • Halogen-free According to IEC 61249-2-21 VDS (V) RDS(on) (Ω) ID (A)a Qg (Typ.) Definition 0.060 at VGS = 10 V 3.6 (cid:129) TrenchFET® Power MOSFET 30 2.1 nC (cid:129) 100 % R Tested 0.075 at VGS = 4.5 V 3.6 g (cid:129) Compliant to RoHS Directive 2002/95/EC APPLICATIONS (cid:129) DC/DC Converter TO-236 (SOT-23) D G 1 3 D S 2 G Top View Si2304DDS (P4)* * Marking Code S Ordering Information: Si2304DDS-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage VDS 30 V Gate-Source Voltage VGS ± 20 TC = 25 °C 3.6a Continuous Drain Current (T = 150 °C) TC = 70 °C I 3.3 J TA = 25 °C D 3.3 TA = 70 °C 2.7 A Pulsed Drain Current IDM 15 TC = 25 °C 1.4 Continuous Source-Drain Diode Current TA = 25 °C IS 0.9b, c TC = 25 °C 1.7 Maximum Power Dissipation TTCA == 2750 °°CC PD 1.11.b1, c W TA = 70 °C 0.7b, c Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C Soldering Recommendations (Peak Temperature)d, e 260 THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambientb, d t ≤ 5 s RthJA 90 115 °C/W Maximum Junction-to-Foot (Drain) Steady State RthJF 60 75 Notes: a. Package limited b. Surface Mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 130 °C/W. Document Number: 65175 www.vishay.com S09-1496-Rev. A, 10-Aug-09 1

New Product Si2304DDS Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 30 V VDS Temperature Coefficient ΔVDS/TJ 31 ID = 250 µA mV/°C VGS(th) Temperature Coefficient ΔVGS(th)/TJ - 5 Gate-Source Threshold Voltage VGS(th) VDS = VGS , ID = 250 µA 1.2 2.2 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA VDS = 30 V, VGS = 0 V 1 Zero Gate Voltage Drain Current IDSS µA VDS = 30 V, VGS = 0 V, TJ = 55 °C 10 On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 10 A VGS = 10 V, ID = 3.2 A 0.049 0.060 Drain-Source On-State Resistancea RDS(on) Ω VGS = 4.5 V, ID = 2.8 A 0.061 0.075 Forward Transconductancea gfs VDS = 15 V, ID = 4.8 A 11 S Dynamicb Input Capacitance Ciss 235 Output Capacitance Coss VDS = 15 V, VGS = 0 V, f = 1 MHz 45 pF Reverse Transfer Capacitance Crss 17 Total Gate Charge Qg VDS = 15 V, VGS = 10 V, ID = 3.4 A 4.5 6.7 2.1 3.2 nC Gate-Source Charge Qgs VDS = 15 V, VGS = 4.5 V, ID = 3.4 A 0.85 Gate-Drain Charge Qgd 0.65 Gate Resistance Rg f = 1 MHz 0.8 4.4 8.8 Ω Turn-On Delay Time td(on) 12 20 Rise Time tr VDD = 15 V, RL = 5.6 Ω 50 75 Turn-Off Delay Time td(off) ID ≅ 2.7 A, VGEN = 4.5 V, Rg = 1 Ω 12 20 Fall Time tf 22 35 ns Turn-On Delay Time td(on) 5 10 Rise Time tr VDD = 15 V, RL = 5.6 Ω 12 20 Turn-Off Delay Time td(off) ID ≅ 2.7 A, VGEN = 10 V, Rg = 1 Ω 10 15 Fall Time tf 5 10 Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS TC = 25 °C 1.4 A Pulse Diode Forward Current ISM 15 Body Diode Voltage VSD IS = 2.7 A, VGS = 0 V 0.8 1.2 V Body Diode Reverse Recovery Time trr 10 20 ns Body Diode Reverse Recovery Charge Qrr 5 10 nC I = 2.7 A, dI/dt = 100 A/µs, T = 25 °C F J Reverse Recovery Fall Time ta 6 ns Reverse Recovery Rise Time tb 4 Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 65175 2 S09-1496-Rev. A, 10-Aug-09

New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 15 5 VGS=10Vthru4V 12 4 - DrainCurrent(A)ID 69 VGS=3V - DrainCurrent(A)ID 23 TTCC==2-5 5 °5C °C 3 1 TC=125 °C 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VDS-Drain-to-SourceVoltage(V) VGS-Gate-to-SourceVoltage(V) Output Characteristics Transfer Characteristics 0.10 300 250 Ciss 0.08 Ω) ( stance 0.06 VGS=4.5V ce(pF) 200 esi an - On-R 0.04 VGS=10V Capacit 150 S(on) C - 100 RD Coss 0.02 50 Crss 0.00 0 0 3 6 9 12 15 0 5 10 15 20 25 30 ID-DrainCurrent(A) VDS-Drain-to-SourceVoltage(V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 10 1.6 ID=3.4A 1.5 ID=3.2A V) 8 VGS=10V ( 1.4 e g e olta VDS=7.5V anc 1.3 e-to-SourceV 46 VDS=V1D5SV=24V - On-Resistn)(Normalized) 11..12 Gat DS(o 1.0 - R GS 2 0.9 V 0.8 0 0.7 0 1 2 3 4 5 - 50 - 25 0 25 50 75 100 125 150 Qg-TotalGateCharge(nC) TJ-JunctionTemperature(°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 65175 www.vishay.com S09-1496-Rev. A, 10-Aug-09 3

New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 100 0.14 ID=3.2A Ω) 0.12 A) e( urrent( 10 sistanc 0.10 ceC TJ=150 °C TJ=25 °C n-Re - Sour 1 - Oon) 0.08 TJ=125 °C IS DS( R 0.06 TJ=25 °C 0.1 0.04 0.0 0.3 0.6 0.9 1.2 1.5 0 2 4 6 8 10 VSD-Source-to-DrainVoltage(V) VGS-Gate-to-SourceVoltage(V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 2.4 25 2.2 20 2.0 V) W) 15 (S(th) 1.8 ID=250 µA wer( G o V P 10 1.6 5 1.4 1.2 0 - 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10 100 1000 TJ-Temperature(°C) Time (s) Threshold Voltage Single Pulse Power 100 LimitedbyRDS(on)* 10 A) 100µs ( nt e urr C 1 1ms n ai Dr 10ms - ID 100ms 0.1 1s,10s TA=25 °C DC SinglePulse BVDSSLimited 0.01 0.1 1 10 100 VDS-Drain-to-SourceVoltage(V) *VGS>minimumVGSatwhichRDS(on)isspecified Safe Operating Area, Junction-to-Ambient www.vishay.com Document Number: 65175 4 S09-1496-Rev. A, 10-Aug-09

New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 5 2.0 4 1.5 A) ( PackageLimited nt urre 3 (W) C er 1.0 n w Drai 2 Po - D I 0.5 1 0 0.0 0 25 50 75 100 125 150 25 50 75 100 125 150 TC-CaseTemperature(°C) TC-CaseTemperature(°C) Current Derating* Power Derating * The power dissipation P is based on T = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper D J(max) dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 65175 www.vishay.com S09-1496-Rev. A, 10-Aug-09 5

New Product Si2304DDS Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 1 DutyCycle=0.5 nt e Transiance 0.2 ctivemped 0.1 Notes: eI edEffermal 0.1 0.05 PDM zh maliT t1 Nor 0.02 1.DutyCyclet,2D= t1 t2 2.PerUnitBase=RthJA=130 °C/W 3.TJM-TA=PDMZthJA(t) SinglePulse 4.SurfaceMounted 0.01 10-4 10-3 10-2 10-1 1 10 100 1000 SquareWavePulseDuration(s) Normalized Thermal Transient Impedance, Junction-to-Ambient 1 DutyCycle=0.5 nt e Transiance 0.2 ctivemped 0.1 eI Effmal 0.1 eder alizTh 0.05 m 0.02 or N SinglePulse 0.01 10-4 10-3 10-2 10-1 1 SquareWavePulseDuration(s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65175. www.vishay.com Document Number: 65175 6 S09-1496-Rev. A, 10-Aug-09

Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 E 1 2 e S e1 D 0.10 mm C A A2 0.004" C q 0.25 mm Gauge Plane Seating Plane Seating Plane A1 C L L1 MILLIMETERS INCHES Dim Min Max Min Max A 0.89 1.12 0.035 0.044 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 0.055 e 0.95 BSC 0.0374 Ref e1 1.90 BSC 0.0748 Ref L 0.40 0.60 0.016 0.024 L1 0.64 Ref 0.025 Ref S 0.50 Ref 0.020 Ref q 3° 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 www.vishay.com 09-Jul-01 1

AN807 Vishay Siliconix (cid:1) Mounting LITTLE FOOT SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated ambient air. This pattern uses all the available area underneath the circuit and small-signal packages which have been been modified body for this purpose. to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. 0.114 2.9 0.081 See Application Note 826, Recommended Minimum Pad 2.05 Patterns With Outline Drawing Access for Vishay Siliconix 0.150 3.8 MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET 0.059 footprint . In converting this footprint to the pad set for a power 1.5 device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. 0.0394 0.037 1.0 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional Since surface-mounted packages are small, and reflow soldering function of providing the thermal connection from the package to is the most common way in which these are affixed to the PC the PC board. The total cross section of a copper trace connected board, “thermal” connections from the planar copper to the pads to the drain may be adequate to carry the current required for the have not been used. Even if additional planar copper area is used, application, but it may be inadequate thermally. Also, heat spreads there should be no problems in the soldering process. The actual in a circular fashion from the heat source. In this case the drain pin solder connections are defined by the solder mask openings. By is the heat source when looking at heat spread on the PC board. combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. Figure 1 shows the footprint with copper spreading for the SOT-23 A final item to keep in mind is the width of the power traces. The package. This pattern shows the starting point for utilizing the absolute minimum power trace width must be determined by the board area available for the heat spreading copper. To create this amount of current it has to carry. For thermal reasons, this pattern, a plane of copper overlies the drain pin and provides minimum width should be at least 0.020 inches. The use of wide planar copper to draw heat from the drain lead and start the traces connected to the drain plane provides a low-impedance process of spreading the heat so it can be dissipated into the path for heat to move away from the device. Document Number: 70739 www.vishay.com 26-Nov-03 1

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SOT-23 0.037 0.022 (0.950) (0.559) 6 2) 9 5) 0 9 4 4 1 6 0 2 0. 2. 0. 1. ( ( 9 4) 2 2 0 7 0. 0. ( 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index A P P L I C A T I O N N O T E Document Number: 72609 www.vishay.com Revision: 21-Jan-08 25

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