Si7309DN Vishay Siliconix P-Channel 60-V (D-S) MOSFET FEATURES PRODUCT SUMMARY • Halogen-free According to IEC 61249-2-21 VDS (V) RDS(on) (Ω) ID (A)a Qg (Typ.) Available 0.115 at VGS = - 10 V - 8 (cid:129) TrenchFET® Power MOSFET - 60 14.5 nC 0.146 at VGS = - 4.5 V - 8 (cid:129) Low Thermal Resistance PowerPAK® Package with Small Size and Low 1.07 mm Profile APPLICATIONS PowerPAK 1212-8 (cid:129) CCFL inverter (cid:129) Class D-amp S 3.30 mm S 3.30 mm 1 S 2 S 3 G 4 G D 8 D 7 D 6 D 5 Bottom View D Ordering Information: Si7309DN-T1-E3 (Lead (Pb)-free) Si7309DN-T1-GE3 (Lead (Pb)-free and Halogen-free) P-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol Limit Unit Drain-Source Voltage VDS - 60 V Gate-Source Voltage VGS ± 20 TC = 25 °C - 8a T = 70 °C - 7.8 Continuous Drain Current (T = 150 °C) C I J TA = 25 °C D - 3.9b, c TA = 70 °C - 3.1b, c A Pulsed Drain Current (10 µs Width) IDM - 20 Continuous Source-Drain Diode Current TTCA == 2255 °°CC IS - 2-. 78ab, c Avalanche Current L = 0.1 mH IAS - 15 Single-Pulse Avalanche Energy EAS 11 mJ TC = 25 °C 19.8 Maximum Power Dissipation TTCA == 2750 °°CC PD 31.22b.7, c W TA = 70 °C 2.1b, c Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit Maximum Junction-to-Ambienta, d RthJA 31 39 °C/W Maximum Junction-to-Case (Drain) Steady State RthJC 5 6.3 Notes: a.Package limited. b.Surface Mounted on 1" x 1" FR4 board. c. t = 10 s. d.See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. e.Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. f. Maximum under Steady State conditions is 81 °C/W. Document Number: 73434 www.vishay.com S-83051-Rev. B, 29-Dec-08 1

Si7309DN Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = - 250 µA - 60 V VDS Temperature Coefficient ΔVDS/TJ - 50 ID = - 250 µA mV/°C VGS(th) Temperature Coefficient ΔVGS(th)/TJ + 3.8 Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 µA - 1 - 3 V Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 ns VDS = - 60 V, VGS = 0 V - 1 Zero Gate Voltage Drain Current IDSS µA VDS = - 60 V, VGS = 0 V, TJ = 85 °C - 10 On-State Drain Currenta ID(on) VDS ≥ - 5 V, VGS = - 10 V - 20 A VGS = - 10 V, ID = - 3.9 A 0.092 0.115 Drain-Source On-State Resistancea RDS(on) Ω VGS = - 4.5 V, ID = - 3.5 A 0.120 0.146 Forward Transconductancea gfs VDS = - 15 V, ID = - 3.9 A 10 S Dynamicb Input Capacitance Ciss 600 Output Capacitance Coss VDS = - 30 V, VGS = 0 V, f = 1 MHz 70 pF Reverse Transfer Capacitance Crss 50 Total Gate Charge Qg VDS = - 30 V, VGS = - 10 V, ID = - 3.9 A 14.5 22 7.5 12 nC Gate-Source Charge Qgs VDS = - 30 V, VGS = - 4.5 V, ID = - 3.9 A 2.2 Gate-Drain Charge Qgd 3.7 Gate Resistance Rg f = 1 MHz 14 Ω Turn-On Delay Time td(on) 25 40 Rise Time tr VDD = - 30 V, RL = 9.4 Ω 80 120 Turn-Off Delay Time td(off) ID ≅ - 3.2 A, VGEN = - 4.5 V, Rg = 1 Ω 33 50 Fall Time tf 35 50 ns Turn-On Delay Time td(on) 10 15 Rise Time tr VDD = - 30 V, RL = 9.4 Ω 15 25 Turn-Off Delay Time td(off) ID ≅ - 3.2 A, VGEN = - 10 V, Rg = 1 Ω 30 45 Fall Time tf 33 50 Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS TC = 25 °C - 8 A Pulse Diode Forward Current ISM - 20 Body Diode Voltage VSD IS = - 1.3 A, VGS = 0 V - 0.8 - 1.2 V Body Diode Reverse Recovery Time trr 30 50 ns Body Diode Reverse Recovery Charge Qrr 32 50 nC I = - 1.3 A, dI/dt = - 100 A/µs, T = 25 °C F J Reverse Recovery Fall Time ta 17 ns Reverse Recovery Rise Time tb 13 Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com Document Number: 73434 2 S-83051-Rev. B, 29-Dec-08

Si7309DN Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 20 5 VGS = 10 thru 5 V 16 4 A) A) Current ( 12 4 V Current ( 3 - Drain D 8 - Drain D 2 TC = 125 °C I I 4 1 25 °C 3 V - 55 °C 0 0 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics 0.30 1000 )Ω 0.25 800 m esistance ( 0.20 VGS = 4.5 V ance (pF) 600 Ciss n-R 0.15 acit O p - S(on) 0.10 VGS = 10 V C - Ca 400 D R 200 0.05 Coss Crss 0.00 0 0 4 8 12 16 20 0 10 20 30 40 50 60 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage Capacitance 10 1.8 ID = 3.9 A VGS = 10 V, 4.5 V e (V) 8 1.6 ID = 3.9 A Source Voltag 6 VDS = 30 V VDS = 48 V n-Resistancemalized) 11..24 ate-to- 4 - Oon)(Nor 1.0 G S( - S RD G 2 V 0.8 0 0.6 0 3 6 9 12 15 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 73434 www.vishay.com S-83051-Rev. B, 29-Dec-08 3

Si7309DN Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 20 0.30 TJ = 150 °C e ()Ω ID = 3.9 A 10 anc 0.25 st Current (A) ce On-Resi 0.20 TA = 125 °C e ur c o ur S 0.15 - SoIS TJ = 25 °C Drain-to- TA = 25 °C - n) 0.10 o S( D R 1 0.05 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2 3 4 5 6 7 8 9 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage 2.4 50 2.2 40 ID = 250 µA V) 2.0 W) 30 V (GS(th) 1.8 Power ( 20 1.6 10 1.4 0 - 50 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10 100 1000 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power, Junction-to-Ambient 100 Limited by RDS(on)* 10 100 µs A) nt ( 1 1 ms e urr 10 ms C n 100 ms Drai 0.1 1 s - D 10 s I TA = 25 °C DC Single Pulse 0.01 0.001 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area www.vishay.com Document Number: 73434 4 S-83051-Rev. B, 29-Dec-08

Si7309DN Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 12 25 10 20 A) 8 W) urrent ( 6 Package Limited pation ( 15 C si Drain 4 er Dis 10 I - D Pow 5 2 0 0 25 50 75 100 125 150 0 25 50 75 100 125 150 TC - Case Temperature (°C) TC - Case Temperature (°C) Current Derating* Power Derating 100 A) nt ( e urr C e h c n 10 a al v A k a e P I - C TA= BVL -·VID DD 1 10-6 10-5 10-4 10-3 TA - Time In Avalanche (s) Single Pulse Avalanche Capability * The power dissipation P is based on T = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper D J(max) dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 73434 www.vishay.com S-83051-Rev. B, 29-Dec-08 5

Si7309DN Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 2 1 nt Duty Cycle = 0.5 e Transiance e ed 0.2 ctivmp Notes: ed Effeermal I 0.1 0.1 PDM malizTh 0.05 t1 Nor 0.02 1. Duty Cycle,t 2D = t1 t2 2. Per Unit Base = RthJA = 65 °C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 nt Duty Cycle = 0.5 e Transiance 0.2 e ed ctivmp 0.1 ed Effeermal I 0.1 zh maliT 0.05 or N 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73434. www.vishay.com Document Number: 73434 6 S-83051-Rev. B, 29-Dec-08

Package Information www.vishay.com Vishay Siliconix PowerPAK® 1212-8, (Single / Dual) L H E2 K W D4 E4 θ 8 M 1 1 e Z 2 2 D1 D D2 D5 3 4 5 4b θ L1 E3 θ θ A1 Backside view of single pad L A H E2 K E4 c H 4 2 D 1 E1 Detail Z 2x) D1 E D3( 2 2 5 D D Notes 3 1 1. Inch will govern K 2 Dimensions exclusive of mold gate burrs D2 4b 3. Dimensions exclusive of mold flash and cutting burrs E3 Backside view of dual pad MILLIMETERS INCHES DIM. MIN. NOM. MAX. MIN. NOM. MAX. A 0.97 1.04 1.12 0.038 0.041 0.044 A1 0.00 - 0.05 0.000 - 0.002 b 0.23 0.30 0.41 0.009 0.012 0.016 c 0.23 0.28 0.33 0.009 0.011 0.013 D 3.20 3.30 3.40 0.126 0.130 0.134 D1 2.95 3.05 3.15 0.116 0.120 0.124 D2 1.98 2.11 2.24 0.078 0.083 0.088 D3 0.48 - 0.89 0.019 - 0.035 D4 0.47 typ. 0.0185 typ D5 2.3 typ. 0.090 typ E 3.20 3.30 3.40 0.126 0.130 0.134 E1 2.95 3.05 3.15 0.116 0.120 0.124 E2 1.47 1.60 1.73 0.058 0.063 0.068 E3 1.75 1.85 1.98 0.069 0.073 0.078 E4 0.034 typ. 0.013 typ. e 0.65 BSC 0.026 BSC K 0.86 typ. 0.034 typ. K1 0.35 - - 0.014 - - H 0.30 0.41 0.51 0.012 0.016 0.020 L 0.30 0.43 0.56 0.012 0.017 0.022 L1 0.06 0.13 0.20 0.002 0.005 0.008  0° - 12° 0° - 12° W 0.15 0.25 0.36 0.006 0.010 0.014 M 0.125 typ. 0.005 typ. ECN: S16-2667-Rev. M, 09-Jan-17 DWG: 5882 Revison: 09-Jan-17 1 Document Number: 71656 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

AN822 Vishay Siliconix ® PowerPAK 1212 Mounting and Thermal Considerations Johnson Zhao MOSFETs for switching applications are now available The PowerPAK 1212-8 has a footprint area compara- with die on resistances around 1 mΩ and with the ble to TSOP-6. It is over 40 % smaller than standard capability to handle 85 A. While these die capabilities TSSOP-8. Its die capacity is more than twice the size represent a major advance over what was available of the standard TSOP-6’s. It has thermal performance just a few years ago, it is important for power MOSFET an order of magnitude better than the SO-8, and 20 packaging technology to keep pace. It should be obvi- times better than TSSOP-8. Its thermal performance is ous that degradation of a high performance die by the better than all current SMT packages in the market. It package is undesirable. PowerPAK is a new package will take the advantage of any PC board heat sink technology that addresses these issues. The PowerPAK capability. Bringing the junction temperature down also 1212-8 provides ultra-low thermal impedance in a increases the die efficiency by around 20 % compared small package that is ideal for space-constrained with TSSOP-8. For applications where bigger pack- applications. In this application note, the PowerPAK ages are typically required solely for thermal consider- 1212-8’s construction is described. Following this, ation, the PowerPAK 1212-8 is a good option. mounting information is presented. Finally, thermal Both the single and dual PowerPAK 1212-8 utilize the and electrical performance is discussed. same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both THE PowerPAK PACKAGE versions an excellent choice for applications with The PowerPAK 1212-8 package (Figure 1) is a deriva- space constraints. tive of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the PowerPAK 1212 SINGLE MOUNTING die attach pad is exposed to provide a direct, low resis- To take the advantage of the single PowerPAK 1212-8’s tance thermal path to the substrate the device is thermal performance see Application Note 826, mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller Recommended Minimum Pad Patterns With Outline package, with the same level of thermal performance. Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this (Please refer to application note “PowerPAK SO-8 document. Mounting and Thermal Considerations.”) In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improve- ment in thermal performance. Figure 1. PowerPAK 1212 Devices Document Number 71681 www.vishay.com 03-Mar-06 1

AN822 Vishay Siliconix PowerPAK 1212 DUAL To take the advantage of the dual PowerPAK 1212-8’s ture profile used, and the temperatures and time thermal performance, the minimum recommended duration, are shown in Figures 2 and 3. For the lead land pattern can be found in Application Note 826, (Pb)-free solder profile, see http://www.vishay.com/ Recommended Minimum Pad Patterns With Outline doc?73257. Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this doc- ument. The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the Pow- erPAK 1212-8 dual package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the ther- mal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-to- ambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an Ramp-Up Rate + 6 °C /Second Maximum area of about 0.3 to 0.5 in2 of will yield little improve- Temperature at 155 ± 15 °C 120 Seconds Maximum ment in thermal performance. Temperature Above 180 °C 70 - 180 Seconds Maximum Temperature 240 + 5/- 0 °C Time at Maximum Temperature 20 - 40 Seconds REFLOW SOLDERING Ramp-Down Rate + 6 °C/Second Maximum Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected Figure 2. Solder Reflow Temperature Profile to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humid- ity, HAST, or pressure pot. The solder reflow tempera- 10 s (max) 210 - 220 °C 3 °C/s (max) 4 °C/s (max) 183 °C 140 - 170 °C 50 s (max) 3° C/s (max) 60 s (min) Reflow Zone Pre-Heating Zone Maximum peak temperature at 240 °C is allowed. Figure 3. Solder Reflow Temperatures and Time Durations www.vishay.com Document Number 71681 2 03-Mar-06

AN822 Vishay Siliconix TABLE 1: EQIVALENT STEADY STATE PERFORMANCE Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8 Configuration Single Dual Single Dual Single Dual Single Dual Single Dual Thermal Resiatance R (C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5 thJC PowerPAK 1212 Standard SO-8 Standard TSSOP-8 TSOP-6 49.8 °C 85 °C 149 °C 125 °C 2.4 °C/W 20 °C/W 52 °C/W 40 °C/W PC Board at 45 °C Figure 4. Temperature of Devices on a PC Board THERMAL PERFORMANCE Introduction Spreading Copper A basic measure of a device’s thermal performance is Designers add additional copper, spreading copper, to the junction-to-case thermal resistance, Rθjc, or the the drain pad to aid in conducting heat from a device. It junction to- foot thermal resistance, Rθjf. This parameter is helpful to have some information about the thermal is measured for the device mounted to an infinite heat performance for a given area of spreading copper. sink and is therefore a characterization of the device Figure 5 and Figure 6 show the thermal resistance of a only, in other words, independent of the properties of the PowerPAK 1212-8 single and dual devices mounted on object to which the device is mounted. Table 1 shows a a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter- comparison of the PowerPAK 1212-8, PowerPAK SO-8, nal layers and the backside layer are solid copper. The standard TSSOP-8 and SO-8 equivalent steady state internal layers were chosen as solid copper to model the performance. large power and ground planes common in many appli- By minimizing the junction-to-foot thermal resistance, the cations. The top layer was cut back to a smaller area and MOSFET die temperature is very close to the tempera- at each step junction-to-ambient thermal resistance ture of the PC board. Consider four devices mounted on measurements were taken. The results indicate that an a PC board with a board temperature of 45 °C (Figure 4). area above 0.2 to 0.3 square inches of spreading copper Suppose each device is dissipating 2 W. Using the junc- gives no additional thermal performance improvement. tion-to-foot thermal resistance characteristics of the A subsequent experiment was run where the copper on PowerPAK 1212-8 and the other SMT packages, die the back-side was reduced, first to 50 % in stripes to temperatures are determined to be 49.8 °C for the Pow- mimic circuit traces, and then totally removed. No signif- erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for icant effect was observed. standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the Power- PAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on r whereas a rise DS(ON) of over 40 °C will cause an increase in r as high DS(ON) as 20 %. Document Number 71681 www.vishay.com 03-Mar-06 3

AN822 Vishay Siliconix 105 130 Spreading Copper (sq. in.) 120 Spreading Copper (sq. in.) 95 110 85 100 W) W) C/ 75 C/ 90 R(°AJht 65 R(°AJ ht 80 50 % 100 % 70 100 % 55 0 % 50 % 60 0 % 45 50 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance CONCLUSIONS As a derivative of the PowerPAK SO-8, the PowerPAK The PowerPAK 1212-8 combines small size with attrac- 1212-8 uses the same packaging technology and has tive thermal characteristics. By minimizing the thermal been shown to have the same level of thermal perfor- rise above the board temperature, PowerPAK simplifies mance while having a footprint that is more than 40 % thermal design considerations, allows the device to run smaller than the standard TSSOP-8. cooler, keeps r low, and permits the device to DS(ON) Recommended PowerPAK 1212-8 land patterns are handle more current than a same- or larger-size MOS- provided to aid in PC board layout for designs using this FET die in the standard TSSOP-8 or SO-8 packages. new package. www.vishay.com Document Number 71681 4 03-Mar-06

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single 0.152 (3.860) 0.039 0.068 0.010 (0.990) (1.725) (0.255) 0.016 (0.405) 8 5) 4 0) 8 3 9 9 0 2 0 3 0. 2. 0. 2. ( ( 0.026 (0.660) 0.025 0.030 (0.635) (0.760) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index A P P L I C A T I O N N O T E Document Number: 72597 www.vishay.com Revision: 21-Jan-08 7

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