Si3440DV Vishay Siliconix N-Channel 150-V (D-S) MOSFET FEATURES PRODUCT SUMMARY • Halogen-free According to IEC 61249-2-21 V (V) R (Ω) I (A) DS DS(on) D Definition 150 0.375 at VGS = 10 V 1.5 (cid:129) TrenchFET® Power MOSFET 0.400 at VGS = 6.0 V 1.4 (cid:129) PWM Optimized for Fast Switching In Small Footprint (cid:129) 100 % R Tested g (cid:129) Compliant to RoHS Directive 2002/95/EC APPLICATIONS (cid:129) Primary Side Switch for Low Power DC/DC Converters TSOP-6 (1, 2, 5, 6) D Top View 1 6 3 mm 2 5 (3) G 3 4 2.85 mm (4) S Ordering Information: Si3440DV-T1-E3 (Lead (Pb)-free) Si3440DV-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS T = 25 °C, unless otherwise noted A Parameter Symbol 5 s Steady State Unit Drain-Source Voltage VDS 150 V Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 175 °C)a TTAA == 2855 °°CC ID 11..51 10..28 A Pulsed Drain Current IDM 6 Single Avalanche Current IAS 4 L = 0.1 mH Single Avalanche Energy (Duty Cycle ≤ 1 %) EAS 0.8 mJ Continuous Source Current (Diode Conduction)a IS 1.7 1.0 A TA = 25 °C 2.0 1.14 Maximum Power Dissipationa PD W TA = 85 °C 1.0 0.59 Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C THERMAL RESISTANCE RATINGS Parameter Symbol Typical Maximum Unit t ≤ 5 s 45 62.5 Maximum Junction-to-Ambienta RthJA Steady State 90 110 °C/W Maximum Junction-to-Foot (Drain) Steady State RthJF 25 30 Notes: a. Surface Mounted on 1" x 1" FR4 board. Document Number: 72380 www.vishay.com S09-0766-Rev. D, 04-May-09 1

Si3440DV Vishay Siliconix SPECIFICATIONS T = 25 °C, unless otherwise noted J Parameter Symbol Test Conditions Min. Typ. Max. Unit Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 2 4 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA VDS = 150 V, VGS = 0 V 1 Zero Gate Voltage Drain Current IDSS µA VDS = 150 V, VGS = 0 V, TJ = 85 °C 5 On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 4 A VGS = 10 V, ID = 1.5 A 0.310 0.375 Drain-Source On-State Resistancea RDS(on) Ω VGS = 6.0 V, ID = 1.4 A 0.330 0.400 Forward Transconductancea gfs VDS = 15 V, ID = 1.5 A 4.1 S Diode Forward Voltagea VSD IS = 1.7 A, VGS = 0 V 0.8 1.2 V Dynamicb Total Gate Charge Qg 5.4 8 Gate-Source Charge Qgs VDS = 75 V, VGS = 10 V, ID = 1.5 A 1.1 nC Gate-Drain Charge Qgd 1.9 Gate Resistance Rg f = 1 MHz 4 9 15 Ω Turn-On Delay Time td(on) 8 15 Rise Time tr VDD = 75 V, RL = 75 Ω 10 15 Turn-Off Delay Time td(off) ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω 20 30 ns Fall Time tf 15 25 Source-Drain Reverse Recovery Time trr IF = 1.7 A, dI/dt = 100 A/µs 40 60 Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 4.0 4.0 VGS = 10 V thru 5V 3.5 3.5 3.0 3.0 A) A) nt ( 2.5 nt ( 2.5 e e urr urr C 2.0 C 2.0 n n ai ai - DrID 11..05 - DrID 11..05 TC = 125 °C 4 V 25 °C 0.5 0.5 3 V - 55 °C 0.0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics www.vishay.com Document Number: 72380 2 S09-0766-Rev. D, 04-May-09

Si3440DV Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.5 320 )Ω 0.4 240 Ciss ce ( VGS = 6.0 V F) n p esista 0.3 VGS = 10 V ance ( n-R acit 160 O p - 0.2 Ca S(on) C - D 80 R 0.1 Crss Coss 0.0 0 0 1 2 3 4 0 10 20 30 40 50 60 70 80 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current Capacitance 10 2.5 VDS = 75 V VGS = 10 V Source Voltage (V) 68 ID = 1.5 A On-Resistance malized) 12..50 ID = 1.5 A Gate-to- 4 - S(on)(Nor - RD 1.0 S G 2 V 0 0.5 0 1 2 3 4 5 6 -50 -25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 10 1.0 0.8 Current (A) TJ = 150 °C sistance ()Ω 0.6 ID = 1.5 A ource On-Re - SS - on) 0.4 I S( D R 0.2 TJ = 25 °C 1 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Document Number: 72380 www.vishay.com S09-0766-Rev. D, 04-May-09 3

Si3440DV Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 0.8 30 25 0.4 ID = 250 µA V) 20 e ( nc 0.0 W) Varia wer ( 15 S(th) -0.4 Po G 10 V -0.8 5 -1.2 0 -50 -25 0 25 50 75 100 125 150 0.01 0.1 1 10 100 600 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 10 IDMLimited Limited byRDS(on)* P(t) = 0.0001 1 (A) P(t) = 0.001 nt Curre 0.1 LIiDm(oitne)d P(t) = 0.01 n ai Dr P(t) = 0.1 - P(t) = 1 D I 0.01 TA = 25 °C P(t) = 10 Single Pulse DC BVDSS Limited 0.001 0.1 1 10 100 1000 VDS-Drain-to-SourceVoltage(V) *VGS>minimumVGSatwhichRDS(on)isspecified Safe Operating Area 2 1 nt Duty Cycle = 0.5 e e Transiedance 0.2 ctivmp Notes: ed Effeermal I 0.1 0.1 PDM malizTh 0.05 t1 Nor 0.02 1. Duty Cyclet,2 D = t1 t2 2. Per Unit Base = RthJA = 90°C/W Single Pulse 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient www.vishay.com Document Number: 72380 4 S09-0766-Rev. D, 04-May-09

Si3440DV Vishay Siliconix TYPICAL CHARACTERISTICS 25°C, unless otherwise noted 2 1 nt Duty Cycle = 0.5 e e Transiedance 0.2 ctivmp zed Effehermal I 0.1 00..105 aliT m or 0.02 N Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72380. Document Number: 72380 www.vishay.com S09-0766-Rev. D, 04-May-09 5

Package Information Vishay Siliconix TSOP: 5/6−LEAD JEDEC Part N umber: MO-193C e1 e1 5 4 6 5 4 E1 E E1 E 1 1 2 3 2 3 -B- -B- e b 0.15 M C B A e b 0.15 M C B A 5-LEAD TSOP 6-LEAD TSOP -A- 4x 1 D 0.17 Ref R c A2 A R L 2 Gauge Plane Seating Plane Seating Plane L 0.08 C -C- A1 4x 1 (L1 ) MILLIMETERS INCHES Dim Min Nom Max Min Nom Max A 0.91 - 1.10 0.036 - 0.043 A1 0.01 - 0.10 0.0004 - 0.004 A2 0.90 - 1.00 0.035 0.038 0.039 b 0.30 0.32 0.45 0.012 0.013 0.018 c 0.10 0.15 0.20 0.004 0.006 0.008 D 2.95 3.05 3.10 0.116 0.120 0.122 E 2.70 2.85 2.98 0.106 0.112 0.117 E1 1.55 1.65 1.70 0.061 0.065 0.067 e 0.95 BSC 0.0374 BSC e 1 1.80 1.90 2.00 0.071 0.075 0.079 L 0.32 - 0.50 0.012 - 0.020 L 1 0.60 Ref 0.024 Ref L 2 0.25 BSC 0.010 BSC R 0.10 - - 0.004 - - 0 4 8 0 4 8 1 7 Nom 7 Nom ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540 Document Number: 71200 www.vishay.com 18-Dec-06 1

AN823 Vishay Siliconix (cid:1) Mounting LITTLE FOOT TSOP-6 Power MOSFETs Surface mounted power MOSFET packaging has been based on Since surface mounted packages are small, and reflow soldering integrated circuit and small signal packages. Those packages is the most common form of soldering for surface mount have been modified to provide the improvements in heat transfer components, “thermal” connections from the planar copper to the required by power MOSFETs. Leadframe materials and design, pads have not been used. Even if additional planar copper area is molding compounds, and die attach materials have been used, there should be no problems in the soldering process. The changed. What has remained the same is the footprint of the actual solder connections are defined by the solder mask packages. openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. The basis of the pad design for surface mounted power MOSFET A final item to keep in mind is the width of the power traces. The is the basic footprint for the package. For the TSOP-6 package absolute minimum power trace width must be determined by the outline drawing see http://www.vishay.com/doc?71200 and see amount of current it has to carry. For thermal reasons, this http://www.vishay.com/doc?72610 for the minimum pad footprint. minimum width should be at least 0.020 inches. The use of wide In converting the footprint to the pad set for a power MOSFET, you traces connected to the drain plane provides a low impedance must remember that not only do you want to make electrical path for heat to move away from the device. connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. REFLOW SOLDERING In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated Vishay Siliconix surface-mount packages meet solder reflow circuit, typical connections would be made with traces that are reliability requirements. Devices are subjected to solder reflow as a 0.020 inches wide. Since the drain pins serve the additional test preconditioning and are then reliability-tested using function of providing the thermal connection to the package, this temperature cycle, bias humidity, HAST, or pressure pot. The level of connection is inadequate. The total cross section of the solder reflow temperature profile used, and the temperatures and copper may be adequate to carry the current required for the time duration, are shown in Figures 2 and 3. application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose. 0.167 4.25 Ramp-Up Rate +6(cid:2)C/Second Maximum 0.074 Temperature @ 155 (cid:1) 15(cid:2)C 120 Seconds Maximum 1.875 0.014 0.122 0.35 3.1 Temperature Above 180(cid:2)C 70 − 180 Seconds 0.026 Maximum Temperature 240 +5/−0(cid:2)C 0.65 Time at Maximum Temperature 20 − 40 Seconds Ramp-Down Rate +6(cid:2)C/Second Maximum 0.049 0.049 0.010 1.25 1.25 0.25 FIGURE 1. Recommended Copper Spreading Footprint FIGURE 2. Solder Reflow Temperature Profile Document Number: 71743 www.vishay.com 27-Feb-04 1

AN823 Vishay Siliconix 10 s (max) 255 − 260(cid:2)C 1(cid:2)4(cid:2)C/s (max) 3-6(cid:2)C/s (max) 217(cid:2)C 140 − 170(cid:2)C 60 s (max) 3(cid:2)C/s (max) 60-120 s (min) Reflow Zone Pre-Heating Zone Maximum peak temperature at 240(cid:2)C is allowed. FIGURE 3. Solder Reflow Temperature and Time Durations THERMAL PERFORMANCE A basic measure of a device’s thermal performance is the On-Resistance vs. Junction Temperature junction-to-case thermal resistance, R(cid:1) , or the 1.6 jc junction-to-foot thermal resistance, R(cid:1)jf. This parameter is VGS = 4.5 V measured for the device mounted to an infinite heat sink and ID = 6.1 A is therefore a characterization of the device only, in other 1.4 e words, independent of the properties of the object to which the c n a doef vthicee T isS OmPo-u6n.ted. Table 1 shows the thermal performance esiistzed) 1.2 n-Rmali TABLE 1. − On)(Nor 1.0 o S( D Equivalent Steady State Performance—TSOP-6 r 0.8 Thermal Resistance R(cid:1)jf 30(cid:2)C/W 0.6 −50 −25 0 25 50 75 100 125 150 SYSTEM AND ELECTRICAL IMPACT OF TJ − Junction Temperature ((cid:2)C) TSOP-6 FIGURE 4. Si3434DV In any design, one must take into account the change in MOSFET r with temperature (Figure 4). DS(on) www.vishay.com Document Number: 71743 2 27-Feb-04

Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR TSOP-6 0.099 (2.510) 9 3) 4 6) 1 2 6 2 1 0 0 6 0. 3. 0. 1. ( ( 8 9) 2 9 0 6 0. 0. ( 0.039 0.020 0.019 (1.001) (0.508) (0.493) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index E T O N N O I T A C I L P P A www.vishay.com Document Number: 72610 26 Revision: 21-Jan-08

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