IRLL014, SiHLL014 www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY • Surface mount VDS (V) 60 • Available in tape and reel RDS(on) () VGS = 5.0 V 0.20 • Dynamic dV/dt rating Q max. (nC) 8.4 • Logic-level gate drive g • R specified at V = 4 V and 5 V Q (nC) 3.5 DS(on) GS gs • Fast switching Available Q (nC) 6.0 gd • Ease of paralleling Configuration Single • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 D DESCRIPTION Third generation power MOSFETs from Vishay provide the SOT-223 designer with the best combination of fast switching, D ruggedized device design, low on-resistance and G cost-effectiveness. S The SOT-223 package is designed for surface-mounting D G using vapor phase, infrared, or wave soldering techniques. Its unique package design allows for easy automatic Marking code: LA S pick-and-place as with other SOT or SOIC packages but has the added advantage of improved thermal performance N-Channel MOSFET due to an enlarged tab for heatsinking. Power dissipation of greater than 1.25 W is possible in a typical surface mount application. ORDERING INFORMATION Package SOT-223 Lead (Pb)-free and Halogen-free SiHLL014TR-GE3 Lead (Pb)-free IRLL014TRPbF a Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted) C PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage V 60 DS V Gate-Source Voltage V ± 10 GS T = 25 °C 2.7 Continuous Drain Current V at 10 V C I GS T = 100 °C D 1.7 A C Pulsed Drain Current a I 22 DM Linear Derating Factor 0.025 W/°C Linear Derating Factor (PCB mount) e 0.017 Single Pulse Avalanche Energy b E 100 mJ AS Repetitive Avalanche Current a I 2.7 A AR Repetitive Avalanche Energy a E 0.31 mJ AR Maximum Power Dissipation T = 25 °C 3.1 C P W Maximum Power Dissipation (PCB mount) e T = 25 °C D 2.0 A Peak Diode Recovery dV/dt c dV/dt 4.5 V/ns Operating Junction and Storage Temperature Range T , T -55 to +150 J stg °C Soldering Recommendations (Peak temperature) d for 10 s 300 Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 25 V, starting TJ = 25 °C, L = 16 mH, Rg = 25 , IAS = 2.7 A (see fig. 12). c. ISD  10 A, dI/dt  90 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. When mounted on 1" square PCB (FR-4 or G-10 material). S16-0015-Rev. F, 18-Jan-16 1 Document Number: 91319 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRLL014, SiHLL014 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL MIN. TYP. MAX. UNIT Maximum Junction-to-Ambient  R - - 60 (PCB mount) a thJA °C/W Maximum Junction-to-Case (Drain) R - - 40 thJC Note a. When mounted on 1" square PCB (FR-4 or G-10 material). SPECIFICATIONS (T = 25 °C, unless otherwise noted) J PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage V V = 0 V, I = 250 μA 60 - - V DS GS D VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.073 - V/°C Gate-Source Threshold Voltage V V = V , I = 250 μA 1.0 - 2.0 V GS(th) DS GS D Gate-Source Leakage I V = ± 10 V - - ± 100 nA GSS GS V = 60 V, V = 0 V - - 25 DS GS Zero Gate Voltage Drain Current I μA DSS V = 48 V, V = 0 V, T = 125 °C - - 250 DS GS J V = 5.0 V I = 1.6 A b - - 0.20 GS D Drain-Source On-State Resistance RDS(on) V = 4.0 V I = 1.4 A b - - 0.28  GS D Forward Transconductance g V = 25 V, I = 1.6 A 3.2 - - S fs DS D Dynamic Input Capacitance C - 400 - iss V = 0 V, GS Output Capacitance C V = 25 V, - 170 - pF oss DS f = 1.0 MHz, see fig. 5 Reverse Transfer Capacitance C - 42 - rss Total Gate Charge Q - - 8.4 g I = 10 A, V = 48 V, Gate-Source Charge Q V = 5.0 V D DS - - 3.5 nC gs GS see fig. 6 and 13 b Gate-Drain Charge Q - - 6.0 gd Turn-On Delay Time t - 9.3 - d(on) Rise Time tr VDD = 30 V, ID = 10 A, - 110 - ns Turn-Off Delay Time td(off) Rg = 12 , RD = 2.8 , see fig. 10 b - 17 - Fall Time t - 26 - f Internal Drain Inductance L Between lead, D - 4.0 - D 6 mm (0.25") from nH package and center of G Internal Source Inductance LS die contact - 6.0 - S Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS MOSFET symbol D - - 2.7 showing the  A integral reverse G Pulsed Diode Forward Current a ISM p - n junction diode S - - 22 Body Diode Voltage V T = 25 °C, I = 2.7 A, V = 0 V b - - 1.6 V SD J S GS Body Diode Reverse Recovery Time t - 65 130 ns rr T = 25 °C, I = 10 A, dI/dt = 100 A/μs b J F Body Diode Reverse Recovery Charge Q - 0.33 0.65 μC rr Forward Turn-On Time t Intrinsic turn-on time is negligible (turn-on is dominated by L and L ) on S D Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. S16-0015-Rev. F, 18-Jan-16 2 Document Number: 91319 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRLL014, SiHLL014 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 101TopV7543G....S5005 VVVV sistance 32..05 IVDG =S 1=0 1 A0 V 3.0 V e ent (A) 10B0ottom2.27.55 VV e On Red) 2.0 Curr ourcmaliz 1.5 Drain 10-1 n-to-S(Nor 1.0 I, D 2.25 V Drai 10-2 20 µs Pulse Width , on) 0.5 TC = 25 °C RDS( 0.0 10-1 100 101 - 60- 40- 20 0 20 40 60 80 100120 140 160 VDS, Drain-to-Source Voltage (V) TJ, Junction Temperature (°C) Fig. 1 - Typical Output Characteristics, T = 25 °C Fig. 4 - Normalized On-Resistance vs. Temperature C TopV7G.S5V 700 VGS = 0 V, f = 1 MHz 5.0V C = C + C , C Shorted 101 43..05VV 600 Ciss = Cgs gd ds 3.0V rss gd Current (A) 10B0ottom22.7.55VV ance (pF) 450000 Coss = Cds C+i sCsgd Drain 10-1 2.25 V apacit 300 Coss , D C 200 I 10-2 20µs PulseWidth 100 Crss T = 150 °C C 0 10-1 100 101 100 101 VDS, Drain-to-SourceVoltage (V) VDS, Drain-to-Source Voltage (V) Fig. 2 - Typical Output Characteristics, T = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage C 101 10 I = 10 A D V) 150 °C ge ( 6 ent (A) 100 e Volta 6 VDS =V 3D0S V= 48 V Curr 10-1 25 °C ourc n S ai o- 4 Dr e-t , D 10-2 at I G , S 2 20 µs Pulse Width VG For test circuit 10-3 VDS = 25 V see figure 13 0 2 2.5 3 3.5 4 4.5 5 0 2 4 6 8 10 VGS, Gate-to-Source Voltage (V) QG, Total Gate Charge (nC) Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S16-0015-Rev. F, 18-Jan-16 3 Document Number: 91319 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRLL014, SiHLL014 www.vishay.com Vishay Siliconix R D V A) TJ = 150 °C DS nt ( 101 VGS D.U.T. e urr Rg + C -VDD n ai Dr T = 25 °C 10 V e 100 J Pulse width ≤ 1 µs ers Duty factor ≤ 0.1 % v e R , D Fig. 10a - Switching Time Test Circuit S I V = 0 V GS 10-1 V 0.4 0.8 1.2 1.6 2.0 2.4 DS 90 % V , Source-to-Drain Voltage (V) SD Fig. 7 - Typical Source-Drain Diode Forward Voltage 10 % V GS 103 t t t t d(on) r d(off) f 5 Fig. 10b - Switching Time Waveforms 2 Operation in this area limited by R A) 102 DS(on) nt ( 5 e 2 urr 10 C 100 µs n 5 ai 1 ms Dr 2 , D 1 10 ms I 5 TC = 25 °C 2 TJ = 150 °C Single Pulse 0.1 0.1 2 5 1 2 5 10 2 5 102 2 5 103 V , Drain-to-Source Voltage (V) DS Fig. 8 - Maximum Safe Operating Area 3.0 2.5 A) nt ( 2.0 e Curr 1.5 n ai Dr 1.0 , D I 0.5 0.0 25 50 75 100 125 150 T , Case Temperature (°C) C Fig. 9 - Maximum Drain Current vs. Case Temperature S16-0015-Rev. F, 18-Jan-16 4 Document Number: 91319 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRLL014, SiHLL014 www.vishay.com Vishay Siliconix 102 )C D = 0.50 ZthJ 10 0.20 e ( 0.10 s n 0.05 o sp 1 0.02 PDM e R 0.01 mal Single Pulse t1 er 10-1 (Thermal Response) t2 h T Notes: 1. Duty Factor, D = t/t 1 2 2. Peak T = P x Z + T j DM thJC C 10-2 10-5 10-4 10-3 10-2 0.1 1 101 102 103 t , Rectangular Pulse Duration (s) 1 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L V V DS DS Vary tp to obtain tp required I AS V DD Rg D.U.T + V - DD V DS I AS 10 V t 0.01 Ω p I AS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms mJ) 250 gy ( Top 1.I2D A er 200 1.7 A En Bottom 2.7 A e h c an 150 al v A e 100 s ul P e gl 50 n Si , AS 0 VDD = 25 V E 25 50 75 100 125 150 Starting T, Junction Temperature (°C) J Fig. 12c - Maximum Avalanche Energy vs. Drain Current S16-0015-Rev. F, 18-Jan-16 5 Document Number: 91319 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

IRLL014, SiHLL014 www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. Q 50 kΩ G VGS 12 V 0.2 µF 0.3 µF QGS QGD + V D.U.T. - DS V G V GS 3 mA Charge I I G D Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations D.U.T. • Low stray inductance • Ground plane • Low leakage inductance current transformer - + - + - Rg • dV/dt controlled by Rg + •• DISrDi vceorn staromlleed t ybpye d aust yD f.aUc.Tto.r “D” -VDD • D.U.T. - device under test Driver gate drive Period D = P.W. P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery Body diode forward current current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91319. S16-0015-Rev. F, 18-Jan-16 6 Document Number: 91319 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information Vishay Siliconix SOT-223 (HIGH VOLTAGE) D B A 3 0.08 (0.003) B1 C 00..1100 ((00..000044))MMCC BMM A 4 3 H E 0.20 (0.008)MC AM L1 1 2 3 4 x L 3 x B e θ 0.10 (0.004)MC BM e1 4 x C MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. A 1.55 1.80 0.061 0.071 B 0.65 0.85 0.026 0.033 B1 2.95 3.15 0.116 0.124 C 0.25 0.35 0.010 0.014 D 6.30 6.70 0.248 0.264 E 3.30 3.70 0.130 0.146 e 2.30 BSC 0.0905 BSC e1 4.60 BSC 0.181 BSC H 6.71 7.29 0.264 0.287 L 0.91 - 0.036 - L1 0.061 BSC 0.0024 BSC θ - 10' - 10' ECN: S-82109-Rev. A, 15-Sep-08 DWG: 5969 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension do not include mold flash. 4. Outline conforms to JEDEC outline TO-261AA. Document Number: 91363 www.vishay.com Revision: 15-Sep-08 1

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