High Performance, Digital Output Gyroscope Data Sheet ADXRS453 FEATURES GENERAL DESCRIPTION Complete rate gyroscope on a single chip The ADXRS453 is an angular rate sensor (gyroscope) intended ±300°/sec angular rate sensing for industrial, instrumentation, and stabilization applications in Ultrahigh vibration rejection: 0.01°/sec/g high vibration environments. An advanced, differential, quad Excellent 16°/hour null bias stability sensor design rejects the influence of linear acceleration, enabling Internal temperature compensation the ADXRS453 to offer high accuracy rate sensing in harsh 2000 g powered shock survivability environments where shock and vibration are present. SPI digital output with 16-bit data-word The ADXRS453 uses an internal, continuous self-test architec- Low noise and low power ture. The integrity of the electromechanical system is checked by 3.3 V to 5 V operation applying a high frequency electrostatic force to the sense structure −40°C to +105°C operation to generate a rate signal that can be differentiated from the base- Ultrasmall, light, and RoHS compliant band rate data and internally analyzed. Two package options Low cost SOIC_CAV package for yaw rate (z-axis) response The ADXRS453 is capable of sensing an angular rate of up to Innovative ceramic vertical mount package (LCC_V) for ±300°/sec. Angular rate data is presented as a 16-bit word that pitch and roll response is part of a 32-bit SPI message. APPLICATIONS The ADXRS453 is available in a 16-lead plastic cavity SOIC (SOIC_CAV) and an SMT-compatible vertical mount package Rotation sensing in high vibration environments (LCC_V), and is capable of operating across a wide voltage Rotation sensing for industrial and instrumentation range (3.3 V to 5 V). applications High performance platform stabilization FUNCTIONAL BLOCK DIAGRAM CP5 VX HIGH VOLTAGE GENERATION ADXRS453 PDD LDO REGULATOR DVDD HV DRIVE AVDD CLOCK ARITHMETIC PHASE- DIVIDER LOGIC UNIT LOCKED LOOP AMPLITUDE DECIMATION Y DETECT FILTER OR M E MOSI TEMPERATURE M BAND-PASS 12-BIT DEMOD CALIBRATION S/ SPI MISO FILTER ADC ER INTERFACE SCLK T S CS GI Q DAQ Q FILTER DEFTAEUCLTTION RE Z-AXIS ANGULAR RATE SENSOR P DAQ SELF-TEST DVSS CONTROL PSS AVSS EEPROM 09155-001 Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

ADXRS453 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  ADXRS453 Signal Chain Timing ............................................. 13  Applications ....................................................................................... 1  SPI Communication Protocol ....................................................... 14  General Description ......................................................................... 1  Command/Response ................................................................. 14  Functional Block Diagram .............................................................. 1  Device Data Latching ................................................................. 15  Revision History ............................................................................... 2  SPI Timing Characteristics ....................................................... 16  Specifications ..................................................................................... 3  Command/Response Bit Definitions ....................................... 17  Absolute Maximum Ratings ............................................................ 4  Fault Register Bit Definitions ................................................... 18  Thermal Resistance ...................................................................... 4  Recommended Start-Up Sequence with CHK Bit Assertion ...................................................................................... 20  Rate Sensitive Axis ....................................................................... 4  Rate Data Format ............................................................................ 21  ESD Caution .................................................................................. 4  Memory Map and Registers .......................................................... 22  Pin Configurations and Function Descriptions ........................... 5  Memory Map .............................................................................. 22  Typical Performance Characteristics ............................................. 7  Memory Register Definitions ................................................... 23  Theory of Operation ........................................................................ 9  Package Orientation and Layout Information ............................ 25  Continuous Self-Test .................................................................... 9  Solder Profile............................................................................... 26  Mechanical Performance ............................................................... 10  Package Marking Codes ............................................................ 27  Noise Performance ......................................................................... 11  Outline Dimensions ....................................................................... 28  Applications Information .............................................................. 12  Ordering Guide .......................................................................... 29  Calibrated Performance ............................................................. 12  Mechanical Considerations for Mounting .............................. 12  Application Circuits ................................................................... 12  REVISION HISTORY 12/11—Rev. A to Rev. B Changes to Features Section............................................................ 1 Changes to Rate Sensitive Axis Section ......................................... 4 Deleted Endnote 1, Table 3 .............................................................. 4 Deleted Figure 5; Renumbered Sequentially ................................. 6 Changes to Figure 4 .......................................................................... 6 Changes to Figure 32 ...................................................................... 25 Deleted Figure 36 ............................................................................ 26 6/11—Rev. 0 to Rev. A Changes to Bit 30 and Bit 31 in Table 9 ....................................... 14 Updated Outline Dimensions ....................................................... 29 Changes to Ordering Guide .......................................................... 30 1/11—Revision 0: Initial Version Rev. B | Page 2 of 32

Data Sheet ADXRS453 SPECIFICATIONS T = T to T , P = 5 V, angular rate = 0°/sec, bandwidth = f/200 (~77.5 Hz), ±1 g, continuous self-test on. A MIN MAX DD 0 Table 1. Parameter Test Conditions/Comments Symbol Min Typ Max Unit MEASUREMENT RANGE Full-scale range FSR ±300 ±400 °/sec SENSITIVITY See Figure 2 Nominal Sensitivity 80 LSB/°/sec Sensitivity Tolerance T = −40°C to +105°C −3 +3 % A Nonlinearity1 Best fit straight line 0.05 % FSR rms Cross-Axis Sensitivity2 −3 +3 % NULL ACCURACY T = 25°C ±0.4 °/sec A T = −40°C to +105°C ±0.5 °/sec A NOISE PERFORMANCE Rate Noise Density T = 25°C 0.015 °/sec/√Hz A T = 105°C 0.023 °/sec/√Hz A LOW-PASS FILTER Cutoff (−3 dB) Frequency f/200 f 77.5 Hz 0 LP Group Delay3 f = 0 Hz t 3.25 4 4.75 ms LP SENSOR RESONANT FREQUENCY f 13 15.5 19 kHz 0 SHOCK AND VIBRATION IMMUNITY Sensitivity to Linear Acceleration DC to 5 kHz 0.01 °/sec/g Vibration Rectification 0.0002 °/sec/g2 SELF-TEST See the Continuous Self-Test section Magnitude 2559 LSB Fault Register Threshold Compared to LOCSTx register data 2239 2879 LSB Sensor Data Status Threshold Compared to LOCSTx register data 1279 3839 LSB Frequency f/32 f 485 Hz 0 ST ST Low-Pass Filter Cutoff (−3 dB) Frequency f/8000 1.95 Hz 0 Group Delay3 52 64 76 ms SPI COMMUNICATIONS Clock Frequency 8.08 MHz Voltage Input High MOSI, CS, SCLK 0.85 × P P + 0.3 V DD DD Voltage Input Low MOSI, CS, SCLK −0.3 P × 0.15 V DD Voltage Output Low MISO, current = 3 mA 0.5 V Voltage Output High MISO, current = −2 mA P − 0.5 V DD Pull-Up Current CS, P = 3.3 V, CS = P × 0.15 60 200 μA DD DD CS, P = 5 V, CS = P × 0.15 80 300 μA DD DD MEMORY REGISTERS See the Memory Register Definitions section Temperature Register Value at 45°C 0 LSB Scale Factor 5 LSB/°C Quadrature, Self-Test, and Rate Registers Scale Factor 80 LSB/°/sec POWER SUPPLY Supply Voltage P 3.15 5.25 V DD Quiescent Supply Current I 6.0 8.0 mA DD Turn-On Time Power-on to 0.5°/sec of final value 100 ms 1 Maximum limit is guaranteed by Analog Devices, Inc., characterization. 2 Cross-axis sensitivity specification does not include effects due to device mounting on a printed circuit board (PCB). 3 Minimum and maximum limits are guaranteed by design. Rev. B | Page 3 of 32

ADXRS453 Data Sheet ABSOLUTE MAXIMUM RATINGS RATE SENSITIVE AXIS Table 2. Parameter Rating The ADXRS453 is available in two package options. Acceleration (Any Axis, 0.5 ms)  The SOIC_CAV package is for applications that require Unpowered 2000 g z-axis (yaw) rate sensing. Powered 2000 g  The LCC_V (vertical mount) package is for applications Supply Voltage (P ) −0.3 V to +6.0 V DD that require x-axis or y-axis (pitch or roll) rate sensing. Output Short-Circuit Duration Indefinite The package has terminals on two faces. However, the termi- (Any Pin to Ground) nals on the back are for internal evaluation only and should Operating Temperature Range not be used in the end application. The terminals on the LCC_V Package −55°C to +125°C bottom of the package incorporate metallization bumps SOIC_CAV Package −40°C to +125°C that ensure a minimum solder thickness for improved solder Storage Temperature Range joint reliability. These bumps are not present on the back LCC_V Package −65°C to +150°C terminals and, therefore, poor solder joint reliability can be SOIC_CAV Package −40°C to +150°C encountered if the back terminals are used in the end Stresses above those listed under Absolute Maximum Ratings application. For the outline dimensions of this package, see may cause permanent damage to the device. This is a stress Figure 38. rating only; functional operation of the device at these or any RATE other conditions above those indicated in the operational AXIS Z-AXIS section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect + device reliability. 16 THERMAL RESISTANCE + θsoJAl dise rsepde cinif iae dp rfoinrt tehde c wirocrusitt- bcaosaer dc o(nPdCiBti)o nfosr, tshuartf aisc,e f-omr oau dnetv ice SOIC PACKAGE9 RAAXTISE LCC_V PACKAGE 09155-002 Figure 2. Rate Signal Increases with Clockwise Rotation packages. Table 3. Thermal Resistance ESD CAUTION Package Type θ θ Unit JA JC 16-Lead SOIC_CAV (RG-16-1) 191.5 25 °C/W 14-Lead Ceramic LCC_V (EY-14-1) 185.5 23 °C/W Rev. B | Page 4 of 32

Data Sheet ADXRS453 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DVDD 1 16 SCLK RSVD 2 15 MOSI RSVD 3 14 AVDD ADXRS453 CS 4 TOP VIEW 13 DVSS MISO 5 (Not to Scale) 12 RSVD PDD 6 11 AVSS PSS 7 10 RSVD VX 8 9 CP5 09155-003 Figure 3. Pin Configuration, 16-Lead SOIC_CAV Table 4. Pin Function Descriptions, 16-Lead SOIC_CAV Pin No. Mnemonic Description 1 DV Digital Regulated Voltage. See Figure 25 for the application circuit diagram. DD 2 RSVD Reserved. This pin must be connected to DV . SS 3 RSVD Reserved. This pin must be connected to DV . SS 4 CS Chip Select. 5 MISO Master In/Slave Out. 6 P Supply Voltage. DD 7 P Switching Regulator Ground. SS 8 V High Voltage Switching Node. See Figure 25 for the application circuit diagram. X 9 CP5 High Voltage Supply. See Figure 25 for the application circuit diagram. 10 RSVD Reserved. This pin must be connected to DV . SS 11 AV Analog Ground. SS 12 RSVD Reserved. This pin must be connected to DV . SS 13 DV Digital Signal Ground. SS 14 AV Analog Regulated Voltage. See Figure 25 for the application circuit diagram. DD 15 MOSI Master Out/Slave In. 16 SCLK SPI Clock. Rev. B | Page 5 of 32

ADXRS453 Data Sheet PDD PSS MOSI DVSS CS VX RSVD 14 13 12 11 10 9 8 1 2 3 4 5 6 7 S D O D K 5 D AVS AVD MIS DVD SCL CP RSV TOP VIEW (Not to Scale) NOTES 1.THE PACKAGE HAS TERMINALS ON TWO FACES. HOWEVER, THE TERMINALS ON THE BACK ARE FOR INTERNAL EVALUATION ONLY AND SHOULD NOT BE USED IN THE END APPLICATION. THE TERMINALS ON THE BOTTOM OF THE PACKAGE INCORPORATE METALLIZATION BUMPS THAT ENSURE A MINIMUM SOLDER THICKNESS FOR IMPROVED SOLDER JOINT RELIABILITY. THESE BUMPS ARE NOT PRESENT ON THE BACK TERMINALS AND, THEREFORE, POOR SOLDER JISNOE TIENH FTEI GR EEUNLRDIEA A B3P8ILP.ILTIYC ACTAINO NB.E F EONRC TOHUEN OTEURTELDIN IEF DTIHMEE NBSAICOKN TSE ORFM TINHAISL SP AACRKEA UGSEE,D 09155-004 Figure 4. Pin Configuration, 14-Terminal LCC_V Table 5. Pin Function Descriptions, 14-Terminal LCC_V Pin No. Mnemonic Description 1 AV Analog Ground. SS 2 AV Analog Regulated Voltage. See Figure 26 for the application circuit diagram. DD 3 MISO Master In/Slave Out. 4 DV Digital Regulated Voltage. See Figure 26 for the application circuit diagram. DD 5 SCLK SPI Clock. 6 CP5 High Voltage Supply. See Figure 26 for the application circuit diagram. 7 RSVD Reserved. This pin must be connected to DV . SS 8 RSVD Reserved. This pin must be connected to DV . SS 9 V High Voltage Switching Node. See Figure 26 for the application circuit diagram. X 10 CS Chip Select. 11 DV Digital Signal Ground. SS 12 MOSI Master Out/Slave In. 13 P Switching Regulator Ground. SS 14 P Supply Voltage. DD Rev. B | Page 6 of 32

Data Sheet ADXRS453 TYPICAL PERFORMANCE CHARACTERISTICS 20 40 18 35 %) 16 %) ON ( 14 ON ( 30 LATI 12 LATI 25 U U P P O 10 O 20 P P F F O 8 O T T 15 N N E 6 E C C R R 10 PE 4 PE 2 5 0–2.0 –1.6 –1.2 –0.8 –E0R.4ROR0 (°/se0c.4) 0.8 1.2 1.6 2.0 09155-006 0–2.0 –1.6 –1.2 –0.8 –E0R.4ROR0 (°/se0c.4) 0.8 1.2 1.6 2.0 09155-009 Figure 5. SOIC_CAV Null Accuracy at 25°C Figure 8. LCC_V Null Accuracy at 25°C 30 30 25 25 %) %) N ( N ( O O TI 20 TI 20 A A L L U U P P O 15 O 15 P P F F O O T T N 10 N 10 E E C C R R E E P P 5 5 0 0 –3.0 –2.5 –2.0 –1.5 –1.0 E–0.5RROR0 (°/s0.5ec) 1.0 1.5 2.0 2.5 3.0 09155-007 –3.0 –2.5 –2.0 –1.5 –1.0 E–0.5RROR0 (°/s0.5ec) 1.0 1.5 2.0 2.5 3.0 09155-010 Figure 6. SOIC_CAV Null Drift over Temperature Figure 9. LCC_V Null Drift over Temperature 25 25 %) 20 %) 20 N ( N ( O O TI TI LA 15 LA 15 U U P P O O P P F F O 10 O 10 T T N N E E C C R R PE 5 PE 5 0 0 –3.0 –2.5 –2.0 –1.5CHA–1.0NGE–0.5 IN S0ENSIT0.5IVIT1.0Y (%)1.5 2.0 2.5 3.0 09155-008 –0.030 –0.025 –0.020 –0.015CHA–0.010NGE–0.005 IN S0ENSI0.005TIVIT0.010Y (%)0.015 0.020 0.025 0.030 09155-011 Figure 7. SOIC_CAV Sensitivity Error at 25°C Figure 10. LCC_V Sensitivity Error at 25°C Rev. B | Page 7 of 32

ADXRS453 Data Sheet 30 45 40 25 %) %) 35 N ( N ( O O TI 20 TI 30 A A L L U U 25 P P O 15 O P P F F 20 O O T T N 10 N 15 E E C C R R E E 10 P P 5 5 0 –3 –2 –1 ERRO0R (%) 1 2 3 09155-012 0 –3 –2 –1 ERRO0R (%) 1 2 3 09155-015 Figure 11. SOIC_CAV Sensitivity Drift over Temperature Figure 14. LCC_V Sensitivity Drift over Temperature 1 1 c) c) e e s s E (°/ 0.1 E (°/ 0.1 C C N N A A RI RI A A V V N N A A L L AL 0.01 AL 0.01 T T O O O O R R 0.001 0.001 0.0000001 0.000001 0.00001 0.0001AVERA0.001GING0.01 TIME 0.1(Hours1) 10 100 100009155-013 0.0000001 0.000001 0.00001 0.0001AVERA0.001GING0.01 TIME 0.1(Hours1) 10 100 100009155-016 Figure 12. Typical Root Allan Variance at 40°C Figure 15. Typical Root Allan Variance at 105°C 3 3 2 2 ec) 1 1 s UTPUT (°/ 0 ROR (%) 0 O R L E UL –1 –1 N –2 –2 –3–50 –30 –10 10TEMP3E0RATU5R0E (°C7)0 90 110 130 09155-014 –3–50 –30 –10 10TEMP3E0RATU5R0E (°C7)0 90 110 130 09155-017 Figure 13. Null Output over Temperature, 16 Devices Soldered on PCB Figure 16. Sensitivity over Temperature, 16 Devices Soldered on PCB Rev. B | Page 8 of 32

Data Sheet ADXRS453 THEORY OF OPERATION CONTINUOUS SELF-TEST The ADXRS453 operates on the principle of a resonator gyroscope. Figure 17 shows a simplified version of one of four polysilicon The ADXRS453 gyroscope implements a complete electro- sensing structures. Each sensing structure contains a dither frame mechanical self-test. An electrostatic force is applied to the that is electrostatically driven to resonance. This produces the gyroscope frame, resulting in a deflection of the capacitive sense necessary velocity element to produce a Coriolis force when the fingers. This deflection is exactly equivalent to deflection that device experiences angular rate. In the SOIC_CAV package, the occurs as a result of external rate input. The output from the ADXRS453 is designed to sense a z-axis (yaw) angular rate; the beam structure is processed by the same signal chain as a true LCC_V vertical mount package orients the device such that it rate output signal, providing complete coverage of both the can sense pitch or roll angular rate on the same PCB. electrical and mechanical components. The electromechanical self-test is performed continuously during operation at a rate higher than the output bandwidth of the device. The self-test routine generates equivalent positive and negative rate deflections. This information can then be filtered with no overall effect on the demodulated rate output. X Y Z RATE SIGNAL WITH CONTINUOUS SELF-TEST SIGNAL. SELF-TEST AMPLITUDE. LOW FREQUENCY RATE 09155-018 INTTOE TRTHNAEABF SLiLgLPEuYE Lr CCeIIM OF1IIM8TC.SPA C.AToRIOnENtDinuous Self-Test DIeNmFOoRdMuAlaTtIiOoNn. 09155-019 Figure 17. Simplified Gyroscope Sensing Structure The difference amplitude between the positive and negative When the sensing structure is exposed to angular rate, the self-test deflections is filtered to f/8000 (~1.95 Hz) and is 0 resulting Coriolis force couples into an outer sense frame, continuously monitored and compared to hard-coded self-test which contains movable fingers that are placed between fixed limits. If the measured amplitude exceeds these limits (listed in pickoff fingers. This forms a capacitive pickoff structure that Table 1), one of two error conditions is asserted, depending on senses Coriolis motion. The resulting signal is fed to a series of the magnitude of the self-test error. gain and demodulation stages that produce the electrical rate  For less severe self-test error magnitudes, the CST bit of the signal output. The quad sensor design rejects linear and angular fault register is asserted. However, the status bits (ST[1:0]) acceleration, including external g-forces and vibration. This is in the sensor data response remain set to 01 for valid achieved by mechanically coupling the four sensing structures sensor data. such that external g-forces appear as common-mode signals  For more severe self-test errors, the CST bit of the fault that can be removed by the fully differential architecture register is asserted and the status bits (ST[1:0]) in the implemented in the ADXRS453. sensor data response are set to 00 for invalid sensor data. The resonator requires 22.5 V (typical) for operation. Because Table 1 lists the thresholds for both of these failure conditions. only 5 V is typically available in most applications, a switching If desired, the user can access the self-test information by issuing regulator is included on chip. a read command to the self-test memory register (Address 0x04). See the SPI Communication Protocol section for more informa- tion about error reporting. Rev. B | Page 9 of 32

ADXRS453 Data Sheet MECHANICAL PERFORMANCE Shock response is also excellent, as shown in Figure 21 and The ADXRS453 has excellent shock and vibration rejection. Figure 22. Figure 21 shows a 99 g input stimulus applied to Figure 19 shows the output noise response of the ADXRS453 in each axis, and Figure 22 shows the typical response to this a vibration free environment. Figure 20 shows the response of shock in each axis. Shock response of 0.01°/sec/g is apparent. the same device to 15 g rms random vibration (50 Hz to 5 kHz). As shown in Figure 20, no frequencies are particularly sensitive to vibration. Response to vibration in all axes is similar. 0.1 40 20 Hz) 0 PUT (°/sec/ 0.01 TIMULUS (g) ––2400 T S RO OU 0.001 NPUT –60 Y I G –80 –100 0.00015 FREQUE5N0CY (Hz) 500 09155-020 –1200 0.05 TIME (0S.e1c0onds) 0.15 0.20 09155-022 Figure 19. ADXRS453 Output Noise Response with No Vibration Applied Figure 21. 99 g Shock Input 0.1 10 8 6 Hz) c) 4 OUTPUT (°/sec/ 0.01 O OUTPUT (°/se –220 YRO 0.001 GYR –4 G –6 –8 0.00015 FREQUE5N0CY (Hz) 500 09155-021 –100 0.05 TIME (0S.e1c0onds) 0.15 0.20 09155-023 Figure 20. ADXRS453 Output Noise Response with 15 g RMS Random Figure 22. Typical Output Response Due to 99 g Shock (see Figure 21) Vibration (50 Hz to 5 kHz) Applied Rev. B | Page 10 of 32

Data Sheet ADXRS453 NOISE PERFORMANCE Noise increases fairly linearly with temperature, as shown in The ADXRS453 noise performance is very consistent from Figure 23. device to device and varies very predictably with temperature. Table 6 contains statistical noise data at three temperature 0.050 points for a large population of ADXRS453 devices (more than 0.045 3000 parts from several manufacturing lots). 0.040 Hz) Table 6. Statistical Noise Data 0.035 c/ e Noise (°/sec/√Hz) Y (°/s 0.030 Temperature Mean Standard Deviation T 0.025 SI −40°C 0.0109 0.0012 DEN 0.020 +25°C 0.0149 0.0015 E +105°C 0.0222 0.0019 NOIS 0.015 0.010 0.005 0–50 0 TEMPERA5T0URE (°C) 100 150 09155-024 Figure 23. Noise Density vs. Temperature, 16 Devices Rev. B | Page 11 of 32

ADXRS453 Data Sheet APPLICATIONS INFORMATION CALIBRATED PERFORMANCE 1 DVDD SCLK 16 1µF The ADXRS453 gyroscope uses internal EEPROM memory to RSVD MOSI store its temperature calibration information. The calibration 1µF information is encoded into the device during factory test. The RSVD AVDD calibration data is used to perform offset, gain, and self-test cor- GND CS DVSS rections over temperature. By storing this information internally, 3.3VTO 5V MISO RSVD the ADXRS453 eliminates the need for the customer to perform system level temperature calibration. PDD AVSS 1µF MECHANICAL CONSIDERATIONS FOR MOUNTING PSS RSVD 100nF Mount the ADXRS453 in a location close to a hard mounting 8 VX CP5 9 470µH pPoCiBn tl oocf atthieo nP C(tBh.a tM iso,u ant ttihneg etnhde AofD aX leRvSe4r5 o3r aitn a tnh eu nmsiudpdpleo rotfe da GND >24V BDRIEOADKEDOWN GND 09155-026 trampoline, as shown in Figure 24) can result in apparent mea- Figure 25. Recommended Application Circuit, SOIC_CAV Package surement errors because the gyroscope is subject to the resonant vibration of the PCB. Locating the gyroscope near a hard mounting point helps to ensure that any PCB resonances at the gyroscope 3.3VTO 5V TOP VIEW are above the frequency at which harmful aliasing with the 1 14 internal electronics can occur. To ensure that aliased signals do AVSS PDD 1µF 1µF not couple into the baseband measurement range, design the AVDD PSS module so that the first system level resonance occurs at a frequency higher than 800 Hz. MISO MOSI 1µF GYROSCOPE DVDD DVSS PCB SCLK CS GND 100nF MOUNTING POINTS 09155-025 GND CRPS5VD RSVVXD 470µH Figure 24. Incorrectly Placed Gyroscope APPLICATION CIRCUITS GND Figure 25 and Figure 26 show the recommended application circuits for the ADXRS453 gyroscope. These application circuits >24V BDRIEOADKEDOWN 09155-027 provide a connection reference for the available package types. Figure 26. Recommended Application Circuit, LCC_V Package Note that DV , AV , and P are all individually connected to DD DD DD ground through 1 μF capacitors; do not connect these supplies together. In addition, an external diode and inductor must be connected for proper operation of the internal shunt regulator (see Table 7). These components allow the internal resonator drive voltage to reach its required level. Table 7. Components for ADXRS453 Application Circuits Component Qty Description Inductor 1 470 μH Diode 1 >24 V breakdown voltage Capacitor 3 1 μF Capacitor 1 100 nF Rev. B | Page 12 of 32

Data Sheet ADXRS453 ADXRS453 SIGNAL CHAIN TIMING The transfer function for the rate data LPF is given as The ADXRS453 primary signal chain is shown in Figure 27. The 1Z642 signal chain is the series of necessary functional circuit blocks   through which the rate data is generated and processed. This 1Z1  sequence of electromechanical elements determines how quickly where: the device can translate an external rate input stimulus to an SPI 1 1 T   word that is sent to the master device. f 16kHz(typ) 0 The group delay, which is a function of the filter characteristic, (f is the resonant frequency of the ADXRS453.) 0 is the time required for the output of the low-pass filter to be The transfer function for the continuous self-test LPF is given as within 10% of the external rate input. In Figure 27, the group delay is shown to be ~4 ms. Additional delay can be observed 1 due to the timing of SPI transactions and the population of the 6463Z1 rate data into the internal device registers. Figure 27 illustrates where: this delay through each element of the signal chain. 16 T   1ms(typ) f 0 (f is the resonant frequency of the ADXRS453.) 0 PRIMARY SIGNAL CHAIN 4ms GROUP DELAY <2.2ms ARITHMETIC DELAY <5µs <5µs <5µs LOGIC UNIT Y DELAY DELAY DELAY OR M E M MISO RATE DATA S/ SPI BAFNILDT-PEARSS 12-BIT ADC DEMOD LPF TER TRANSACTION MOSI S GI E CONTINUOUS R Z-AXIS ANGULAR SELF-TEST RATE SENSOR LPF GRO<U6P4 mDEsLAY 09155-028 Figure 27. Primary Signal Chain and Associated Delays Rev. B | Page 13 of 32

ADXRS453 Data Sheet SPI COMMUNICATION PROTOCOL COMMAND/RESPONSE The device response to the initial command is 0x00000001. This response prevents the transmission of random data to the Input/output is handled through a 32-bit command/response master device upon the initial command/response exchange. SPI interface. With the command/response SPI interface, the The SPI interface uses the ADXRS453 pins described in Table 8. response to a command is issued during the next sequential SPI exchange (see Figure 28). Table 8. SPI Signals The format for the interface is defined as follows: Signal Pin Description Clock Phase = Clock Polarity = 0 Serial Clock SCLK Exactly 32 clock cycles during CS active Chip Select CS Active low chip select pin Table 9 shows the commands that can be sent from the master Master Out/ MOSI Input for data sent to the gyroscope device to the gyroscope. Table 10 shows the responses to these Slave In (slave) from the main controller (master) commands from the gyroscope. For descriptions of the bits in Master In/ MISO Output for data sent to the main controller the commands and responses, see the Command/Response Bit Slave Out (master) from the gyroscope (slave) Definitions section and the Fault Register Bit Definitions section. CS 32 CLOCK 32 CLOCK CYCLES CYCLES SCLK MOSI COMMAND N COMMAND N + 1 MISO RESPONSE N – 1 RESPONSE N 09155-029 Figure 28. SPI Protocol Table 9. SPI Commands Bit Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sensor SQ1 SQ0 1 SQ2 CHK P Data Read 1 0 0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 P Write 0 1 0 SM2 SM1 SM0 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 D14D13 D12D11D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P Table 10. SPI Responses Bit Command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sensor SQ2 SQ1 SQ0 P0 ST1 ST0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PLL Q NVM POR PWR CST CHK P1 Data Read 0 1 0 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12D11D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P1 Write 0 0 1 P0 1 1 1 0 SM2 SM1 SM0 D15 D14 D13 D12D11D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P1 R/W Error 0 0 0 P0 1 1 1 0 SM2 SM1 SM0 0 0 SPI RE DU PLL Q NVM POR PWR CST CHK P1 Rev. B | Page 14 of 32

Data Sheet ADXRS453 DEVICE DATA LATCHING Note that the transmitted data is only as recent as the sequential transmission delay implemented by the system. Conditions that To allow for rapid acquisition of data from the ADXRS453, result in a sequential transfer delay of several seconds cause the device data latching is implemented, as shown in Figure 29. next sequential device response to contain data that is several When the chip select pin is asserted (CS goes low), the data seconds old. in the device is latched into memory. When the full MOSI command is received and the chip select pin is deasserted (CS goes high), the data is shifted into the SPI port registers in preparation for the next sequential command/response exchange. Device data latching allows for an extremely fast sequential transfer delay of 0.1 μs (see Table 11). DEVICE DATA IS LATCHED AFTER THE ASSERTION OF CS. LATCHED DATA IS TRANSMITTED DURING THE NEXT SEQUENTIAL COMMAND/RESPONSE EXCHANGE. CS 32 CLOCK 32 CLOCK 32 CLOCK SCLK CYCLES CYCLES CYCLES MOSI COMMAND N COMMAND N + 1 COMMAND N + 2 0x… 0x… 0x… MISO RE0SxP0O0N00S0E0 0N1 – 1 RESP0Ox…NSE N RESPO0Nx…SE N + 1 09155-031 Figure 29. Device Data Latching Rev. B | Page 15 of 32

ADXRS453 Data Sheet SPI TIMING CHARACTERISTICS  Parameters are valid for 3.0 V ≤ DVDD ≤ 5.5 V. The following conditions apply to the SPI command/response  Capacitive load for all signals is assumed to be ≤80 pF. timing characteristics in Table 11:  Ambient temperature is −40°C ≤ TA ≤ +105°C.  The MISO pull-up is 47 kΩ or 110 μA.  All timing parameter are guaranteed through characterization.  All timing is shown with respect to 10% DVDD and 90% of the actual delivered voltage waveform. Table 11. SPI Command/Response Timing Characteristics Symbol Min Max Unit Description f 8.08 MHz SPI operating frequency OP t 1/2 × t − 13 ns SCLK high time SCLKH SCLK t 1/2 × t − 13 ns SCLK low time SCLKL SCLK t 123.7 ns SCLK period SCLK t 5.5 13 ns SCLK fall time F t 5.5 13 ns SCLK rise time R t 37 ns Data input (MOSI) setup time SU t 49 ns Data input (MOSI) hold time HIGH t 20 ns Data output (MISO) access time A t 40 ns Data output (MISO) valid after SCLK V t 0 ns Data output (MISO) lag time LAG_MISO t 40 ns Data output (MISO) disable time DIS t 1/2 × t ns Enable (CS) lead time LEAD SCLK t 1/2 × t ns Enable (CS) lag time LAG_CS SCLK t 0.1 μs Sequential transfer delay TD CS t TD t SCLK t R tLEAD tSCLKH tSCLKL tF tLAG_CS SCLK t t LAG_MISO A tV tDIS MISO MSB LSB t HIGH t SU MOSI MSB LSB 09155-030 Figure 30. SPI Timings Rev. B | Page 16 of 32

Data Sheet ADXRS453 COMMAND/RESPONSE BIT DEFINITIONS SPI Bit The SPI bit is set when either of the following occurs: Table 12. SPI Interface Bit Definitions Bits Description  Too many or not enough bits were transmitted. SQ2 to SQ0 Sequence bits (from master)  A message from the control module contains a parity error. SM2 to SM0 Sensor module bits (from master) A SPI error causes the device to issue a R/W error response A8 to A0 Register address regardless of the SPI command type issued by the master D15 to D0 Data device (see Table 10). In addition, any error during a sensor P Command odd parity data request results in the device issuing a read/write error. SPI SPI command/response RE Bit RE Request error DU Data unavailable The request error (RE) bit is the communication error bit trans- ST1, ST0 Status bits mitted from the ADXRS453 device to the control module. Request P0 Response, odd parity, Bits[31:16] errors can occur when P1 Response, odd parity, Bits[31:0]  An invalid command is sent from the control module.  A read/write command specifies an invalid memory SQ2 to SQ0 Bits register. The SQ2 to SQ0 bits provide the system with a means of synchro-  A write command attempted to write to a nonwritable nizing the data samples that are received from multiple sensors. memory register. To facilitate correct synchronization, the ADXRS453 gyroscope DU Bit includes the SQ[2:0] bits in the response sequence as they were received in the request. After the chip select pin is deasserted (CS goes high), the user SM2 to SM0 Bits must wait 0.1 μs before reasserting the CS pin to initiate another command/response frame with the device. Failure to adhere to The SM2 to SM0 bits are the sensor module bits from the master this timing specification may result in a data unavailable (DU) device. These bits are not implemented in the ADXRS453 and error. are hard-coded to 000 for all occurrences. ST1 and ST0 Bits A8 to A0 Bits The status bits (ST1 and ST0) are used to signal to the master The A8 to A0 bits represent the memory address for data read or device the type of data contained in the response message (see data write. These bits should be supplied by the master when the Table 13). memory registers are being accessed; these bits are ignored for all sensor data requests. For a complete description of the available Table 13. Status Bit Code Definitions memory registers, see the Memory Register Definitions section. ST[1:0] Contents of Bits[D15:D0] D15 to D0 Bits 00 Invalid data for sensor data response The D15 to D0 bits are the 16-bit device data, which can 01 Valid sensor data contain any of the following: 10 Sensor self-test data 11 Read/write response  Data from the master to be written to a memory register, as specified by the A8 to A0 bits. Either of the following conditions can result in the ST[1:0] bits  Sensor rate output data from the slave. being set to 00 during a sensor data response:  Device data from the slave read from the memory register  The self-test response is sufficiently different from its specified by the A8 to A0 bits, as well as the data from the nominal value (see the Specifications section for the next sequential register. appropriate limits).  Following a write command, the 16-bit data that is written  The PLL fault bit is active (see the PLL Bit section). to the specified memory register in the ADXRS453 and is P0 Bit reflected back to the master device for correlation. P0 is the parity bit that establishes odd parity for Bits[31:16] P Bit of the device response. A parity bit (P) is required for all master-to-slave data transmis- P1 Bit sions. The communication protocol requires one parity bit to P1 is the parity bit that establishes odd parity for the entire achieve odd parity for the entire 32-bit command. “Don’t care” 32-bit device response. bits are also factored into the parity calculation. Rev. B | Page 17 of 32

ADXRS453 Data Sheet FAULT REGISTER BIT DEFINITIONS UV Bit Table 14 describes the bits available for signaling faults to The UV fault bit is asserted if the internally regulated voltage the user. The individual bits of the fault registers are updated (nominally 3 V) is observed to be less than 2.77 V. This mea- asynchronously, depending on their respective detection criteria; surement is low-pass filtered to prevent artifacts such as noise however, it is recommended that the fault registers be read at a spikes from asserting a fault condition. When a UV fault occurs, rate of at least 250 Hz. When asserted, an individual status bit the PWR fault bit is asserted simultaneously. Because the UV is not deasserted until it is read by the master device. If the error fault bit is not transmitted as part of a sensor data response, it is persists after a fault register read, the status bit is immediately recommended that the user read back the FAULT1 and FAULT0 reasserted and remains asserted until the next sequential memory registers upon the assertion of a PWR error to determine command/response exchange. The bits in the FAULT0 register are the specific error condition. appended to every sensor data response (see Table 10). Both PLL Bit fault registers can be accessed by issuing a read command to The PLL bit indicates that the device has experienced a failure Address 0x0A. in the phase-locked loop functional circuit block. This occurs Table 14. Fault Register Bit Definitions when the PLL fails to achieve synchronization with the resonator Register Bit Name Description structure. If the PLL status flag is active, the ST[1:0] bits of the sensor data response are set to 00, indicating that the response FAULT1 Fail Failure that sets the ST[1:0] bits to 00 contains potentially invalid rate data. AMP Amplitude detection failure OV Regulator overvoltage Q Bit UV Regulator undervoltage A Q fault is asserted based on two independent quadrature FAULT0 PLL Phase-locked loop failure calculations. Q Quadrature error  The quad memory register (Address 0x08) contains a value NVM Nonvolatile memory fault corresponding to the total instantaneous quadrature present POR Power-on or reset failed to initialize in the device. If this value exceeds 4096 LSB, a Q fault is PWR Power regulation failed due to over- voltage or undervoltage condition issued. CST Continuous self-test failure or amplitude  An internal quadrature accumulator records the amount detection failed of quadrature correction performed by the ADXRS453. A CHK Check: generate faults Q fault is issued when the quadrature error present in the Fail Bit device has contributed to an equivalent of 4°/sec (typical) of rate offset. The fail flag is asserted when the ST[1:0] bits are set to 00 (see the ST1 and ST0 Bits section). Assertion of the fail bit indicates NVM Bit that the device has experienced a gross failure and that the sensor An NVM error is transmitted to the control module when the data could be invalid. internal nonvolatile memory data fails a checksum calculation. AMP Bit This check is performed once every 50 μs and does not include the PIDx memory registers. The AMP fault bit is asserted when the measured amplitude of the silicon resonator has been significantly reduced. This POR Bit condition can occur if the voltage supplied to CP5 falls below An internal check is performed on device startup to ensure that the requirements of the internal voltage regulator. This fault bit the volatile memory of the device is functional. This is accom- is OR’ed with the CST fault bit; therefore, during a sensor data plished by programming a known value from the device ROM request, the CST bit position represents either an AMP failure into a volatile memory register. This value is then continuously or a CST failure. The full fault register can be read from memory compared to the known value in ROM every 1 μs for the duration to determine the specific failure. of the device operation. If the value stored in the volatile memory OV Bit changes or does not match the value stored in ROM, the POR error flag is asserted. The value stored in ROM is rewritten to The OV fault bit is asserted if the internally regulated voltage the volatile memory upon a device power cycle. (nominally 3 V) is observed to exceed 3.3 V. This measurement is low-pass filtered to prevent artifacts such as noise spikes from asserting a fault condition. When an OV fault occurs, the PWR fault bit is asserted simultaneously. Because the OV fault bit is not transmitted as part of a sensor data response, it is recommended that the user read back the FAULT1 and FAULT0 memory registers upon the assertion of a PWR error to determine the specific error condition. Rev. B | Page 18 of 32

Data Sheet ADXRS453 PWR Bit CHK Bit The device performs a continuous check of the internal 3 V The CHK bit is transmitted by the control module to the regulated voltage level. If either an overvoltage (OV) or under- ADXRS453 as a method of generating faults. By asserting the voltage (UV) fault is asserted, the PWR bit is also asserted. This CHK bit, the device creates conditions that result in the gener- condition occurs if the regulated voltage is observed to be either ation of all faults represented in the fault registers. For example, above 3.3 V or below 2.77 V. An internal low-pass filter removes the self-test amplitude is deliberately altered to exceed the fault high frequency glitching effects to prevent the PWR bit from detection threshold, resulting in a self-test error. In this way, the being asserted unnecessarily. To determine whether the fault is device is capable of checking both its ability to detect a fault a result of an overvoltage or undervoltage condition, the OV condition and its ability to report that fault condition to the and UV fault bits must be read. control module. CST Bit The fault conditions are initiated nearly simultaneously; how- ever, the timing for receiving fault codes when the CHK bit is The ADXRS453 is designed with continuous self-test function- asserted depends on the time required to generate each unique ality. The measured self-test amplitudes are compared to the fault. It takes no more than 50 ms for all internal faults to be limits presented in Table 1. Deviations from these values result generated and the fault register to be updated to reflect the in reported self-test errors. The two thresholds for a self-test condition of the device. Until the CHK bit is cleared, the status failure are as follows: bits (ST[1:0]) are set to 10, indicating that the data should be  Self-test value > ±512 LSB from nominal results in the interpreted by the control module as self-test data. After the assertion of the self-test flag in the fault register. CHK bit is deasserted, an additional 50 ms are required for the  Self-test value > ±1856 LSB from nominal results in the fault conditions to decay and for the device to return to normal assertion of the self-test flag in the fault register and the operation. See the Recommended Start-Up Sequence with CHK setting of the ST[1:0] bits to 00, indicating that the rate Bit Assertion section for the proper methodology for asserting data contained in the sensor data response is potentially the CHK bit. invalid. Rev. B | Page 19 of 32

ADXRS453 Data Sheet RECOMMENDED START-UP SEQUENCE WITH CHK in the next sequential command/response exchange. This results BIT ASSERTION in an apparent one-transaction delay before the data resulting from the assertion of the CHK bit is reported by the device. For Figure 31 illustrates a recommended start-up sequence that can all other read/write interactions with the device, no such delay be implemented by the user. Alternate start-up sequences can exists, and the MOSI command is serviced during the next be used, but the response from the ADXRS453 must be handled sequential command/response exchange. correctly. If the start-up sequence is implemented immediately after power is applied to the device, the total time to implement Note that if the CHK bit is deasserted and the user tries to obtain the following fault detection routine is approximately 200 ms. data from the device before the CST fault flag clears, the device reports the data as error data. As described in the Device Data Latching section, the data present in the device upon the assertion of the CS signal is used MOSI: SENSOR DATA REQUEST MOSI: SENSOR DATA MOSI: SENSOR DATA MOSI: SENSOR DATA CHK BIT ASSERTED REQUEST (THIS CLEARS REQUEST REQUEST THE CHK BIT) MISO: STANDARD INITIAL MISO: CHK RESPONSE MISO: CHK RESPONSE RESPONSE MISO: SENSOR DATA ST[1:0] = 10 ST[1:0] = 10 RESPONSE DATA LATCH POINT CS X X X 32 CLOCK 32 CLOCK 32 CLOCK 32 CLOCK SCLK CYCLES CYCLES CYCLES CYCLES MOSI 0x20000003 0x20000000 0x20000000 0x20000000 MISO 0x00000001 0x… (PA0xR…ITFYF D OERP E0xN…DEFNET) (PA0xR…ITFYF D OERP E0xN…DEFNET) t = 100ms t = 150ms t = 200ms t = 200ms +tTD t = 200ms + 2tTD POWER IS WHEN THE 100ms START-UP A 50ms DELAY IS REQUIRED ANOTHER 50ms DELAY MUST THE FAULT BITS OF THE ALL FAULT APPLIED TO TIME HAS ELAPSED, THE SO THAT THE GENERATION BE OBSERVED TO ALLOW ADXRS453 REMAIN ACTIVE CONDITIONS ARE THE DEVICE. MASTER DEVICE IS FREE TO OF FAULTS WITHIN THE THE FAULT CONDITIONS TO UNTIL CLEARED. DUE TO CLEARED, AND ALL WAIT 100ms TO ASSERT THE CHK BIT AND DEVICE IS ALLOWED TO CLEAR. IF THE DEVICE IS THE REQUIRED DECAY SUBSEQUENT DATA ALLOW FOR START THE PROCESS OF COMPLETE. HOWEVER, FUNCTIONING PROPERLY, PERIOD FOR EACH FAULT EXCHANGES NEED THE INTERNAL INTERNAL ERROR BECAUSE THE DEVICE DATA THE MISO RESPONSE CONDITION, FAULT ONLY OBSERVE CIRCUITRY TO CHECKING. DURING THE IS LATCHED BEFORE THE CONTAINS ALL ACTIVE CONDITIONS REMAIN THE SEQUENTIAL BE INITIALIZED. FIRST COMMAND/ CHK BIT IS ASSERTED, THE FAULTS, AS WELL AS HAVING PRESENT UPON THE TRANSFER DELAY RESPONSE EXCHANGE DEVICE RESPONSE DURING SET THE MESSAGE FORMAT IMMEDIATE DEASSERTION TIMING AFTER POWER-ON, THE THIS COMMAND/RESPONSE TO SELF-TEST DATA. THIS IS OF THE CHK BIT. THIS PARAMETER. ADXRS453 IS DESIGNED EXCHANGE DOES NOT INDICATED THROUGH THE ST RESULTS IN A SECOND TO ISSUE A PREDEFINED CONTAIN FAULT BITS BEING SET TO 10. SEQUENTIAL RESPONSE IN RESPONSE. INFORMATION. THIS WHICH THE FAULT BITS ARE RESPONSE CAN BE ASSERTED. AGAIN, THE DISCARDED. RESPONSE IS FORMATTED AS SELF-TEST DATA IBINNIDTTSEIC NHATATIOVINENG AB LTELHEYAN.T S TEHTE FAULT 09155-032 Figure 31. Recommended Start-Up Sequence Rev. B | Page 20 of 32

Data Sheet ADXRS453 RATE DATA FORMAT The data is formatted as a twos complement number with a scale The ADXRS453 gyroscope transmits rate data in a 16-bit format factor of 80 LSB/°/sec. Therefore, the highest obtainable value as part of a 32-bit SPI data frame. See Table 10 for the full 32-bit for positive (clockwise) rotation is 0x7FFF (decimal +32,767), format of the sensor data response. The rate data is transmitted and the highest obtainable value for negative (counterclockwise) MSB first, from D15 to D0. rotation is 0x8000 (decimal −32,768). Performance of the device is not guaranteed above ±24,000 LSB (±300°/sec). Table 15. Rate Data 16-Bit Rate Data Decimal (LSBs) Hex (D15:D0) Description +32,767 0x7FFF Maximum possible positive data value (not guaranteed) … … … +24,000 0x5DC0 +300°/sec rotation (positive FSR) … … … +160 0x00A0 +2°/sec rotation … … … +80 0x0050 +1°/sec rotation … … … +40 0x0028 +0.5°/sec rotation … … … +20 0x0014 +0.025°/sec rotation … … … 0 0x0000 Zero rotation value … … … −20 0xFFEC −0.025°/sec rotation … … … −40 0xFFD8 −0.5°/sec rotation … … … −80 0xFFB0 −1°/sec rotation … … … −160 0xFF60 −2°/sec rotation … … … −24,000 0xA240 −300°/sec rotation (negative FSR) … … … −32,768 0x8000 Maximum possible negative data value (not guaranteed) Rev. B | Page 21 of 32

ADXRS453 Data Sheet MEMORY MAP AND REGISTERS MEMORY MAP Data is transmitted MSB first. For proper acquisition of data from the memory register, make the read request to the even-numbered Table 16 provides a list of the memory registers that can be register address only; for example, to read the LOCSTx registers, read from or written to by the user. See the SPI Communication Address Register 0x04, but not Register 0x05. For a description of Protocol section for the proper input sequence to read from or each memory register listed in Table 16, see the Memory Register write to a specific memory register. Each memory register has Definitions section. eight bits of data; however, when a read request is performed, the data always returns as a 16-bit message. This is accomplished by appending the data from the next sequential register to the memory address that was specified. Table 16. Memory Register Map Address Register Name D7 (MSB) D6 D5 D4 D3 D2 D1 D0 (LSB) 0x00 RATE1 RTE15 RTE14 RTE13 RTE12 RTE11 RTE10 RTE9 RTE8 0x01 RATE0 RTE7 RTE6 RTE5 RTE4 RTE3 RTE2 RTE1 RTE0 0x02 TEM1 TEM9 TEM8 TEM7 TEM6 TEM5 TEM4 TEM3 TEM2 0x03 TEM0 TEM1 TEM0 Unused Unused Unused Unused Unused Unused 0x04 LOCST1 LCST15 LCST14 LCST13 LCST12 LCST11 LCST10 LCST9 LCST8 0x05 LOCST0 LCST7 LCST6 LCST5 LCST4 LCST3 LCST2 LCST1 LCST0 0x06 HICST1 HCST15 HCST14 HCST13 HCST12 HCST11 HCST10 HCST9 HCST8 0x07 HICST0 HCST7 HCST6 HCST5 HCST4 HCST3 HCST2 HCST1 HCST0 0x08 QUAD1 QAD15 QAD14 QAD13 QAD12 QAD11 QAD10 QAD9 QAD8 0x09 QUAD0 QAD7 QAD6 QAD5 QAD4 QAD3 QAD2 QAD1 QAD0 0x0A FAULT1 Unused Unused Unused Unused Fail AMP OV UV 0x0B FAULT0 PLL Q NVM POR PWR CST CHK 0 0x0C PID1 PIDB15 PIDB14 PIDB13 PIDB12 PIDB11 PIDB10 PIDB9 PIDB8 0x0D PID0 PIDB7 PIDB6 PIDB5 PIDB4 PIDB3 PIDB2 PIDB1 PIDB0 0x0E SN3 SNB31 SNB30 SNB29 SNB28 SNB27 SNB26 SNB25 SNB24 0x0F SN2 SNB23 SNB22 SNB21 SNB20 SNB19 SNB18 SNB17 SNB16 0x10 SN1 SNB15 SNB14 SNB13 SNB12 SNB11 SNB10 SNB9 SNB8 0x11 SN0 SNB7 SNB6 SNB5 SNB4 SNB3 SNB2 SNB1 SNB0 Rev. B | Page 22 of 32

Data Sheet ADXRS453 MEMORY REGISTER DEFINITIONS Low CST (LOCSTx) Registers The SPI-accessible memory registers are described in this section. Addresses: 0x04 (LOCST1) As noted in the Memory Map section, when requesting data 0x05 (LOCST0) from a memory register, only the first sequential memory address Register update rate: f/16 (~970 Hz) should be addressed. The data returned by the device contains 16 0 bits of memory register information. Bits[15:8] contain the MSB Scale factor: 80 LSB/°/sec of the requested information, and Bits[7:0] contain the LSB. The LOCSTx registers contain the value of the temperature compensated and low-pass filtered continuous self-test delta. Rate (RATEx) Registers This value is a measure of the difference between the positive Addresses: 0x00 (RATE1) and negative self-test deflections and corresponds to the values 0x01 (RATE0) presented in Table 1. The device issues a CST error if the value of the self-test exceeds the established self-test limits. The self-test Register update rate: f/32 (~485 Hz) 0 data is filtered to f/8000 (~1.95 Hz) to prevent false triggering 0 Scale factor: 80 LSB/°/sec of the CST fault bit. The data is presented as a 16-bit, twos com- The RATEx registers contain the temperature compensated rate plement number, with a scale factor of 80 LSB/°/sec. output of the device, filtered to f0/200 (~77.5 Hz). This data can MSB LSB also be accessed by issuing a sensor data read request to the device. D15 D14 D13 D12 D11 D10 D9 D8 The data is presented as a 16-bit, twos complement number. LCST15 LCST14 LCST13 LCST12 LCST11 LCST10 LCST9 LCST8 MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 LCST7 LCST6 LCST5 LCST4 LCST3 LCST2 LCST1 LCST0 RTE15 RTE14 RTE13 RTE12 RTE11 RTE10 RTE9 RTE8 High CST (HICSTx) Registers D7 D6 D5 D4 D3 D2 D1 D0 RTE7 RTE6 RTE5 RTE4 RTE3 RTE2 RTE1 RTE0 Addresses: 0x06 (HICST1) 0x07 (HICST0) Temperature (TEMx) Registers Register update rate: f/16 (~970 Hz) Addresses: 0x02 (TEM1) 0 Scale factor: 80 LSB/°/sec 0x03 (TEM0) The HICSTx registers contain the unfiltered self-test information. Register update rate: f/32 (~485 Hz) 0 The HICSTx data can be used to supplement fault diagnosis in Scale factor: 5 LSB/°C safety critical applications because sudden shifts in the self-test The TEMx registers contain a value corresponding to the response can be detected. However, the CST bit of the fault temperature of the device. The data is presented as a 10-bit, register is not set when the HICSTx data is observed to exceed twos complement number. 0 LSB corresponds to a temperature the self-test limits. Only the LOCSTx memory registers, which of approximately 45°C (see Table 17). are designed to filter noise and the effects of sudden temporary self-test spiking due to external disturbances, control the asser- MSB LSB tion of the CST fault bit. The data is presented as a 16-bit, twos D15 D14 D13 D12 D11 D10 D9 D8 complement number. TEM9 TEM8 TEM7 TEM6 TEM5 TEM4 TEM3 TEM2 D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB TEM1 TEM0 Unused D15 D14 D13 D12 D11 D10 D9 D8 HCST15 HCST14 HCST13 HCST12 HCST11 HCST10 HCST9 HCST8 D7 D6 D5 D4 D3 D2 D1 D0 Table 17. Sample Temperatures and TEMx Register Contents HCST7 HCST6 HCST5 HCST4 HCST3 HCST2 HCST1 HCST0 Temperature Value of TEM1 and TEM0 Registers1 45°C 0000 0000 00XX XXXX 85°C 0011 0010 00XX XXXX 0°C 1100 0111 11XX XXXX 1 X = don’t care. Rev. B | Page 23 of 32

ADXRS453 Data Sheet Quad Memory (QUADx) Registers Part ID (PIDx) Registers Addresses: 0x08 (QUAD1) Addresses: 0x0C (PID1) 0x09 (QUAD0) 0x0D (PID0) Register update rate: f/64 (~240 Hz) Register update rate: Not applicable 0 Scale factor: 80 LSB/°/sec equivalent Scale factor: Not applicable The QUADx registers contain a value corresponding to the amount The (PIDx) registers contain a 16-bit number that identifies the of quadrature error present in the device at a given time. Quadra- version of the ADXRS453. Combined with the serial number, this ture can be likened to a measurement of the error of the motion information allows for a higher degree of device individualization of the resonator structure and can be caused by stresses and aging and tracking. The initial product ID is R01 (0x5201), with sub- effects. The quadrature data is filtered to f/200 (~77.5 Hz) and can sequent versions of silicon incrementing this value to R02, R03, 0 be read frequently to detect sudden shifts in the level of quadrature. and so on. The data is presented as a 16-bit, twos complement number. MSB LSB MSB LSB D15 D14 D13 D12 D11 D10 D9 D8 D15 D14 D13 D12 D11 D10 D9 D8 PIDB15 PIDB14 PIDB13 PIDB12 PIDB11 PIDB10 PIDB9 PIDB8 QAD15 QAD14 QAD13 QAD12 QAD11 QAD10 QAD9 QAD8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 PIDB7 PIDB6 PIDB5 PIDB4 PIDB3 PIDB2 PIDB1 PIDB0 QAD7 QAD6 QAD5 QAD4 QAD3 QAD2 QAD1 QAD0 Serial Number (SNx) Registers Fault (FAULTx) Registers Addresses: 0x0E (SN3) Addresses: 0x0A (FAULT1) 0x0F (SN2) 0x0B (FAULT0) 0x10 (SN1) Register update rate: Not applicable 0x11 (SN0) Scale factor: Not applicable Register update rate: Not applicable The FAULTx registers contain the state of the error flags in the Scale factor: Not applicable device. The FAULT0 register is appended to the end of every The SNx registers contain a 32-bit identification number that device data transmission (see Table 10); however, this register uniquely identifies the device. To read the entire serial number, can also be accessed independently through its memory location. two memory read requests must be initiated. The first read The individual fault bits are updated asynchronously, requiring request to Address 0x0E returns the upper 16 bits of the serial <5 μs to activate, as soon as the fault condition exists on chip. When number, and the following read request to Address 0x10 returns toggled, each fault bit remains active until the fault register is read the lower 16 bits of the serial number. or a sensor data command is received. If the fault is still active after the bit is read, the fault bit is immediately reasserted. MSB LSB D31 D30 D29 D28 D27 D26 D25 D24 MSB LSB SNB31 SNB30 SNB29 SNB28 SNB27 SNB26 SNB25 SNB24 D15 D14 D13 D12 D11 D10 D9 D8 D23 D22 D21 D20 D19 D18 D17 D16 Unused Fail AMP OV UV SNB23 SNB22 SNB21 SNB20 SNB19 SNB18 SNB17 SNB16 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 PLL Q NVM POR PWR CST CHK 0 SNB15 SNB14 SNB13 SNB12 SNB11 SNB10 SNB9 SNB8 D7 D6 D5 D4 D3 D2 D1 D0 SNB7 SNB6 SNB5 SNB4 SNB3 SNB2 SNB1 SNB0 Rev. B | Page 24 of 32

Data Sheet ADXRS453 PACKAGE ORIENTATION AND LAYOUT INFORMATION ADXRS453 (PACKAGE FRONT) 14 8 1 7 NOTES 1.THE PACKAGE HAS TERMINALS ON TWO FACES. HOWEVER, THE TERMINALS ON THE BACK ARE FOR INTERNAL EVALUATION ONLY AND SHOULD NOT BE USED IN THE END APPLICATION. THE TERMINALS ON THE BOTTOM OF THE PACKAGE INCORPORATE METALLIZATION BUMPS THAT ENSURE A MINIMUM SOLDER THICKNESS FOR IMPROVED SOLDER JOINT RELIABILITY. THESE BUMPS ARE NOT PRESENT ON THE BACK TERMINALS ATPEANRCDMK, TAINHGAEELR,S ES FAEORER EFE IUG, SPUEORDOE I RN3 8 ST.OHLED EENRD J AOPINPTL IRCEALTIIAOBNI.L FITOYR C TAHNE BOEU ETNLICNOEU DNITMEERNESDIO IFN ST HOEF BTAHCISK 09155-033 Figure 32. 14-Lead Ceramic LCC_V, Vertical Mount 0.55 0.55 0.55 11.232 0.95 0.95 1.55 1.55 1.27 2.55 9.462 5.55 0.572 2.55 1.691 09155-034 1.5 1 0.8 0.8 1 1.5 09155-035 Figure 33. Sample SOIC_CAV Solder Pad Layout (Land Pattern), Figure 34. Sample LCC_V Solder Pad Layout (Land Pattern), Dimensions Dimensions Shown in Millimeters, Not to Scale Shown in Millimeters, Not to Scale Rev. B | Page 25 of 32

ADXRS453 Data Sheet SOLDER PROFILE SUPPLIER TP ≥ TC USER TP ≤ TC TC TC – 5°C SUPPLIERtP USERtP TP TC – 5°C MAXIMUM RAMP-UP RATE = 3°C/sec tP MAXIMUM RAMP-DOWN RATE = 6°C/sec TL TSMAX PREHEAT AREA t L E R U T A ER TSMIN P M E T t S 25 TIME 25°CTO PEAK TIME 09155-037 Figure 35. Recommended Soldering Profile Table 18. Recommended Soldering Profile Limits Profile Feature Sn63/Pb37 Pb-Free Average Ramp Rate (T to T) 3°C/sec max 3°C/sec max L P Preheat Minimum Temperature (T ) 100°C 150°C SMIN Maximum Temperature (T ) 150°C 200°C SMAX Time (T to T ), t 60 sec to 120 sec 60 sec to 120 sec SMIN SMAX S Ramp-Up Rate (T to T) 3°C/sec max 3°C/sec max SMAX L Time Maintained Above Liquidous (t) 60 sec to 150 sec 60 sec to 150 sec L Liquidous Temperature (T) 183°C 217°C L Classification Temperature (T )1 220°C 250°C C Peak Temperature (T) T + 0°C/−5°C T + 0°C/−5°C P C C Time Within 5°C of Actual Peak Temperature (t) 10 sec to 30 sec 20 sec to 40 sec P Ramp-Down Rate (T to T) 6°C/sec max 6°C/sec max P L Time 25°C to Peak Temperature 6 minutes max 8 minutes max 1 Based on IPC/JEDEC J-STD-020D.01 for SnPb and Pb-free processes. Package volume < 350 mm3, package thickness > 2.5 mm. Rev. B | Page 26 of 32

Data Sheet ADXRS453 PACKAGE MARKING CODES XRS453 XRS453 BEYZ n BRGZ n #YYWW #YYWW LLLLLLLLL LLLLLLLLL 09155-038 Figure 36. LCC_V and SOIC_CAV Package Marking Codes Table 19. Package Code Designations Marking Meaning XRS Angular rate sensor 453 Series number B Temperature grade (−40°C to +105°C) RG Package designator (SOIC_CAV package) EY Package designator (LCC_V package) Z RoHS compliant n Revision number # Pb-free designation YYWW Assembly date code LLLLLLLLL Assembly lot code (up to nine characters) Rev. B | Page 27 of 32

ADXRS453 Data Sheet OUTLINE DIMENSIONS 10.30BSC 16 9 10.42 DETAILA BSC 7.80 BSC 1 0.25GAGE 8 PLANE PIN1 INDICATOR 1.27BSC 8° 4° 0.87 9.59BSC 0° 0.77 3.73 0.67 3.58 1.50 3.43 1.35 1.20 0.28 0.18 0.58 COPL0A.1N00.A0R8ITY 000...544050 000...776505 00..4388 DETAILA 072409-B Figure 37. 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV] (RG-16-1) Dimensions shown in millimeters FRONTVIEW 9.20 9.00SQ 4.40 8.80 8.08 4.00 8.00 0.350 3.60 0R.2E7F5 7.92 0.305 BACKVIEW 0.260 7.70 7.18 7.55 7.10 7.40 7.02 0.50 1 2 3 4 5 6 7 TYP 1R.1E7F5 SIDEVIEW R0.20 8 9 10 11 12 13 14 CR0.E3F0 (PINS12.,060) (PIN1.S610,7) 00..657050NMOINM RE(FPINS12.,560) TOEFRPMAICNKAALGSEOANRBEAFCOKRSIDE 0.60 1.00 EVALUATIONTESTINGONLY. (PINS3-5) (PINS9-10, 0.30 12-13) 0.80 0.30 REF (PINS10, REF 0.35 11,12) 1.70 REF REF (ALLPINS) 1 2 3 4 5 6 7 0.35 1.70 14 13 12 11 10 9 8 REF REF (ALLPINS) 0.80REF 1.40 (METALLIZATIONBUMP (PINS1, 0.80 BUMPHEIGHT0.03NOM) 7,8,14) (PINS2,6, 9,13) 0.40 BOT(TPOINMS3V-I5E,W10-(1P2A)DSSIDE) 04-08-2010-A Figure 38. 14-Terminal Ceramic Leadless Chip Carrier, Vertical Form [LCC_V] (EY-14-1) Dimensions shown in millimeters Rev. B | Page 28 of 32

Data Sheet ADXRS453 ORDERING GUIDE Temperature Package Model1 Range Package Description Option ADXRS453BEYZ −40°C to +105°C 14-Terminal Ceramic Leadless Chip Carrier, Vertical Form [LCC_V] EY-14-1 ADXRS453BEYZ-RL −40°C to +105°C 14-Terminal Ceramic Leadless Chip Carrier, Vertical Form [LCC_V] EY-14-1 ADXRS453BRGZ −40°C to +105°C 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV] RG-16-1 ADXRS453BRGZ-RL −40°C to +105°C 16-Lead Small Outline, Plastic Cavity Package [SOIC_CAV] RG-16-1 EVAL-ADXRS453Z Evaluation Board, SOIC_CAV EVAL-ADXRS453Z-V Evaluation Board, LCC_V EVAL-ADXRS453Z-M Analog Devices Inertial Sensor Evaluation System (Includes ADXRS453 Satellite) EVAL-ADXRS453Z-S ADXRS453 Satellite, Standalone, to be used with Inertial Sensor Evaluation System 1 Z = RoHS Compliant Part. Rev. B | Page 29 of 32

ADXRS453 Data Sheet NOTES Rev. B | Page 30 of 32

Data Sheet ADXRS453 NOTES Rev. B | Page 31 of 32

ADXRS453 Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09155-0-12/11(B) Rev. B | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-ADXRS453Z-M EVAL-ADXRS453Z ADXRS453BRGZ EVAL-ADXRS453Z-S EVAL-ADXRS453Z-V ADXRS453BEYZ ADXRS453BRGZ-RL ADXRS453BEYZ-RL