1200 MHz to 2400 MHz Quadrature Modulator with 1550 MHz to 2150 MHz Frac-N PLL and Integrated VCO Data Sheet ADRF6702 FEATURES The integrated fractional-N PLL/synthesizer generates a 2× f LO input to the IQ modulator. The phase detector together with an IQ modulator with integrated fractional-N PLL external loop filter is used to control the VCO output. The VCO Output frequency range: 1200 MHz to 2400 MHz output is applied to a quadrature divider. To reduce spurious Internal LO frequency range: 1550 MHz to 2150 MHz components, a sigma-delta (Σ-Δ) modulator controls the Output P1dB: 13.1 dBm @ 2140 MHz programmable PLL divider. Output IP3: 29.1 dBm @ 2140 MHz Noise floor: −159.6 dBm/Hz @ 1960 MHz The IQ modulator has wideband differential I and Q inputs, Baseband bandwidth: 750 MHz (3 dB) which support baseband as well as complex IF architectures. SPI serial interface for PLL programming The single-ended modulator output is designed to drive a Integrated LDOs and LO buffer 50 Ω load impedance and can be disabled. Power supply: 5 V/240 mA The ADRF6702 is fabricated using an advanced silicon- 40-lead 6 mm × 6 mm LFCSP germanium BiCMOS process. It is available in a 40-lead, APPLICATIONS exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package. Cellular communications systems Performance is specified from −40°C to +85°C. A lead-free GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE evaluation board is available. Broadband wireless access systems Table 1. Satellite modems Part No. Internal LO Range ±3 dB RF Balun Range OUT GENERAL DESCRIPTION ADRF6701 750 MHz 400 MHz 1150 MHz 1250 MHz The ADRF6702 provides a quadrature modulator and ADRF6702 1550 MHz 1200 MHz synthesizer solution within a small 6 mm × 6 mm footprint 2150 MHz 2400 MHz while requiring minimal external components. ADRF6703 2100 MHz 1550 MHz The ADRF6702 is designed for RF outputs from 1200 MHz to 2600 MHz 2650 MHz 2400 MHz. The low phase noise VCO and high performance ADRF6704 2500 MHz 2050 MHz quadrature modulator make the ADRF6702 suitable for next 290 MHz 3000 MHz generation communication systems requiring high signal dynamic range and linearity. The integration of the IQ modulator, PLL, and VCO provides for significant board savings and reduces the BOM and design complexity. FUNCTIONAL BLOCK DIAGRAM VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 34 29 27 22 17 10 1 LOSEL 36 ADRF6702 LON 37 40 DECL3 LOP 38 BUFFER DIV÷ID2ER 9 DECL2 BUFFER 2:1 2 DECL1 DACTLAK 1132 INTESRPFIACE FRARCETGION MODULUS INTREEGGER MUX LE 14 THIRD-ORDER INFTREARCPTOIOLANTAOLR VCO 18 QP ×2 N COUNTER PRESCALER CORE ÷2 19 QN REFIN 6 21 TO 123 ÷2 0/90 32 IN ÷2 MUX – PHASE C25H0AµRAG,E PUMP 33 IP ÷4 TEMP + FREQUENCY 500µA (DEFAULT), SENSOR DETECTOR 750µA, MUXOUT 8 1000µA 4 7 11 15 20 21 23 25 28 30 31 35 24 5 3 39 16 26 N1.O NTCE S= NO CONNECT. DO NOT CONNECTTO TGHNISD PIN. NFCigure 1R. S ET CPVTUNE ENOP RFOUT 08568-001 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.

ADRF6702 Data Sheet TABLE OF CONTENTS Features..............................................................................................1 Device Programming and Register Sequencing.....................19 Applications.......................................................................................1 Register Summary..........................................................................20 General Description.........................................................................1 Register Description.......................................................................21 Functional Block Diagram..............................................................1 Register 0—Integer Divide Control (Default: 0x0001C0)....21 Revision History...............................................................................2 Register 1—Modulus Divide Control (Default: 0x003001)..22 Specifications.....................................................................................3 Register 2—Fractional Divide Control (Default: 0x001802)22 Timing Characteristics................................................................6 Register 3—Σ-Δ Modulator Dither Control (Default: Absolute Maximum Ratings............................................................7 0x10000B)....................................................................................23 ESD Caution..................................................................................7 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)...................................................24 Pin Configuration and Function Descriptions.............................8 Register 5—LO Path and Modulator Control (Default: Typical Performance Characteristics...........................................10 0x0000D5)...................................................................................26 Theory of Operation......................................................................16 Register 6—VCO Control and VCO Enable (Default: PLL + VCO..................................................................................16 0x1E2106)....................................................................................27 Basic Connections for Operation.............................................16 Register 7—External VCO Enable...........................................27 External LO.................................................................................16 Characterization Setups.................................................................28 Loop Filter...................................................................................17 Evaluation Board............................................................................30 DAC-to-IQ Modulator Interfacing..........................................18 Evaluation Board Control Software.........................................30 Adding a Swing-Limiting Resistor...........................................18 Outline Dimensions.......................................................................35 IQ Filtering..................................................................................19 Ordering Guide..........................................................................35 Baseband Bandwidth.................................................................19 REVISION HISTORY 10/11—Rev. A to Rev. B Changes Table 1................................................................................1 7/11—Rev. 0 to Rev. A Changes to Noise Floor in Features Section and Table 1............1 Changes to Specifications Section..................................................2 Changes to Figure 16, Figure 17, and Figure 18.........................12 Changes to Figure 28......................................................................14 Changes to Figure 32 and Figure 34.............................................15 Added Figure 34, Renumbered Sequentially..............................15 Changes to Figure 35......................................................................17 Added Figure 40..............................................................................19 Changes to Figure 52......................................................................31 4/11—Revision 0: Initial Version Rev. B | Page 2 of 36

Data Sheet ADRF6702 SPECIFICATIONS V = 5 V; T = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q S A frequency (f ) = 1 MHz; f = 38.4 MHz; f = 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted. BB PFD REF Table 2. Parameter Test Conditions/Comments Min Typ Max Unit OPERATING FREQUENCY RANGE IQ modulator (±3 dB RF output range) 1200 2400 MHz PLL LO range 1550 2150 MHz RF OUTPUT = 1850 MHz RFOUT pin Nominal Output Power Baseband VIQ = 1 V p-p differential 4 dBm IQ Modulator Voltage Gain RF output divided by baseband input voltage 0 dB OP1dB 13.5 dBm Carrier Feedthrough −41.2 dBm Sideband Suppression −43.7 dBc Quadrature Error ±1 Degrees I/Q Amplitude Balance 0.02 dB Second Harmonic P − P (f ± (2 × f )) −62.2 dBc OUT LO BB Third Harmonic P − P (f ± (3 × f )) −50.6 dBc OUT LO BB Output IP2 f1 = 3.5 MHz, f2 = 4.5 MHz, P ≈ −2 dBm per tone 56 dBm BB BB OUT Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P ≈ −2 dBm per tone 31 dBm BB BB OUT Noise Floor I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset −158.9 dBm/Hz RF OUTPUT = 1960 MHz RFOUT pin Nominal Output Power Baseband VIQ = 1 V p-p differential 4.1 dBm IQ Modulator Voltage Gain RF output divided by baseband input voltage 0.1 dB OP1dB 13.6 dBm Carrier Feedthrough −40.6 dBm Sideband Suppression −53.9 dBc Quadrature Error +0.7/−1.7 Degrees I/Q Amplitude Balance 0.03 dB Second Harmonic P − P (f ± (2 × f )) −74.6 dBc OUT LO BB Third Harmonic P − P (f ± (3 × f )) −54.1 dBc OUT LO BB Output IP2 f1 = 3.5 MHz, f2 = 4.5 MHz, P ≈ −2 dBm per tone 66.4 dBm BB BB OUT Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P ≈ −2 dBm per tone 30.1 dBm BB BB OUT Noise Floor I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset −159.6 dBm/Hz RF OUTPUT = 2140 MHz RFOUT pin Nominal Output Power Baseband VIQ = 1 V p-p differential 3.8 dBm IQ Modulator Voltage Gain RF output divided by baseband input voltage −0.2 dB OP1dB 13.1 dBm Carrier Feedthrough −46.8 dBm Sideband Suppression −44.4 dBc Quadrature Error ±1 Degrees I/Q Amplitude Balance 0.02 dB Second Harmonic P − P (f ± (2 × f )) −71.8 dBc OUT LO BB Third Harmonic P − P (f ± (3 × f )) −57.3 dBc OUT LO BB Output IP2 f1 = 3.5 MHz, f2 = 4.5 MHz, P ≈ −2 dBm per tone 70.4 dBm BB BB OUT Output IP3 f1 = 3.5 MHz, f2 = 4.5 MHz, P ≈ −2 dBm per tone) 29.1 dBm BB BB OUT Noise Floor I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset −158.1 dBm/Hz SYNTHESIZER SPECIFICATIONS Synthesizer specifications referenced to the modulator output Internal LO Range 1550 2150 MHz Figure of Merit (FOM)1 −220.5 dBc/Hz/Hz Rev. B | Page 3 of 36

ADRF6702 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE CHARACTERISTICS REFIN, MUXOUT pins REFIN Input Frequency 12 160 MHz REFIN Input Capacitance 4 pF Phase Detector Frequency 20 40 MHz MUXOUT Output Level Low (lock detect output selected) 0.25 V High (lock detect output selected) 2.7 V MUXOUT Duty Cycle 50 % CHARGE PUMP Charge Pump Current Programmable to 250 μA, 500 μA, 750 μA, 1000 μA 500 μA Output Compliance Range 1 2.8 V PHASE NOISE (FREQUENCY = Closed loop operation (see Figure 35 for loop filter design) 1850 MHz, f = 38.4 MHz) PFD 10 kHz offset −110.8 dBc/Hz 100 kHz offset −105.8 dBc/Hz 1 MHz offset −124.6 dBc/Hz 10 MHz offset −150 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.27 °rms Reference Spurs f /2 −112 dBc PFD f −84 dBc PFD f × 2 −87 dBc PFD f × 3 −93 dBc PFD f × 4 −90 dBc PFD PHASE NOISE (FREQUENCY = Closed loop operation (see Figure 35 for loop filter design) 1960 MHz, f = 38.4 MHz) PFD 10 kHz offset −108.5 dBc/Hz 100 kHz offset −104.2 dBc/Hz 1 MHz offset −125.1 dBc/Hz 10 MHz offset −149.9 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.25 °rms Reference Spurs f /2 −110 dBc PFD f −83 dBc PFD f × 2 −97 dBc PFD f × 3 −91 dBc PFD f × 4 −97 dBc PFD PHASE NOISE (FREQUENCY = Closed loop operation (see Figure 35 for loop filter design) 2140 MHz, f = 38.4 MHz) PFD 10 kHz offset −107.5 dBc/Hz 100 kHz offset −102.7 dBc/Hz 1 MHz offset −126.1 dBc/Hz 10 MHz offset −150.4 dBc/Hz Integrated Phase Noise 1 kHz to 10 MHz integration bandwidth 0.25 °rms Reference Spurs f /2 −111 dBc PFD f −86 dBc PFD f × 2 −88 dBc PFD f × 3 −91 dBc PFD f × 4 −99 dBc PFD RF OUTPUT HARMONICS Measured at RFOUT, frequency = 2140 MHz Second harmonic −47 dBc Third harmonic −74 dBc LO INPUT/OUTPUT LOP, LON Output Frequency Range Divide by 2 circuit in LO path enabled 1550 2150 MHz Divide by 2 circuit in LO path disabled 3100 4300 MHz LO Output Level at 1960 MHz 2× LO or 1× LO mode, into a 50 Ω load, LO buffer enabled 1 dBm LO Input Level Externally applied 2× LO, PLL disabled 0 dBm LO Input Impedance Externally applied 2× LO, PLL disabled 50 Ω Rev. B | Page 4 of 36

Data Sheet ADRF6702 Parameter Test Conditions/Comments Min Typ Max Unit BASEBAND INPUTS IP, IN, QP, QN pins I and Q Input DC Bias Level 400 500 600 mV Bandwidth P ≈ −7 dBm, RF flatness of IQ modulator output calibrated out OUT 0.5 dB 350 MHz 3 dB 750 MHz Differential Input Impedance 920 Ω Differential Input Capacitance 1 pF LOGIC INPUTS CLK, DATA, LE, ENOP, LOSEL Input High Voltage, V 1.4 3.3 V INH Input Low Voltage, V 0 0.7 V INL Input Current, I /I 0.1 μA INH INL Input Capacitance, C 5 pF IN TEMPERATURE SENSOR VPTAT voltage measured at MUXOUT Output Voltage T = 25°C, RL ≥10 kΩ (LO buffer disabled) 1.64 V A Temperature Coefficient T = −40°C to +85°C, RL ≥10 kΩ 3.9 mV/°C A POWER SUPPLIES VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 Voltage Range 4.75 5 5.25 V Supply Current Normal Tx mode (PLL and IQMOD enabled, LO buffer disabled) 240 mA Tx mode using external LO input (internal VCO/PLL disabled) 130 mA Tx mode with LO buffer enabled 290 mA Power-down mode 22 μA 1 The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) – 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz, fREF power = 10 dBm (500 V/μs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset. Rev. B | Page 5 of 36

ADRF6702 Data Sheet TIMING CHARACTERISTICS Table 3. Parameter Limit Unit Test Conditions/Comments t 20 ns min LE to CLK setup time 1 t 10 ns min DATA to CLK setup time 2 t 10 ns min DATA to CLK hold time 3 t 25 ns min CLK high duration 4 t 25 ns min CLK low duration 5 t 10 ns min CLK to LE setup time 6 t 20 ns min LE pulse width 7 t t 4 5 CLK t t 2 3 DB2 DB1 DB0(LSB) DATA DB23(MSB) DB22 (CONTROLBITC3) (CONTROLBITC2) (CONTROLBITC1) t t t 6 7 1 LE 08568-002 Figure 2. Timing Diagram Rev. B | Page 6 of 36

Data Sheet ADRF6702 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 4. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage (VCC1 to VCC7) 5.5 V other conditions above those indicated in the operational Digital I/O, CLK, DATA, LE −0.3 V to +3.6 V section of this specification is not implied. Exposure to absolute LOP, LON 18 dBm maximum rating conditions for extended periods may affect IP, IN, QP, QN −0.5 V to +1.5 V device reliability. REFIN −0.3 V to +3.6 V θ (Exposed Paddle Soldered Down)1 35°C/W JA Maximum Junction Temperature 150°C ESD CAUTION Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C 1 Per JDEC standard JESD 51-2. Rev. B | Page 7 of 36

ADRF6702 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3E L LCEDNUTVPOLNOLESOLDNG7CCVPINIDNG 0987654321 4333333333 VCC1 1 PIN 1 30GND DECL1 2 INDICATOR 29VCC6 CP 3 28GND RGSNEDT 45 ADRF6702 2267RVCFOC5UT REFIN 6 TOP VIEW 25GND GND 7 (Not to Scale) 24NC MUXOUT 8 23GND DECL2 9 22VCC4 VCC210 21GND 11213141516171819102 DAKEDP3PND NGTADLCLNGONECCVQQNG NOTES 12 .. NTLHOCE W= E NIXMOPP OCEOSDENADNNECPCAE DTG.D RDLOOEU NSNOHDTO P UCLLOADNN NBEEE. CSTOTLOD ETRHEISD PTION. A 08568-003 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. Mnemonic Description 1, 10, 17, 22, 27, 29, 34 VCC1, VCC2, VCC3, Power Supply Pins. The power supply voltage range is 4.75 V to 5.25 V. Drive all of VCC4, VCC5, VCC6, these pins from the same power supply voltage. Decouple each pin with 100 pF and VCC7 0.1 μF capacitors located close to the pin. 2 DECL1 Decoupling Node for Internal 3.3 V LDO. Decouple this pin with 100 pF and 0.1 μF capacitors located close to the pin. 3 CP Charge Pump Output Pin. Connect VTUNE to this pin through the loop filter. If an external VCO is being used, connect the output of the loop filter to the VCO’s voltage control pin. The PLL control loop should then be closed by routing the VCO’s frequency output back into the ADRF6702 through the LON and LOP pins. 4, 7, 11, 15, 20, 21, 23, GND Ground. Connect these pins to a low impedance ground plane. 25, 28, 30, 31, 35 24 NC Do not connect to this pin. 5 RSET Charge Pump Current. The nominal charge pump current can be set to 250 μA, 500 μA, 750 μA, or 1000 μA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (CP reference source). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (I ) can be externally tweaked according to the following NOMINAL equation: ⎛217.4×I ⎞ R =⎜ CP ⎟ −37.8Ω SET ⎜⎝ INOMINAL ⎟⎠ where I is the base charge pump current in microamps. For further details on the CP charge pump current, see the Register 4—PLL Charge Pump, PFD, and Reference Path Control section. 6 REFIN Reference Input. The nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin has high input impedance and should be ac-coupled. If REFIN is being driven by laboratory test equipment, the pin should be externally terminated with a 50 Ω resistor (place the ac-coupling capacitor between the pin and the resistor). When driven from an 50 Ω RF signal generator, the recommended input level is 4 dBm. 8 MUXOUT Multiplexer Output. This output allows a digital lock detect signal, a voltage proportional to absolute temperature (VPTAT), or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by programming DB21 to DB23 in Register 4. 9 DECL2 Decoupling Node for 2.5 V LDO. Connect 100 pF, 0.1 μF, and 10 μF capacitors between this pin and ground. 12 DATA Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits. Rev. B | Page 8 of 36

Data Sheet ADRF6702 Pin No. Mnemonic Description 13 CLK Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. 14 LE Latch Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. 16 ENOP Modulator Output Enable/Disable. See Table 6. 18, 19, 32, 33 QP, QN, IN, IP Modulator Baseband Inputs. Differential in-phase and quadrature baseband inputs. These inputs should be dc-biased to 0.5 V. 26 RFOUT RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to its load. 36 LOSEL LO Select. This digital input pin determines whether the LOP and LON pins operate as inputs or outputs. This pin should not be left floating. LOP and LON become inputs if the LOSEL pin is set low and the LDRV bit of Register 5 is set low. External LO drive must be a 2× LO. In addition to setting LOSEL and LDRV low and providing an external 2× LO, the LXL bit of Register 5 (DB4) must be set to 1 to direct the external LO to the IQ modulator. LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set to 1. A 1× LO or 2× LO output can be selected by setting the LDIV bit of Register 5 (DB5) to 1 or 0 respectively (see Table 7). 37, 38 LON, LOP Local Oscillator Input/Output. The internally generated 1× LO or 2× LO is available on these pins. When internal LO generation is disabled, an external 1× LO or 2× LO can be applied to these pins. 39 VTUNE VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.3 V to 2.5 V. If the external VCO mode is activated, this pin can be left open. 40 DECL3 Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 μF capacitor between this pin and ground. EP Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Table 6. Enabling RFOUT ENOP Register 5 Bit DB6 RFOUT X1 0 Disabled 0 X1 Disabled 1 1 Enabled 1 X = don’t care. Table 7. LO Port Configuration1, 2 LON/LOP Function LOSEL Register 5 Bit DB5(LDIV) Register 5 Bit DB4(LXL) Register 5 Bit DB3 (LDRV) Input (2× LO) 0 X 1 0 Output (Disabled) 0 X 0 0 Output (1× LO) 0 0 0 1 Output (1× LO) 1 0 0 0 Output (1× LO) 1 0 0 1 Output (2× LO) 0 1 0 1 Output (2× LO) 1 1 0 0 Output (2× LO) 1 1 0 1 1 X = don’t care. 2 LOSEL should not be left floating. Rev. B | Page 9 of 36

ADRF6702 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS V = 5 V; T = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q S A frequency (f ) = 1 MHz; f = 38.4 MHz; f = 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted. BB PFD REF 10 10 TA=–40°C 9 TTAA==++2855°°CC 9 8 8 m) m) dB 7 dB 7 ( ( R R E 6 E 6 W W O O TP 5 TP 5 VS=5V U U TP 4 TP 4 U U O O SB 3 SB 3 VS=5.25V VS=4.75V S S 2 2 1 1 0 0 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-104 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-107 Figure 4. Single Sideband (SSB) Output Power (POUT) vs. Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown LO Frequency (fLO) and Power Supply; Multiple Devices Shown 20 20 TA=–40°C 19 TTAA==++2855°°CC 19 m) m) B 18 B 18 d d ( ( ON 17 ON 17 SI SI ES 16 ES 16 R R P P M 15 M 15 O O VS=5V VS=5.25V C C T 14 T 14 U U P P T 13 T 13 U U BO 12 BO 12 VS=4.75V d d 1 1 11 11 10 10 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-105 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-108 Figure 5. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) Figure 8. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown and Power Supply 0 20 0 20 THIRD-ORDER THIRD-ORDER –10 DISTORTION(dBc) 16 –10 SSBOUTPUT DISTORTION(dBc) 16 SECOND-ORDERDISTORTION(dBc),THIRD-ORDERDISTORTION(dBc),CARRIERFEEDTHROUGH(dBm),SIDEBANDSUPPRESSION(dBc)–––––––87654320000000 CSAURPRPSIREIDERESFBSEIAOENDNDT(HdBRcO)UGPHSOS(dWBBESOmREU)C(TdOPBNUmDT)-ORDER –––048118422SSBOUTPUTPOWER(dBm) SECOND-ORDERDISTORTION(dBc),THIRD-ORDERDISTORTION(dBc),CARRIERFEEDTHROUGH(dBm),SIDEBANDSUPPRESSION(dBc)–––––––87654320000000 FEEDTCHARROSRUUIPGEPHRSRI(DEdESBPBSmOIAO)WNNED(RDdSIB(SEdcTCB)OOmRN)TDIO-ONR(DdEBRc) –––048118422SSBOUTPUTPOWER(dBm) –90 DISTORTION(dBc) –16 –90 –16 –1000.1 BASEBANDINPUTVOL1TAGE(Vp-pDifferential) 10–20 08568-106 –1000.1 BASEBANDINPUTVOL1TAGE(Vp-pDifferential) 10–20 08568-109 Figure 6. SSB Output Power, Second- and Third-Order Distortion, Carrier Figure 9. SSB Output Power, Second- and Third-Order Distortion, Carrier Feedthrough and Sideband Suppression vs. Baseband Differential Input Feedthrough and Sideband Suppression vs. Baseband Differential Input Voltage (fOUT = 1960 MHz) Voltage (fOUT = 2140 MHz) Rev. B | Page 10 of 36

Data Sheet ADRF6702 0 0 TA=–40°C TA=–40°C TA=+25°C TA=+25°C –10 TA=+85°C –10 TA=+85°C m) m) dB –20 dB –20 ( ( H H G G U –30 U –30 O O R R H H T –40 T –40 D D E E E E F –50 F –50 R R E E RI RI R –60 R –60 A A C C –70 –70 –80 –80 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-110 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-113 Figure 10. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature; Figure 13. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After Multiple Devices Shown Nulling at 25°C; Multiple Devices Shown 0 0 TA=–40°C TA=–40°C –10 TTAA==++2855°°CC –10 TTAA==++2855°°CC Bc) –20 Bc) –20 d d ( ( ON –30 ON –30 SI SI S S RE –40 RE –40 P P P P U –50 U –50 S S D D AN –60 AN –60 B B E E D –70 D –70 SI SI –80 –80 –91055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-111 –91055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-114 Figure 11. Sideband Suppression vs. LO Frequency (fLO) and Temperature; Figure 14. Sideband Suppression vs. LO Frequency (fLO) and Temperature Multiple Devices Shown After Nulling at 25°C; Multiple Devices Shown 90 –20 TA=–40°C –25 TA=+25°C 80 OIP2 c),Bc)–30 TA=+85°C m) 70 (dBN(d–35 B NO 2(d 60 TIORTI–40 THIRD-ORDERDISTORTION TIP3ANDIP 4500 OIP3 DERDISTORRDERDISTO–––554505 OUTPU 2300 THIRD-ORSECOND-O–––766050 10 TTAA==–+4205°°CC –75 105501T6A00=1+68550°C170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-112 –8105501S6E0C0O16N5D0-O17R0D0E1R7L5OD0IFS1RT8O0E0QR1TU8IEO5N0NC1Y90(M0H19z5)02000205021002150 08568-115 Figure 12. OIP3 and OIP2 vs. LO Frequency (fLO) and Temperature Figure 15. Second- and Third-Order Distortion vs. LO Frequency (fLO) and (POUT ≈ −2 dBm per Tone); Multiple Devices Shown Temperature Rev. B | Page 11 of 36

ADRF6702 Data Sheet Hz (dBc/Hz) –––1230000 TTTAAA === –++428055°°°CCC ms) 100...098 TTTAAA===–++428055°°°CCC Y = 1850M –––456000 3.5kHz LOOP FILTER NOISE(°r 00..76 EQUENC –––789000 PHASE 0.5 R D 0.4 F–100 E OISE, LO –––111231000 130kHz LOOP FILTER NTEGRAT 00..32 E N–140 I 0.1 AS–150 PH–1601k 10k OFFS1E00Tk FREQUEN1CMY (Hz) 10M 100M 08568-116 1055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-119 Figure 16. Phase Noise vs. Offset Frequency and Temperature, Figure 19. Integrated Phase Noise vs. LO Frequency fLO = 1850 MHz, 3.5 KHz Filter Hz (dBc/Hz) –––1230000 TTTAAA === –++428055°°°CCC –––898500 TTTAAA===++–428055°°°CCC OFFSET=1kHz M –95 0 –40 196 –50 3.5kHz LOOP FILTER Hz)–100 EQUENCY = ––––67890000 NOISE(dBc/––––111101125050 OFFSET=100kHz E, LO FR–––111021000 PHASE––112350 OIS–130 130kHz LOOP FILTER –135 OFFSET=5MHz E N–140 –140 AS–150 –145 PH–1601k 10k OFFS1E00Tk FREQUEN1CMY (Hz) 10M 100M 08568-117 –151055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-120 Figure 17. Phase Noise vs. Offset Frequency and Temperature, Figure 20. Phase Noise vs. LO Frequency at 1 kHz, 100 kHz, and 5 MHz Offsets fLO = 1960 MHz, 3.5 KHz Filter Hz (dBc/Hz) –––1230000 TTTAAA === –++428055°°°CCC ––––88990505 TTTAAA===–++428055°°°CCC 0M –40 –100 NCY = 214 –––567000 3.5kHz LOOP FILTER E(dBc/Hz)–––111011505 OFFSET=10kHz EQUE ––8900 NOIS––112205 OFFSET=1MHz FR–100 SE–130 SE, LO ––112100 130kHz LOOP FILTER PHA––113450 OI–130 –145 E N–140 –150 AS–150 –155 PH–1601k 10k OFFS1E00Tk FREQUEN1CMY (Hz) 10M 100M 08568-118 –161055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-121 Figure 18. Phase Noise vs. Offset Frequency and Temperature, Figure 21. Phase Noise vs. LO Frequency at 10 kHz and 1 MHz Offsets fLO = 2140 MHz, 3.5 KHz Filter Rev. B | Page 12 of 36

Data Sheet ADRF6702 –70 –70 2×PFDFREQUENCY TA=–40°C 2×PFDFREQUENCY TA=–40°C –75 4×PFDFREQUENCY TTAA==++2855°°CC –75 4×PFDFREQUENCY TTAA==++2855°°CC –80 –80 –85 –85 c) c) B B (d –90 (d –90 L L E E V –95 V –95 E E L L UR–100 UR–100 P P S–105 S–105 –110 –110 –115 –115 –120 –120 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-122 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-126 Figure 22. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) at Figure 25. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) at LO Modulator Output Output –70 –70 1×PFDFREQUENCY TA=–40°C 1×PFDFREQUENCY TA=–40°C –75 3×PFDFREQUENCY TTAA==++2855°°CC –75 3×PFDFREQUENCY TTAA==++2855°°CC –80 –80 –85 –85 c) c) B B (d –90 (d –90 L L E E V –95 V –95 E E L L UR–100 UR–100 P P S–105 S–105 0.5×PFDFREQUENCY –110 –110 –115 –115 0.5×PFDFREQUENCY –121055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-123 –121055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-125 Figure 23. PLL Reference Spurs vs. LO Frequency (0.5× PFD, 1× PFD, Figure 26. PLL Reference Spurs vs. LO Frequency (0.5× PFD, 1× PFD, and and 3× PFD) at Modulator Output 3× PFD) at LO Output 2.8 0 TA=–40°C 2.6 TTAA==++2855°°CC –20 2.4 –40 2.2 c/Hz) –60 LO=1943.26MHz B TUNE(V) 21..08 NOISE(d––18000 LO=1841.074MHz LO=2140.48MHz V E S 1.6 A–120 H P 1.4 –140 1.2 –160 1.1055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-124 –1801k 10k FREQU1E0N0kCY(Hz) 1M 10M 08568-127 Figure 24. VTUNE vs. LO Frequency and Temperature Figure 27. Open-Loop VCO Phase Noise at 1841.074 MHz, 1943.26 MHz, and 2140.48 MHz Rev. B | Page 13 of 36

ADRF6702 Data Sheet 100 1850MHz Bm) 0 1960MHz d 90 2140MHz H( –10 G %) 80 OU –20 AGE ( 70 DTHR –30 PERCENT 5600 DLOFEE ––5400 TIVE 40 RAN –60 SSBOUTPUTPOWER A E UL 30 OW –70 M P CU 20 PUT –80 LOFEEDTHROUGH 10 UT –90 O B –0164 –163 –162 –161NO–IS1E60 FL–O1O59R (–d1B5m8/H–z1)57 –156 –155 –154 08568-128 SS –101055016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-130 Figure 28. IQ Modulator Noise Floor Cumulative Distributions at 1850 MHz, Figure 30. SSB Output Power and LO Feedthrough with RF Output Disabled 1960 MHz, and 2140 MHz 2.0 25 z) 1.9 H (M 20 1.8 z H 0M 15 1.7 6 9 OM1 10 (V) 1.6 FR TAT 1.5 N 5 P O V 1.4 TI A VI 0 1.3 E D CY –5 1.2 N UE 1.1 Q –10 E R 1.0 F –150 50 100 TIM1E50(µs) 200 250 300 08568-129 –40 Figu–1re5 31. VPTTEAM1T0P VEoRltAaTgUeR vE3s(5.° TCe)mperat6u0re 85 08568-131 Figure 29. Frequency Deviation from LO Frequency at LO = 1.97 GHz to 1.96 GHz vs. Lock Time Rev. B | Page 14 of 36

Data Sheet ADRF6702 0 –1 –2 –3 RF OUTPUT –4 dB) –5 SS ( –6 O L –7 N R –8 U LO INPUT LO = 1550MHz ET –9 LO = 2150MHz R –10 –11 –12 –13 –14 155016001650170017L5O0 F18R0E0Q1U8E50NC19Y0 (0M1H9z5)02000205021002150 08568-032 08568-234 Figure 32. Input Return Loss of LO Input (LON, LOP Driven Through MABA- Figure 34. Smith Chart Representation of RF Output 007159 1:1 Balun) and Output Return Loss of RFOUT vs. Frequency 280 270 260 mA) 250 TA=+85°C ( NT 240 RE TA=+25°C R 230 U C LY 220 PP TA=–40°C U 210 S 200 190 180 155016001650170017L5O0F1R80E0Q1U8E5N0C1Y90(M0H19z5)02000205021002150 08568-133 Figure 33. Power Supply Current vs. Frequency and Temperature (PLL and IQMOD Enabled, LO Buffer Disabled) Rev. B | Page 15 of 36

ADRF6702 Data Sheet THEORY OF OPERATION The ADRF6702 integrates a high performance IQ modulator BASIC CONNECTIONS FOR OPERATION with a state of the art fractional-N PLL. The ADRF6702 also Figure 35 shows the basic connections for operating the integrates a low noise VCO. The programmable SPI port allows ADRF6702 as they are implemented on the device’s evaluation the user to control the fractional-N PLL functions and the board. The seven power supply pins should be individually modulator optimization functions. This includes the capability decoupled using 100 pF and 0.1 μF capacitors located as close to operate with an externally applied LO or VCO. as possible to the pins. A single 10 μF capacitor is also recom- The quadrature modulator core within the ADRF6702 is a part mended. The three internal decoupling nodes (labeled DECL3, of the next generation of industry-leading modulators from DECL2, and DECL1) should be individually decoupled with Analog Devices, Inc. The baseband inputs are converted to capacitors as shown in Figure 35. currents and then mixed to RF using high performance NPN The four I and Q inputs should be driven with a bias level of transistors. The mixer output currents are transformed to a 500 mV. These inputs are generally dc-coupled to the outputs of single-ended RF output using an integrated RF transformer a dual DAC (see the DAC-to-IQ Modulator Interfacing and IQ balun. The high performance active mixer core, coupled with Filtering sections for more information). the low-loss RF transformer balun results in an exceptional OIP3 and OP1dB, with a very low output noise floor for excel- A 1 V p-p (0.353 V rms) differential sine wave on the I and Q lent dynamic range. The use of a passive transformer balun inputs results in a single sideband output power of +4.1 dBm (at rather than an active output stage leads to an improvement 1960 MHz) at the RFOUT pin (this pin should be ac-coupled as in OIP3 with no sacrifice in noise floor. At 1960 MHz the shown in Figure 35). This corresponds to an IQ modulator ADRF6702 typically provides an output P1dB of 13.6 dBm, voltage gain of +0.1 dB. OIP3 of 30.1 dBm, and an output noise floor of −156.5 dBm/Hz. The reference frequency for the PLL (typically 1 V p-p between Typical image rejection under these conditions is −44.4 dBc 12 MHz and 160 MHz) should be applied to the REFIN pin, with no additional I and Q gain compensation. which should be ac-coupled. If the REFIN pin is being driven PLL + VCO from a 50 Ω source (for example, a lab signal generator), the pin should be terminated with 50 Ω as shown in Figure 35 (an The fractional divide function of the PLL allows the frequency RF drive level of +4 dBm should be applied). Multiples or multiplication value from REFIN to the LOP/LON outputs to fractions of the REFIN signal can be brought back off-chip at be a fractional value rather than restricted to an integer as in the multiplexer output pin (MUXOUT). A lock-detect signal traditional PLLs. In operation, this multiplication value is INT and an analog voltage proportional to the ambient temperature + (FRAC/MOD) where INT is the integer value, FRAC is the can also be brought out on this pin by setting the appropriate fractional value, and MOD is the modulus value, all of which bits on (DB21-DB23) in Register 4 (see the Register Description are programmable via the SPI port. In previous fractional-N section). PLL designs, the fractional multiplication was achieved by EXTERNAL LO periodically changing the fractional value in a deterministic way. The downside of this was often spurious components close The internally generated local oscillator (LO) signal can be to the fundamental signal. In the ADRF6702, a sigma delta brought off-chip as either a 1× LO or a 2× LO (via pins LOP modulator is used to distribute the fractional value randomly, and LON) by asserting the LOSEL pin and making the appro- thus significantly reducing the spurious content due to the priate internal register settings. The LO output must be disabled fractional function. whenever the RF output of the IQ modulator is disabled. The LOP and LON pins can also be used to apply an external LO. This can be used to bypass the internal PLL/VCO or if operation using an external VCO is desired. To turn off the PLL Register 6, Bits[20:17] must be zero. Rev. B | Page 16 of 36

Data Sheet ADRF6702 VCC R43 VR+CE5DCV C28 S2 1(004k0Ω2) (0R042Ω002) 10µF R47 (3216) (1004k0Ω2) C7 C27 C25 C23 C20 C19 C9 VCC 0(0.14µ02F) 0(0.14µ02F) 0(0.14µ02F) 0(0.14µ02F) 0(0.14µ02F) 0(0.14µ02F) 0(0.14µ02F) LE (USB) R39 DATA (USB) 10kΩ C8 C26 C24 C22 C21 C18 C10 CLK (USB) S1 (0402) VDD 1(0V040D0pD2F) 1(0V04D00pD2F) 1(00V40D0p2DF) 1(00V40D0p2DF) 1(00V40D0p2DF) 1(00V40D0pD2F) 1(00400p2F) ENOP CLK DATA LE (0140R0k42Ω0) LOSEL36 34 29 27 22 17 10 1 16 13 12 14 9 DECLC120106pF C0.117µF C104µ2F LON SPI (0402) (0402) (0603) EXT LO 54 13 1(00C4006p2F)LOP3387 BUFFER DIV÷ID2ER INTERFACE 2 DECLC110102pF C0.111µF CO4P1EN MABAT-030715910C05pF FRARCETGION MODULUS INTREEGGER BUFFER M2U:1X (0402) (0402) (0603) (0402) ADRF6702 QP RSEEFE_( I4T0N94ER.0X972ΩT3) 1(0C04020p92F) REFIN 6 ÷÷×242 MUX TIENTFMTHREIPARRCDPT-OOIOLRANDTAEO+–LRRFREPNQH2 UCA1EOSTNEUOCN 1YT2E3R PC2550RH00EAµµSRAA÷CG ,2(ADEL EPEFURAMUPLT), CVOCROE 0÷/920 113892 QINN RRO(032P430E2N) QQINPN REFOUT OPEN SENSOR DETECTOR 750µA, OPEN ORP1E6N MUXOUT 8 4 7 11 15 20 21 23 25 28 30 31 35 241000µA 5 3 39 40 26 33 IP (0402) IP (0402) NC R2 RSET CP VTUNE DECL3 ORFPOENUT GNDTECSPT (O0RP430E82N) (0RR04(3Ω9007 241)002k(O0)ΩP40E2RN)6(0541002k)Ω R0(0Ω64202) VOTPUENNE 1(00C4003p2F) RFOUT (OPOPEINNT) 2C2p1F4 R3(0k16Ω003) C6.183pF C224p0F (O0RP460E32N) (0603) C15 (0603) (0603) 2.7nF (1206) R11 R12 OPEN 0Ω (0402) (0402) C43 C2 C1 10µF OPEN 100pF N1.O NTCE S= NO CONNECT. DO NOT CONNECTTO THIS PIN. (0603) (0402) (0402) 08568-023 Figure 35. Basic Connections for Operation (Loop Filter Set to 130 kHz) LOOP FILTER Table 8. Recommended Loop Filter Components The loop filter is connected between the CP and VTUNE pins. Component 130 kHz Loop Filter 2.5 kHz Loop Filter The return for the loop filter components should be to Pin 40 C14 22 pF 0.1 μF (DECL3). The loop filter design in Figure 35 results in a 3 dB R10 3 kΩ 68 Ω loop bandwidth of 130 kHz. The ADRF6702 closed loop phase C15 2.7 nF 4.7 μF noise was also characterized using a 2.5 kHz loop filter design. R9 10 kΩ 270 Ω The recommended components for both filter designs are C13 6.8 pF 47 nF shown in Table 8. For assistance in designing loop filters with R65 10 kΩ 0 Ω other characteristics, download the most recent revision of C40 22 pF Open ADIsimPLL™ from www.analog.com/adisimpll. Operation with R37 0 Ω 0 Ω an external VCO is possible. In this case, the return for the loop R11 Open Open filter components is ground (assuming a ground reference on R12 0 Ω 0 Ω the external VCO tuning input). The output of the loop filter is connected to the external VCO’s tuning pin. The output of the VCO is brought back into the device on the LOP and LON pins (using a balun if necessary). Rev. B | Page 17 of 36

ADRF6702 Data Sheet DAC-TO-IQ MODULATOR INTERFACING AD9122 ADRF6702 The ADRF6702 is designed to interface with minimal components OUT1_P IP RBIP to members of the Analog Devices, Inc., family of TxDACs®. These 50Ω RSL dual-channel differential current output DACs provide an output RBIN (SEETEXT) 50Ω current swing from 0 mA to 20 mA. The interface described in OUT1_N IN this section can be used with any DAC that has a similar output. An example of an interface using the AD9122 TxDAC is shown in Figure 36. The baseband inputs of the ADRF6702 require OUT2_N QN RBQN a dc bias of 500 mV. The average output current on each of the 50Ω RSL outputs of the AD9122 is 10 mA. Therefore, a single 50 Ω resis- RBQP (SEETEXT) tcourr rteon gt roofu 1n0d mfrAom fl oeawcihn ogf t thhreo DugAhC e oauchtp ouft st hrees ureltssi sinto arns, atvheursa ge OUT2_P 50Ω QP 08568-034 Figure 37. AC Voltage Swing Reduction Through the Introduction producing the desired 500 mV dc bias for the inputs to the of a Shunt Resistor Between the Differential Pair ADRF6702. The value of this ac voltage swing limiting resistor (R as shown SL in Figure 37) is chosen based on the desired ac voltage swing AD9122 ADRF6702 and IQ modulator output power. Figure 38 shows the relation- OUT1_P IN ship between the swing-limiting resistor and the peak-to-peak RBIP 50Ω ac swing that it produces when 50 Ω bias-setting resistors are RBIN 50Ω used. A higher value of swing-limiting resistor will increase the OUT1_N IP output power of the ADRF6702 and signal-to-noise ratio (SNR) at the cost if higher intermodulation distortion. For most applications, the optimum value for this resistor will be between OUT2_N QN 100 Ω and 300 Ω. RBQN 50Ω When setting the size of the swing-limiting resistor, the input RBQP OUT2_P 50Ω QP 08568-033 iTmhpe eId aanndc eQ o ifn tphuet Is ahnadv eQ a idnipffuetrse snhtioaul lidn pbuet t raekseinst ainntcoe aocfc 9o2u0n Ωt. . Figure 36. Interface Between the AD9122 and ADRF6702 with 50 Ω Resistors As a result, the effective value of the swing-limiting resistance is to Ground to Establish the 500 mV DC Bias for the ADRF6702 Baseband Inputs 920 Ω in parallel with the chosen swing-limiting resistor. For The AD9122 output currents have a swing that ranges from example, if a swing-limiting resistance of 200 Ω is desired 0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage (based on Figure 37), the value of RSL should be set such that swing going into the ADRF6702 baseband inputs ranges from 200 Ω = (920 × R )/(920 + R ) SL SL 0 V to 1 V (with the DAC running at 0 dBFS). So the resulting resulting in a value for R of 255 Ω. drive signal from each differential pair is 2 V p-p differential SL with a 500 mV dc bias. 2.0 1.8 ADDING A SWING-LIMITING RESISTOR The voltage swing for a given DAC output current can be p-p) 1.6 V 1.4 reduced by adding a third resistor to the interface. This resistor ( G is placed in the shunt across each differential pair, as shown in WIN 1.2 S Figure 37. It has the effect of reducing the ac swing without L 1.0 A changing the dc bias already established by the 50 Ω resistors. NTI 0.8 E R E 0.6 F F DI 0.4 0.2 010 100 RSL(Ω) 1000 10000 08568-035 Figure 38. Relationship Between the AC Swing-Limiting Resistor and the Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors Rev. B | Page 18 of 36

Data Sheet ADRF6702 IQ FILTERING 1000 1.2 An antialiasing filter must be placed between the DAC and 900 1.0 modulator to filter out Nyquist images and broadband DAC CAPACITANCE noise. The interface for setting up the biasing and ac swing discussed in the Adding a Swing-Limiting Resistor section, E (Ω) 800 0.8 E (pF) lends itself well to the introduction of such a filter. The filter ANC 700 RESISTANCE 0.6 ANC can be inserted between the dc bias setting resistors and the ST CIT SI A ac swing-limiting resistor. Doing so establishes the input and E P R 600 0.4 CA output impedances for the filter. Unless a swing-limiting resistor of 100 Ω is chosen, the filter 500 0.2 must be designed to support different source and load impedances. In addition, the differential input capacitance of 400 0 tdhees iIg ann. dM Qod ienrpnu ftisl t(e1r pdFe)s isghno tuolodl sb ea lflaocwto froerd t hinet osi mthue lfaitlitoenr and 0 100 BASEBA2N0D0 FREQUE3N0C0Y (MHz) 400 500 08568-141 Figure 40. Differential Baseband Input R and Input C Equivalents (Shunt R design of filters with differing source and load impedances as and Shunt C) well as inclusion of reactive load components. DEVICE PROGRAMMING AND REGISTER BASEBAND BANDWIDTH SEQUENCING Figure 39 shows the frequency response of the ADRF6702’s The device is programmed via a 3-pin SPI port. The timing baseband inputs. This plot shows 0.5 dB and 3 dB bandwidths requirements for the SPI port are shown in Table 3 and Figure 2. of 350 MHz and 750 MHz respectively. Any flatness variations Eight programmable registers, each with 24 bits, control the across frequency at the ADRF6702 RF output have been operation of the device. The register functions are listed in calibrated out of this measurement. Table 9. The eight registers should initially be programmed 4 in reverse order, starting with Register 7 and finishing with c) Register 0. Once all eight registers have been initially B d 2 E( programmed, any of the registers can be updated without any S ON 0 attention to sequencing. P S E Software is available on the ADRF6702 product page at R CY –2 www.analog.com that allows programming of the evaluation N QUE –4 board from a PC running Windows® XP or Windows Vista. E FR To operate correctly under Windows XP, Version 3.5 of D –6 N Microsoft .NET must be installed. To run the software on A B SE –8 a Windows 7 PC, XP emulation mode must be used (using BA Virtual PC). –10 10 BBFREQU1E00NCY(MHz) 1000 08568-134 Figure 39. Baseband Bandwidth Rev. B | Page 19 of 36

ADRF6702 Data Sheet REGISTER SUMMARY Table 9. Register Functions Register Function Register 0 Integer divide control (for the PLL) Register 1 Modulus divide control (for the PLL) Register 2 Fractional divide control (for the PLL) Register 3 Σ-Δ modulator dither control Register 4 PLL charge pump, PFD, and reference path control Register 5 LO path and modulator control Register 6 VCO control and VCO enable Register 7 External VCO enable Rev. B | Page 20 of 36

Data Sheet ADRF6702 REGISTER DESCRIPTION REGISTER 0—INTEGER DIVIDE CONTROL Integer Divide Ratio (DEFAULT: 0x0001C0) The integer divide ratio bits are used to set the integer value in With Register 0, Bits[2:0] set to 000, the on-chip integer divide Equation 2. The INT, FRAC, and MOD values make it possible control register is programmed as shown in Figure 41. to generate output frequencies that are spaced by fractions of the PFD frequency. The VCO frequency (f ) equation is Divide Mode VCO f = 2 × f × (INT + (FRAC/MOD)) (2) Divide mode determines whether fractional mode or integer VCO PFD mode is used. In integer mode, the RF VCO output frequency where: (f ) is calculated by INT is the preset integer divide ratio value (24 to 119 in VCO fractional mode). f = 2 × f × (INT) (1) VCO PFD MOD is the preset fractional modulus (1 to 2047). where: FRAC is the preset fractional divider ratio value (0 to MOD − 1). f is the output frequency of the internal VCO. VCO f is the frequency of operation of the phase-frequency detector. PFD INT is the integer divide ratio value (21 to 123 in integer mode). DIVIDE RESERVED MODE INTEGER DIVIDE RATIO CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) DM DIVIDE MODE 0 FRACTIONAL (DEFAULT) 1 INTEGER ID6 ID5 ID4 ID3 ID2 ID1 ID0 INTEGER DIVIDE RATIO 0 0 1 0 1 0 1 21 (INTEGER MODE ONLY) 0 0 1 0 1 1 0 22 (INTEGER MODE ONLY) 0 0 1 0 1 1 1 23 (INTEGER MODE ONLY) 0 0 1 1 0 0 0 24 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 56 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 119 1 1 1 1 0 0 0 120 (INTEGER MODE ONLY) 1 1 1 1 0 0 1 121 (INTEGER MODE ONLY) 11 11 11 11 00 11 01 112223 ((IINNTTEEGGEERR MMOODDEE OONNLLYY)) 08568-014 Figure 41. Register 0—Integer Divide Control Register Map Rev. B | Page 21 of 36

ADRF6702 Data Sheet REGISTER 1—MODULUS DIVIDE CONTROL REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x003001) (DEFAULT: 0x001802) With Register 1, Bits[2:0] set to 001, the on-chip modulus With Register 2, Bits[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 42. divide control register is programmed as shown in Figure 43. Modulus Value Fractional Value The modulus value is the preset fractional modulus ranging The FRAC value is the preset fractional modulus ranging from from 1 to 2047. 0 to <MDR. RESERVED MODULUS VALUE CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1) MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 MODULUS VALUE 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 2 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 0 0 0 0 0 0 1536 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... .1.. 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... .2.0.47 08568-015 Figure 42. Register 1—Modulus Divide Control Register Map RESERVED FRACTIONAL VALUE CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 C3(0) C2(1) C1(0) FD10 FD9 FD8 FD7 FD6 FD5 FD4 FD3 FD2 FD1 FD0 FRACTIONAL VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 0 0 0 0 0 0 0 0 768 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... FRACTIONAL VALUE MUST BE LESS THAN MODULUS. <MDR 08568-016 Figure 43. Register 2—Fractional Divide Control Register Map Rev. B | Page 22 of 36

Data Sheet ADRF6702 REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL The default value of the dither magnitude (15) should be set to a (DEFAULT: 0x10000B) recommended value of 1. With Register 3, Bits[2:0] set to 011, the on-chip Σ-Δ modulator The dither restart value can be programmed from 0 to 217 − 1, dither control register is programmed as shown in Figure 44. The though a value of 1 is typically recommended. recommended and default setting for dither enable is enabled (1). DITHER DITHER MAGNITUDE ENABLE DITHER RESTART VALUE CONTROL BITS DB23 DB22 DB21 DB20 DB19DB18DB17DB16DB15DB14DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 DITH1 DITH0 DEN DV16DV15DV14DV13DV12DV11DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 C3(0)C2(1)C1(1) DITH1 DITH0 DITHER MAGNITUDE 0 0 15 (DEFAULT) 0 1 7 1 0 3 1 1 1 (RECOMMENDED) DEN DITHER ENABLE 0 DISABLE 1 ENABLE (DEFAULT, RECOMMENDED) DITHER RESTART DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DDVV22 DV1 DV0 VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 0x00001 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...... ... ... ... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1... 1..1.... 1... 1... .0.x.1FFFF 08568-017 Figure 44. Register 3—Σ-Δ Modulator Dither Control Register Map Rev. B | Page 23 of 36

ADRF6702 Data Sheet REGISTER 4—PLL CHARGE PUMP, PFD, AND fractional spurs. The magnitude of the phase offset is deter- REFERENCE PATH CONTROL (DEFAULT: mined by the following equation: 0x0AA7E4) θ ΔΦ(deg)=22.5 PFD,OFS (4) With Register 4, Bits[2:0] set to 100, the on-chip charge pump, I CP,MULT PFD, and reference path control register is programmed as The default value of the phase offset multiplier (10 × 22.5°) shown in Figure 45. should be set to a recommended value of 6 × 22.5°. CP Current This phase offset can be either positive or negative depending The nominal charge pump current can be set to 250 μA, 500 μA, on the value of DB17 in Register 4. 750 μA, or 1000 μA using DB10 and DB11 of Register 4 and by The reference frequency applied to the PFD can be manipulated setting DB18 to 0 (CP reference source). using the internal reference path source. The external reference In this mode, no external RSET is required. If DB18 is set to 1, frequency applied can be internally scaled in frequency by 2×, the four nominal charge pump currents (I ) can be NOMINAL 1×, 0.5×, or 0.25×. This allows a broader range of reference externally tweaked according to the following equation: frequency selections while keeping the reference frequency ⎛217.4× I ⎞ applied to the PFD within an acceptable range. R = ⎜ CP ⎟ −37.8Ω (3) SET ⎜⎝ INOMINAL ⎟⎠ The device also has a MUXOUT pin that can be programmed to output a selection of several internal signals. The default where I is the base charge pump current in microamps. CP mode is to provide a lock-detect output to allow the user to The PFD phase offset multiplier (θ ), which is set by verify when the PLL has locked to the target frequency. In PFD,OFS Bits[16:12] of Register 4, causes the PLL to lock with a addition, several other internal signals can be passed to the nominally fixed phase offset between the PFD reference signal MUXOUT pin as described in Figure 35. and the divided-down VCO signal. This phase offset is used to linearize the PFD-to-CP transfer function and can improve Rev. B | Page 24 of 36

Data Sheet ADRF6702 MRUEXF SOEULPEUCTT INPPUATT HREF CSUORRCURERPEFCNET PPOFDL PFDM PUHLATSIEP LOIEFRFSET CURCRPENT CPSOURCE CONCTPROL PFD EDGE BPAFDCDEK LALAANYSTIH- CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0) PAB1 PAB0 PFD ANTIBACKLASH DELAY 0 0 0ns (DEFAULT) 1 0 0.5ns 0 1 0.75ns 1 1 0.9ns REFERENCE PATH EDGE PE0 SENSITIVITY 0 FALLING EDGE 1 RISING EDGE (DEFAULT) DIVIDER PATH EDGE PE1 SENSITIVITY 0 FALLING EDGE 1 RISING EDGE (DEFAULT) CPC1CPC0 CHARGE PUMP CONTROL 0 0 BOTH ON 0 1 PUMP DOWN 1 0 PUMP UP 1 1 TRISTATE (DEFAULT) CPS CHARGE PUMP CONTROL SOURCE 0 CONTROL BASED ON STATE OF DB7/DB8 (CP CONTROL) 1 CONTROL FROM PFD (DEFAULT) CPP1 CPP0 CHARGE PUMP CURRENT 0 0 250µA 0 1 500µA (DEFAULT) 1 0 750µA 1 1 1000µA CPB4 CPB3 CPB2 CPB1 CPB0 PFD PHASE OFFSET MULTIPLIER 0 0 0 0 0 0 × 22.5°/ICP,MULT 0 0 0 0 1 1 × 22.5°/ICP,MULT 0 0 1 1 0 6 × 22.5°/ICP,MULT (RECOMMENDED) 0 1 0 1 0 10 × 22.5°/ICP,MULT (DEFAULT) 1 0 0 0 0 16 × 22.5°/ICP,MULT 1 1 1 1 1 31 × 22.5°/ICP,MULT CPBD PFD PHASE OFFSET POLARITY 0 NEGATIVE 1 POSITIVE (DEFAULT) CPM CHARGE PUMP CURRENT REFERENCE SOURCE 0 INTERNAL (DEFAULT) 1 EXTERNAL INPUT REF RS1 RS0 PATH SOURCE 0 0 2× REFIN 1 0 REFIN (DEFAULT) 0 1 0.5× REFIN 1 1 0.25× REFIN RMS2 RMS1 RMS0 REF OUTPUT MUX SELECT 0 0 0 LOCK DETECT (DEFAULT) 0 0 1 VPTAT 0 1 0 REFIN (BUFFERED) 0 1 1 0.5× REFIN (BUFFERED) 1 0 0 2× REFIN (BUFFERED) 111 011 101 TRRREEISSSEETRRAVVTEEEDD 08568-018 Figure 45. Register 4—PLL Charge Pump, PFD, and Reference Path Control Register Map Rev. B | Page 25 of 36

ADRF6702 Data Sheet REGISTER 5—LO PATH AND MODULATOR Table 10. LO Port Configuration1, 2 CONTROL (DEFAULT: 0x0000D5) Register 5, Register 5, Register 5, LON/LOP Bit DB5 Bit DB4 Bit DB3 With Register 5, Bits[2:0] set to 101, the LO path and modulator Function LOSEL (LDIV) (LXL) (LDRV) control register is programmed as shown in Figure 46. Input (2× LO) 0 X 1 0 Output (Disabled) 0 X 0 0 The modulator output or the complete modulator can be Output (1× LO) 0 0 0 1 disabled using the modulator bias enable and modulator Output (1× LO) 1 0 0 0 output enable addresses of Register 5. Output (1× LO) 1 0 0 1 The LO port (LOP and LON pins) can be used to apply an Output (2× LO) 0 1 0 1 external 2× LO (that is, bypass internal PLL) to the IQ Output (2× LO) 1 1 0 0 modulator. A differential LO drive of 0 dBm is recommended. Output (2× LO) 1 1 0 1 The LO port can also be used as an output where a 2× LO or 1 X = don’t care. 1× LO can be brought out and used to drive another mixer. 2 LOSEL should not be left floating. The nominal output power provided at the LO port is 3 dBm. The internal VCO of the device can also be bypassed. In this The mode of operation of the LO port is determined by the case, the charge pump output drives an external VCO through status of the LOSEL pin (3.3 V logic) along with the settings the loop filter. The loop is completed by routing the VCO into in a number of internal registers (see Table 10). the device through the LO port. LO MOD RF LO LO OUTPUT RESERVED BIAS OUTPUT OUTPUT IN/OUT DRIVER CONTROL BITS ENABLE ENABLE DIVIDER CONTROLENABLE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBE RFEN LDIV LXL LDRV C3(1) C2(0) C1(1) LO OUTPUT DRIVER LDRV ENABLE 0 DRIVER OFF (DEFAULT) 1 DRIVER ON LXL LO INPUT/OUTPUT CONTROL 0 LO OUTPUT (DEFAULT) 1 LO INPUT LDIV LO OUTPUT DIVIDE MODE 0 DIVIDE BY 1 1 DIVIDE BY 2 (DEFAULT) RFEN RF OUTPUT ENABLE 0 DISABLE 1 ENABLE (DEFAULT) MBE MOD BIAS ENABLE 01 DENISAABBLLEE (DEFAULT) 08568-019 Figure 46. Register 5—LO Path and Modulator Control Register Map Rev. B | Page 26 of 36

Data Sheet ADRF6702 REGISTER 6—VCO CONTROL AND VCO ENABLE REGISTER 7—EXTERNAL VCO ENABLE (DEFAULT: 0x1E2106) With Register 7, Bits[2:0] set to 111, the external VCO control With Register 6, Bits[2:0] set to 110, the VCO control and register is programmed as shown in Figure 48. enable register is programmed as shown in Figure 47. The external VCO enable bit allows the use of an external VCO The VCO tuning band is normally selected automatically by the in the PLL instead of the internal VCO. This can be advantageous band calibration algorithm, although the user can directly select in cases where the internal VCO is not capable of providing the the VCO band using Register 6. desired frequency or where the internal VCO’s phase noise is higher than desired. By setting this bit (DB22) to 1, and setting The VCO BS SRC bit (DB9) determines whether the result of Register 6, Bits[15:10] to 0, the internal VCO is disabled, and the calibration algorithm is used to select the VCO band or if the output of an external VCO can be fed into the part differ- the band selected is based on the value in VCO band select entially on Pin 38 and Pin 37 (LOP and LON). Because the loop (DB8 to DB3). filter is already external, the output of the loop filter simply The VCO amplitude can be controlled through Register 6. The needs to be connected to the external VCO’s tuning voltage pin. VCO amplitude setting can be controlled between 0 and 63. The default value of 8 should be set to a recommended value of 63. The internal VCOs can be disabled using Register 6. The internal charge pump can be disabled through Register 6. By default, the charge pump is enabled. To turn off the PLL (for example, if the ADRF6702 is being driven by an external LO), set Register 6, Bits[20:17] to zero. RESERVED CEHPNUAAMRBGPLEE ENL3A.D3BOVLEVECNOA BLDLEO ENVACBOLE SWVCITOCH VCO AMPLITUDE BCVWTC RSOLW VCO BAND SELECT FROM SPI CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15DB14DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 CPEN L3EN LVEN VCO EN VCO SW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5VBS4VBS3VBS2VBS1VBS0C3(1)C2(1)C1(0) CPEN CHARGE PUMP ENABLE VC[5:0] VCO AMPLITUDE VBS[5:0] VCO BAND SELECT FROM SPI 0 DISABLE 0x00 0 0x00 1 ENABLE (DEFAULT) …. …. 0x01 0x18 8 (DEFAULT) …. DEFAULT 0x20 …. …. 0x3F L3EN 3.3V LDO ENABLE 0x2B 43 …. …. 0 DISABLE 0x3F 63 (RECOMMENDED) VBSRC VCO BW CAL AND SW SOURCE CONTROL 1 ENABLE (DEFAULT) 0 BAND CAL (DEFAULT) VCO SW VCO SWITCH CONTROL FROM SPI 1 SPI LVEN VCO LDO ENABLE 0 REGULAR (DEFAULT) 0 DISABLE 1 BAND CAL 1 ENABLE (DEFAULT) VCO EN VCO ENABLE 01 DENISAABBLLEE (DEFAULT) 08568-020 Figure 47. Register 6—VCO Control and VCO Enable Register Map EXTERNAL VCO RES ENABLE RESERVED CONTROL BITS DB23 DB22 DB21 DB20 DB19 DB18DB17DB16DB15DB14DB13DB12DB11DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 XVCO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C3(1)C2(1) C1(1) XVCO EXTERNAL VCO ENABLE 01 IENXTTEERRNNAALL V VCCOO (DEFAULT) 08568-021 Figure 48. Register 7—External VCO Enable Register Map Rev. B | Page 27 of 36

ADRF6702 Data Sheet CHARACTERIZATION SETUPS Figure 49 and Figure 50 show characterization bench setups For phase noise and reference spurs measurements, see the used to characterize the ADRF6702. The setup shown in phase noise setup on Figure 50. Phase noise was measured on Figure 49 was used to do most of the testing. An automated LO and modulator output. VEE program was used to control equipment over the IEEE bus. The setup was used to measure SSB, OIP2, OIP3, OP1dB, LO, and USB NULL. ADRF670xTESTRACKASSEMBLY(INTERNALVCOCONFIGURATION) E3631APOWERSUPPLY ALLINSTRUMENTSARECONNECTEDINDAISYCHAIN (+6VADJUSTEDTO5V) FASHIONVIAGBIPCABLEUNLESSOTHERWISENOTED. +5VFOR VPOSTO34950 MODULE 34401ADMM(FORSUPPLY CURRENTMEASUREMENT) PROGRAMMING 34980A ANDDCCABLE WITH34950AND(×2)34921MODULES (×6FORMULTISITE) INPUT (RFOUT) AGILENTE4440APSASPECTRUMANALYZER 9-PINDSUB CONNECTOR 10-PINCONNECTOR (REGISTER DCHEADER PROGRAMMING) REFIN KEITHLEYS46SWITCHSYSTEM#1 6dB (FORRFOUTANDREFINON6SITES) ADRF6702 EVALBOARD RFOUT OUTPUT(REF) KEITHLEYS46SWITCHSYSTEM#2 (FORBASEBANDINPUTSON6SITES) 6dB ROHDEANDSCHWARTZSMT06SIGNALGENERATOR (REFIN) BASEBANDINPUTSAT1MHz BASEBANDOUTPUTS (IN,IP,QN,QP) AEROFLEXIFR3416FREQUENCYGENERATOR (WITHBASEBANDOUTPUTSAT1MHz) CONNECTEDTOSYSPTCECMOVNIATRUOSLBTOGPIBADAPTER 08568-043 Figure 49. General Characterization Setup Rev. B | Page 28 of 36

Data Sheet ADRF6702 ADRF670xPHASENOISESTANDSETUP ALLINSTRUMENTSARECONNECTEDINDAISYCHAINFASHION VIAGBIPCABLEUNLESSOTHERWISENOTED. ROHDEANDSCHWARTZ SMA100SIGNALGENERATOR REFIN AGILENTE4440A SPECTRUM AGILENTE5052SIGNALSOURCE ANALYZER ANALYZER IFOUT KEITHLEYS46SWITCHSYSTEM2 (FORIFOUTANDREFINON6SITES) REFIN LOOUT BASEBANDINPUTS (IP,IN,QP,QN) IFR3416SIGNALGENERATOR KEITHLEYS46SWITCHSYSTEM1 (BASEBANDSOURCE) (FORBASEBANDINPUTSON6SITES) 10PINCONNECTOR (DCMEASUREMENT,+5VPOS) AND9PINDSUB CONNECTOR(VCOANDPLL PROGRAMMING) ADRF6702 EVALBOARD 34980AMULTIFUNCTIONSWITCH (WITH34950AND34921MODULES) AGILENTE3631APOWER SUPPLY INPUTDC (INDCAIGMMILOEEDANEST,US3RU4E4PM0P1ELANYDTC)MUMRRENT CONNECTEDTOSYSPTCECMOVNIATRUOSLBTOGPIBADAPTER 08568-044 Figure 50. Characterization Setup for Phase Noise and Reference Spur Measurements Rev. B | Page 29 of 36

ADRF6702 Data Sheet EVALUATION BOARD Figure 52 shows the schematic of the device’s RoHS-compliant To operate correctly under Windows XP, Version 3.5 of evaluation board. This board was designed using Rogers 4350 Microsoft .NET must be installed. To run the software on a material to minimize losses at high frequencies. FR4 material Windows 7 PC, XP emulation mode must be used (using would also be adequate but with the slightly higher trace loss Virtual PC). of this material. Whereas the on-board USB interface circuitry of the evaluation board is powered directly from the PC, the main section of the evaluation board requires a separate 5 V power supply. The evaluation board is designed to operate using the internal VCO (default configuration) of the device or with an external VCO. To use an external VCO, R62 and R12 should be removed. 0 Ω resistors should be placed in R63 and R11. A side-launched SMA connector (Johnson 142-0701-851) must be soldered to the pad labeled VTUNE. The input of the external VCO should be connected to the VTUNE SMA connector and a portion of the VCO’s output should be connected to the EXT LO SMA connector. In addition to these hardware changes, internal register settings must also be changed (as detailed in the Register Description section) to enable operation with an external VCO. Adedsdcirtiiboenda li nc oTnafbigleu 1ra1t.i on options for the evaluation board are 08568-135 Figure 51. Control Software Opening Menu The serial port of the ADRF6702 can be programmed from a Figure 51 shows the opening window of the software where the PC’s USB port (a USB cable is provided with the evaluation user selects the device being programmed. Figure 55 shows a board). The on-board USB interface circuitry can if desired be screen shot of the control software’s main controls with the bypassed by removing the 0 Ω resistors, R15, R17, and R18 (see default settings displayed. The text box in the bottom left corner Figure 52) and driving the ADRF6702 serial interface through provides an immediate indication of whether the software is the P3 4-pin header (P3 must be first installed, Samtec TSW- successfully communicating with the evaluation board. If the 104-08-G-S). evaluation board is connected to the PC via the USB cable EVALUATION BOARD CONTROL SOFTWARE provided and the software is successfully communicating with the on-board USB circuitry, this text box shows the following USB-based programming software is available to download message: ADRF6X0X eval board connected. from the ADRF6702 product page at www.analog.com (Evaluation Board Software Rev 6.1.0). To install the software, download and extract the zip file. Then run the following installation file: ADRF6X0X_6p1p0_customer_installer.exe. Rev. B | Page 30 of 36

Data Sheet ADRF6702 VCC R43 VR+CE5DCV C28 S2 1(004k0Ω2) (0R042Ω002) 10µF R47 (3216) 10kΩ (0402) C7 C27 C25 C23 C20 C19 C9 VCC 0(0.14µ0F2) 0(0.14µ0F2) 0(0.14µ0F2) 0(0.14µ0F2) 0(0.14µ0F2) 0(0.14µ02F) 0(0.14µ0F2) LE (USB) R39 DATA (USB) 10kΩ C8 C26 C24 C22 C21 C18 C10 CLK (USB) S1 (0402) VDD 1(0V040D0pD2F) 1(0V04D00pD2F) 1(00V40D0pD2F) 1(00V40D0p2DF) 1(00V40D0p2DF) 1(00V40D0pD2F) 1(00400p2F) ENOP CLK DATA LE (0140R0k42Ω0) LOSEL36 34 29 27 22 17 10 1 16 13 12 14 9 DECLC120106pF C0.117µF C104µ2F LON SPI (0402) (0402) (0603) EXT LO 54 31 1(00C4006p2F)LOP3387 BUFFER DIV÷ID2ER INTERFACE 2 DECLC110102pF C0.111µF CO4P1EN MABAT-030715910C05pF FRARCETGION MODULUS INTREEGGER BUFFER M2U:1X (0402) (0402) (0603) (0402) ADRF6702 QP RSEEFE_( I4T0N9E4R.0X972ΩT3) 1(0C04020p92F) REFIN6 ÷÷×242 MUX TIENTFMTHREIPARRCDPT-OOIOLRANDTAEO–+LRRFREPNQH2 UCA1EOSTNEUOCN 1YT2E3R PC2550RH00EAµµSRAA÷CG ,2(ADEL EPEFURAMUPLT), CVOCROE 0÷/920 113892 QINN RRO(032P43E02N) QQINPN REFOUT OPEN SENSOR DETECTOR 750µA, OPEN ORP1E6N MUXOUT 8 4 7 11 15 20 21 23 25 28 30 31 35 241000µA 5 3 39 40 26 33 IP (0402) IP (0402) NC R2 RSET CP VTUNE DECL3 ROFPOEUNT GNDTECSPT (O0RP430E82N) (0RR04(3Ω9007 241)002k(O0)ΩP40E2RN)6(0541002k)Ω R0(0Ω64202) VOTPUENNE 1(00C4003p2F) RFOUT (OPOPEINNT) 2C2p1F4 R3(0k16Ω003) C6.183pF C224p0F (O0RP460E32N) (0603) C15 (0603) (0603) 2.7nF (1206) R11 R12 OPEN 0Ω (0402) (0402) C43 C2 C1 10µF OPEN 100pF N1.O NTCE S= NO CONNECT. DO NOT CONNECTTO THIS PIN. (0603) (0402) (0402) 08568-027 Figure 52. Evaluation Board Schematic (Loop Filter Set to 130 kHz) 08568-047 Figure 54. Evaluation Board Bottom Layer 08568-048 Figure 53. Evaluation Board Top Layer Rev. B | Page 31 of 36

ADRF6702 Data Sheet Table 11. Evaluation Board Configuration Options Default Condition/Option Component Description Settings S1, R39, R40 LO select. Switch and resistors to ground LOSEL pin. The LOSEL pin setting in combination with internal register settings, determines whether the LOP/LON pins function as inputs or outputs. With the LOSEL pin grounded, register settings can set the LOP/LON pins to be inputs or outputs. EXT LO, T3 LO input/output. An external 1× LO or 2× LO can be applied to T3 = Macom MABA-007159 this single-ended input connector. Alternatively, the internal EXT LO SMA connector = installed 1× or 2× LO can be brought out on this pin. The differential LO signal on LOP and LON is converted to a single-ended signal using a broadband 1:1 balun (Macom MABA-007159, 4.5 MHz to 3000 MHz frequency range). The balun footprint on the evaluation board is also designed to accommodate Johanson baluns: 3600BL14M050 (1:1, 3.3 GHz to 3.9 GHz) and 3700BL15B050E (1:1, 3.4 GHz to 4 GHz). REFIN SMA Connector, R73 Reference input. The input reference frequency for the PLL is F = 153.6 MHz REFIN applied to this connector. Input resistance is set by R73 (49.9 Ω). R73 = 49.9 Ω REFOUT SMA Connector, R16 Multiplexer output. The REFOUT connector connects directly REFOUT SMA connector = open to the device’s MUXOUT pin. The on-board multiplexer can R16 = open be programmed to bring out the following signals: REFIN, 2× REFIN, REFIN/2, REFIN/4, Temperature sensor output voltage (VPTAT), Lock detect indicator. CP Test Point, R38 Charge pump test point. The unfiltered charge pump signal CP = open can be probed at this test point. Note that this pin should not R38 = open be probed during critical measurements such as phase noise. C13, C14, C15, C40R9, R10, R37, R65 Loop filter. Loop filter components. See Table 8 R11, R12, R62, R63, VTUNE SMA Internal vs. external VCO. When the internal VCO is enabled, R12 = 0 Ω (0402) Connector the loop filter components connect directly to the VTUNE pin R11 = open (0402) (Pin 39) by installing a 0 Ω resistor in R62. In addition, the loop R62 = 0 Ω (0402) filter components should be returned to Pin 40 (DECL3) by R63 = open (0402) installing a 0 Ω resistor in R12. VTUNE = open To use an external VCO, R62 should be left open. A 0 Ω resistor should be installed in R63, and the voltage input of the VCO should be connected to the VTUNE SMA connector. The output of the VCO is brought back into the PLL via the LO IN/OUT SMA connector. In addition, the loop filter components should be returned to ground by installing a 0 Ω resistor in R11. Loop filter return. R2 RSET. This pin is unused and should be left open. R2 = open (0402) R23, R3 Baseband input termination. Termination resistors for the R3 = R23 = open (0402) baseband filter of the DAC can be placed on R23 and R3. In addition to terminating the baseband filters, these resistors also scale down the baseband voltage from the DAC without changing the bias level. These resistors are generally set in the 100 Ω to 300 Ω range. P3 4-Pin Header, R15, R17, R18 USB circuitry bypass. The USB circuitry can be bypassed, P3 = open allowing for the serial port of the ADRF6702 to be driven R15, R17, R18 = 0 Ω (0402) directly. P3 (Samtec TSW-104-08-G-S) must be installed, and 0 Ω resistors (R15, R17 and R18) must be removed. Rev. B | Page 32 of 36

Data Sheet ADRF6702 08568-136 Figure 55. Main Controls of the Evaluation Board Control Software Rev. B | Page 33 of 36

ADRF6702 Data Sheet 08568-028 Figure 56. USB Interface Circuitry on the Customer Evaluation Board Rev. B | Page 34 of 36

Data Sheet ADRF6702 OUTLINE DIMENSIONS 6.00 0.60 MAX BSC SQ 0.60 MAX PIN 1 INDICATOR 31 40 30 1 PIN 1 0.50 INDICATOR VTIOEPW BS5C.7 5SQ BSC EXPPAODSED 44..2150 SQ 0.50 (BOTTOM VIEW) 3.95 0.40 21 10 20 11 0.30 0.25 MIN 4.50 12° MAX 0.80 MAX REF 0.65 TYP 0.05 MAX FOR PROPER CONNECTION OF 1.00 0.02 NOM TTHHEE PEIXNP COOSNEDFI GPAUDR,A RTEIOFNE RA NTOD 0.85 0.30 FUNCTION DESCRIPTIONS 0.80 0.23 0.20 REF COPLANARITY SECTION OF THIS DATA SHEET. SEATING 0.08 PLANE 0.18 COMPLIANTTO JEDEC STANDARDS MO-220-VJJD-2 072108-A Figure 57. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm × 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters ORDERING GUIDE Model1 Temperature Range (°C) Package Description Package Option ADRF6702ACPZ-R7 −40°C to +85°C 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-40-1 ADRF6702-EVALZ Evaluation Board 1 Z = RoHS Compliant Part. Rev. B | Page 35 of 36

ADRF6702 Data Sheet NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08568-0-10/11(B) Rev. B | Page 36 of 36