1-/2-/4-Channel Digital Potentiometers AD8400/AD8402/AD8403 FEATURES FUNCTIONAL BLOCK DIAGRAM 256-position variable resistance device RDAC1 Replaces 1, 2, or 4 potentiometers AD8403 8-BIT 8 A1 1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VDD DAC LATCH BW11 Power shutdown—less than 5 μA DGND SELECT CKRS SHDN AGND1 1 3-wire,SPI-compatible serial data input 2 RDAC2 8 A2 10 MHz update data loading rate 3 L8A-TBCITH W2 A1,A0 4 B2 2.7 V to 5.5 V single-supply operation 2 CK RS SHDN AGND2 Qualified for automotive applications 10-BIT RDAC3 SERIAL 8 8-BIT 8 A3 LATCH LATCH W3 APPLICATIONS B3 SDI D CK RS SHDN AGND3 Mechanical potentiometer replacement CKQ RS CLK RDAC4 Programmable filters, delays, time constants 8-BIT 8 A4 CS LATCH W4 Volume control, panning B4 Line impedance matching CK RS SHDN AGND4 P ower supply adjustment SDO RS SHDN 01092-001 GENERAL DESCRIPTION Figure 1. The AD8400/AD8402/AD8403 provide a single-, dual-, or quad-channel, 256-position, digitally controlled variable resistor 100 (VR) device.1 These devices perform the same electronic adjust- RWA RWB ment function as a mechanical potentiometer or variable )B A R resistor. The AD8400 contains a single variable resistor in the al 75 n compact SOIC-8 package. The AD8402 contains two independent mi o variable resistors in space-saving SOIC-14 surface-mount of N packages. The AD8403 contains four independent variable % 50 resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each (D) (B W part contains a fixed resistor with a wiper contact that taps the R fixed resistor value at a point determined by the digital code (D), A 25 W loaded into the controlling serial input register. The resistance R between the wiper and either endpoint of the fixed resistor vthaer iVesR li lnaetcahrl.y E wacithh vraersipaebclte troe stihseto dri ogiftfaelr sc oad ceo mtrapnlestfeelryr ed into 00 64 CODE1(D28ecimal) 192 25501092-002 programmable value of resistance between the A terminal and Figure 2. RWA and RWB vs. Code the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs, avoiding any make-before-break or break-before-make operation. (continued on Page 3) 1 The terms digital potentiometer, VR, and RDAC are used interchangeably. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved.

AD8400/AD8402/AD8403 TABLE OF CONTENTS Features .............................................................................................. 1  ESD Caution................................................................................ 11  Applications ....................................................................................... 1  Pin Configurations and Function Descriptions ......................... 12  General Description ......................................................................... 1  Typical Performance Characteristics ........................................... 14  Functional Block Diagram .............................................................. 1  Test Circuits ..................................................................................... 19  Revision History ............................................................................... 2  Theory of Operation ...................................................................... 20  Specifications ..................................................................................... 4  Programming the Variable Resistor ......................................... 20  Electrical Characteristics—10 kΩ Version ................................ 4  Programming the Potentiometer Divider ............................... 21  Electrical Characteristics—50 kΩ and 100 kΩ Versions ......... 6  Digital Interfacing ...................................................................... 21  Electrical Characteristics—1 kΩ Version .................................. 8  Applications ..................................................................................... 24  Electrical Characteristics—All Versions ................................. 10  Active Filter ................................................................................. 24  Timing Diagrams ........................................................................ 10  Outline Dimensions ....................................................................... 26  Absolute Maximum Ratings .......................................................... 11  Ordering Guide .......................................................................... 30  Serial Data-Word Format .......................................................... 11  Automotive Products ................................................................. 31  REVISION HISTORY 7/10—Rev. D to Rev. E 11/01—Rev. B to Rev. C Changes to Features Section ............................................................ 1 Addition of new Figure ..................................................................... 1 Changes to IAB Continuous Current Parameter (Table 5) ......... 11 Edits to Specifications ....................................................................... 2 Updated Outline Dimensions ........................................................ 26 Edits to Absolute Maximum Ratings .............................................. 6 Changes to Ordering Guide ........................................................... 30 Edits to TPCs 1, 8, 12, 16, 20, 24, 35 ............................................... 9 Added Automotive Products Section ........................................... 31 Edits to the Programming the Variable Resistor Section .......................... 13 10/05—Rev. C to Rev. D Updated Format .................................................................. Universal Changes to Features ........................................................................... 1 Changes to Table 1 ............................................................................. 4 Changes to Table 2 ............................................................................. 6 Changes to Table 3 ............................................................................. 8 Changes to Table 5 ........................................................................... 11 Added Figure 36 ............................................................................... 18 Replaced Figure 37 .......................................................................... 19 Changes to Theory of Operation Section ..................................... 20 Changes to Applications Section ................................................... 24 Updated Outline Dimensions ........................................................ 26 Changes to Ordering Guide ........................................................... 28 Rev. E | Page 2 of 32

AD8400/AD8402/AD8403 GENERAL DESCRIPTION (continued from Page 1) Each VR has its own VR latch that holds its programmed The AD8400 is available in the SOIC-8 surface mount. The resistance value. These VR latches are updated from an SPI- AD8402 is available in both surface-mount (SOIC-14) and compatible, serial-to-parallel shift register that is loaded from 14-lead PDIP packages, while the AD8403 is available in a a standard 3-wire, serial-input digital interface. Ten data bits narrow-body, 24-lead PDIP and a 24-lead, surface-mount make up the data-word clocked into the serial input register. package. The AD8402/AD8403 are also offered in the 1.1 mm thin TSSOP-14/TSSOP-24 packages for PCMCIA applications. The data-word is decoded where the first two bits determine All parts are guaranteed to operate over the extended industrial the address of the VR latch to be loaded, and the last eight bits temperature range of −40°C to +125°C. are the data. A serial data output pin at the opposite end of the serial register allows simple daisy chaining in multiple VR applications without additional external decoding logic. The reset (RS) pin forces the wiper to midscale by loading 80 H into the VR latch. The SHDN pin forces the resistor to an end- to-end open-circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made that will produce new wiper positions when the device is taken out of shutdown. Rev. E | Page 3 of 32

AD8400/AD8402/AD8403 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—10 KΩ VERSION V = 3 V ± 10% or 5 V ± 10%, V = V , V = 0 V, −40°C ≤ T ≤ +125°C, unless otherwise noted. DD A DD B A Table 1. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL R , V = no connect −1 ±1/4 +1 LSB WB A Resistor Nonlinearity2 R-INL R , V = no connect −2 ±1/2 +2 LSB WB A Nominal Resistance3 R T = 25°C, model: AD840XYY10 8 10 12 kΩ AB A Resistance Tempco ΔR /ΔT V = V , wiper = no connect 500 ppm/°C AB AB DD Wiper Resistance R V = 5V, I = V /R 50 100 Ω W DD W DD AB R V = 3V, I = V /R 200 Ω W DD W DD AB Nominal Resistance Match ΔR/R CH 1 to CH 2, CH 3, or CH 4, V = V , T = 25°C 0.2 1 % AB AB DD A DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −2 ±1/2 +2 LSB Differential Nonlinearity4 DNL V = 5 V −1 ±1/4 +1 LSB DD DNL V = 3 V, T = 25°C −1 ±1/4 +1 LSB DD A DNL V = 3 V, T = −40°C to +85°C −1.5 ±1/2 +1.5 LSB DD A Voltage Divider Tempco ΔV /ΔT Code = 80 15 ppm/°C W H Full-Scale Error V Code = FF −4 −2.8 0 LSB WFSE H Zero-Scale Error V Code = 00 0 1.3 2 LSB WZSE H RESISTOR TERMINALS Voltage Range5 V 0 V V A, B, W DD Capacitance6 Ax, Capacitance Bx C f = 1 MHz, measured to GND, code = 80 75 pF A, B H Capacitance6 Wx C f = 1 MHz, measured to GND, code = 80 120 pF W H Shutdown Current7 I A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 μA Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 100 200 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High V V = 5 V 2.4 V IH DD Input Logic Low V V = 5 V 0.8 V IL DD Input Logic High V V = 3 V 2.1 V IH DD Input Logic Low V V = 3 V 0.6 V IL DD Output Logic High V R = 2.2 kΩ to V V − 0.1 V OH L DD DD Output Logic Low V I = 1.6 mA, V = 5 V 0.4 V OL OL DD Input Current I V = 0 V or 5 V, V = 5 V ±1 μA IL IN DD Input Capacitance6 C 5 pF IL POWER SUPPLIES Power Supply Range V range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 5 μA DD IH DD IL Supply Current (TTL)8 I V = 2.4 V or 0.8 V, V = 5.5 V 0.9 4 mA DD IH DD Power Dissipation (CMOS)9 P V = V or V = 0 V, V = 5.5 V 27.5 μW DISS IH DD IL DD Power Supply Sensitivity PSS V = 5 V ± 10% 0.0002 0.001 %/% DD PSS V = 3 V ± 10% 0.006 0.03 %/% DD Rev. E | Page 4 of 32

AD8400/AD8402/AD8403 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth −3 dB BW_10 K R = 10 kΩ 600 kHz Total Harmonic Distortion THD V = 1 V rms + 2 V dc, V = 2 V dc, f = 1 kHz 0.003 % W A B V Settling Time t V = V , V = 0 V, ±1% error band 2 μs W S A DD B Resistor Noise Voltage eNWB RWB = 5 kΩ, f = 1 kHz, RS = 0 9 nV/√Hz Crosstalk11 C V = V , V = 0 V −65 dB T A DD B 1 Typical represents average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38. IW = 50 μA for VDD = 3 V and IW = 400 μA for VDD = 5 V for the 10 kΩ versions. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. Rev. E | Page 5 of 32

AD8400/AD8402/AD8403 ELECTRICAL CHARACTERISTICS—50 KΩ AND 100 KΩ VERSIONS V = 3 V ± 10% or 5 V ± 10%, V = V , V = 0 V, −40°C ≤ T ≤ +125°C, unless otherwise noted. DD A DD B A Table 2. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL R , V = No Connect −1 ±1/4 +1 LSB WB A Resistor Nonlinearity2 R-INL R , V = No Connect −2 ±1/2 +2 LSB WB A Nominal Resistance3 R T = 25°C, Model: AD840XYY50 35 50 65 kΩ AB A R T = 25°C, Model: AD840XYY100 70 100 130 kΩ AB A Resistance Tempco ΔR /ΔT V = V , Wiper = No Connect 500 ppm/°C AB AB DD Wiper Resistance R V = 5V, I = V /R 50 100 Ω W DD W DD AB R V = 3V, I = V /R 200 Ω W DD W DD AB Nominal Resistance Match ΔR/R CH 1 to CH 2, CH 3, or CH 4, V = V , T = 25°C 0.2 1 % AB AB DD A DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −4 ±1 +4 LSB Differential Nonlinearity4 DNL V = 5 V −1 ±1/4 +1 LSB DD DNL V = 3 V, T = 25°C −1 ±1/4 +1 LSB DD A DNL V = 3 V, T = −40°C to +85°C −1.5 ±1/2 +1.5 LSB DD A Voltage Divider Tempco ΔV /ΔT Code = 80 15 ppm/°C W H Full-Scale Error V Code = FF −1 −0.25 0 LSB WFSE H Zero-Scale Error V Code = 00 0 +0.1 +1 LSB WZSE H RESISTOR TERMINALS Voltage Range5 V , V , V 0 V V A B W DD Capacitance6 Ax, Bx C , C f = 1 MHz, measured to GND, code = 80 15 pF A B H Capacitance6 Wx C f = 1 MHz, measured to GND, code = 80 80 pF W H Shutdown Current7 I A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 μA Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 100 200 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High V V = 5 V 2.4 V IH DD Input Logic Low V V = 5 V 0.8 V IL DD Input Logic High V V = 3 V 2.1 V IH DD Input Logic Low V V = 3 V 0.6 V IL DD Output Logic High V R = 2.2 kΩ to V V − 0.1 V OH L DD DD Output Logic Low V I = 1.6 mA, V = 5 V 0.4 V OL OL DD Input Current I V = 0 V or 5 V, V = 5 V ±1 μA IL IN DD Input Capacitance6 C 5 pF IL POWER SUPPLIES Power Supply Range V range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 5 μA DD IH DD IL Supply Current (TTL)8 I V = 2.4 V or 0.8 V, V = 5.5 V 0.9 4 mA DD IH DD Power Dissipation (CMOS)9 P V = V or V = 0 V, V = 5.5 V 27.5 μW DISS IH DD IL DD Power Supply Sensitivity PSS V = 5 V ± 10% 0.0002 0.001 %/% DD PSS V = 3 V ± 10% 0.006 0.03 %/% DD Rev. E | Page 6 of 32

AD8400/AD8402/AD8403 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth −3 dB BW_50 K R = 50 kΩ 125 kHz BW_100 K R = 100 kΩ 71 kHz Total Harmonic Distortion THD V = 1 V rms + 2 V dc, V = 2 V dc, f = 1 kHz 0.003 % W A B V Settling Time t_50 K V = V , V = 0 V, ±1% error band 9 μs W S A DD B t _100 K V = V , V = 0 V, ±1% error band 18 μs S A DD B Resistor Noise Voltage eNWB_50 K RWB = 25 kΩ, f = 1 kHz, RS = 0 20 nV/√Hz e NWB_100 K RWB = 50 kΩ, f = 1 kHz, RS = 0 29 nV/√Hz Crosstalk11 C V = V , V = 0 V −65 dB T A DD B 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38. IW = VDD/R for VDD = 3 V or 5 V for the 50 kΩ and 100 kΩ versions. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. Rev. E | Page 7 of 32

AD8400/AD8402/AD8403 ELECTRICAL CHARACTERISTICS—1 KΩ VERSION V = 3 V ± 10% or 5 V ± 10%, V = V , V = 0 V, −40°C ≤ T ≤ +125°C, unless otherwise noted. DD A DD B A Table 3. Parameter Symbol Conditions Min Typ1 Max Unit DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs) Resistor Differential NL2 R-DNL R , V = no connect −5 −1 +3 LSB WB A Resistor Nonlinearity2 R-INL R , V = no connect −4 ±1.5 +4 LSB WB A Nominal Resistance3 R T = 25°C, model: AD840XYY1 0.8 1.2 1.6 kΩ AB A Resistance Tempco ΔR /ΔT V = V , wiper = no connect 700 ppm/°C AB AB DD Wiper Resistance R V = 5V, I = V /R 53 100 Ω W DD W DD AB R V = 3V, I = V /R 200 Ω W DD W DD AB Nominal Resistance Match ΔR/R CH 1 to CH 2, V = V , T = 25°C 0.75 2 % AB AB DD A DC CHARACTERISTICS POTENTIOMETER DIVIDER (Specifications Apply to All VRs) Resolution N 8 Bits Integral Nonlinearity4 INL −6 ±2 +6 LSB Differential Nonlinearity4 DNL V = 5 V −4 −1.5 +2 LSB DD DNL V = 3 V, T = 25°C −5 −2 +5 LSB DD A Voltage Divider Temperature Coefficient ΔV /ΔT Code = 80H 25 ppm/°C W Full-Scale Error V Code = FF −20 −12 0 LSB WFSE H Zero-Scale Error V Code = 00 0 6 10 LSB WZSE H RESISTOR TERMINALS Voltage Range5 V , V , V 0 V V A B W DD Capacitance6 Ax, Bx C , C f = 1 MHz, measured to GND, code = 80 75 pF A B H Capacitance6 Wx C f = 1 MHz, measured to GND, code = 80 120 pF W H Shutdown Supply Current7 I A_SD VA = VDD, VB = 0 V, SHDN = 0 0.01 5 μA Shutdown Wiper Resistance RW_SD VA = VDD, VB = 0 V, SHDN = 0, VDD = 5 V 50 100 Ω DIGITAL INPUTS AND OUTPUTS Input Logic High V V = 5 V 2.4 V IH DD Input Logic Low V V = 5 V 0.8 V IL DD Input Logic High V V = 3 V 2.1 V IH DD Input Logic Low V V = 3 V 0.6 V IL DD Output Logic High V R = 2.2 kΩ to V V − 0.1 V OH L DD DD Output Logic Low V I = 1.6 mA, V = 5 V 0.4 V OL OL DD Input Current I V = 0 V or 5 V, V = 5 V ±1 μA IL IN DD Input Capacitance6 C 5 pF IL POWER SUPPLIES Power Supply Range V range 2.7 5.5 V DD Supply Current (CMOS) I V = V or V = 0 V 0.01 5 μA DD IH DD IL Supply Current (TTL)8 I V = 2.4 V or 0.8 V, V = 5.5 V 0.9 4 mA DD IH DD Power Dissipation (CMOS)9 P V = V or V = 0 V, V = 5.5 V 27.5 μW DISS IH DD IL DD Power Supply Sensitivity PSS ΔV = 5 V ± 10% 0.0035 0.008 %/% DD PSS ΔV = 3 V ± 10% 0.05 0.13 %/% DD Rev. E | Page 8 of 32

AD8400/AD8402/AD8403 Parameter Symbol Conditions Min Typ1 Max Unit DYNAMIC CHARACTERISTICS6, 10 Bandwidth −3 dB BW_1 K R = 1 kΩ 5,000 kHz Total Harmonic Distortion THD V = 1 V rms + 2 V dc, V = 2 V dc, f = 1 kHz 0.015 % W A B V Settling Time t V = V , V = 0 V, ±1% error band 0.5 μs W S A DD B Resistor Noise Voltage eNWB RWB = 500 Ω, f = 1 kHz, RS = 0 3 nV/√Hz Crosstalk11 C V = V , V = 0 V −65 dB T A DD B 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. See the test circuit in Figure 38. IW = 500 μA for VDD = 3 V and IW = 2.5 mA for VDD = 5 V for 1 kΩ version. 3 VAB = VDD, wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All dynamic characteristics use VDD = 5 V. 11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. Rev. E | Page 9 of 32

AD8400/AD8402/AD8403 ELECTRICAL CHARACTERISTICS—ALL VERSIONS V = 3 V ± 10% or 5 V ± 10%, V = V , V = 0 V, −40°C ≤ T ≤ +125°C, unless otherwise noted. DD A DD B A Table 4. Parameter Symbol Conditions Min Typ1 Max Unit SWITCHING CHARACTERISTICS2, 3 Input Clock Pulse Width t , t Clock level high or low 10 ns CH CL Data Setup Time t 5 ns DS Data Hold Time t 5 ns DH CLK to SDO Propagation Delay4 t R = 1 kΩ to 5 V, C ≤ 20 pF 1 25 ns PD L L CS Setup Time tCSS 10 ns CS High Pulse Width tCSW 10 ns Reset Pulse Width t 50 ns RS CLK Fall to CS Rise Hold Time tCSH 0 ns CS Rise to Clock Rise Setup tCS1 10 ns 1 Typicals represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 3 See the timing diagram in Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = 3 V or 5 V. To avoid false clocking, a minimum input logic slew rate of 1 V/μs should be maintained. 4 Propagation delay depends on the value of VDD, RL, and CL (see the Applications section). TIMING DIAGRAMS 1 SDI A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 CLK t 0 1 RS DACREGISTERLOAD RS 1 0 CS t VOUTV0DVD0 01092-003 VOUTVDVDD/D2 ±1%ERRORSBAND ±1% 01092-005 Figure 3. Timing Diagram Figure 5. Reset Timing Diagram 1 (DATAS IND)I Ax ORDx Ax ORDx 0 tDS tDH 1 SDO (DATA OUT) A'xORD'x A'xORD'x 0 tPD_MIN tPD_MAX 1 tCH tCS1 CLK 0 tCL 1 tCSS tCSH CS tCSW 0 tS VDD ±1% VOUT0V ±1%ERRORBAND 01092-004 Figure 4. Detailed Timing Diagram Rev. E | Page 10 of 32

AD8400/AD8402/AD8403 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 5. Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress VDD to GND −0.3 V, +8 V rating only; functional operation of the device at these or any VA, VB, VW to GND 0 V, VDD other conditions above those indicated in the operational Maximum Current section of this specification is not implied. Exposure to absolute IWB, IWA Pulsed ±20 mA maximum rating conditions for extended periods may affect IWB Continuous (RWB ≤ 1 kΩ, A Open)1 ±5 mA device reliability. I Continuous (R ≤ 1 kΩ, B Open)1 ±5 mA WA WA I Continuous (R = 1 kΩ/10 kΩ/ ±2.1 mA/±2.1 mA/ AB AB 50 kΩ/100 kΩ)1 ±540 μA/±540 μA SERIAL DATA-WORD FORMAT Digital Input and Output Voltage 0 V, 7 V to GND Table 6. Operating Temperature Range −40°C to +125°C ADDR DATA Maximum Junction Temperature 150°C B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 (TJ Maximum) A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Storage Temperature −65°C to +150°C MSB LSB MSB LSB Lead Temperature (Soldering, 10 sec) 300°C 29 2 8 2 7 2 0 Package Power Dissipation (T max − T )/θ J A JA Thermal Resistance (θ ) JA SOIC (R-8) 158°C/W PDIP (N-14) 83°C/W PDIP (N-24) 63°C/W SOIC (R-14) 120°C/W SOIC (R-24) 70°C/W TSSOP-14 (RU-14) 180°C/W TSSOP-24 (RU-24) 143°C/W 1 Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package; VDD = 5 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. E | Page 11 of 32

AD8400/AD8402/AD8403 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS B1 1 8 A1 AGND 1 14 B1 AGND2 1 24 B1 GND 2 AD8400 7 W1 B2 2 13 A1 B2 2 23 A1 SCDSI 34 (NToOtPtoVSIEcWale) 65 VCDLDK01092-006 WA22 34 (NAToOtDPto8V4SIE0cWa2le) 1112 WVD1D AGNWDA422 345 AD8403 222210 WABG31ND1 Figure 6. AD8400 Pin Configuration DGND 5 10 RS TOPVIEW B4 6 (NottoScale) 19 A3 SHDN 6 9 CLK CS 7 8 SDI 01092-007 WA44 78 1187 WAG3ND3 Figure 7. AD8402 Pin Configuration DGND 9 16 VDD SHDN 10 15 RS SCDSI 1112 1143 CSDLKO 01092-008 Figure 8. AD8403 Pin Configuration Table 7. AD8400 Pin Function Descriptions Pin No. Mnemonic Description 1 B1 Terminal B RDAC. 2 GND Ground. 3 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 4 SDI Serial Data Input. 5 CLK Serial Clock Input, Positive Edge Triggered. 6 V Positive Power Supply. Specified for operation at both 3 V and 5 V. DD 7 W1 Wiper RDAC, Addr = 00. 2 8 A1 Terminal A RDAC. Table 8. AD8402 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND Analog Ground.1 2 B2 Terminal B RDAC 2. 3 A2 Terminal A RDAC 2. 4 W2 Wiper RDAC 2, Addr = 01. 2 5 DGND Digital Ground.1 6 SHDN Terminal A Open Circuit. Shutdown controls Variable Resistor 1 and Variable Resistor 2. 7 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 8 SDI Serial Data Input. 9 CLK Serial Clock Input, Positive Edge Triggered. 10 RS Active Low Reset to Midscale. Sets RDAC registers to 80H. 11 V Positive Power Supply. Specified for operation at both 3 V and 5 V DD 12 W1 Wiper RDAC 1, Addr = 00. 2 13 A1 Terminal A RDAC 1. 14 B1 Terminal B RDAC 1. 1 All AGND pins must be connected to DGND. Rev. E | Page 12 of 32

AD8400/AD8402/AD8403 Table 9. AD8403 Pin Function Descriptions Pin No. Mnemonic Description 1 AGND2 Analog Ground 2.1 2 B2 Terminal B RDAC 2. 3 A2 Terminal A RDAC 2. 4 W2 Wiper RDAC 2, Addr = 01. 2 5 AGND4 Analog Ground 4.1 6 B4 Terminal B RDAC 4. 7 A4 Terminal A RDAC 4. 8 W4 Wiper RDAC 4, Addr = 11. 2 9 DGND Digital Ground.1 10 SHDN Active Low Input. Terminal A open circuit. Shutdown controls Variable Resistor 1 through Variable Resistor 4. 11 CS Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded, based on the address bits, and loaded into the target DAC register. 12 SDI Serial Data Input. 13 SDO Serial Data Output. Open drain transistor requires a pull-up resistor. 14 CLK Serial Clock Input, Positive Edge Triggered. 15 RS Active Low Reset to Midscale. Sets RDAC registers to 80H. 16 V Positive Power Supply. Specified for operation at both 3 V and 5 V. DD 17 AGND3 Analog Ground 3.1 18 W3 Wiper RDAC 3, Addr = 10. 2 19 A3 Terminal A RDAC 3. 20 B3 Terminal B RDAC 3. 21 AGND1 Analog Ground 1.1 22 W1 Wiper RDAC 1, Addr = 00. 2 23 A1 Terminal A RDAC 1. 24 B1 Terminal B RDAC 1. 1 All AGND pins must be connected to DGND. Rev. E | Page 13 of 32

AD8400/AD8402/AD8403 TYPICAL PERFORMANCE CHARACTERISTICS 10 60 VDD=3V OR5V SS=1205UNITS RAB=10kΩ VDD=4.5V TA=25°C  8 48 )Ω ESISTANCE (k 64 FREQUENCY 3264 R 2 12 RWB RWA 0 0 0 32 64 9C6ODE1(D28ecima1l)60 192 224 25601092-009 40.0 42.5 45.0 4W7.5IPE5R0.0RE5S2IS.5TA5N5C.0E(5Ω7).5 60.0 62.5 65.0 01092-012 Figure 9. Wiper to End Terminal Resistance vs. Code Figure 12. 10 kΩ Wiper-Contact-Resistance Histogram 5 1.0 80H VDD=5V FFH 4 B) S 40H R (L 0.5 E (V) 3 20H RRO TA=+25°C AG Y E TA=–40°C V VOLTWB 2 CODE=10H NLINEARIT 0 O N –0.5 1 NL TA=+85°C 05H TA=25°C I VDD=5V 00 1 2 IWBC3URRENT4(mA) 5 6 701092-010 –1.0 0 32 6D4IGITAL96 INPUT12C8ODE1(D60ecima1l)92 224 25601092-013 Figure 10. Resistance Linearity vs. Conduction Current Figure 13. Potentiometer Divider Nonlinearity Error vs. Code 1.0 60 VDD=5V SVSDD==184.45VUNITS TA=25°C 48 0.5 B) TA=+85°C S R (L NCY 36 O E R 0 U R Q E E NL TA=–40°C FR 24 R-I TA=+25°C –0.5 12 –1.00 32 6D4IGITA9L6 INPUT12C8ODE1(D60ecima1l9)2 224 25601092-011 0 35 37 39 4W1IPE4R3RES4I5STAN4C7E(Ω49) 51 53 55 01092-014 Figure 11. Resistance Step Position Nonlinearity Error vs. Code Figure 14. 50 kΩ Wiper-Contact-Resistance Histogram Rev. E | Page 14 of 32

AD8400/AD8402/AD8403 60 700 SS=184UNITS VDD=5V TVADD==254°.C5V C) 600 VTAA==–N4O0°CCO/+N8N5°ECCT 48 m/° RWBMEASURED p 500 p O ( FREQUENCY 3264 MODE TEMPC 324000000 T A T S 100 O 12 E H R 0 0 –100 40.0 42.5 45.0 4W7.5IPE5R0.R0ES52IS.5TA5N5C.0E(5Ω7).5 60.0 62.5 65.0 01092-015 0 32 64 9C6ODE1(D28ecima1l)60 192 224 25601092-018 Figure 15. 100 kΩ Wiper-Contact-Resistance Histogram Figure 18. ΔRWB/ΔT Rheostat Mode Tempco 10 20mV RAB(END-TO-END) 8 )Ω k CE ( RW AN 6 (20mV/DIV) T S SI E NAL R 4 RCOWDBE(W=IP80EHR-TO-END) MI O N CS 2 (5V/DIV) RAB=10kΩ 5V 500ns 0–75 –50 –25 TE0MPERA2T5URE(5°C0) 75 100 12501092-016 TIME500ns/DIV 01092-019 Figure 16. Nominal Resistance vs. Temperature Figure 19. One Position Step Change at Half-Scale (Code 7FH to 80H) 6 70 O (ppm/C)° 6500 VVTVADABD====–204VV50V°C/+85°C –1–260 C84O00DE=FF C P 20 ODE TEM 3400 AIN (dB) ––1284 1008 R M G –30 04 E 20 MET –36 02 TIO 10 –42 N 01 E POT 0 –48 TA=25°C –100 32 64 9C6ODE1(D28ecima1l)60 192 224 25601092-017 –5410 100 FR1EkQUENCY(1H0zk) 100k 1M01092-020 Figure 20. 10 kΩ Gain vs. Frequency vs. Code Figure 17. ΔVWB/ΔT Potentiometer Mode Tempco (See Figure 43) Rev. E | Page 15 of 32

AD8400/AD8402/AD8403 0.75 10 CODE=80H FILTER=22kHz VDD=5V VDD=5V 0.50 SS=158UNITS TA=25°C 1 E (%) 0.25 AVERAGE+2SIGMA %) NC E ( A S ST 0 AVERAGE OI 0.1 ESI + N R D B H W–0.25 T RΔ AVERAGE–2SIGMA 0.01 –0.50 –0.750 100 HOU2R0S0 OF OPE3R00ATIONA4T01050°C 500 60001092-021 0.00110 100 FREQUE1NkCY(Hz) 10k 100k01092-024 Figure 21. Long-Term Drift Accelerated by Burn-In Figure 24. Total Harmonic Distortion Plus Noise vs. Frequency (See Figure 41 and Figure 42) 2V 45.25μs OUTPUT VOUT (50mV/DIV) INPUT 5V 5μs 50mV 200ns TIME500μs/DIV 01092-022 TIME200ns/DIV 01092-025 Figure 22. Large Signal Settling Time Figure 25. Digital Feedthrough vs. Time 6 6 CODE=FFH CODE=FFH 0 0 80H –6 –6 –12 80H –12 40H dB) –18 2400HH dB) –18 2100HH N ( –24 N ( –24 GAI –30 10H GAI –30 08H 08H 04H –36 –36 04H 02H –42 –42 02H 01H –48 –48 01H –541k 10kFREQUENCY(H1z0)0k 1M01092-023 –541k 10kFREQUENCY(Hz1)00k 1M01092-026 Figure 23. 50 kΩ Gain vs. Frequency vs. Code Figure 26. 100 kΩ Gain vs. Frequency vs. Code Rev. E | Page 16 of 32

AD8400/AD8402/AD8403 12 B/DIV) TCVADODD==E255=°VC80H 6 f–3dB=700kHz,R=10kΩ 1d 0 0. SS ( –6 ATNE R=10kΩ dB) –12 f–3dB=71kHz,R=100kΩ X N FL AIN ( –18 f–3dB=125kHz,R=50kΩ AI G G D R=50kΩ –24 E Z ALI –30 M NOR R=100kΩ –36 VVIDND==150V0mVrms RL=1MΩ –42 10 100 FR1kEQUENCY1(H0kz) 100k 1M01092-027 1k 10kFREQUENCY(Hz)100k 1M01092-030 Figure 27. Normalized Gain Flatness vs. Frequency Figure 30. −3 dB Bandwidths (See Figure 43) 10 1200 TA=25°C A:VDD=5.5V TA=25°C CODE=55H 1000 B:VDD=3.3V A) A) CODE=55H ENT (m 1 ENT (μ 800 CD::VVCDDODDD==E53=..53FVVFH RR RR CODE=FFH U U PLY C VDD=5V PLY C 600 P P I – SUDD 0.1 I – SUDD 400 A B VDD=3V 200 C D 0.01 0 0 1 DIGITAL2 INPUTVOLT3AGE(V) 4 501092-028 1k 10k FREQU1E0N0kCY(Hz) 1M 10M01092-031 Figure 28. Supply Current vs. Digital Input Voltage Figure 31. Supply Current vs. Clock Frequency 80 160 TVCADOD=D=E25+=°5C8V0DHC±1Vp-pAC 140 TA=25°C CL=10pF VDD=2.7V 60 VA=4V,VB=0V 120 100 B) RR (d 40 ()ΩON 80 PS R VDD=5.5V 60 20 40 20 0100 1k FREQU1E0NkCY(Hz) 100k 1M01092-029 00 1 2 VBIA3S(V) 4 5 601092-032 Figure 29. Power Supply Rejection Ratio vs. Frequency Figure 32. AD8403 Incremental Wiper On Resistance vs. VDD (See Figure 40) (See Figure 39) Rev. E | Page 17 of 32

AD8400/AD8402/AD8403 1 LOGIC INPUT B) 0 VOLTAGE=0,VDD d N ( –10 GAI –20 A)μ NT ( 0.1 E R s) R PHASE (Degree ––49500 TVADD==255°VC I – SUPPLY CUDD 0.01 VDD=5.5V WHAIPLEFR-SSCEATLEAT80H VDD=3.3V 100k 200k 400k FREQUE1MNCY(Hz)2M 4M 6M 10M01092-033 0.001–55 –35 –15 5TEMP2E5RATU4R5E(°C)65 85 105 12501092-035 Figure 33. 1 kΩ Gain and Phase vs. Frequency Figure 35. Supply Current vs. Temperature 100 6 VDD=5V 5 RAB= 1kΩ RRENT (nA) (mA)B_MAX 4 TVAA== 2V5B°C=OPEN U W WN C 10 CAL I 3 DO ETI SHUTA THEOR 2 RAB= 10kΩ I 1 RAB= 50kΩ RAB= 100kΩ 1–55 –35 –15 5TEMP2E5RATU4R5E(°C)65 85 105 12501092-034 00 32 64 9C6ODE 1(D2e8cima1l)60 192 224 256 01092-057 Figure 34. Shutdown Current vs. Temperature Figure 36. IWB_MAX vs. Code Rev. E | Page 18 of 32

AD8400/AD8402/AD8403 TEST CIRCUITS A DUT B DUT V+=VDD W 5V V+ AW 1LSB=V+/256 ~ VIN OP279 VOUT OFFSET B VMS 01092-036 GND 2.5VDC 01092-040 Figure 37. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 41. Inverting Programmable Gain NOCONNECT 5V VOUT DAUWT IW VIN ~ W OP279 B OFFSET A B VMS 01092-037 GND 2.5V DUT 01092-041 Figure 38. Resistor Position Nonlinearity Error Figure 42. Noninverting Programmable Gain (Rheostat Operations; R-INL, R-DNL) DUT A +15V VMS2 A W VW IW=VDD/RNOMINAL VIN ~ DUT W OP42 VOUT B OFFSET B VMS1 RW=[VMS1–VMS2]/IW01092-038 GND 2.5V –15V 01092-042 Figure 39. Wiper Resistance Figure 43. Gain vs. Frequency 0.1V DUT RSW= ISW VA W CODE= H V+ ~ VDD AW PVS+R=RV(DdDB±)=102%0LOG(ΔVMS) B ISW +–0.1V B VMS ΔVDD PSS(%/%)=ΔΔVVMDDS%% 01092-039 VBIAS A=NC01092-043 Figure 40. Power Supply Sensitivity (PSS, PSRR) Figure 44. Incremental On Resistance Rev. E | Page 19 of 32

AD8400/AD8402/AD8403 THEORY OF OPERATION The AD8400/AD8402/AD8403 provide a single, dual, and quad PROGRAMMING THE VARIABLE RESISTOR channel, 256-position, digitally controlled variable resistor (VR) Rheostat Operation device. Changing the programmed VR setting is accomplished The nominal resistance of the VR (RDAC) between Terminal A by clocking in a 10-bit serial data-word into the SDI (Serial and Terminal B is available with values of 1 kΩ, 10 kΩ, 50 kΩ, Data Input) pin. The format of this data-word is two address and 100 kΩ. The final digits of the part number determine the bits, MSB first, followed by eight data bits, also MSB first. nominal resistance value; that is, 10 kΩ = 10; 100 kΩ = 100. Table 6 provides the serial register data-word format. The The nominal resistance (R ) of the VR has 256 contact points AD8400/AD8402/AD8403 have the following address assign- AB accessible by the wiper terminal, and the resulting resistance ments for the ADDR decoder, which determines the location can be measured either across the wiper and B terminals (R ) of the VR latch receiving the serial register data in Bit B7 to WB or across the wiper and A terminals (R ). The 8-bit data-word Bit B0: WA loaded into the RDAC latch is decoded to select one of the VR# = A1 × 2 + A0 + 1 (1) 256 possible settings. The wiper’s first connection starts at the B terminal for data 00 . This B terminal connection has a wiper The single-channel AD8400 requires A1 = A0 = 0. The dual- H contact resistance of 50 Ω. The second connection (for the 10 kΩ channel AD8402 requires A1 = 0. VR settings can be changed part) is the first tap point located at 89 Ω = [R (nominal one at a time in random sequence. A serial clock running at AB resistance) + R = 39 Ω + 50 Ω] for data 01 . The third 10 MHz makes it possible to load all four VRs under 4 μs W H connection is the next tap point representing 78 Ω + 50 Ω = (10 × 4 × 100 ns) for AD8403. The exact timing requirements 128 Ω for data 02 . Each LSB data value increase moves the are shown in Figure 3, Figure 4, and Figure 5. H wiper up the resistor ladder until the last tap point is reached at The AD8400/AD8402/AD8403 do not have power-on midscale 10,011 Ω. Note that the wiper does not directly connect to the preset, so the wiper can be at any random position at power-up. B terminal even for data 00H. See Figure 45 for a simplified However, the AD8402/AD8403 can be reset to midscale by diagram of the equivalent RDAC circuit. asserting the RS pin, simplifying initial conditions at power-up. The AD8400 contains one RDAC, the AD8402 contains Both parts have a power shutdown SHDN pin that places the two independent RDACs, and the AD8403 contains four VR in a zero-power-consumption state where Terminal Ax is independent RDACs. The general transfer equation that open-circuited and the Wiper Wx is connected to Terminal Bx, determines the digitally programmed output resistance resulting in the consumption of only the leakage current in the between Wx and Bx is VR. In shutdown mode, the VR latch settings are maintained so that upon returning to the operational mode, the VR settings R (D)= D × R + R (2) return to the previous resistance values. The digital interface is WB 256 AB W still active in shutdown, except that SDO is deactivated. Code where D, in decimal, is the data loaded into the 8-bit RDAC# changes in the registers can be made during shutdown that will latch, and R is the nominal end-to-end resistance. produce new wiper positions when the device is taken out of AB shutdown. For example, when the A terminal is either open-circuited or tied to the Wiper W, the following RDAC latch codes result in Ax SHDN RS the following RWB (for the 10 kΩ version): Table 10. RS D7 D (Dec) R (Ω) Output State D6 WB D5 255 10,011 Full scale D4 RS D3 128 5,050 Midscale (RS = 0 condition) D2 D1 1 89 1 LSB D0 Wx 0 50 Zero-scale (wiper contact resistance) Note that in the zero-scale condition, a finite wiper resistance of 50 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 mA to RDAC avoid degradation or possible destruction of the internal switch LATCH DECAONDDER RSRS=RNOMINAL/256 Bx 01092-044 c ontact. Figure 45. AD8402/AD8403 Equivalent VR (RDAC) Circuit Rev. E | Page 20 of 32

AD8400/AD8402/AD8403 Like a mechanical potentiometer, RDAC is symmetrical. The Here the output voltage is dependent on the ratio of the internal resistance between the Wiper W and Terminal A also produces resistors, not the absolute value; therefore, the temperature drift a digitally controlled complementary resistance, R . When improves to 15 ppm/°C. WA these terminals are used, the B terminal can be tied to the wiper At the lower wiper position settings, the potentiometer divider or left floating. R starts at the maximum and decreases as the WA temperature coefficient increases because the contribution of data loaded into the RDAC latch increases. The general transfer the CMOS switch wiper resistance becomes an appreciable equation for this R is WA portion of the total resistance from the B terminal to the 256−D Wiper W. See Figure 17 for a plot of potentiometer tempco R (D)= ×R +R (3) WA 256 AB W performance vs. code setting. where D is the data loaded into the 8-bit RDAC# latch, and R DIGITAL INTERFACING AB is the nominal end-to-end resistance. The AD8400/AD8402/AD8403 contain a standard SPI- compatible, 3-wire, serial input control interface. The three For example, when the B terminal is either open-circuited or inputs are clock (CLK), chip select (CS), and serial data input tied to the Wiper W, the following RDAC latch codes result in (SDI). The positive-edge sensitive CLK input requires clean the following R (for the 10 kΩ version): WA transitions to avoid clocking incorrect data into the serial input Table 11. register. For the best result, use logic transitions faster than D (Dec) R (Ω) Output State WA 1 V/μs. Standard logic families work well. If mechanical switches 255 89 Full-Scale are used for product evaluation, they should be debounced by 128 5,050 Midscale (RS = 0 Condition) a flip-flop or other suitable means. The block diagrams in 1 10,011 1 LSB Figure 46, Figure 47, and Figure 48 show the internal digital 0 10,050 Zero-Scale circuitry in more detail. When CS is taken active low, the clock loads data into the 10-bit serial register on each positive clock The typical distribution of RAB from channel to channel edge (see Table 12). matches within ±1%. However, device-to-device matching is process lot dependent and has a ±20% variation. The tem- CS VDD perature coefficient, or the change in RAB with temperature, CLK D7 A1 is 500 ppm/°C. EN RDAC W1 LATCH ADDR NO.1 B1 The wiper-to-end-terminal resistance temperature coefficient A1 DEC D0 A0 has the best performance over the 10% to 100% of adjustment D7 range where the internal wiper contact switches do not con- 10-BIT tribute any significant temperature related errors. The graph in RSEEGR AD8400 Figure 18 shows the performance of RWB tempco vs. code. Using SDI DI D0 the potentiometer with codes below 32 results in the larger 8 temperature coefficients plotted. GND 01092-045 PROGRAMMING THE POTENTIOMETER DIVIDER Figure 46. AD8400 Block Diagram Voltage Output Operation The digital potentiometer easily generates an output voltage CS AD8402 VDD proportional to the input voltage applied to a given terminal. CLK D7 A1 For example, connecting the A terminal to 5 V and the B termi- EN LRADTACCH W1 nal to ground produces an output voltage at the wiper starting ADDR NOR.1 B1 A1 DEC D0 at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage A0 applied across the A to B terminals divided by the 256-position D7 10-BIT D7 A4 resolution of the potentiometer divider. The general equation SER RDAC W4 REG LATCH defining the output voltage with respect to ground for any given SDI DI D0 NOR.2 B4 input voltage applied to the A to B terminals is D0 8 D VW = 256×VAB+VB (4) SHDN DGND RS AGND 01092-046 Operation of the digital potentiometer in the voltage divider Figure 47. AD8402 Block Diagram mode results in more accurate operation over temperature. Rev. E | Page 21 of 32

AD8400/AD8402/AD8403 If two AD8403 RDACs are daisy-chained, it requires 20 bits CS VDD of address and data in the format shown in Table 6. During CLK D7 A1 shutdown (SHDN = logic low), the SDO output pin is forced EN RDAC W1 LATCH to the off (logic high) state to disable power dissipation in the NO.1 B1 ADDR R pull-up resistor. See Figure 50 for equivalent SDO output circuit A1 DEC D0 SDO DO A0 schematic. D7 The data setup and hold times in the specification table deter- SER AD8403 REG mine the data valid time requirements. The last 10 bits of the data-word entered into the serial register are held when CS A4 returns high. At the same time CS goes high it gates the address SDI DI D0 D7 RDAC W4 decoder, which enables one of the two (AD8402) or four (AD8403) LATCH NO.4 B4 positive edge-triggered RDAC latches. See Figure 49 and Table 13. 8 D0 R Table 13. Address Decode Table A1 A0 Latch Decoded SHDN DGND RS AGND 01092-047 00 01 RRDDAACC##12 Figure 48. AD8403 Block Diagram 1 0 RDAC#3 AD8403 Only 1 1 RDAC#4 AD8403 Only Table 12. Input Logic Control Truth Table1 CLK CS RS SHDN Register Activity AD8403 RDAC1 L L H H No SR effect; enables SDO pin RDAC2 CS ADDR P L H H Shift one bit in from the SDI pin. The DECODE 10th previously entered bit is shifted RDAC4 out of the SDO pin. CLK X P H H Loona Ad1 S, RA 0d adteac iondtoe R(TDaAbCle l1at3c)h. based SDI RESGERISIATELR 01092-048 X H H H No operation Figure 49. Equivalent Input Control Logic X X L H Sets all RDAC latches to midscale, wiper centered, and SDO latch The target RDAC latch is loaded with the last eight bits of the cleared serial data-word completing one RDAC update. In the case of X H P H Latches all RDAC latches to 80 H AD8403, four separate 10-bit data-words must be clocked in to X H H L Open-circuits all Resistor A terminals, change all four VR settings. connects W to B, turns off SDO output transistor. SHDN 1 P = positive edge, X = don’t care, SR = shift register CS SDO SERIAL The serial data output (SDO) pin, which exists only on the SDI REGISTER D Q AD8403 and not on the AD8400 or AD8402, contains an CKRS otrpaennsf-edrr daianta, nto-c thhaen SnDelI FpEinT othf atht ree nqeuxirte ps aac pkuaglle-.u Tp hree spisutlolr- utop CRLKS 01092-049 resistor termination voltage may be larger than the V supply Figure 50. Detailed SDO Output Schematic of the AD8403 DD (but less than the max V of 8 V) of the AD8403 SDO output DD device. For example, the AD8403 could operate at VDD = 3.3 V, All digital pins are protected with a series input resistor and and the pull-up for interface to the next device could be set at 5 V. parallel Zener ESD structure shown in Figure 51. This structure This allows for daisy-chaining several RDACs from a single proc- applies to digital pins CS, SDI, SDO, RS, SHDN, and CLK. The essor serial data line. The clock period needs to be increased digital input ESD protection allows for mixed power supply when using a pull-up resistor to the SDI pin of the following applications where 5 V CMOS logic can be used to drive an device in the series. Capacitive loading at the daisy-chain node AD8400, AD8402, or AD8403 operating from a 3 V power SDO to SDI between devices must be accounted for in order to supply. Analog Pin A, Pin B, and Pin W are protected with a transfer data successfully. When daisy chain is used, CS should 20 Ω series resistor and parallel Zener diode (see Figure 52). be kept low until all the bits of every package are clocked into their respective serial registers and the address and data bits are in the proper decoding location. Rev. E | Page 22 of 32

AD8400/AD8402/AD8403 DIGITAL 1kΩ Listing I. Macro Model Net List for RDAC PINS LOGIC 01092-050 .PARAM DW=255, RDAC=10E3 Figure 51. Equivalent ESD Protection Circuits * .SUBCKT DPOT (A,W,) * 20Ω CA A 0 {DW/256*90.4E-12+30E-12} A,B,W 01092-051 RCAWW W A 0 W 1 2{(01E-D-1W2 /256)*RDAC+50} RBW W B {DW/256*RDAC+50} Figure 52. Equivalent ESD Protection Circuit (Analog Pins) CB B 0 {(1-DW/256)*90.4E-12+30E-12} * .ENDS DPOT RDAC 10kΩ A B The total harmonic distortion plus noise (THD + N), shown in Figure 41, is measured at 0.003% in an inverting op amp circuit CA CB CW using an offset ground and a rail-to-rail OP279 amplifier. 120pF Thermal noise is primarily Johnson noise, typically 9 nV/√Hz for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device, W thermal noise becomes 29 nV/√Hz. Channel-to-channel CA=90.4pF (DW/256)+30pF CB=90.4pF [1–(DW/256)]+30pF 01092-052 cthroiss sistaollka tmioena, stuhree es xletrsas gthroanu n−d6 5p idnBs part of v=id 1e0d0 o knH tzh.e T poa acckhaigeev eto Figure 53. RDAC Circuit Simulation Model for RDAC = 10 kΩ segregate the individual RDACs must be connected to circuit ground. AGND and DGND pins should be at the same voltage The AC characteristics of the RDAC are dominated by the potential. Any unused potentiometers in a package should be internal parasitic capacitances and the external capacitive loads. connected to ground. Power supply rejection is typically −35 dB The −3 dB bandwidth of the AD8403AN10 (10 kΩ resistor) at 10 kHz. Care is needed to minimize power supply ripple in measures 600 kHz at half scale as a potentiometer divider. high accuracy applications. Figure 30 provides the large signal Bode plot characteristics of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ. The gain flatness vs. frequency graph of the 1 kΩ version predicts filter applications performance (see Figure 33). A parasitic simulation model has been developed and is shown in Figure 53. Listing I provides a macro model net list for the 10 kΩ RDAC. Rev. E | Page 23 of 32

AD8400/AD8402/AD8403 APPLICATIONS The digital potentiometer (RDAC) allows many of the applica- 256 tions of a mechanical potentiometer to be replaced by a solid- 224 state solution offering compact size and freedom from vibration, shock, and open contact problems encountered in hostile al) 192 m environments. A major advantage of the digital potentiometer eci 160 is its programmability. Any settings can be saved for later recall E (D in system memory. OD 128 C AL 96 The two major configurations of the RDAC include the T GI potentiometer divider (basic 3-terminal application) and DI 64 the rheostat (2-terminal configuration) connections shown 32 in Figure 37 and Figure 38. CAeDr8ta4i0n0 b/AouDn8d4a0r2y/ AcoDn8d4it0i3o nosp meruatsito bne. Fsairtisstf,i aeldl afonra lporgo psiegrn als 00.1 INVERTING1 GAIN(V/V) 1001092-053 must remain within the GND to V range used to operate the Figure 54. Inverting Programmable Gain Plot DD single-supply AD8400/AD8402/AD8403. For standard potentiometer divider applications, the wiper output can be ACTIVE FILTER used directly. For low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the OP291 or the OP279. The state variable active filter is one of the standard circuits Second, for ac signals and bipolar dc adjustment applications, used to generate a low-pass, high-pass, or band-pass filter. a virtual ground is generally needed. Whichever method is used The digital potentiometer allows full programmability of the to create the virtual ground, the result must provide the necessary frequency, gain, and Q of the filter outputs. Figure 55 shows sink and source current for all connected loads, including the filter circuit using a 2.5 V virtual ground, which allows a adequate bypass capacitance. Figure 41 shows one channel of ±2.5 V input and output swing. RDAC2 and RDAC3 set the P the AD8402 connected in an inverting programmable gain LP, HP, and BP cutoff and center frequencies, respectively. amplifier circuit. The virtual ground is set at 2.5 V, which allows These variable resistors should be programmed with the same the circuit output to span a ±2.5 V range with respect to virtual data (as with ganged potentiometers) to maintain the best ground. The rail-to-rail amplifier capability is necessary for the Circuit Q. Figure 56 shows the measured filter response at the widest output swing. As the wiper is adjusted from its midscale band-pass output as a function of the RDAC2 and RDAC3 reset position (80 ) toward the A terminal (code FF ), the settings that produce a range of center frequencies from 2 kHz H H voltage gain of the circuit is increased in successively larger to 20 kHz. The filter gain response at the band-pass output is increments. Alternatively, as the wiper is adjusted toward the B shown in Figure 57. At a center frequency of 2 kHz, the gain is terminal (code 00 ), the signal becomes attenuated. The plot in adjusted over a −20 dB to +20 dB range determined by RDAC1. H Figure 54 shows the wiper settings for a 100:1 range of voltage Circuit Q is adjusted by RDAC4. For more detailed reading on gain (V/V). Note the ±10 dB of pseudologarithmic gain around the state variable active filter, see Analog Devices’ application 0 dB (1 V/V). This circuit is mainly useful for gain adjustments note AN-318. in the range of 0.14 V/V to 4 V/V; beyond this range the step sizes become very large, and the resistance of the driving circuit 10kΩ can become a significant term in the gain equation. RDAC4 10kΩ B 0.01μF VIN 0.01μF BRDAC1 A1 B A2 B LOW- RDAC2 A3 PASS RDAC3 A4 BAND- OP279×2 PASS HPAIGSHS- 01092-054 Figure 55. Programmable State Variable Active Filter Rev. E | Page 24 of 32

AD8400/AD8402/AD8403 40 40 –0.16 20.0000k –19.01 2.00000k 20 20 B) 0 B) 0 d d E ( E ( D D U–20 U–20 T T LI LI P P M M A–40 A–40 –60 –60 –8020 100 FRE1kQUENCY(Hz)10k 100k 200k01092-055 –8020 100 FRE1QkUENCY(Hz)10k 100k 200k01092-056 Figure 56. Programmed Center Frequency Band-Pass Response Figure 57. Programmed Amplitude Band-Pass Response Rev. E | Page 25 of 32

AD8400/AD8402/AD8403 OUTLINE DIMENSIONS 5.00(0.1968) 4.80(0.1890) 8 5 4.00(0.1574) 6.20(0.2441) 3.80(0.1497) 1 4 5.80(0.2284) 1.27(0.0500) 0.50(0.0196) BSC 1.75(0.0688) 0.25(0.0099) 45° 0.25(0.0098) 1.35(0.0532) 8° 0.10(0.0040) 0° COPLANARITY 0.51(0.0201) 0.10 SEATING 0.31(0.0122) 0.25(0.0098) 10..2470((00..00510507)) PLANE 0.17(0.0067) COMPLIANTTOJEDECSTANDARDSMS-012-AA C(RINOEFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIOARRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 012407-A Figure 58. 8-Lead Standard Small outline package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 14 8 0.280 (7.11) 0.250 (6.35) 1 7 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.110 (2.79) SEATING PLANE 0.014 (0.36) PLANE 0.010 (0.25) 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINEOFRPEANRREERENN LCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 070606-A Figure 59. 14-Lead Plastic Dual-In-Line Package [PDIP] Narrow Body (N-14) Dimensions shown in inches and (millimeters) Rev. E | Page 26 of 32

AD8400/AD8402/AD8403 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 14 8 6.20 (0.2441) 3.80 (0.1496) 1 7 5.80 (0.2283) 1.27 (0.0500) 0.50 (0.0197) BSC 1.75 (0.0689) 0.25 (0.0098) 45° 0.25 (0.0098) 1.35 (0.0531) 8° 0.10 (0.0039) 0° COPLANARITY SEATING 0.10 0.51 (0.0201) PLANE 0.25 (0.0098) 1.27 (0.0500) 0.31 (0.0122) 0.17 (0.0067) 0.40 (0.0157) COMPLIANTTO JEDEC STANDARDS MS-012-AB C(RINOEFNPETARRREOENNLCLTEIHN EOGSN EDLSIYM)AEANNRDSEI AORRNOESU NANORDEET DAIN-PO MPFRIFLO LMPIIMRLELIATIMTEEER TFSEO; RIRN ECUQHSU EDI VIINMA LEDENENSSTIIOGSN NFS.OR 060606-A Figure 60. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) 5.10 5.00 4.90 14 8 4.50 4.40 6.40 BSC 4.30 1 7 PIN 1 0.65 BSC 1.05 1.00 1M.2A0X 0.20 0.80 0.09 0.75 0.15 8° 0.60 0.05 0.30 SPLEAATNIENG 0° 0.45 COPLANARITY 0.19 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 061908-A Figure 61. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. E | Page 27 of 32

AD8400/AD8402/AD8403 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 0.280 (7.11) 0.250 (6.35) 1 12 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.100 (2.54) 0.300 (7.62) BSC 0.060 (1.52) 0.195 (4.95) 0.210 (5.33) MAX 0.130 (3.30) MAX 0.115 (2.92) 0.015 0.150 (3.81) (0.38) 0.015 (0.38) 0.130 (3.30) MIN GAUGE 0.115 (2.92) SEATING PLANE 00..001140 ((00..3265)) PLANE 0.022 (0.56) 0.008 (0.20) 0.005 (0.13) 0.430 (10.92) 0.018 (0.46) MIN MAX 0.014 (0.36) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) COMPLIANTTO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS (RCINOEFRPEANRREEREN NLCTEEHA EODSNSEL MSY)AAAYNR BDEE AR CROOEU NNNFODIGETUDAR-POEPFDRFOA INSPC RWHIAH ETOEQL UFEIO VORAR LU EHSNAETL ISFN FLDOEEARSDIGSN.. 071006-A Figure 62. 24-Lead Plastic Dual-In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 15.60(0.6142) 15.20(0.5984) 24 13 7.60(0.2992) 7.40(0.2913) 1 10.65(0.4193) 12 10.00(0.3937) 0.75(0.0295) 45° 2.65(0.1043) 0.25(0.0098) 0.30(0.0118) 2.35(0.0925) 8° 0.10(0.0039) 0° COPLANARITY 0.10 1.27B(0S.C0500) 00..5311((00..00210212)) SPLEAATNIENG 00..3230((00..00103709)) 10..2470((00..00510507)) COMPLIANTTOJEDECSTANDARDSMS-013-AD C(RINEOFNPEATRRREOENNLCLTEIHNEOGSNDELISYM)AEANNRDSEIAORRNOESUNANORDETEDAIN-POMPFRIFLOLMPIMIRLELIATIMTEEERTFSEO;RIRNECUQHSUEDIVIINMAELDENENSSTIIOGSNNFS.OR 06-07-2006-A Figure 63. 24-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-24) Dimensions shown in millimeters and (inches) Rev. E | Page 28 of 32

AD8400/AD8402/AD8403 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.15 0.05 8° 0.75 0.30 SEATING 0.20 0° 0.60 0.19 PLANE 0.09 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 64. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters Rev. E | Page 29 of 32

AD8400/AD8402/AD8403 ORDERING GUIDE Number of End-to-End Temperature Package Package Ordering Model1, 2, 3 Channels R (kΩ) Range (°C) Description Option Quantity Branding Information AB AD8400AR10 1 10 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A10 AD8400AR10-REEL 1 10 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A10 AD8400ARZ10 1 10 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A10 AD8400ARZ10-REEL 1 10 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A10 AD8400AR50 1 50 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A50 AD8400AR50-REEL 1 50 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A50 AD8400ARZ50 1 50 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A50 AD8400ARZ50-REEL 1 50 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A50 AD8400AR100 1 100 −40 to +125 8-Lead SOIC_N R-8 98 AD8400AC AD8400AR100-REEL 1 100 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400AC AD8400ARZ100 1 100 −40 to +125 8-Lead SOIC_N R-8 98 AD8400AC AD8400ARZ100-REEL 1 100 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400AC AD8400AR1 1 1 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A1 AD8400AR1-REEL 1 1 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A1 AD8400ARZ1 1 1 −40 to +125 8-Lead SOIC_N R-8 98 AD8400A1 AD8400ARZ1-REEL 1 1 −40 to +125 8-Lead SOIC_N R-8 2,500 AD8400A1 AD8402AN10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10 AD8402ANZ10 2 10 −40 to +125 14-Lead PDIP N-14 25 AD8402A10 AD8402AR10 2 10 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A10 AD8402AR10-REEL 2 10 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A10 AD8402ARU10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10 AD8402ARU10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10 AD8402ARUZ10 2 10 −40 to +125 14-Lead TSSOP RU-14 96 8402A10 AD8402ARUZ10-REEL 2 10 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A10 AD8402ARZ10 2 10 −40 to +125 14-Lead SOIC_N R-14 96 AD8402A10 AD8402ARZ10-REEL 2 10 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A10 AD8402AR50 2 50 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A50 AD8402AR50-REEL 2 50 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A50 AD8402ARU50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50 AD8402ARU50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50 AD8402ARUZ50 2 50 −40 to +125 14-Lead TSSOP RU-14 96 8402A50 AD8402ARUZ50-REEL 2 50 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A50 AD8402ARZ50 2 50 −40 to +125 14-Lead SOIC_N R-14 96 AD8402A50 AD8402ARZ50-REEL 2 50 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A50 AD8402AR100 2 100 −40 to +125 14-Lead SOIC_N R-14 56 AD8402AC AD8402AR100-REEL 2 100 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402AC AD8402ARU100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C AD8402ARU100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C AD8402ARUZ100 2 100 −40 to +125 14-Lead TSSOP RU-14 96 8402A-C AD8402ARUZ100-REEL 2 100 −40 to +125 14-Lead TSSOP RU-14 2,500 8402A-C AD8402ARZ100 2 100 −40 to +125 14-Lead SOIC_N R-14 96 AD8402AC AD8402ARZ100-REEL 2 100 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402AC AD8402AR1 2 1 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A1 AD8402AR1-REEL 2 1 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A1 AD8402ARU1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 8402A1 AD8402ARUZ1 2 1 −40 to +125 14-Lead TSSOP RU-14 96 AD8402A1 AD8402ARUZ1-REEL 2 1 −40 to +125 14-Lead TSSOP RU-14 2,500 AD8402A1 AD8402ARZ1 2 1 −40 to +125 14-Lead SOIC_N R-14 56 AD8402A1 AD8402ARZ1-REEL 2 1 −40 to +125 14-Lead SOIC_N R-14 2,500 AD8402A1 Rev. E | Page 30 of 32

AD8400/AD8402/AD8403 Number of End-to-End Temperature Package Package Ordering Model1, 2, 3 Channels R (kΩ) Range (°C) Description Option Quantity Branding Information AB AD8403AN10 4 10 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A10 AD8403AR10 4 10 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A10 AD8403AR10-REEL 4 10 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A10 AD8403ARU10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10 AD8403ARU10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10 AD8403ARUZ10 4 10 −40 to +125 24-Lead TSSOP RU-24 63 8403A10 AD8403ARUZ10-REEL 4 10 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A10 AD8403ARZ10 4 10 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A10 AD8403ARZ10-REEL 4 10 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A10 AD8403AN50 4 50 −40 to +125 24-Lead PDIP N-24-1 15 AD8403A50 AD8403AR50 4 50 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A50 AD8403AR50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A50 AD8403ARU50 4 50 −40 to +125 24-Lead TSSOP RU-24 63 8403A50 AD8403ARUZ50 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50 AD8403ARUZ50-REEL 4 50 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A50 AD8403ARZ50 4 50 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A50 AD8403ARZ50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A50 AD8403AR100 4 100 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A100 AD8403AR100-REEL 4 100 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A100 AD8403ARU100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100 AD8403ARU100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100 AD8403ARUZ100 4 100 −40 to +125 24-Lead TSSOP RU-24 63 8403A100 AD8403ARUZ100-REEL 4 100 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A100 AD8403ARZ100 4 100 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A100 AD8403ARZ100-REEL 4 100 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A100 AD8403AR1 4 1 −40 to +125 24-Lead SOIC_W RW-24 31 AD8403A1 AD8403AR1-REEL 4 1 −40 to +125 24-Lead SOIC_W RW-24 1,000 AD8403A1 AD8403ARU1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1 AD8403ARU1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1 AD8403ARUZ1 4 1 −40 to +125 24-Lead TSSOP RU-24 63 8403A1 AD8403ARUZ1-REEL 4 1 −40 to +125 24-Lead TSSOP RU-24 2,500 8403A1 AD8403ARZ1 4 1 −40 to +125 24-Lead SOIC_W RW-24 63 AD8403A1 AD8403ARZ1-REEL 4 1 −40 to +125 24-Lead SOIC_W RW-24 2,500 AD8403A1 AD8403WARZ50-REEL 4 50 −40 to +125 24-Lead SOIC_W RW-24 2,500 EVAL-AD8403SDZ Evaluation Board 1 Non-lead-free parts have date codes in the format of either YWW or YYWW, and lead-free parts have date codes in the format of #YWW, where Y/YY is the year of production and WW is the work week. For example, a non-lead-free part manufactured in the 30th work week of 2005 has the date code of either 530 or 0530, while a lead-free part has the date code of #530. 2 Z = RoHS Compliant Part. 3 W = Qualified for Automotive Applications. AUTOMOTIVE PRODUCTS The AD8403W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. Rev. E | Page 31 of 32

AD8400/AD8402/AD8403 NOTES © 2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01092-0-7/10(E) Rev. E | Page 32 of 32

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: EVAL-AD8403SDZ AD8403ARUZ1 AD8402AR10 AD8402ARZ100 AD8402AR50 AD8400ARZ10 AD8400ARZ100 AD8402ARUZ1 AD8402ARZ50 AD8403AR10 AD8402ARUZ100 AD8403AN10 AD8403ARZ10 AD8403ARUZ50 AD8402ARU10 AD8400ARZ1 AD8403ARUZ100 AD8402AR100 AD8402ANZ10 AD8400AR50 AD8400AR10 AD8402ARZ1 AD8403ARZ50 AD8403ARUZ10 AD8400ARZ50 AD8402ARUZ10 AD8403ARZ1 AD8403AR1 AD8402ARZ10 AD8402AR1 AD8403ARU10 AD8403ARZ100 AD8403ARU100 AD8402AN10 AD8403AR100 AD8402ARUZ50 AD8400AR10-REEL AD8400ARZ100-REEL AD8400ARZ10-REEL AD8400ARZ1-REEL AD8400ARZ50-REEL AD8402AR1-REEL AD8402AR50-REEL AD8402ARU50-REEL AD8402ARUZ100-REEL AD8402ARUZ10-REEL AD8402ARUZ1-REEL AD8402ARZ100-REEL AD8402ARZ10-REEL AD8402ARZ1-REEL AD8402ARZ50-REEL AD8403ARU100-REEL AD8403ARU10-REEL AD8403ARUZ100-REEL AD8403ARUZ10-REEL AD8403ARUZ1-REEL AD8403ARZ100-REEL AD8403ARZ10-REEL AD8403ARZ1-REEL AD8403ARZ50-REEL AD8403ARUZ50-REEL AD8403WARZ50-REEL