(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:13)(cid:16)(cid:14)(cid:20)(cid:16)(cid:21) (cid:20)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27)(cid:28)(cid:29)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27) SCDS054I − MARCH 1998 − REVISED OCTOBER 2003 (cid:1) 5-Ω Switch Connection Between Two Ports (cid:1) Latch-Up Performance Exceeds 100 mA Per (cid:1) Rail-to-Rail Switching on Data I/O Ports JESD 78, Class II (cid:1) I Supports Partial-Power-Down Mode off Operation D, DBQ, DGV, OR PW PACKAGE RGY PACKAGE (TOP VIEW) (TOP VIEW) C B4 1 16 VCC B4 VC B3 2 15 B5 1 16 B2 3 14 B6 B3 2 15 B5 B1 4 13 B7 B2 3 14 B6 A 5 12 B8 B1 4 13 B7 NC 6 11 S0 A 5 12 B8 OE 7 10 S1 NC 6 11 S0 GND 8 9 S2 OE 7 10 S1 8 9 NC − No internal connection D 2 N S G NC − No internal connection description/ordering information The SN74CBTLV3251 device is a 1-of-8 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The select inputs (S0, S1, S2) control the data flow. The FET multiplexers/demultiplexers are disabled when the output-enable (OE) input is high. This device is fully specified for partial-power-down applications using I . The I feature ensures that off off damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING QFN − RGY Tape and reel SN74CBTLV3251RGYR CL251 Tube SN74CBTLV3251D SSOOIICC −− DD CCBBTTLLVV33225511 Tape and reel SN74CBTLV3251DR −−4400°°CC ttoo 8855°°CC SSOP (QSOP) − DBQ Tape and reel SN74CBTLV3251DBQR CL251 TSSOP − PW Tape and reel SN74CBTLV3251PWR CL251 TVSOP − DGV Tape and reel SN74CBTLV3251DGVR CL251 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:25)(cid:27)(cid:14)(cid:29)(cid:23)(cid:5)(cid:7)(cid:24)(cid:14)(cid:2) (cid:29)(cid:17)(cid:7)(cid:17) (cid:30)(cid:31)!"#$%&(cid:30)"(cid:31) (cid:30)’ ()##*(cid:31)& %’ "! +),-(cid:30)(%&(cid:30)"(cid:31) .%&*/ Copyright  2003, Texas Instruments Incorporated (cid:25)#".)(&’ ("(cid:31)!"#$ &" ’+*((cid:30)!(cid:30)(%&(cid:30)"(cid:31)’ +*# &0* &*#$’ "! (cid:7)*1%’ (cid:24)(cid:31)’&#)$*(cid:31)&’ ’&%(cid:31).%#. 2%##%(cid:31)&3/ (cid:25)#".)(&(cid:30)"(cid:31) +#"(*’’(cid:30)(cid:31)4 ."*’ (cid:31)"& (cid:31)*(*’’%#(cid:30)-3 (cid:30)(cid:31)(-).* &*’&(cid:30)(cid:31)4 "! %-- +%#%$*&*#’/ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:13)(cid:16)(cid:14)(cid:20)(cid:16)(cid:21) (cid:20)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27)(cid:28)(cid:29)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27) SCDS054I − MARCH 1998 − REVISED OCTOBER 2003 FUNCTION TABLE INPUTS FFUUNNCCTTIIOONN OE S2 S1 S0 L L L L A port = B1 port L L L H A port = B2 port L L H L A port = B3 port L L H H A port = B4 port L H L L A port = B5 port L H L H A port = B6 port L H H L A port = B7 port L H H H A port = B8 port H X X X Disconnect logic diagram (positive logic) 5 4 A SW B1 3 SW B2 2 SW B3 1 SW B4 15 SW B5 14 SW B6 13 SW B7 12 SW B8 11 S0 10 S1 9 S2 7 OE 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:13)(cid:16)(cid:14)(cid:20)(cid:16)(cid:21) (cid:20)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27)(cid:28)(cid:29)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27) SCDS054I − MARCH 1998 − REVISED OCTOBER 2003 simplified schematic, each FET switch A B (OE) absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V I Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W (see Note 2): DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V VCC = 2.3 V to 2.7 V 1.7 VVIIHH HHiigghh--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 2 VCC = 2.3 V to 2.7 V 0.7 VVIILL LLooww--lleevveell ccoonnttrrooll iinnppuutt vvoollttaaggee VV VCC = 2.7 V to 3.6 V 0.8 TA Operating free-air temperature −40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:13)(cid:16)(cid:14)(cid:20)(cid:16)(cid:21) (cid:20)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27)(cid:28)(cid:29)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27) SCDS054I − MARCH 1998 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VIK VCC = 3 V, II = −18 mA −1.2 V II VCC = 3.6 V, VI = VCC or GND ±1 µA Ioff VCC = 0, VI or VO = 0 to 3.6 V 20 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA ∆ICC‡ Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA Ci Control inputs VI = 3 V or 0 3 pF A port 40.5 CCiioo((OOFFFF)) VVOO == 33 VV oorr 00,, OOEE == VVCCCC ppFF B port 6 II = 64 mA 5 8 VVCCCC == 22..33 VV,, VVII == 00 II = 24 mA 5 8 TTYYPP aatt VVCCCC == 22..55 VV VI = 1.7 V, II = 15 mA 27 40 rroonn§§ ΩΩ II = 64 mA 5 7 VVII == 00 VVCCCC == 33 VV II = 24 mA 5 7 VI = 2.4 V, II = 15 mA 10 15 †All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. §Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 V VCC = 3.3 V PPAARRAAMMEETTEERR FROM TO ± 0.2 V ± 0.3 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX A or B¶ B or A 0.15 0.25 ttppdd nnss S A 1 6.1 1 5.3 ten S B 1 4.1 1 3.6 ns tdis S B 1 3.5 1 3.3 ns ten OE A or B 1 5.2 1 4.5 ns tdis OE A or B 1 6.7 1 7.2 ns ¶The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:12)(cid:13) (cid:8)(cid:14)(cid:15)(cid:16)(cid:9)(cid:14)(cid:8)(cid:7)(cid:17)(cid:18)(cid:19) (cid:13)(cid:16)(cid:14)(cid:20)(cid:16)(cid:21) (cid:20)(cid:19)(cid:7) (cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27)(cid:28)(cid:29)(cid:19)(cid:22)(cid:23)(cid:8)(cid:7)(cid:24)(cid:25)(cid:8)(cid:19)(cid:26)(cid:19)(cid:27) SCDS054I − MARCH 1998 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output RL S1 Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC tPHZ/tPZH GND CL (see Note A) RL VCC CL RL V∆ 2.5 V ±0.2 V 30 pF 500 Ω 0.15 V 3.3 V ±0.3 V 50 pF 500 Ω 0.3 V LOAD CIRCUIT VCC Timing Input VCC/2 0 V tw tsu th VCC VCC Input VCC/2 VCC/2 Data Input VCC/2 VCC/2 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC VCC Output Input VCC/2 VCC/2 VCC/2 VCC/2 Control 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VCC Output VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + V∆ VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output VOH Waveform 2 VOH Output VCC/2 VCC/2 S1 at GND VCC/2 VOH − V∆ VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 74CBTLV3251DBQRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL251 & no Sb/Br) SN74CBTLV3251D ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3251 & no Sb/Br) SN74CBTLV3251DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL251 & no Sb/Br) SN74CBTLV3251DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL251 & no Sb/Br) SN74CBTLV3251DR ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3251 & no Sb/Br) SN74CBTLV3251PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL251 & no Sb/Br) SN74CBTLV3251RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL251 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBTLV3251DBQR SSOP DBQ 16 2500 330.0 12.5 6.4 5.2 2.1 8.0 12.0 Q1 SN74CBTLV3251DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74CBTLV3251DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74CBTLV3251PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBTLV3251RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Oct-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBTLV3251DBQR SSOP DBQ 16 2500 340.5 338.1 20.6 SN74CBTLV3251DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74CBTLV3251DR SOIC D 16 2500 333.2 345.9 28.6 SN74CBTLV3251PWR TSSOP PW 16 2000 367.0 367.0 35.0 SN74CBTLV3251RGYR VQFN RGY 16 3000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE DBQ0016A SSOP - 1.75 mm max height SCALE 2.800 SHRINK SMALL-OUTLINE PACKAGE C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 14X .0250 [0.635] 16 1 2X .189-.197 .175 [4.81-5.00] [4.45] NOTE 3 8 9 16X .008-.012 B .150-.157 [0.21-0.30] .069 MAX [3.81-3.98] [1.75] NOTE 4 .007 [0.17] C A B .005-.010 TYP [0.13-0.25] SEE DETAIL A .010 [0.25] GAGE PLANE .004-.010 0 - 8 [0.11-0.25] .016-.035 [0.41-0.88] DETAIL A (.041 ) TYPICAL [1.04] 4214846/A 03/2014 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 inch, per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MO-137, variation AB. www.ti.com

EXAMPLE BOARD LAYOUT DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM SEE DETAILS 1 16 16X (.016 ) [0.41] 14X (.0250 ) [0.635] 8 9 (.213) [5.4] LAND PATTERN EXAMPLE SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL .002 MAX .002 MIN [0.05] [0.05] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214846/A 03/2014 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBQ0016A SSOP - 1.75 mm max height SHRINK SMALL-OUTLINE PACKAGE 16X (.063) [1.6] SYMM 1 16 16X (.016 ) [0.41] SYMM 14X (.0250 ) [0.635] 8 9 (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.127 MM] THICK STENCIL SCALE:8X 4214846/A 03/2014 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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