Product Sample & Technical Tools & Support & Folder Buy Documents Software Community ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 ISO752xC Low-Power 5 kV Dual-Channel Digital Isolators RMS 1 Features 3 Description • HighestSignalingRate:1Mbps The ISO7520C and ISO7521C provide galvanic 1 isolation of up to 4243 V for 1 minute per UL and • PropagationDelayLessThan20ns RMS 6000 V per VDE. These devices are also certified PK • Low-PowerConsumption to 5000 V reinforced insulation per end equipment RMS • WideAmbientTemperature:–40°Cto105°C standards IEC 60950-1, IEC 61010-1, and IEC 60601-1. These digital isolators have two isolated • 50kV/µsTransientImmunityTypical channels with unidirectional (ISO7520C) and • OperatesFrom3.3-Vor5-VSupplyandLogic bidirectional (ISO7521C) channel configurations. Levels Each isolation channel has a logic input and output • 3.3-Vand5.0-VLevelTranslation buffer separated by a silicon oxide (SiO ) insulation 2 barrier. Used in conjunction with isolated power • SafetyandRegulatoryApprovals supplies, these devices prevent noise currents on a – 6000V IsolationperDINVVDEV0884-10 PK data bus or other circuits from entering the local andDINEN61010-1 ground and interfering with or damaging sensitive – 4243V Isolationfor1MinuteperUL1577 circuitry. The devices have TTL input thresholds and RMS can operate from 3.3- and 5-V supplies. All inputs are – CSAComponentAcceptanceNotice5A,IEC 5-Vtolerantwhensuppliedfrom3.3-Vsupplies. 60950-1,IEC61010-1,andIEC60601-1End EquipmentStandards NOTE: The ISO7520C and ISO7521C are specified for signaling rates up to 1 Mbps. Due to their fast – TUV5000V IsolationperEN60950-1and RMS response time, these devices will also transmit faster EN61010-1 data with much shorter pulse widths. Designers must – CQCCertificationperGB4943.1-2011 add external filtering to remove spurious signals with inputpulseduration <20ns,ifdesired. 2 Applications DeviceInformation(1) • Opto-CouplerReplacementin: PARTNUMBER PACKAGE BODYSIZE(NOM) – IndustrialField-Buses ISO7520C – ProfiBuses SOIC(16) 10.30mm×7.50mm ISO7521C – ModBuses (1) For all available packages, see the orderable addendum at – DeviceNet™DataBuses theendofthedatasheet. – ServoControlInterfaces – MotorControl – PowerSupplies – BatteryPacks SimplifiedSchematic VCCI VCCO Isolation Capacitor INx OUTx GNDI GNDO (1) V andGNDIaresupplyandgroundconnectionsrespectivelyfortheinputchannels. CCI (2) V andGNDOaresupplyandgroundconnectionsrespectivelyfortheoutputchannels. CCO 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com Table of Contents 1 Features.................................................................. 1 5%..............................................................................9 2 Applications........................................................... 1 6.14 TypicalCharacteristics............................................9 3 Description............................................................. 1 7 ParameterMeasurementInformation................10 4 RevisionHistory..................................................... 2 8 DetailedDescription............................................ 11 5 PinConfigurationandFunctions......................... 4 8.1 Overview.................................................................11 8.2 FunctionalBlockDiagram.......................................11 6 Specifications......................................................... 4 8.3 FeatureDescription.................................................12 6.1 AbsoluteMaximumRatings .....................................4 8.4 DeviceFunctionalModes........................................14 6.2 ESDRatings..............................................................4 9 ApplicationandImplementation........................ 15 6.3 RecommendedOperatingConditions.......................5 6.4 ThermalInformation..................................................5 9.1 ApplicationInformation............................................15 6.5 ElectricalCharacteristics:V andV at5V± 9.2 TypicalApplication .................................................15 CC1 CC2 5%..............................................................................6 10 PowerSupplyRecommendations..................... 17 6.6 ElectricalCharacteristics:VCC1at5V±5%,VCC2at 11 Layout................................................................... 17 3.3V±5%.................................................................6 11.1 LayoutGuidelines.................................................17 6.7 ElectricalCharacteristics:V at3.3V±5%,V CC1 CC2 11.2 LayoutExample....................................................17 at5V±5%................................................................7 12 DeviceandDocumentationSupport................. 18 6.8 ElectricalCharacteristics:V andV at3.3V± CC1 CC2 5%..............................................................................7 12.1 DocumentationSupport........................................18 6.9 PowerDissipationCharacteristics............................7 12.2 RelatedLinks........................................................18 6.10 SwitchingCharacteristics:V andV at5V± 12.3 CommunityResources..........................................18 CC1 CC2 5%..............................................................................8 12.4 Trademarks...........................................................18 6.11 SwitchingCharacteristics:V at5V±5%,V 12.5 ElectrostaticDischargeCaution............................18 CC1 CC2 at3.3V±5%.............................................................8 12.6 Glossary................................................................18 6.12 SwitchingCharacteristics:VCC1at3.3V±5%,VCC2 13 Mechanical,Packaging,andOrderable at5V±5%................................................................8 Information........................................................... 18 6.13 SwitchingCharacteristics:V andV at3.3V± CC1 CC2 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(October2013)toRevisionE Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 ChangesfromRevisionC(November2011)toRevisionD Page • DeletedNote1fromtheINSULATIONCHARACTERISTICStable..................................................................................... 12 • ChangedtheREGULATORYINFORMATIONtable,TUVcolumnFrom:CertificateNumber:U8V110877311006 To:CertificateNumber:U8V130977311010..................................................................................................................... 14 ChangesfromRevisionB(June2011)toRevisionC Page • Changedallthedevicesnumbersbyaddinga'C'totheend................................................................................................ 1 • ChangedtheSafetyandRegulatoryApprovalsFeature........................................................................................................ 1 • ChangedtheDescriptionsection............................................................................................................................................ 1 • ChangedtheIEC60664-1RatingsTable............................................................................................................................ 12 • ChangedtheINSULATIONCHARACTERISTICStable....................................................................................................... 12 2 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 ChangesfromRevisionA(September2010)toRevisionB Page • Changed5thFeaturessubbullets........................................................................................................................................... 1 • ChangedthefirstSWITCHINGCHARtable,MAXvalue,2ndrowfrom3.5to3.7andthirdrowfrom4to4.9.................... 8 • ChangedthesecondSWITCHINGCHARtable,MAXvalue,2ndrowfrom4to5.6andthirdrowfrom5to6.3................. 8 • ChangedthethirdSWITCHINGCHARtable,MAXvalue,3rdrowfrom5to8.5.................................................................. 8 • ChangedthefourthSWITCHINGCHARtable,MAXvalue,3rdrowfrom6to6.8................................................................ 9 • ChangedREGULATORYINFORMATIONtable,from:FileNumber:pending,to:FileNumber:E181974........................ 14 ChangesfromOriginal(June2010)toRevisionA Page • AddedPINDESCRIPTIONtable............................................................................................................................................ 4 • Changedt unitsinSwitchingCharacteristicsTable............................................................................................................. 8 fs • Changedt unitsinSwitchingCharacteristicsTable............................................................................................................. 8 fs • Changedt unitsinSwitchingCharacteristicsTable............................................................................................................. 8 fs • Changedt unitsinSwitchingCharacteristicsTable............................................................................................................. 9 fs • DeletedV testconditionsfromINSULATIONCHARACTERSISTCStable .................................................................. 12 IORM • AddedV parameterandSpecificationsinINSULATIONCHARACTERSISTCStable..................................................... 12 PR • ChangedV rowoftheINSULATIONCHARACTERISTICStables................................................................................ 12 IOTM • ChangedV SpecificationsinINSULATIONCHARACTERISTICStable.......................................................................... 12 ISO • ChangedMinimuminternalgaplimitfrom0.016to0.014mm............................................................................................. 12 Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 5 Pin Configuration and Functions DWPackage 16-PinSOIC TopView ISO7520C ISO7521C GND1 1 16 GND2 GND1 1 16 GGNNDD22 NC 2 15 NC NC 2 15 NC V 3 14 V V 3 14 V CC1 CC2 CC1 CC2 INA 4 13 OUTA OUTA 4 13 INA INB 5 12 OUTB INB 5 12 OUTB NC 6 11 NC NC 6 11 NC GND1 7 10 NC GND1 7 10 NC NC 8 9 GND2 NC 8 9 GND2 PinFunctions PIN I/O DESCRIPTION NAME ISO7520C ISO7521C GND1 1,7 1,7 — GroundconnectionforV CC1 GND2 9,16 9,16 — GroundconnectionforV CC2 INA 4 13 I Input,channelA INB 5 5 I Input,channelB NC 2,6,8,10,11,15 2,6,8,10,11,15 — Nointernalconnection OUTA 13 4 O Output,channelA OUTB 12 12 O Output,channelB V 3 3 — Powersupply,V CC1 CC1 V 14 14 — Powersupply,V CC2 CC2 6 Specifications 6.1 Absolute Maximum Ratings(1) MIN MAX UNIT V ,V Supplyvoltage(2) –0.5 6 V CC1 CC2 V VoltageatINx,OUTx –0.5 V +0.5(3) V I CC I OutputCurrent –15 15 mA O T Maximumjunctiontemperature 150 °C J T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagevaluesexceptdifferentialI/Obusvoltagesarewithrespecttonetworkgroundterminalandarepeakvoltagevalues. (3) Maximumvoltagemustnotexceed6V. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±4000 V Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 V (ESD) Machinemodel(MM) ±200 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 4 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT Supplyvoltage-3.3-VOperation 3.15 3.3 3.45 V V ,V CC1 CC2 Supplyvoltage-5-VOperation 4.75 5 5.25 I High-leveloutputcurrent –4 mA OH I Low-leveloutputcurrent 4 mA OL V High-leveloutputvoltage 2 5.25 V IH V Low-leveloutputvoltage 0 0.8 V IL T Ambienttemperature -40 105 °C A T (1) Junctiontemperature –40 136 °C J 1/t Signalingrate 0 1 Mbps ui t Inputpulseduration 1 µs ui (1) TomaintaintherecommendedoperatingconditionsforT,seeThermalInformation. J 6.4 Thermal Information ISO7520C,ISO7521C THERMALMETRIC(1) DW[SOIC] UNIT 16PINS R Junction-to-ambientthermalresistance 79.9 °C/W θJA R Junction-to-case(top)thermalresistance 44.6 °C/W θJC(top) R Junction-to-boardthermalresistance 51.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 18.0 °C/W JT ψ Junction-to-boardcharacterizationparameter 42.2 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report,SPRA953. Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 6.5 Electrical Characteristics: V and V at 5 V ± 5% CC1 CC2 V andV at5V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I =–4mA;SeeFigure4 V –0.8(1) 4.6 OH CCO V High-leveloutputvoltage V OH I =–20µA;SeeFigure4 V –0.1 5 OH CCO I =4mA;SeeFigure4 0.2 0.4 OL V Low-leveloutputvoltage V OL I =20µA;SeeFigure4 0 0.1 OL V Inputthresholdvoltagehysteresis 400 mV I(HYS) I High-levelinputcurrent INxatV (2) 10 µA IH CCI I Low-levelinputcurrent INxat0V –10 µA IL CMTI Common-modetransientimmunity V =V or0V;SeeFigure6 25 50 kV/µs I CCI SUPPLYCURRENT(ALLINPUTSSWITCHINGWITHSQUARE-WAVECLOCKSIGNALFORDYNAMICICCMEASUREMENT) ISO7520C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 0.4 1 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 3 6 mA CC2 CC2 I CCI ISO7521C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 2 4 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 2 4 mA CC2 CC2 I CCI (1) V isthesupplyvoltage,V orV ,fortheoutputchannelthatisbeingmeasured. CCO CC1 CC2 (2) V isthesupplyvoltage,V orV ,fortheinputchannelthatisbeingmeasured. CCI CC1 CC2 6.6 Electrical Characteristics: V at 5 V ± 5%, V at 3.3 V ± 5% CC1 CC2 V at5V±5%,V at3.3V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT IOH=–4mA; ISO7521C(5-Vside) VCCO–0.8 4.6 V High-leveloutputvoltage SeeFigure4 ISO7520C/7521C(3.3-Vside) V –0.4 3 V OH CCO I =–20µA;SeeFigure4 V –0.1 V OH CCO CCO I =4mA;SeeFigure4 0.2 0.4 OL V Low-leveloutputvoltage V OL I =20µA;SeeFigure4 0 0.1 OL V Inputthresholdvoltagehysteresis 400 mV I(HYS) I High-levelinputcurrent INxatV 10 µA IH CCI I Low-levelinputcurrent INxat0V –10 µA IL CMTI Common-modetransientimmunity V =V or0V;SeeFigure6 25 40 kV/µs I CCI SUPPLYCURRENT(ALLINPUTSSWITCHINGWITHSQUARE-WAVECLOCKSIGNALFORDYNAMICICCMEASUREMENT) ISO7520C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 0.4 1 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 2 4.5 mA CC2 CC2 I CCI ISO7521C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 2 4 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 1.5 3.5 mA CC2 CC2 I CCI 6 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 6.7 Electrical Characteristics: V at 3.3 V ± 5%, V at 5 V ± 5% CC1 CC2 V at3.3V±5%,V at5V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT IOH=–4mA; ISO7520C/7521C(5-Vside) VCCO–0.8 4.6 V High-leveloutputvoltage SeeFigure4 ISO7521C(3.3-Vside) V –0.4 3 V OH CCO I =–20µA;SeeFigure4 V –0.1 V OH CCO CCO I =4mA;SeeFigure4 0.2 0.4 OL V Low-leveloutputvoltage V OL I =20µA;SeeFigure4 0 0.1 OL V Inputthresholdvoltagehysteresis 400 mV I(HYS) I High-levelinputcurrent INxatV 10 µA IH CCI I Low-levelinputcurrent INxat0V –10 µA IL CMTI Common-modetransientimmunity V =V or0V;SeeFigure6 25 40 kV/µs I CCI SUPPLYCURRENT(ALLINPUTSSWITCHINGWITHSQUARE-WAVECLOCKSIGNALFORDYNAMICICCMEASUREMENT) ISO7520C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 0.2 0.7 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 3 6 mA CC2 CC2 I CCI ISO7521C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 1.5 3.5 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 2 4 mA CC2 CC2 I CCI 6.8 Electrical Characteristics: V and V at 3.3 V ± 5% CC1 CC2 V andV at3.3V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT I =–4mA;SeeFigure4 V –0.4 3 OH CCO V High-leveloutputvoltage V OH I =–20µA;SeeFigure4 V –0.1 3.3 OH CCO I =4mA;SeeFigure4 0.2 0.4 OL V Low-leveloutputvoltage V OL I =20µA;SeeFigure4 0 0.1 OL V Inputthresholdvoltagehysteresis 400 mV I(HYS) I High-levelinputcurrent INxatV µA IH CCI I Low-levelinputcurrent INxat0V –10 µA IL CMTI Common-modetransientimmunity V =V or0V;SeeFigure6 25 40 kV/µs I CCI SUPPLYCURRENT(ALLINPUTSSWITCHINGWITHSQUARE-WAVECLOCKSIGNALFORDYNAMICICCMEASUREMENT) ISO7520C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 0.2 0.7 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 2 4.5 mA CC2 CC2 I CCI ISO7521C I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 1.5 3.5 mA CC1 CC1 I CCI I SupplycurrentforV DCto1Mbps V =V or0V,15-pFload 1.5 3.5 mA CC2 CC2 I CCI 6.9 Power Dissipation Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) ISO7520C,ISO7521C PARAMETER DW[SOIC] UNIT 16PINS Devicepowerdissipation,V =V =5.25V,T =150°C, P CC1 CC2 J 42 mW D C =15pF,Inputa0.5MHz50%dutycyclesquarewave L Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 6.10 Switching Characteristics: V and V at 5 V ± 5% CC1 CC2 V andV at5V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelaytime SeeFigure4 9 14 ns PLH PHL PWD(1) Pulsewidthdistortion|t –t | 0.3 3.7 ns PHL PLH t Part-to-partskewtime 4.9 ns sk(pp) t Channel-to-channeloutputskewtime 3.6 ns sk(o) t Outputsignalrisetime 1 ns r SeeFigure4 t Outputsignalfalltime 1 ns f t Fail-safeoutputdelaytimefrominputpowerloss SeeFigure5 6 µs fs (1) Alsoknownaspulseskew. 6.11 Switching Characteristics: V at 5 V ± 5%, V at 3.3 V ± 5% CC1 CC2 V at5V±5%,V at3.3V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelaytime SeeFigure4 10 17 ns PLH PHL PWD(1) Pulsewidthdistortion|t –t | 0.5 5.6 ns PHL PLH t Part-to-partskewtime 6.3 ns sk(pp) t Channel-to-channeloutputskewtime 4 ns sk(o) t Outputsignalrisetime 2 ns r SeeFigure4 t Outputsignalfalltime 2 ns f t Fail-safeoutputdelaytimefrominputpowerloss SeeFigure5 6 µs fs (1) Alsoknownaspulseskew. 6.12 Switching Characteristics: V at 3.3 V ± 5%, V at 5 V ± 5% CC1 CC2 V at3.3V±5%,V at5V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelaytime SeeFigure4 10 17 ns PLH PHL PWD(1) Pulsewidthdistortion|t –t | 0.5 4 ns PHL PLH t Part-to-partskewtime 8.5 ns sk(pp) t Channel-to-channeloutputskewtime 4 ns sk(o) t Outputsignalrisetime 2 ns r SeeFigure4 t Outputsignalfalltime 2 ns f t Fail-safeoutputdelaytimefrominputpowerloss SeeFigure5 6 µs fs (1) Alsoknownaspulseskew. 8 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 6.13 Switching Characteristics: V and V at 3.3 V ± 5% CC1 CC2 V andV at3.3V±5%,T =–40°Cto105°C CC1 CC2 A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ,t Propagationdelaytime SeeFigure4 12 20 ns PLH PHL PWD(1) Pulsewidthdistortion|t –t | 1 5 ns PHL PLH t Part-to-partskewtime 6.8 ns sk(pp) t Channel-to-channeloutputskewtime 5.5 ns sk(o) t Outputsignalrisetime 2 ns r SeeFigure4 t Outputsignalfalltime 2 ns f t Fail-safeoutputdelaytimefrominputpowerloss SeeFigure5 6 µs fs (1) Alsoknownaspulseskew. 6.14 Typical Characteristics 2.62 0 2.61 mA −10 TA= 25°C V − hreshold− 222...556890 FS+ ut Current −−3200 T p −40 Fail-Saoltagefe V 22222.....5555534567 FS− −High-Level OutH −−−−87650000 VCC1,VCC2at 3.3 VVCC1,VCC2at 5 V O 2.52 I −90 −55 −35 −15 5 25 45 65 85 105 125 0 1 2 3 4 5 6 TA−Free-AirTemperature−°C G006 VOH−High-Level Output Voltage−V G007 Figure1.Fail-SafeVoltageThresholdvsFree-Air Figure2.High-LevelOutputCurrentvsHigh-LevelOutput Temperature Voltage 80 mA 70 TA= 25°C − urrent 60 VCC1,VCC2at 5 V ut C 50 p ut 40 O vel 30 VCC1,VCC2at 3.3 V e L w- 20 o L − 10 L O I 0 0 1 2 3 4 5 6 VOL−Low-Level Output Voltage−V G008 Figure3.Low-LevelOutputCurrentvsLow-LevelOutputVoltage Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 7 Parameter Measurement Information ER VCCI RRI VI 1.4V 1.4V GeInnepruattor VI 5IN0W SOLATIONBA OVUOT CL tPLH 90% tPV0HOLVH NOTEA I NOBTE VO VCCO/2 VCCO/2 10% V tr tf OL A. Theinputpulseissuppliedbyageneratorhavingthefollowingcharacteristics:PRR≤50kHz,50%dutycycle,t ≤3 r ns,t ≤3ns,Z =50Ω. f O B. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L Figure4. SwitchingCharacteristicTestCircuitandVoltageWaveforms V I VCCI VCCI RIER V 2.7V IN = 0 BAR OUT V I t 0V N O ISOLATIO CL VO fs 50% FAILSAFVE OHHIGH V NOTE OL A A. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L Figure5. Fail-safeDelayTimeTestCircuitandVoltageWaveforms V V CCI CCO C = 0.1μF ±1% C = 0.1μF ±1% Pass-fail criteria– output must remain er stable. arri IN B OUT S1 n atio + ol s C V or V I L OH OL NoteA – GNDI GNDO + V – CM A. C =15pFandincludesinstrumentationandfixturecapacitancewithin±20%. L Figure6. Common-ModeTransientImmunityTestCircuit 10 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 8 Detailed Description 8.1 Overview The isolator in Figure 7 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to 1 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal through the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low frequency channel. Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, alow-passfilter(LPF)isneededtoremovethehigh-frequencycarrierfromtheactualdatabeforepassingitonto theoutputmultiplexer. 8.2 Functional Block Diagram Isolation barrier OSC LPF Low-frequency channel PWM VREF (DC...100 kbps) 0 IN Out 1 S DCL High-frequency channel (100 kbps... VREF 1 Mbps) Figure7. ConceptualBlockDiagramofaDigitalCapacitiveIsolator Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 8.3 Feature Description 8.3.1 InsulationCharacteristics overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS SPECIFICATION UNIT Maximumrepetitivepeakisolation V 1414 V IORM voltage PEAK Methoda,Afterenvironmentaltestssubgroup1, V =V x1.6,t=10s, 2262 PR IORM Partialdischarge<5pC Methodb1, V Inputtooutputtestvoltage V =V x1.875,t=1s(100%Productiontest) 2651 V PR PR IORM PEAK Partialdischarge<5pC AfterInput/OutputSafetyTestSubgroup2/3, V =V x1.2,t=10s, 1697 PR IORM Partialdischarge<5pC V MaximumTransientIsolationvoltage t=60sec(qualification) 6000 V IOTM PEAK V =V =4243V ,t=60sec(qualification); WithstandingIsolationvoltageperUL TEST ISO RMS V V =1.2×V =5092V ,t=1sec(100% 4243 V ISO 1577 TEST ISO RMS RMS production) R Isolationresistance V =500VatT =150°C >109 Ω S IO S Pollutiondegree 2 8.3.2 IEC60664-1RatingsTable PARAMETER TESTCONDITIONS SPECIFICATION BasicIsolationGroup MaterialGroup II Ratedmainsvoltages<=150Vrms I-IV InstallationClassification Ratedmainsvoltages<=600Vrms I-III Ratedmainsvoltages<=1000Vrms I-II 8.3.3 PackageInsulationandSafety-RelatedSpecifications overrecommendedoperatingconditions(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT L(I01) Minimumairgap(Clearance) Shortestterminal-to-terminaldistancethroughair 8.34 mm Shortestterminal-to-terminaldistanceacrossthe L(I02) Minimumexternaltracking(Creepage) 8.1 mm packagesurface Trackingresistance(ComparativeTracking CTI DINEN60112(VDE0303-11);IEC60112 >400 V Index) Minimuminternalgap(InternalClearance) Distancethroughtheinsulation 0.014 mm V =500V,T =25ºC >1012 R Isolationresistance,inputtooutput(1) IO A Ω IO V =500V,100ºC≤T ≤T max >1011 IO A A C Barriercapacitanceinputtooutput(1) V =0.4sin(2πft),f=1MHz 2 pF IO IO C Inputcapacitancetoground(2) V =V /2+0.4sin(2πft),f=1MHz,V =5V 2 pF I I CC CC (1) Allpinsoneachsideofthebarriertiedtogethercreatinga2-terminaldevice. (2) Measuredfrominputpintoground. 12 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 emptyparaforspaceabovetheNOTE NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of theisolatorontheprinted-circuit-board(PCB)donotreducethisdistance. Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribsonaprintedcircuitboardareusedtohelpincreasethesespecifications. 8.3.4 SafetyLimitingValues Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current-limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT θ =79.9°C/W,V =5.25V,T =150°C,T =25°C 298 JA I J A Is Safetyinput,output,orsupplycurrent mA θ =79.9°C/W,V =3.45V,T =150°C,T =25°C 453 JA I J A Ts MaximumCaseTemperature 150 °C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface-Mount Packages.Thepoweristherecommendedmaximuminputvoltagetimesthecurrent.Thejunctiontemperatureis thentheambienttemperatureplusthepowertimesthejunction-to-airthermalresistance. 500 A V and V at 3.45 V m CC1 CC2 nt - 400 e r ur 300 C ng VCC1and VCC2at 5.25 V miti 200 Li y et 100 af S 0 0 50 100 150 200 250 Case Temperature - °C Figure8. DW-16R ThermalDeratingCurveforVDE ΘJC Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 8.3.5 RegulatoryInformation VDE TUV CSA UL CQC Certifiedaccordingto ApprovedunderCSA DINVVDEV0884-10 ComponentAcceptance Recognizedunder1577 CertifiedaccordingtoEN CertifiedaccordingtoGB (VDEV0884-10):2006- Notice5A,IEC60950-1, ComponentRecognition 60950-1andEN61010-1 4943.1-2011 12andDINEN61010-1 IEC61010-1,andIEC Program (VDE0411-1):2011-07 60601-1 5000V Isolation RMS Rating; Reinforcedinsulationper CSA60950-1-07+A1and 5000V Isolation BasicInsulation RMS IEC60950-12ndEd.+A1, Rating; MaximumTransient 380V maxworking ReinforcedInsulation,400 RMS ReinforcedInsulation, Isolationvoltage,6000 voltage; SingleProtection,4243 V maximumworking Altitude≤5000m,Tropical V RMS Reinforcedinsulationper V Withstanding PK voltage; RMS Climate,250V MaximumRepetitive CSA61010-1-04andIEC IsolationVoltage RMS BasicInsulation,600 maximumworkingvoltage PeakIsolationVoltage, 61010-12ndEd,300 V maximumworking 1414V RMS V maxworking PK voltage RMS voltage; 2MeansofPatient Protectionat125V RMS perIEC60601-1(3rdEd.) CertificateNumber: CertificateNumber:U8V MasterContractNumber: CertificateNumber: FileNumber:E181974 40016131 130977311010 220991 CQC14001109542 8.4 Device Functional Modes Table1.DeviceFunctionTable V (1) V (1) INPUT(INA,INB)(1) OUTPUT(OUTA,OUTB)(1) CCI CCO H H PU PU L L Open H PD PU X H X PD X Undetermined (1) V =Input-sideV ;V =Output-sideV ;PU=PoweredUp(Vcc≥3.15V);PD=Powered CCI CC CCO CC Down(Vcc≤2.1V);X=Irrelevant;H=HighLevel;L=LowLevel Input Output VCCI VCCI VCCI VCCO 1 M(cid:13) 500 (cid:13) 8 (cid:13) IN OUT 13 (cid:13)(cid:3) Figure9. EquivalentInputandOutputSchematicDiagrams 14 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The ISO7520C and ISO7521C are high-performance, dual-channel digital isolators with a 5-kV isolation RMS voltage. The isolator uses single-ended TTL-logic switching technology. The supply voltage range is from 3.15 V to 5.25 V for both supplies, V and V . When designing with digital isolators, it is important to keep in mind CC1 CC2 that due to the single-ended design structure, digital isolators do not conform to any specific interface standard and are only intended for isolating single-ended TTL digital signal lines. The isolator is typically placed between the data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface typeorstandard. 9.2 Typical Application The ISO7521C can be used with Texas Instruments' mixed signal micro-controller, digital-to-analog converter, transformerdriver,andvoltageregulatortocreateanisolated4-to20-mAcurrentloop. 3 14 V V 4 CC1 CC2 13 ISO7521 5 12 1, 7 9, 16 Figure10. Isolated4-20mACurrentLoop 9.2.1 DesignRequirements FortheISO7521C,usetheparametersshowninTable2. Table2.ISO752xCDesignParameters PARAMETER VALUE Supplyvoltage 3.15Vto5.25V DecouplingcapacitorbetweenV andGND1 0.1µF CC1 DecouplingcapacitorfromV andGND2 0.1µF CC2 Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 9.2.2 DetailedDesignProcedure Unlike optocouplers, which need external components to improve performance, provide bias, or limit current, the ISO7521Conlyneedstwoexternalbypasscapacitorstooperate. ISO7521C V V CC1 CC2 GND1 GND1 1 16 GND2 GND2 0.1µF 0.1µF NC 2 15 NC GND1 N GND2 VCC1 3 O 14 VCC2 I T OUTA OUTA 4 A 13 INA INA L INB INB 5 O 12 OUTB OUTB S NC 6 I 11 NC GND1 GND1 7 10 NC NC 8 9 GND2 GND2 Figure11. TypicalISO7521CCircuitHook-up 9.2.3 ApplicationCurve 1.6 V − 1.5 VIT+, 5 V d ol sh 1.4 e hr T 1.3 VIT+, 3.3 V g n chi 1.2 wit e S 1.1 VIT−, 5 V g olta 1.0 V VIT−, 3.3 V ut 0.9 p n I 0.8 −55 −35 −15 5 25 45 65 85 105 125 TA−Free-AirTemperature−°C G005 Figure12.InputVoltageSwitchingThresholdvsFree-AirTemperature 16 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C www.ti.com SLLSE39E–JUNE2010–REVISEDMAY2015 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, TI recommends placing a 0.1-μF bypass capacitor at the input and output supply pins (V and V ). The capacitors must be placed as close to the CC1 CC2 supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are availableintheSN6501datasheet(SLLSEA0). 11 Layout 11.1 Layout Guidelines A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 13). Layer stacking must be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency signallayer. • Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits ofthedatalink. • Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmissionlineinterconnectsandprovidesanexcellentlow-inductancepathforthereturncurrentflow. • Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately100pF/in2. • Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usuallyhavemargintotoleratediscontinuitiessuchasvias. If an additional supply voltage plane or signal layer is needed, add a second power/ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the powerandgroundplaneofeachpowersystemcanbeplacedclosertogether,thusincreasingthehigh-frequency bypass capacitance significantly. For detailed layout recommendations, see Application Note Digital Isolator DesignGuide (SLLA284). 11.1.1 PCBMaterial For digital circuit boards operating at less than 150 Mbps, (or rise and fall times higher than 1 ns), and trace lengths of up to 10 inches, use standard FR-4 epoxy-glass as PCB material. FR-4 (Flame Retardant 4) meets the requirements of Underwriters Laboratories UL94-V0, and is preferred over less expensive alternatives due to its lower dielectric losses at high frequencies, less moisture absorption, greater strength and stiffness, and self- extinguishingflammabilitycharacteristics. 11.2 Layout Example High-speed traces 10 mils Ground plane Keep this space FR-4 40 mils free from planes, traces, pads, and 0r §(cid:3)4.5 vias Power plane 10 mils Low-speed traces Figure13. LayoutRecommendation Copyright©2010–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:ISO7520C ISO7521C

ISO7520C,ISO7521C SLLSE39E–JUNE2010–REVISEDMAY2015 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: ApplicationNoteDigitalIsolatorDesignGuide (SLLA284) IsolationGlossary(SLLA353) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table3.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY ISO7520C Clickhere Clickhere Clickhere Clickhere Clickhere ISO7521C Clickhere Clickhere Clickhere Clickhere Clickhere 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. DeviceNetisatrademarkofOpenDeviceNetVendorAssociation. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 18 SubmitDocumentationFeedback Copyright©2010–2015,TexasInstrumentsIncorporated ProductFolderLinks:ISO7520C ISO7521C

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) ISO7520CDW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 ISO7520CDW & no Sb/Br) ISO7520CDWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 ISO7520CDW & no Sb/Br) ISO7521CDW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 ISO7521CDW & no Sb/Br) ISO7521CDWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 105 ISO7521CDW & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) ISO7520CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 ISO7521CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) ISO7520CDWR SOIC DW 16 2000 350.0 350.0 43.0 ISO7521CDWR SOIC DW 16 2000 350.0 350.0 43.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016B SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4221009/B 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (2) 16X (1.65) SEE SEE DETAILS DETAILS 1 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 8 9 8 9 R0.05 TYP R0.05 TYP (9.3) (9.75) IPC-7351 NOMINAL HV / ISOLATION OPTION 7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE LAND PATTERN EXAMPLE SCALE:4X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4221009/B 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016B SOIC - 2.65 mm max height SOIC SYMM SYMM 16X (2) 16X (1.65) 1 1 16 16 16X (0.6) 16X (0.6) SYMM SYMM 14X (1.27) 14X (1.27) 8 9 8 9 R0.05 TYP R0.05 TYP (9.3) (9.75) IPC-7351 NOMINAL HV / ISOLATION OPTION 7.3 mm CLEARANCE/CREEPAGE 8.1 mm CLEARANCE/CREEPAGE SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:4X 4221009/B 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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