25AA128/25LC128 128K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC128 2.5-5.5V 64 Byte I,E P, SM, SN, ST, MF 25AA128 1.8-5.5V 64 Byte I P, SM, SN, ST, MF Features: Description: • Max. Clock 10 MHz The Microchip Technology Inc. 25AA128/25LC128 • Low-power CMOS Technology (25XX128*) are 128k-bit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial - Max. Write Current: 5 mA at 5.5V, 10 MHz Peripheral Interface (SPI) compatible serial bus. The - Read Current: 5 mA at 5.5V, 10 MHz bus signals required are a clock input (SCK) plus sep- - Standby Current: 5 A at 5.5V arate data in (SI) and data out (SO) lines. Access to the • 16,384 x 8-bit Organization device is controlled through a Chip Select (CS) input. • 64 Byte Page Communication to the device can be paused via the • Self-timed Erase and Write Cycles (5 ms max.) hold pin (HOLD). While the device is paused, • Block Write Protection transitions on its inputs will be ignored, with the - Protect none, 1/4, 1/2 or all of array exception of Chip Select, allowing the host to service higher priority interrupts. • Built-in Write Protection - Power-on/off data protection circuitry The 25XX128 is available in standard packages including 8-lead PDIP, SOIJ and SOIC, and - Write enable latch advanced packaging including 8-lead DFN and 8- - Write-protect pin lead TSSOP. • Sequential Read • High Reliability Package Types (not to scale) - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years TSSOP PDIP/SOIC/SOIJ (ST) (P, SM, SN) - ESD protection: > 4000V • Temperature Ranges Supported; CS 1 8 VCC CS 1 8 8 VCC - Industrial (I): -40C to +85C SO 2 7 HOLD SO 2 2 7 HOLD - Automotive (E): -40°C to +125°C VWSPS 34 65 SSCIK WP 3 LC1 6 SCK • Pb-free and RoHS Compliant VSS 4 25 5 SI Pin Function Table X-Rotated TSSOP DFN (MF) Name Function (X/ST) CS 1 8 VCC CS Chip Select Input HOLD 1 8 SCK 8 SO Serial Data Output VCCSC 23 76 SVISS SO 2 C12 7 HOLD SO 4 5 WP WP 3 5L 6 SCK WP Write-Protect 2 VSS 4 5 SI VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage * 25XX128 is used in this document as a generic part number for the 25AA128, 25LC128 devices.  2003-2011 Microchip Technology Inc. DS21831E-page 1

25AA128/25LC128 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS.........................................................................................................-0.6V to VCC +1.0V Storage temperature.................................................................................................................................-65°C to 150°C Ambient temperature under bias...............................................................................................................-40°C to 125°C ESD protection on all pins..........................................................................................................................................4kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V DC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. D001 VIH1 High-level input .7 VCC VCC+1 V voltage D002 VIL1 Low-level input -0.3 0.3VCC V VCC2.7V D003 VIL2 voltage -0.3 0.2VCC V VCC < 2.7V D004 VOL Low-level output — 0.4 V IOL = 2.1mA D005 VOL voltage — 0.2 V IOL = 1.0mA, VCC < 2.5V D006 VOH High-level output VCC -0.5 — V IOH = -400A voltage D007 ILI Input leakage current — ±1 A CS = VCC, VIN = VSS TO VCC D008 ILO Output leakage — ±1 A CS = VCC, VOUT = VSS TO VCC current D009 CINT Internal Capacitance — 7 pF TA = 25°C, CLK = 1.0MHz, (all inputs and VCC = 5.0V (Note) outputs) D010 ICC Read — 5 mA VCC = 5.5V; FCLK = 10.0MHz; — SO = Open Operating Current 2.5 mA VCC = 2.5V; FCLK = 5.0MHz; SO = Open D011 ICC Write — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D012 ICCS — 5 A CS = VCC = 5.5V, Inputs tied to VCC or Standby Current — VSS, 125°C 1 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C Note: This parameter is periodically sampled and not 100% tested. DS21831E-page 2  2003-2011 Microchip Technology Inc.

25AA128/25LC128 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 1 FCLK Clock Frequency — 10 MHz 4.5V Vcc  5.5V — 5 MHz 2.5V Vcc  4.5V — 3 MHz 1.8V Vcc  2.5V 2 TCSS CS Setup Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 3 TCSH CS Hold Time 100 — ns 4.5V Vcc  5.5V 200 — ns 2.5V Vcc  4.5V 250 — ns 1.8V Vcc  2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 — ns 4.5V Vcc  5.5V 20 — ns 2.5V Vcc  4.5V 30 — ns 1.8V Vcc  2.5V 6 THD Data Hold Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 50 — ns 1.8V Vcc  2.5V 7 TR CLK Rise Time — 100 ns (Note1) 8 TF CLK Fall Time — 100 ns (Note1) 9 THI Clock High Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 10 TLO Clock Low Time 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock — 50 ns 4.5V Vcc  5.5V Low — 100 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 14 THO Output Hold Time 0 — ns (Note1) 15 TDIS Output Disable Time — 40 ns 4.5V Vcc  5.5V(Note1) — 80 ns 2.5V Vcc  4.5V(Note1) — 160 ns 1.8V Vcc  2.5V(Note1) 16 THS HOLD Setup Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site: www.microchip.com.  2003-2011 Microchip Technology Inc. DS21831E-page 3

25AA128/25LC128 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Automotive (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V Param. Sym. Characteristic Min. Max. Units Test Conditions No. 17 THH HOLD Hold Time 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V 18 THZ HOLD Low to Output 30 — ns 4.5V Vcc  5.5V(Note1) High-Z 60 — ns 2.5V Vcc  4.5V(Note1) 160 — ns 1.8V Vcc  2.5V(Note1) 19 THV HOLD High to Output 30 — ns 4.5V Vcc  5.5V Valid 60 — ns 2.5V Vcc  4.5V 160 — ns 1.8V Vcc  2.5V 20 TWC Internal Write Cycle Time — 5 ms (NOTE2) 21 — Endurance 1,000,000 — E/W Page mode, 25°C, VCC = 5.5V (NOTE3) Cycles Note1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site: www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note1) VHI = 4.0V (Note2) CL = 50 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note1: For VCC  4.0V 2: For VCC > 4.0V DS21831E-page 4  2003-2011 Microchip Technology Inc.

25AA128/25LC128 FIGURE 1-1: HOLD TIMING CS 17 17 16 16 SCK 18 19 High-Impedance SO n + 2 n + 1 n n n - 1 Don’t Care 5 SI n + 2 n + 1 n n n - 1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 11 7 Mode 1,1 8 3 SCK Mode 0,0 5 6 SI MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 10 3 Mode 1,1 SCK Mode 0,0 13 15 14 SO MSB out ISB out Don’t Care SI  2003-2011 Microchip Technology Inc. DS21831E-page 5

25AA128/25LC128 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation 2.3 Write Sequence The 25XX128 is a 16,384 byte Serial EEPROM Prior to any attempt to write data to the 25XX128, the designed to interface directly with the Serial Peripheral write enable latch must be set by issuing the WREN Interface (SPI) port of many of today’s popular instruction (Figure2-4). This is done by setting CS low microcontroller families, including Microchip’s PIC® and then clocking out the proper instruction into the microcontrollers. It may also interface with microcon- 25XX128. After all eight bits of the instruction are trollers that do not have a built-in SPI port by using dis- transmitted, the CS must be brought high to set the crete I/O lines programmed properly in firmware to write enable latch. If the write operation is initiated match the SPI protocol. immediately after the WREN instruction without CS being brought high, the data will not be written to the The 25XX128 contains an 8-bit instruction register. The array because the write enable latch will not have been device is accessed via the SI pin, with data being properly set. clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire Once the write enable latch is set, the user may operation. proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with two Table2-1 contains a list of the possible instruction MSBs of the address being “don’t care” bits, and then bytes and format for device operation. All instructions, the data to be written. Up to 64 bytes of data can be addresses and data are transferred MSB first, LSB last. sent to the device before a write cycle is necessary. Data (SI) is sampled on the first rising edge of SCK The only restriction is that all of the bytes must reside after CS goes low. If the clock line is shared with other in the same page. peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX128 in ‘HOLD’ Note: Page write operations are limited to writing mode. After releasing the HOLD pin, operation will bytes within a single physical page, resume from the point when the HOLD was asserted. regardless of the number of bytes actually being written. Physical page 2.2 Read Sequence boundaries start at addresses that are integer multiples of the page buffer size (or The device is selected by pulling CS low. The 8-bit ‘page size’) and, end at addresses that are READ instruction is transmitted to the 25XX128 fol- integer multiples of page size – 1. If a lowed by the 16-bit address, with two MSBs of the Page Write command attempts to write address being “don’t care” bits. After the correct READ across a physical page boundary, the instruction and address are sent, the data stored in the result is that the data wraps around to the memory at the selected address is shifted out on the beginning of the current page (overwriting SO pin. The data stored in the memory at the next data previously stored there), instead of address can be read sequentially by continuing to pro- being written to the next page as might be vide clock pulses. The internal Address Pointer is auto- expected. It is therefore necessary for the matically incremented to the next higher address after application software to prevent page write each byte of data is shifted out. When the highest operations that would attempt to cross a address is reached (3FFFh), the address counter rolls page boundary. over to address 0000h, allowing the read cycle to be For the data to be actually written to the array, the CS continued indefinitely. The read operation is terminated must be brought high after the Least Significant bit (D0) by raising the CS pin (Figure2-1). of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure2-2 and Figure2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. DS21831E-page 6  2003-2011 Microchip Technology Inc.

25AA128/25LC128 BLOCK DIAGRAM STATUS HV Generator Register EEPROM I/O Control Memory X Array Control Logic Logic Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. HOLD R/W Control WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address SI 0 0 0 0 0 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO 7 6 5 4 3 2 1 0  2003-2011 Microchip Technology Inc. DS21831E-page 7

25AA128/25LC128 FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 16-bit Address Data Byte 1 SI 0 0 0 0 0 0 1 0 15 14 13 12 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 Data Byte 3 Data Byte n (64 max) SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS21831E-page 8  2003-2011 Microchip Technology Inc.

25AA128/25LC128 2.4 Write Enable (WREN) and Write The following is a list of conditions under which the Disable (WRDI) write enable latch will be reset: • Power-up The 25XX128 contains a write enable latch. See • WRDI instruction successfully executed Table2-4 for the write-protect functionality matrix. This latch must be set before any write operation will be • WRSR instruction successfully executed completed internally. The WREN instruction will set the • WRITE instruction successfully executed latch, and the WRDI will reset the latch. FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO  2003-2011 Microchip Technology Inc. DS21831E-page 9

25AA128/25LC128 2.5 Read Status Register Instruction The Write Enable Latch (WEL) bit indicates the status (RDSR) of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a The Read Status Register instruction (RDSR) provides ‘0’, the latch prohibits writes to the array. The state of access to the STATUS register. The STATUS register this bit can always be updated via the WREN or WRDI may be read at any time, even during a write cycle. The commands regardless of the state of write protection STATUS register is formatted as follows: on the STATUS register. These commands are shown in Figure2-4 and Figure2-5. TABLE 2-2: STATUS REGISTER The Block Protection (BP0 and BP1) bits indicate 7 6 5 4 3 2 1 0 which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These W/R – – – W/R W/R R R bits are nonvolatile, and are shown in Table2-3. WPEN X X X BP1 BP0 WEL WIP See Figure2-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX128 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO 7 6 5 4 3 2 1 0 DS21831E-page 10  2003-2011 Microchip Technology Inc.

25AA128/25LC128 2.6 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows the only writes to nonvolatile bits in the STATUS register user to write to the nonvolatile bits in the STATUS reg- are disabled. See Table2-4 for a matrix of functionality ister as shown in Table2-2. The user is able to select on the WPEN bit. one of four levels of protection for the array by writing See Figure2-7 for the WRSR timing sequence. to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the TABLE 2-3: ARRAY PROTECTION ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as Array Addresses shown in Table2-3. BP1 BP0 Write-Protected The Write-Protect Enable (WPEN) bit is a nonvolatile 0 0 none bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable 0 1 upper 1/4 (WPEN) bit in the STATUS register control the (3000h-3FFFh) programmable hardware write-protect feature. Hard- 1 0 upper 1/2 ware write protection is enabled when WP pin is low (2000h-3FFFh) and the WPEN bit is high. Hardware write protection is 1 1 all disabled when either the WP pin is high or the WPEN (0000h-3FFFh) bit is low. When the chip is hardware write-protected, FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction Data to STATUS Register SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register  2003-2011 Microchip Technology Inc. DS21831E-page 11

25AA128/25LC128 2.7 Data Protection 2.8 Power-On State The following protection has been implemented to The 25XX128 powers on in the following state: prevent inadvertent writes to the array: • The device is in low-power Standby mode • The write enable latch is reset on power-up (CS=1) • A write enable instruction must be issued to set • The write enable latch is reset the write enable latch • SO is in high-impedance state • After a byte write, page write or STATUS register • A high-to-low-level transition on CS is required to write, the write enable latch is reset enter active state • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: WRITE-PROTECT FUNCTIONALITY MATRIX WEL WPEN WP Protected Blocks Unprotected Blocks STATUS Register (SR bit 1) (SR bit 7) (pin 3) 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care DS21831E-page 12  2003-2011 Microchip Technology Inc.

25AA128/25LC128 3.0 PIN DESCRIPTIONS The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to The descriptions of the pins are listed in Table3-1. install the 25XX128 in a system with WP pin grounded and still be able to write to the STATUS register. The TABLE 3-1: PIN FUNCTION TABLE WP pin functions will be enabled when the WPEN bit is set high. X-Rotated Pin 3.4 Serial Input (SI) Name Pin Function Number Number The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is CS 1 3 Chip Select Input latched on the rising edge of the serial clock. SO 2 4 Serial Data Output 3.5 Serial Clock (SCK) WP 3 5 Write-Protect Pin The SCK is used to synchronize the communication VSS 4 6 Ground between a master and the 25XX128. Instructions, SI 5 7 Serial Data Input addresses or data present on the SI pin are latched on SCK 6 8 Serial Clock Input the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. HOLD 7 1 Hold Input 3.6 Hold (HOLD) VCC 8 2 Supply Voltage Note: The exposed pad on the DFN package The HOLD pin is used to suspend transmission to the can be connected to VSS or left floating. 25XX128 while in the middle of a serial sequence with- out having to retransmit the entire sequence again. It 3.1 Chip Select (CS) must be held high any time this function is not being used. Once the device is selected and a serial A low level on this pin selects the device. A high level sequence is underway, the HOLD pin may be pulled deselects the device and forces it into Standby mode. low to pause further serial communication without However, a programming cycle which is already resetting the serial sequence. The HOLD pin must be initiated or in progress will be completed, regardless of brought low while SCK is low, otherwise the HOLD the CS input signal. If CS is brought high during a function will not be invoked until the next SCK high-to- program cycle, the device will go into Standby mode as low transition. The 25XX128 must remain selected soon as the programming cycle is complete. When the during this sequence. The SI, SCK and SO pins are in device is deselected, SO goes to the high-impedance a high-impedance state during the time the device is state, allowing multiple parts to share the same SPI paused and transitions on these pins will be ignored. To bus. A low-to-high transition on CS after a valid write resume serial communication, HOLD must be brought sequence initiates an internal write cycle. After power- high while the SCK pin is low, otherwise serial up, a low level on CS is required prior to any sequence communication will not resume. Lowering the HOLD being initiated. line at any time will tri-state the SO line. 3.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX128. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will dis- able writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write.  2003-2011 Microchip Technology Inc. DS21831E-page 13

25AA128/25LC128 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN Example: XXXXXXX 25LC128 T/XXXXX I/MF YYWW 0328 NNN 1L7 8-Lead PDIP Example: XXXXXXXX 25AA128 T/XXXNNN I/P 1L7 YYWW 0328 8-Lead SOIC Example: XXXXXXXX 25LC128 T/XXYYWW I/SN 0328 NNN 1L7 8-Lead SOIJ Example: XXXXXXXX 25LC128 T/XXXXXX I/SM e3 YYWWNNN 03281L7 8-Lead TSSOP Example: TSSOP 1st Line Marking XXXX 5LD Device std mark TYWW I328 NNN 1L7 25AA128 5AD 25AA128X 5ADX 25LC128 5LD 25LC128X 5LDX DS21831E-page 14  2003-2011 Microchip Technology Inc.

25AA128/25LC128 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2011 Microchip Technology Inc. DS21831E-page 15

25AA128/25LC128 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e D1 b L N N K E E2 E1 EXPOSED PAD NOTE 1 1 2 2 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW φ A A2 A1 A3 NOTE 2 Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 1.27 BSC Overall Height A – 0.85 1.00 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 4.67 BSC Exposed Pad Length D2 3.85 4.00 4.15 Overall Width E 5.99 BSC Molded Package Width E1 5.74 BSC Exposed Pad Width E2 2.16 2.31 2.46 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-113B DS21831E-page 16  2003-2011 Microchip Technology Inc.

25AA128/25LC128 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L A1 c e eB b1 b Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 Lower Lead Width b .014 .018 .022 Overall Row Spacing § eB – – .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. MicrochipTechnologyDrawingC04-018B  2003-2011 Microchip Technology Inc. DS21831E-page 17

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21831E-page 18  2003-2011 Microchip Technology Inc.

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2011 Microchip Technology Inc. DS21831E-page 19

25AA128/25LC128 (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:6)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:6)(cid:10)(cid:10)(cid:8)(cid:17)(cid:18)(cid:12)(cid:10)(cid:13)(cid:19)(cid:5)(cid:8)(cid:20)(cid:15)(cid:21)(cid:22)(cid:8)(cid:23)(cid:8)(cid:21)(cid:6)(cid:24)(cid:24)(cid:25)(cid:26)(cid:27)(cid:8)(cid:28)(cid:29)(cid:30)(cid:31)(cid:8)(cid:16)(cid:16)(cid:8) (cid:25)(cid:7)!(cid:8)"(cid:15)(cid:17)#$% (cid:21)(cid:25)(cid:12)(cid:5)& (cid:30)(cid:10)(cid:9)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)!(cid:10)"(cid:31)(cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15)(cid:31)(cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2)(cid:31)(cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28)(cid:31)(cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28)(cid:31)(cid:14)%(cid:2)(cid:28)(cid:31)(cid:2) (cid:11)(cid:31)(cid:31)(cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) DS21831E-page 20  2003-2011 Microchip Technology Inc.

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2011 Microchip Technology Inc. DS21831E-page 21

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21831E-page 22  2003-2011 Microchip Technology Inc.

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2011 Microchip Technology Inc. DS21831E-page 23

25AA128/25LC128 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c φ A A2 A1 L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e 0.65 BSC Overall Height A – – 1.20 Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 Overall Width E 6.40 BSC Molded Package Width E1 4.30 4.40 4.50 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. MicrochipTechnologyDrawingC04-086B DS21831E-page 24  2003-2011 Microchip Technology Inc.

25AA128/25LC128 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2003-2011 Microchip Technology Inc. DS21831E-page 25

25AA128/25LC128 APPENDIX A: REVISION HISTORY Revision A(9/03) Original Release Revision B (12/03) Corrections to Section 1.0, Electrical Characteristics. Revision C (5/07) Removed Preliminary status; Revised Table 1-2, Para. 7 and 8; Revised Table 1-3, CL; Revised trademarks; Replaced Package drawings (Rev. AP); Replaced On- Line Support; Revised Product ID section. Revision D (06/09) Added X-Rotated TSSOP to package types; Revised Table 1-2, Param. 21; Revised Table 3-1; Revised TSSOP Line Marking table; Added SOIC Land Pattern; Revised Product ID section. Revision E (7/2011) Added SOIJ (SM) package. DS21831E-page 26  2003-2011 Microchip Technology Inc.

25AA128/25LC128 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, • Development Systems Information Line application notes and sample programs, design resources, user’s guides and hardware support Customers should contact their distributor, documents, latest software releases and archived representative or field application engineer (FAE) for software support. Local sales offices are also available to help • General Technical Support – Frequently Asked customers. A listing of sales offices and locations is Questions (FAQ), technical support requests, included in the back of this document. online discussion groups, Microchip consultant Technical support is available through the web site program member listing at: http://microchip.com/support • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2003-2011 Microchip Technology Inc. DS21831E-page 27

25AA128/25LC128 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480)792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager Total Pages Sent ________ RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: 25AA128/25LC128 Literature Number: DS21831E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21831E-page 28  2003-2011 Microchip Technology Inc.

25AA128/25LC128 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X – X /XX Examples: Device Tape & Reel Temp Range Package a) 25AA128T-I/SN = 128k-bit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, SOIC package b) 25AA128T-I/ST = 128k-bit, 1.8V Serial EEPROM, Industrial temp., Tape & Reel, Device: 25AA128 = 128k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM TSSOP package 25LC128 = 128k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM 25AA128X = 128k-bit, 1.8V, 64-Byte Page, SPI Serial EEPROM c) 25LC128-I/P = 128k-bit, 2.5V Serial EEPROM, in alternate pinout (ST only) Industrial temp., P-DIP package 25LC128X = 128k-bit, 2.5V, 64-Byte Page, SPI Serial EEPROM d) 25LC128T-E/MF = 128k-bit, 2.5V Serial in alternate pinout (ST only) EEPROM, Extended temp., Tape & Reel, DFN package Tape & Reel: Blank = Standard packaging (tube) e) 25LC128XT-I/ST = 128k-bit, 2.5V Serial T = Tape & Reel EEPROM, Industrial temp., Tape & Reel, Temperature I = -40C to+85C Rotated pinout, TSSOP package Range: E = -40C to+125C Package: MF = Micro Lead Frame (6 x 5 mm body), 8-lead P = Plastic DIP (300 mil body), 8-lead SN = Plastic SOIC (3.90 mm body), 8-lead SM = Plastic SOIJ (5.28 mm body), 8-lead ST = TSSOP, 8-lead  2003-2011 Microchip Technology Inc. DS21831E-page 29

25AA128/25LC128 NOTES: DS21831E-page 30  2003-2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, chipKIT, devices in life support and/or safety applications is entirely at chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, hold harmless Microchip from any and all damages, claims, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, suits, or expenses resulting from such use. No licenses are Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, conveyed, implicitly or otherwise, under any Microchip MPLINK, mTouch, Omniscient Code Generation, PICC, intellectual property rights. PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-354-8 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2003-2011 Microchip Technology Inc. DS21831E-page 31

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