Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 TPS6103x 96% Efficient Synchronous Boost Converter With 4A Switch 1 Features 3 Description • 96%EfficientSynchronousBoostConverterWith The TPS6103x devices provide a power supply 1 solution for products powered by either a one-cell Li- 1000-mAOutputCurrent Ion or Li-polymer, or a two to three-cell alkaline, NiCd From1.8-VInput or NiMH battery. The converter generates a stable • DeviceQuiescentCurrent:20-µA(Typ) output voltage that is either adjusted by an external • InputVoltageRange:1.8-Vto5.5-V resistor divider or fixed internally on the chip. It provides high efficient power conversion and is • FixedandAdjustableOutputVoltageOptionsUp capable of delivering output currents up to 1 A at 5 V to5.5-V at a supply voltage down to 1.8 V. The implemented • PowerSaveModeforImprovedEfficiencyatLow boost converter is based on a fixed frequency, pulse- OutputPower width- modulation (PWM) controller using a • LowBatteryComparator synchronous rectifier to obtain maximum efficiency. At low load currents the converter enters Power Save • LowEMI-Converter(IntegratedAntiringingSwitch) mode to maintain a high efficiency over a wide load • LoadDisconnectDuringShutdown current range. The Power Save mode can be • Over-TemperatureProtection disabled, forcing the converter to operate at a fixed • AvailableinaSmall4mmx4mmQFN-16orina switching frequency. It can also operate synchronized to an external clock signal that is applied to the TSSOP-16Package SYNC pin. The maximum peak current in the boost switchislimitedtoavalueof4500mA. 2 Applications All Single Cell Li or Dual Cell Battery Operated The converter can be disabled to minimize battery drain. During shutdown, the load is completely Products as MP-3 Player, PDAs, and Other disconnected from the battery. A low-EMI mode is PortableEquipment implemented to reduce ringing and, in effect, lower radiated electromagnetic energy when the converter entersthediscontinuousconductionmode. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) TPS61030 TPS61031 TSSOP(16) 5.00mm×4.40mm TPS61032 TPS61030 TPS61031 QFN(16) 4.00mmx4.00mm TPS61032 (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic L1 SW VOUT e.g. 5 V up to 6.8µH 1000 mA C2 C3 VBAT R3 2.2µF 220µF 1.8 V to 5 V C1 R1 EN FB Input 10µF LBI R4 R6 R2 SYNC LBO Low Battery Comparator GND PGND Output TPS6103x 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com Table of Contents 1 Features.................................................................. 1 10.3 FeatureDescription...............................................10 2 Applications........................................................... 1 10.4 DeviceFunctionalModes......................................10 3 Description............................................................. 1 11 ApplicationandImplementation........................ 12 4 SimplifiedSchematic............................................. 1 11.1 ApplicationInformation..........................................12 11.2 TypicalApplication ...............................................12 5 RevisionHistory..................................................... 2 12 PowerSupplyRecommendations..................... 18 6 DeviceComparisonTable..................................... 3 13 Layout................................................................... 18 7 PinConfigurationandFunctions......................... 3 13.1 LayoutConsiderations..........................................18 8 Specifications......................................................... 4 13.2 LayoutExample....................................................18 8.1 AbsoluteMaximumRatings......................................4 13.3 ThermalConsiderations........................................18 8.2 ESDRatings ............................................................4 14 DeviceandDocumentationSupport................. 19 8.3 RecommendedOperatingConditions.......................4 14.1 DeviceSupport......................................................19 8.4 ThermalInformation..................................................4 14.2 RelatedLinks........................................................19 8.5 ElectricalCharacteristics...........................................5 14.3 Trademarks...........................................................19 8.6 TypicalCharacteristics..............................................6 14.4 ElectrostaticDischargeCaution............................19 9 ParameterMeasurementInformation..................8 14.5 Glossary................................................................19 10 DetailedDescription............................................. 9 15 Mechanical,Packaging,andOrderable 10.1 Overview.................................................................9 Information........................................................... 19 10.2 FunctionalBlockDiagram.......................................9 5 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionF(October2014)toRevisionG Page • MovedT spectotheAbsoluteMaximumRatingstable.ChangedHandlingRatingstoESDRatings............................... 4 stg • AddedSystemExamples .................................................................................................................................................... 16 ChangesfromRevisionE(January2012)toRevisionF Page • AddedDeviceInformationandHandlingRatingtables,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection ..................................... 1 ChangesfromRevisionD(April2004)toRevisionE Page • ChangedthetemperaturerangeFrom:40°Cto85°CTo:-40°Cto85°C.............................................................................. 3 2 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 6 Device Comparison Table (1) T OUTPUTVOLTAGE PACKAGE PARTNUMBER(1) A DC/DC Adjustable TPS61030 3.3V 16-PinTSSOPPowerPAD™ TPS61031 5V TPS61032 -40°Cto85°C Adjustable TPS61030 3.3V 16-PinQFN TPS61031 5V TPS61032 (1) Contactthefactorytocheckavailabilityofotherfixedoutputvoltageversions. (1) Forallavailablepackages,seetheorderableaddendumattheendofthedatasheet. 7 Pin Configuration and Functions PWPPackage 16-Pins RSAPackage TopView 16-Pins TopView SW 1 16 NC T T U U D SW 2 15 VOUT O O BN PGND 3 14 VOUT V V FG PGND 4 13 VOUT PowerPAD VOUT LBO PGND 5 12 FB NC EN VBAT 6 11 GND LBI 7 10 LBO SW SYNC SYNC 8 9 EN SW LBI D D DT NC−No internal connection GN GN GNBA V P P P PinFunctions PIN NO. I/O DESCRIPTION NAME PWP RSA EN 9 11 I Enableinput.(1/VBATenabled,0/GNDdisabled) FB 12 14 I Voltagefeedbackofadjustableversions GND 11 13 I/O Control/logicground LBI 7 9 I Lowbatterycomparatorinput(comparatorenabledwithEN) LBO 10 12 O Lowbatterycomparatoroutput(opendrain) NC 16 2 Notconnected PGND 3,4,5 5,6,7 I/O Powerground PowerPAD™ Mustbesolderedtoachieveappropriatepowerdissipation.Shouldbeconnectedto PGND. SYNC 8 10 I Enable/disablepowersavemode(1/VBATdisabled,0/GNDenabled,clocksignalfor synchronization) SW 1,2 3,4 I Boostandrectifyingswitchinput VBAT 6 8 I Supplyvoltage VOUT 13,14,15 1,15,16 O DC/DCoutput Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V InputvoltageonLBI –0.3 3.6 V I InputvoltageonSW,VOUT,LBO,VBAT,SYNC,EN,FB –0.3 7 V T Maximumjunctiontemperature –40 150 J °C T Storagetemperaturerange –65 150 stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 8.2 ESD Ratings MIN MAX UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all –2000 2000 pins(1) V Electrostaticdischarge V (ESD) Chargeddevicemodel(CDM),perJEDECspecificationJESD22- –1000 1000 C101,allpins(2) (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 8.3 Recommended Operating Conditions MIN NOM MAX UNIT V SupplyvoltageatVBAT 1.8 5.5 V I T Operatingambienttemperaturerange -40 85 °C A T Operatingvirtualjunctiontemperaturerange -40 125 °C J 8.4 Thermal Information TPS6103x THERMALMETRIC(1) PWP RSA UNIT 16PINS 16PINS R Junction-to-ambientthermalresistance 46.9 35.5 θJA R Junction-to-case(top)thermalresistance 25.8 36.7 θJC(top) R Junction-to-boardthermalresistance 19.4 12.9 θJB °C/W ψ Junction-to-topcharacterizationparameter 0.8 0.5 JT ψ Junction-to-boardcharacterizationparameter 19.3 12.9 JB R Junction-to-case(bottom)thermalresistance 2.2 3.8 θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 4 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 8.5 Electrical Characteristics overrecommendedfree-airtemperaturerangeandoverrecommendedinputvoltagerange(typicalatanambienttemperature rangeof25°C)(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DC/DCSTAGE V Inputvoltagerange 1.8 5.5 V I V TPS61030outputvoltagerange 1.8 5.5 V O V TPS61030feedbackvoltage 490 500 510 mV FB f Oscillatorfrequency 500 600 700 kHz Frequencyrangeforsynchronization 500 700 kHz Switchcurrentlimit VOUT=5V 3600 4000 4500 mA Start-upcurrentlimit 0.4xI mA SW SWNswitchonresistance VOUT=5V 55 mΩ SWPswitchonresistance VOUT=5V 55 mΩ Totalaccuracy -3% 3% Lineregulation 0.6% Loadregulation 0.6% I =0mA,V =VBAT=1.8V, VBAT O EN 10 25 µA VOUT=5V Quiescentcurrent I =0mA,V =VBAT=1.8V, VOUT O EN 10 20 µA VOUT=5V Shutdowncurrent V =0V,VBAT=2.4V 0.1 1 µA EN CONTROLSTAGE V Undervoltagelockoutthreshold V voltagedecreasing 1.5 V UVLO LBI V LBIvoltagethreshold V voltagedecreasing 490 500 510 mV IL LBI LBIinputhysteresis 10 mV LBIinputcurrent EN=VBATorGND 0.01 0.1 µA LBOoutputlowvoltage V =3.3V,I =100µA 0.04 0.4 V O OI LBOoutputlowcurrent 100 µA LBOoutputleakagecurrent V =7V 0.01 0.1 µA LBO V EN,SYNCinputlowvoltage 0.2×VBAT V IL V EN,SYNCinputhighvoltage 0.8×VBAT V IH EN,SYNCinputcurrent ClampedonGNDorVBAT 0.01 0.1 µA Overtemperatureprotection 140 °C Overtemperaturehysteresis 20 °C Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com 8.6 Typical Characteristics Table1.TableOfGraphs DC/DCCONVERTER FIGURE Figure1, Maximumoutputcurrent vsInputvoltage Figure2 vsOutputcurrent(TPS61030)(V =2.5V,V =1.8V,VSYNC=0V) Figure3 O I vsOutputcurrent(TPS61031)(V =3.3V,V =1.8V,2.4V,VSYNC=0V) Figure4 O I Efficiency vsOutputcurrent(TPS61032)(V =5.0V,V =2.4V,3.3V,VSYNC=0V) Figure5 O I vsInputvoltage(TPS61031)(I =10mA,100mA,1000mA,VSYNC=0V) Figure6 O vsInputvoltage(TPS61032)(I =10mA,100mA,1000mA,VSYNC=0V) Figure7 O vsOutputcurrent(TPS61031)(V =2.4V) Figure8 I Outputvoltage vsOutputcurrent(TPS61032)(V =3.3V) Figure9 I No-loadsupplycurrentintoVBAT vsInputvoltage(TPS61032) Figure10 No-loadsupplycurrentintoVOUT vsInputvoltage(TPS61032) Figure11 MinimumLoadResistanceat vsInputvoltage(TPS61032) Figure12 Startup 3.5 3.5 3 3 A A - 2.5 - 2.5 nt nt e e urr urr ut C 2 ut C 2 p p ut ut m O 1.5 m O 1.5 u u m m axi 1 axi 1 M M 0.5 0.5 0 0 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 VI -Input Voltage-V VI -Input Voltage-V Figure1.TPS61031MaximumOutputCurrent Figure2.TPS61032MaximumOutputCurrent vsInputVoltage vsInputVoltage 6 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 100 100 90 90 VBAT= 1.8 V 80 80 VBAT= 2.4 V 70 70 % 60 % 60 Eff-iciency 4500 -Efficiency 4500 30 30 20 20 10 10 0 0 1 10 100 1000 10000 1 10 100 1000 10000 IO-Output Current-mA IO-Output Current-mA VO=2.5V VI=1.8V VO=3.3V Figure3.TPS61030EfficiencyvsOutputCurrent Figure4.TPS61031EfficiencyvsOutputCurrent 100 100 IO= 100 mA 90 VBAT= 2.4 V 80 90 IO= 1000 mA 70 VBAT= 3.3 V IO= 10 mA % 60 % 80 Effici-ency 4500 -Efficiency 70 30 20 60 10 0 50 1 10 100 1000 10000 1.8 2 2.2 2.4 2.6 2.8 3 3.2 IO-Output Current-mA VI-Input Voltage-V V =5V O Figure5.Tps61032EfficiencyvsOutputCurrent Figure6.TPS61031EfficiencyvsInputVoltage 100 3.4 IO= 100 mA 95 90 3.35 85 IO= 10 mA V - Effici-%ency 778050 IO= 1000 mA oltOutput Vage 3.3 65 -O V 3.25 60 55 50 3.2 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 1 10 100 1000 10000 VI-Input Voltage-V IO-Output Current-mA VBAT=2.4V Figure7.TPS61032EfficiencyvsInputVoltage Figure8.TPS61031OutputVoltagevsOutputCurrent Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com 5.2 16 5.15 A 14 85°C µ 5.1 T-A 12 25°C g-Ve 5.05 nto VB 10 –40°C oltaut V 5 urrent I 8 p C Out 4.95 ply 6 -O Sup V 4.9 d 4 a o L 4.85 o- 2 N 4.8 0 1 10 100 1000 10000 2 3 4 5 IO-Output Current-mA VI-Input Voltage-V VBAT=3.3V Figure9.TPS61032OutputVoltage Figure10.TPS61032No-LoadSupplyCurrentintoVbat vsOutputCurrent vsinputVoltage 14 14 85°C µA- 12 25°C Ω-p 12 T u nt Into VOU 108 –40°C nce at Start 108 e a y Curr 6 Resist 6 pl d p a u o d S 4 m L 4 Loa mu No- 2 Mini 2 0 0 2 3 4 5 1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 VI-Input Voltage-V VI -Input Voltage-V Figure11.TPS61032No-LoadSupplyCurrentIntoVout Figure12.MinimumLoadResistanceatStart-Up vsInputVoltage vsInputVoltage 9 Parameter Measurement Information L1 6.8 m H SW VOUT VCC C2 C3 Boost Output VBAT R3 2.2 m F 220 m F Power C1 R1 EN FB Supply 10 m F LBI R4 R6 R2 SYNC LBO Control Output GND PGND List of Components: TPS6103x U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C1, C2 = X7R/X5R Ceramic C3 = Low ESR Tantalum 8 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 10 Detailed Description 10.1 Overview The TPS6103x synchronous step-up converter typically operates at a 600 kHz frequency pulse width modulation (PWM) at moderate to heavy load currents. The converter enters Power Save mode at low load currents to maintain a high efficiency over a wide load. The Power Save mode can also be disabled, forcing the converter to operate at a fixed switching frequency. The TPS6103x family is based on a fixed frequency with multiple feed forward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and the inductor. It can also operate synchronized to an external clock signal that is applied to the SYNC pin. Additionally, TPS6103x integrated the low-battery detector circuit typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user-set thresholdvoltage. 10.2 Functional Block Diagram SW VOUT Anti- VBAT Ringing PGND PGND Gate Control PGND 100 k(cid:1) 10 pF Error Amplifier _ FB Regulator + + VREF = 0.5 V _ Control Logic Oscillator GND Temperature EN Control SYNC GND LBI + Low Battery Comparator _ LBO + _ VREF = 0.5 V GND Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com 10.3 Feature Description 10.3.1 ControllerCircuit The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect andslowwaythroughthecontrolloopandtheerroramplifier.Thecontrolloop,determinedbytheerroramplifier, only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to generateanaccurateandstableoutputvoltage. ThepeakcurrentoftheNMOSswitchisalsosensedtolimitthemaximumcurrentflowingthroughtheswitchand the inductor. The typical peak current limit is set to 4000 mA. An internal temperature sensor prevents the device fromgettingoverheatedincaseofexcessivepowerdissipation. 10.3.2 SynchronousRectifier The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier. Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power conversion efficiency reaches 96%. To avoid ground shift due to the high currents in the NMOS switch, two separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND pin. A special circuit is applied to disconnect the load from the input during shutdown of the converter. In conventional synchronous rectifier circuits, the backgate diode of the high-side PMOS is forward biased in shutdown and allows current flowing from the battery to the output. This device however uses a special circuit which takes the cathode of the backgate diode of the high-side PMOS and disconnects it from the source when theregulatorisnotenabled(EN=low). The benefit of this feature for the system design engineer is that the battery is not depleted during shutdown of the converter. No additional components have to be added to the design to make sure that the battery is disconnectedfromtheoutputoftheconverter. 10.4 Device Functional Modes 10.4.1 DeviceEnable The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is switched off, and the load is isolated from the input (as described in the Synchronous Rectifier Section). This also means that the output voltage can drop below the input voltage during shutdown. During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak currents drawn from the battery. 10.4.1.1 UndervoltageLockout An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than approximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters the shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is implementedinordertopreventthemalfunctioningoftheconverter. 10.4.2 Softstart When the device enables the internal start-up cycle starts with the first step, the precharge phase. During precharge, the rectifying switch is turned on until the output capacitor is charged to a value close to the input voltage.Therectifyingswitchcurrentislimitedinthatphase.Thisalsolimitstheoutputcurrentundershort-circuit conditions at the output. After charging the output capacitor to the input voltage the device starts switching. Until the output voltage is reached, the boost switch current limit is set to 40% of its nominal value to avoid high peak currents at the battery during startup. When the output voltage is reached, the regulator takes control and the switchcurrentlimitissetbackto100%. 10 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 Device Functional Modes (continued) 10.4.3 PowerSaveModeAndSynchronization The SYNC pin can be used to select different operation modes. To enable power save, SYNC must be set low. Power save mode is used to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with one or several pulses and goes again into power save mode once the output voltage exceeds the set threshold voltage. This powersavemodecanbedisabledbysettingtheSYNCtoVBAT. Applying an external clock with a duty cycle between 30% and 70% at the SYNC pin forces the converter to operate at the applied clock frequency. The external frequency has to be in the range of about ±20% of the nominalinternalfrequency.Detailedvaluesareshownintheelectricalcharacteristicsectionofthedatasheet. 10.4.4 LowBatteryDetectorCircuit—LBI/LBO The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI. During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold. ItisactivelowwhenthevoltageatLBIgoesbelow500mV. The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV, which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the application section for more details about the programming of the LBI threshold. If the low-battery detection circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left unconnected.DonotlettheLBIpinfloat. 10.4.5 Low-EMISwitch The device integrates a circuit that removes the ringing that typically appears on the SW node when the converterentersdiscontinuouscurrentmode.Inthiscase,thecurrentthroughtheinductorrampstozeroandthe rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and thereforedampensringing. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com 11 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 11.1 Application Information The TPS6103x dc/dc converters are intended for systems powered by a dual or triple cell NiCd or NiMH battery with a typical terminal voltage between 1.8 V and 5.5 V. They can also be used in systems powered by one-cell Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two or three primary and secondary alkalinebatterycellscanbethepowersourceinsystemswheretheTPS6103xisused. 11.2 Typical Application L1 SW VOUT VCC Boost Output C2 C3 VBAT R3 Power C1 R1 EN FB Supply LBI R4 R6 R2 SYNC LBO Control Output GND PGND TPS6103x Figure13. TypicalApplicationCircuitForAdjustableOutputVoltageOption 11.2.1 DesignRequirements Use the following typical application design procedure to select external components values for the TPS61030 device. Table2.TPS610305VOutputDesignParameters DESIGNPARAMETERS EXAMPLEVALUES InputVoltageRange 1.8Vto5.5V OutputVoltage 5.0V OutputVoltageRipple +/-3%V OUT TransientResponse +/-10%V OUT InputVoltageRipple +/-200mV OutputCurrent 2A OperatingFrequency 600kHz 12 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 11.2.2 DetailedDesignProcedure 11.2.2.1 ProgrammingTheOutputVoltage The output voltage of the TPS61030 dc/dc converter section can be adjusted with an external resistor divider. The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is 5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB pin.ThetypicalcurrentintotheFBpinis0.01 µA,andthevoltageacrossR6istypically500mV.Basedonthose two values, the recommended value for R4 should be lower than 500 kΩ, in order to set the divider current at 1 µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200 kΩ. From that, the value of resistor R3, depending on the needed output voltage (V ), can be calculated using O equation1: (cid:4)V (cid:5) (cid:4) V (cid:5) R3(cid:3)R4(cid:1) O (cid:2)1 (cid:3)180k(cid:1)(cid:1) O (cid:2)1 V 500mV FB (1) If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. If for any reason the value for R4 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is recommended.TherequiredcapacitancevaluecanbeeasilycalculatedusingEquation2: (cid:3)200k(cid:1) (cid:4) CparR3(cid:2)10pF(cid:1) R4 –1 (2) 11.2.2.2 ProgrammingTheLBI/LBOThresholdVoltage The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is generatedon-chip,whichhasavalueof500mV.TherecommendedvalueforR2 isthereforeintherangeof500 kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage V can be BAT, calculatedusingEquation3. (cid:4) V (cid:5) (cid:4) V (cid:5) R1(cid:3)R2(cid:1) BAT (cid:2)1 (cid:3)390k(cid:1)(cid:1) BAT (cid:2)1 V 500mV LBI(cid:2)threshold (3) The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not exceedtheoutputvoltageofthedc/dcconverter.Ifnotused,theLBOpincanbeleftfloatingortiedtoGND. 11.2.2.3 InductorSelection A boost converter normally requires two main passive components for storing energy during the conversion. A boost inductor and a storage capacitor at the output are required. To select the boost inductor, it is recommended to keep the possible peak inductor current below the current limit threshold of the power switch in the chosen configuration. For example, the current limit threshold of the TPS6103x's switch is 4500 mA at an output voltage of 5 V. The highest peak current through the inductor and the switch depends on the output load, theinput(V ),andtheoutputvoltage(V ).Estimationofthemaximumaverageinductorcurrentcanbedone BAT OUT usingEquation4: V I (cid:2)I (cid:1) OUT L OUT V (cid:1)0.8 BAT (4) For example, for an output current of 1000 mA at 5 V, at least 3500 mA of average current flows through the inductorataminimuminputvoltageof1.8V. The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is advisable to work with a ripple of less than 20% of the average inductor current. A smaller ripple reduces the magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way, regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those parameters,itispossibletocalculatethevaluefortheinductorbyusingEquation5: Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com VBAT(cid:1)(cid:3)VOUT–VBAT(cid:4) L(cid:2) (cid:1)IL(cid:1)ƒ(cid:1)VOUT (5) Parameter f is the switching frequency and ΔI is the ripple current in the inductor, i.e., 10% × I . In this example, L L the desired inductor has the value of 5.5 µH. In typical applications a 6.8 µH inductance is recommended. The minimum possible inductance value is 2.2 µH. With the calculated inductance and current values, it is possible to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can lead to higher currents as estimated in equation 4. Also, the losses in the inductor caused by magnetic hysteresis losses and copperlossesareamajorparameterfortotalcircuitefficiency. ThefollowinginductorseriesfromdifferentsuppliershavebeenusedwiththeTPS6103xconverters: Table3.ListOfInductors(1) VENDOR INDUCTORSERIES CDRH124 Sumida CDRH103R CDRH104R 7447779___ WurthElectronik 744771___ EPCOS B82464G (1) SeeThird-PartyProductsDisclaimer 11.2.2.4 CapacitorSelection 11.2.2.4.1 InputCapacitor At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in parallel,placedclosetotheIC,isrecommended. 11.2.2.4.2 OutputCapacitor The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by usingEquation6: IOUT(cid:1)(cid:4)VOUT(cid:2)VBAT(cid:5) Cmin(cid:3) ƒ(cid:1)(cid:1)V(cid:1)VOUT (6) ParameterfistheswitchingfrequencyandΔVisthemaximumallowedripple. With a chosen ripple voltage of 10 mV, a minimum capacitance of 100 µF is needed. The total ripple is larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation7: (cid:1)V (cid:2)I (cid:1)R ESR OUT ESR (7) Anadditionalrippleof80mVistheresultofusingatantalumcapacitorwithalowESRof80mΩ.Thetotalripple is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this example, the total ripple is 90 mV. Additional ripple is caused by load transients. This means that the output capacitanceneedstobelargerthancalculatedabovetomeetthetotalripplerequirements. The output capacitor must completely supply the load during the charging phase of the inductor. A reasonable value of the output capacitance depends on the speed of the load transients and the load current during the load change. With the calculated minimum value of 100 µF and load transient considerations, a recommended output capacitance value is in around 220 µF. For economical reasons this usually is a tantalum capacitor. Because of this the control loop has been optimized for using output capacitors with an ESR of above 30 mΩ. The minimum valuefortheoutputcapacitoris22µF. 14 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 11.2.2.4.2.1 SmallSignalStability When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the range of 10 pF in parallel to R3 helps to obtain small signal stability with lowest ESR output capacitors. For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in Equation 8,canbeused. A (cid:3) d (cid:3) 5(cid:1)(R3(cid:2)R4) REG V R4(cid:1)(1(cid:2)i(cid:1)(cid:2)(cid:1)2.3(cid:1)s) FB (8) 11.2.3 ApplicationCurves Output Voltage 20 mV/Div Output Voltage 50 mV/Div,AC Inductor Current 200 mA/Div Inductor Current 200 mA/Div, DC Timebase-1ms/Div Timebase-200ms/Div VI=3.3V RL=5Ω VI=3.3V RL=100Ω Figure14.TPS61030OutputVoltageinContinuousMode Figure15.TPS61030OutputVoltageinPowerSaveMode Output Current Input Voltage 500 mA/Div, DC 500 mV/Div, DC Output Voltage 20 mV/Div,AC Output Voltage 50 mV/Div,AC Timebase-2 ms/Div Timebase-2 ms/Div VI=2.5V IL=80mAto800mA VI=2.2Vto2.7V RL=50Ω Figure16.TPS61030LoadTransientResponse Figure17.TPS61030LineTransientResponse Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com Enable 5 V/Div, DC Output Voltage 2 V/Div, DC Input Current 500 mA/Div, DC Voltage at SW 2 V/Div, DC Timebase-400ms/Div V =2.4V R =20Ω I L Figure18.TPS61030DC/DCConverterStart-UpAfterEnable 11.2.4 SystemExamples 11.2.4.1 PowerSupplySolutionForMaximumOutputPower Secondapplicationexample L1 SW VOUT VCC 5 V 6.8 m H Boost Output C2 C3 Battery VBAT 2.2 m F 220 m F Input C1 R1 EN FB 10 m F LBI R6 R2 SYNC LBO LBO GND PGND TPS61032 List of Components: U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C1, C2 = X7R,X5R Ceramic C3 = Low ESR Tantalum Figure19. PowerSupplySolutionForMaximumOutputPower 16 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 11.2.4.2 PowerSupplySolutionWithAuxiliaryPositiveOutputVoltage Thirdapplicationexample VCC2 10 V C5 DS1 Unregulated Auxiliary Output C6 0.1 m F 1 m F L1 6.8 m H SW VOUT C2 C3 VBCoCo1s t5 M Vain Output Battery VBAT 2.2 m F 220 m F Input C3 R1 EN 10 m F R6 LBI FB R2 SYNC LBO LBO GND PGND List of Components: TPS61032 U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C3, C5, C6, = X7R,X5R Ceramic C3 = Low ESR Tantalum DS1 = BAT54S Figure20. PowerSupplySolutionWithAuxiliaryPositiveOutputVoltage 11.2.4.3 PowerSupplySolutionwithAuxiliaryNegativeOutputVoltage Fourthapplicationexample VCC2 –5 V C5 DS1 Unregulated C6 Auxiliary Output 1 m F 0.1 m F L1 6.8 m H SW VOUT C2 C3 VBCoCo1s t5 M Vain Output Battery VBAT 2.2 m F 220 m F Input C1 R1 EN 10 m F R6 LBI FB R2 SYNC LBO LBO GND PGND List of Components: TPS61032 U1 = TPS6103xPWP L1 = Sumida CDRH124–6R8 C1, C2, C5, C6 = X7R,X5R Ceramic C3 = Low ESR Tantalum DS1 = BAT54S Figure21. PowerSupplySolutionWithAuxiliaryNegativeOutputVoltage Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 www.ti.com 12 Power Supply Recommendations Thedeviceisdesignedtooperatefromaninputvoltagesupplyrangebetween1.8Vand5.5V.Thisinputsupply must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic or tantalum capacitor withavalueof47 μFisatypicalchoice. 13 Layout 13.1 Layout Considerations As for all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of groundnoise.ConnectthesegroundnodesatanyplaceclosetooneofthegroundpinsoftheIC. The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the control ground, it is recommended to use short traces as well, separated from the power ground traces. This avoids ground shift problems, which can occur due to superimposition of power ground current and control groundcurrent. 13.2 Layout Example VIA to Ground Plane Input Capacitor VIA to VBAT Plane T D D D A N N N Inductor B G G G LBI V P P P Resistor 1 LBI SW SYNC SW Output LBI Exposed PAD Capacitor 2 Resistor 2 EN NC LBO VOUT GND G F V V N B O O D U U Feedback T T Feedback Resistor 2 Output Resistor 1 LBO Resistor Capacitor 1 GND 13.3 Thermal Considerations Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power- dissipationlimitsofagivencomponent. 18 SubmitDocumentationFeedback Copyright©2002–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS61030 TPS61031 TPS61032

TPS61030,TPS61031,TPS61032 www.ti.com SLUS534G–SEPTEMBER2002–REVISEDMARCH2015 Thermal Considerations (continued) Threebasicapproachesforenhancingthermalperformancearelistedbelow: • ImprovingthepowerdissipationcapabilityofthePCBdesign • ImprovingthethermalcouplingofthecomponenttothePCB • Introducingairflowinthesystem The maximum junction temperature (T ) of the TPS6103x devices is 125°C. The thermal resistance of the 16-pin J TSSOP PowerPAD package (PWP) is R = 36.5°C/W (QFN package, RSA, 38.1°C/W), if the PowerPAD is ΘJA soldered. Specified regulator operation is assured to a maximum ambient temperature T of 85°C. Therefore, the A maximum power dissipation for the PWP package is about 1096 mW, for the RSA package it is about 1050 mW. Morepowercanbedissipatedifthemaximumambienttemperatureoftheapplicationislower. T (cid:1)T J(MAX) A 125°C(cid:1)85°C P (cid:2) (cid:2) D(MAX) R(cid:1)JA 36.5°C(cid:3)W (9) 14 Device and Documentation Support 14.1 Device Support 14.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 14.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table4.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER SAMPLE&BUY DOCUMENTS SOFTWARE COMMUNITY TPS61030 Clickhere Clickhere Clickhere Clickhere Clickhere TPS61031 Clickhere Clickhere Clickhere Clickhere Clickhere TPS61032 Clickhere Clickhere Clickhere Clickhere Clickhere 14.3 Trademarks PowerPADisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 14.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 14.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 15 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2002–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS61030 TPS61031 TPS61032

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS61030PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61030 & no Sb/Br) TPS61030PWPG4 ACTIVE HTSSOP PWP 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61030 & no Sb/Br) TPS61030PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61030 & no Sb/Br) TPS61030PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61030 & no Sb/Br) TPS61030RSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 & no Sb/Br) 1030 TPS61030RSARG4 ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 & no Sb/Br) 1030 TPS61031PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61031 & no Sb/Br) TPS61031PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61031 & no Sb/Br) TPS61031PWPRG4 ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61031 & no Sb/Br) TPS61031RSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 & no Sb/Br) 1031 TPS61032PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61032 & no Sb/Br) TPS61032PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 PS61032 & no Sb/Br) TPS61032RSAR ACTIVE QFN RSA 16 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS6 & no Sb/Br) 1032 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS61030PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS61030RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPS61031PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS61031RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 TPS61032PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TPS61032RSAR QFN RSA 16 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS61030PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 TPS61030RSAR QFN RSA 16 3000 350.0 350.0 43.0 TPS61031PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 TPS61031RSAR QFN RSA 16 3000 350.0 350.0 43.0 TPS61032PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0 TPS61032RSAR QFN RSA 16 3000 350.0 350.0 43.0 PackMaterials-Page2

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PACKAGE OUTLINE PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE 6.6 TYP C A 6.2 PIN 1 INDEX 0.1 C AREA 14X 0.65 SEATING 16 PLANE 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 4.5 16X B 0.19 4.3 0.1 C A B SEE DETAIL A (0.15) TYP 2X 0.95 MAX NOTE 5 4X (0.3) 8 9 2X 0.23 MAX NOTE 5 2.31 17 0.25 1.75 GAGE PLANE 1.2 MAX 0.75 0.15 1 16 0 -8 0.50 0.05 DETA 20AIL A THERMAL 2.46 TYPICAL PAD 1.75 4224559/B 01/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may differ or may not be present. www.ti.com

EXAMPLE BOARD LAYOUT PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (3.4) NOTE 9 (2.46) 16X (1.5) SYMM METAL COVERED BY SOLDER MASK 1 16X (0.45) 16 (1.2) TYP (R0.05) TYP SYMM 17 (2.31) (5) (0.6) NOTE 9 14X (0.65) ( 0.2) TYP VIA 8 9 SOLDER MASK (1) TYP DEFINED PAD SEE DETAILS (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDE15.000R MASK DETAILS 4224559/B 01/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. 10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN PWP0016C PowerPAD TM TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE (2.46) BASED ON 16X (1.5) 0.125 THICK METAL COVERED STENCIL BY SOLDER MASK 1 16X (0.45) 16 (R0.05) TYP (2.31) SYMM 17 BASED ON 0.125 THICK STENCIL 14X (0.65) 8 9 SYMM SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL (5.8) THICKNESSES SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.75 X 2.58 0.125 2.46 X 2.31 (SHOWN) 0.15 2.25 X 2.11 0.175 2.08 X 1.95 4224559/B 01/2019 NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design. www.ti.com

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