Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 TLC6C598-Q1 Power Logic 8-Bit Shift Register LED Driver 1 Features 3 Description • QualifiedforAutomotiveApplications The TLC6C598-Q1 is a monolithic, medium-voltage, 1 low-current power 8-bit shift register designed for use • AEC-Q100QualifiedWiththeFollowingResults: in systems that require relatively moderate load – DeviceTemperatureGrade1: –40°Cto125°C power,suchasLEDs. AmbientOperatingTemperatureRange This device contains an 8-bit serial-in, parallel-out – DeviceHBMESDClassificationLevelH2 shift register that feeds an 8-bit D-type storage – DeviceCDMESDClassificationLevelC3B register. Data transfers through both the shift and storage registers on the rising edge of the shift- • WideVccFrom3Vto5.5V register clock (SRCK) and the register clock (RCK), • OutputMaximumRatingof.40V respectively. The storage register transfers data to • EightPowerDMOSTransistorOutputsof50-mA the output buffer when shift register clear (CLR) is ContinuousCurrentWithV =5V high. A low on CLR clears all registers in the device. CC Holding the output enable (G) high, holds all data in • ThermalShutdownProtection the output buffers low, and all drain outputs are off. • EnhancedCascadingforMultipleStages Holding G low makes data from the storage register • AllRegistersClearedWithSingleInput transparent to the output buffers. When data in the • LowPowerConsumption outputbuffersislow,theDMOStransistoroutputsare off. When data is high, the DMOS transistor outputs • SlowSwitchingTime(t andt),WhichHelps r f have sink-current capability. The serial output (SER SignificantlyWithReducingEMI OUT) clocks out of the device on the falling edge of • 16-PinTSSOP-PWPackage SRCK to provide additional hold time for cascaded • 16-PinSOIC-DPackage applications. This provides improved performance for applications where clock signals may be skewed, 2 Applications devices are not located near one another, or the system must tolerate electromagnetic interference. • InstrumentationCluster The device contains built-in thermal shutdown • Tell-TaleLamps protection. • LEDIlluminationandControl Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous TypicalApplicationSchematic sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases Battery 9 V–40 V for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using themachinemodel. 30 mA 30 mA The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature 4/3 rangeof−40°Cto125°C. 8-Bit Shift Register MCU Serial I/F LED Driver DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) SOIC(16) 9.90mmx3.91mm TLC6C598-Q1 TSSOP(16) 5.00mmx4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8.2 FunctionalBlockDiagram.......................................11 2 Applications........................................................... 1 8.3 FeatureDescription.................................................12 3 Description............................................................. 1 8.4 DeviceFunctionalModes........................................12 4 RevisionHistory..................................................... 2 9 ApplicationandImplementation........................ 13 9.1 ApplicationInformation............................................13 5 PinConfigurationandFunctions......................... 3 9.2 TypicalApplication .................................................13 6 Specifications......................................................... 4 10 PowerSupplyRecommendations..................... 16 6.1 AbsoluteMaximumRatings......................................4 11 Layout................................................................... 16 6.2 ESDRatings..............................................................4 6.3 RecommendedOperatingConditions.......................4 11.1 LayoutGuidelines.................................................16 6.4 ThermalInformation..................................................4 11.2 LayoutExample....................................................16 6.5 ElectricalCharacteristics...........................................5 12 DeviceandDocumentationSupport................. 17 6.6 TimingRequirements................................................5 12.1 ReceivingNotificationofDocumentationUpdates17 6.7 SwitchingCharacteristics..........................................6 12.2 CommunityResources..........................................17 6.8 TimingWaveforms....................................................7 12.3 Trademarks...........................................................17 6.9 TypicalCharacteristics..............................................8 12.4 ElectrostaticDischargeCaution............................17 7 ParameterMeasurementInformation..................9 12.5 Glossary................................................................17 8 DetailedDescription............................................ 11 13 Mechanical,Packaging,andOrderable Information........................................................... 17 8.1 Overview.................................................................11 13.1 PackageOptionAddendum..................................18 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(October2015)toRevisionD Page • AddedReceivingNotificationofDocumentationUpdatessection....................................................................................... 17 • AddedneworderablepartnumbertoPackageOptionAddendum..................................................................................... 18 ChangesfromRevisionB(March2013)toRevisionC Page • AddedPinConfigurationandFunctionssection,ESDRatingstable,FeatureDescriptionsection,DeviceFunctional Modes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Device andDocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection .............................. 1 2 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 5 Pin Configuration and Functions PWPackage DPackage 16-PinTSSOP 16-PinSOIC TopView TopView VCC 1 16 GND VCC 1 16 GND SER_IN 2 15 SRCK SER_IN 2 15 SRCK DRAIN0 3 14 DRAIN7 DRAIN0 3 14 DRAIN7 DRAIN1 4 13 DRAIN6 DRAIN1 4 13 DRAIN6 DRAIN2 5 12 DRAIN5 DRAIN2 5 12 DRAIN5 DRAIN3 6 11 DRAIN4 DRAIN3 6 11 DRAIN4 CLR 7 10 RCK CLR 7 10 RCK G 8 9 SER_OUT G 8 9 SER_OUT PinFunctions PIN I/O DESCRIPTION NAME NO. CLR 7 I Shiftregisterclear,active-low.Thestorageregistertransfersdatatotheoutputbuffer whenCLRishigh.DrivingCLRlowclearsalltheregistersinthedevice. DRAIN0 3 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN1 4 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN2 5 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN3 6 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN4 11 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN5 12 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN6 13 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode DRAIN7 14 O Open-drainoutput,LEDcurrent-sinkchannel,connecttoLEDcathode G 8 I Outputenable,active-low.LED-channelenableanddisableinputpin.HavingGlow enablesalldrainchannelsaccordingtotheoutput-latchregistercontent.Whenhigh,all channelsareoff. GND 16 — Powerground,thegroundreferencepinforthedevice.Thispinmustconnecttothe groundplaneonthePCB. RCK 10 I Registerclock.Thedataineachshiftregisterstagetransferstothestorageregisteratthe risingedgeofRCK. SERIN 2 I Serialdatainput.DataonSERINloadsintotheinternalregisteroneachrisingedgeof SRCK. SEROUT 9 O Serialdataoutputofthe8-bitserialshiftregister.Thepurposeofthispinistocascade severaldevicesontheserialbus. SRCK 15 I Serialclockinput.OneachrisingSRCKedge,datatransfersfromSERINtotheinternal serialshiftregisters. V 1 I Powersupplypinforthedevice.TIrecommendsaddinga0.1-μFceramiccapacitorclose CC tothepin. Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Logicsupplyvoltage –0.3 8 V CC V Logicinput-voltagerange –0.3 8 V I V PowerDMOSdrain-to-sourcevoltage –0.3 42 V DS Continuoustotaldissipation SeeThermalInformation T Operatingambienttemperature –40 125 °C A T Operatingjunctiontemperaturerange –40 150 °C J T Storagetemperaturerange –55 165 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,anddonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perAECQ100-002(1) ±2000 Allpins ±750 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perAEC V Q100-011 Cornerpins(1,8,9,and ±750 16) (1) AECQ100-002indicatesHBMstressingisdoneinaccordancewiththeANSI/ESDA/JEDECJS-001specification. 6.3 Recommended Operating Conditions MIN MAX UNIT V Supplyvoltage 3 5.5 V CC V High-levelinputvoltage 2.4 V IH V Low-levelinputvoltage 0.7 V IL T Operatingambienttemperature –40 125 °C A 6.4 Thermal Information TLC6C598-Q1 THERMALMETRIC(1) PW(TSSOP) D(SOIC) UNIT 16PINS 16PINS R Junction-to-ambientthermalresistance 129.4 100 °C/W θJA R Junction-to-case(top)thermalresistance 55.4 45 °C/W θJC(top) R Junction-to-boardthermalresistance 65.8 40 °C/W θJB ψ Junction-to-topcharacterizationparameter 9.9 10 °C/W JT ψ Junction-to-boardcharacterizationparameter 65.2 40 °C/W JB R Junction-to-case(bottom)thermalresistance NA NA °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report(SPRA953). 4 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 6.5 Electrical Characteristics V =5V,T =25°C(unlessotherwisenoted) CC C PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DRAIN0toDRAIN7.Drain-to- 40 V sourcevoltage High-leveloutputvoltage,SER IOH=–20μA 4.9 4.99 V V V =5V OH OUT I =−4mA CC 4.5 4.69 V OH Low-leveloutputvoltage,SER IOH=20μA 0.001 0.01 V V V =5V OL OUT I =4mA CC 0.25 0.4 V OH I High-levelinputcurrent V =5V,V =V 0.2 μA IH CC I CC I Low-levelinputcurrent V =5V,V =0 –0.2 μA IL CC I Alloutputsoff 0.1 1 I Logicsupplycurrent V =5V,noclocksignal μA CC CC Alloutputson 88 160 I Logicsupplycurrentatfrequency f =5MHz,C =30pF Alloutputson 200 μA CC(FRQ) SRCK L V =30V V =5V 0.1 DS CC I Off-statedraincurrent μA DSX V =30V,T =125°C V =5V 0.15 0.3 DS C CC I =20mA,V =5V,T =25°C, D CC A 6 7.41 8.6 SinglechannelON I =20mA,V =5V,T =25°C, D CC A 6.7 8.3 9.6 AllchannelsON I =20mA,V =3.3V,T =25°C, D CC A 7.9 9.34 11.2 SinglechannelON I =20mA,V =3.3V,T =25°C, D CC A 8.7 10.25 12.3 Staticdrain-sourceon-state AllchannelsON r Ω DS(on) resistance I =20mA,V =5V,T =125°C, D CC A 9.1 11.13 12.9 SinglechannelON I =20mA,V =5V,T =125°C, D CC A 10.3 12.28 14.5 AllchannelsON I =20mA,V =3.3V,T =125°C, D CC A 11.6 13.69 16.4 SinglechannelON I =20mA,V =3.3V,T =125°C, D CC A 12.8 14.89 18.2 AllchannelsON T Thermalshutdowntrippoint 150 175 200 ºC SHUTDOWN T Hysteresis 15 ºC hys 6.6 Timing Requirements MIN NOM MAX UNIT t Setuptime,SERINhighbeforeSRCK↑ 15 ns su t Holdtime,SERINhighafterSRCK↑ 15 ns h t SERINpulseduration 40 ns w Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com 6.7 Switching Characteristics V =5V,T =25°C CC J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Propagationdelaytime,low-to-high-leveloutputfromG 220 ns PLH t Propagationdelaytime,high-to-low-leveloutputfromG 75 ns PHL C =30pF,I =48mA L D t Risetime,drainoutput 210 ns r t Falltime,drainoutput 128 ns f t Propagationdelaytime,SRCK↓toSEROUT C =30pF,I =48mA 49.4 ns pd L D t SEROUTrisetime(10%to90%) C =30pF 20 ns or L t SEROUTfalltime(90%to10%) C =30pF 20 ns of L f Serialclockfrequency C =30pF,I =20mA 10 MHz (SRCK) L D t SRCKpulseduration,high 30 ns SRCK_WH t SRCKpulseduration,low 30 ns SRCK_WL 6 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 6.8 Timing Waveforms Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 13). As a result, it takes seven andahalfperiodsofSRCKfordatatotransferfromSERINtoSEROUT. 8 7 6 5 4 3 2 1 SRCK SERIN CLR 1 SEROUT 0 Figure1. SERINtoSEROUTWaveform Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the testcircuitshowninFigure11. 5 V G 50% 50% 0 V tPLH tPHL 10V 90% 90% Output 10% 10% 0.5V t t r f 5 V SRCK 50% 0 V t t su h 5 V SERIN 50% 50% 0 V t w SwitchingTimes,InputSetupandHoldWaveforms SRCK 50% 50% t t pd pd SEROUT 50% 50% SEROUTPropagationDelayWaveform Figure2. SwitchingTimesandVoltageWaveforms Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com 6.9 Typical Characteristics ConditionsforFigure5andFigure6:Singlechannelon,conditionsforFigure7,Figure8andFigure9:Allchannelson 500 350 T = –40(cid:131)C All Channels Off A T A = 25(cid:131)C 300 All Channels On 400 T = 125(cid:131)C A) A A) 250 (cid:29) (cid:29) ent ( 300 ent ( 200 urr urr C C y 200 y 150 pl pl p p Su Su 100 100 50 V = 5V CC 0 0 0.1 1 10 100 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Frequency (MHz) C001 Supply Voltage (V) C002 Figure3.SupplyCurrentvsFrequency Figure4.SupplyCurrentvsSupplyVoltage 12 16 (cid:159)(cid:12) (cid:159)(cid:12) ce ( 10 ce ( 14 n n sta sta 12 esi 8 esi R R 10 e e Stat 6 Stat 8 n- n- O O 6 e 4 e c c ur ur 4 o T = –40(cid:131)C o T = –40(cid:131)C Drain-S 2 TTAA == 21525(cid:131)C(cid:131)C VCC = 5V Drain-S 2 TTAA == 21525(cid:131)C(cid:131)C VCC = 3.3V 0 A 0 A 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Drain Current (mA) C003 Drain Current (mA) C004 Figure5.Drain-to-SourceOn-StateResistancevsDrain Figure6.Drain-to-SourceOn-StateResistancevsDrain Current Current 14 18 (cid:159)(cid:12) (cid:159)(cid:12) e ( 12 e ( 16 c c an an 14 esist 10 esist 12 R R ate 8 ate 10 St St n- 6 n- 8 O O e e 6 urc 4 urc o T = –40(cid:131)C o 4 T = –40(cid:131)C S A S A Drain- 2 TTA == 21525(cid:131)C(cid:131)C VCC = 5V Drain- 2 TTA == 21525(cid:131)C(cid:131)C VCC = 3.3V 0 A 0 A 0 10 20 30 40 50 60 0 10 20 30 40 50 60 Drain Current (mA) C005 Drain Current (mA) C006 Figure7.Drain-to-SourceOn-StateResistancevsDrain Figure8.Drain-to-SourceOn-StateResistancevsDrain Current Current 8 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 Typical Characteristics (continued) ConditionsforFigure5andFigure6:Singlechannelon,conditionsforFigure7,Figure8andFigure9:Allchannelson 18 350 (cid:159)(cid:12) ttpPlLhH e ( 16 300 ttpPhHlL c an 14 ttrr Resist 12 e (ns) 250 ttff ate 10 Tim 200 urce On-St 68 Switching 110500 o 4 T = –40(cid:131)C S A Drain- 2 TTA == 21525(cid:131)C(cid:131)C Ids = 20mA 50 0 A 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 –60 –40 –20 0 20 40 60 80 100 120 140 Supply Voltage (V) C007 Ambient Temperature ((cid:131)C) C008 Figure9.Drain-to-SourceOn-StateResistancevsDrain Figure10.SwitchingTimevsAmbientTemperature Current 7 Parameter Measurement Information Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12 thatwithGheldlowandCLRheldhigh,thestatusofeachdrainchangesontherisingedgeoftheregisterclock, indicatingthetransferofdatatotheoutputbuffersatthattime. 5 V 10 V V CC CLR I R = 200W D L SRCK Output MCU SERIN DRAIN RCK CL= 30 pF (see NoteA) G GND Copyright © 2016,Texas Instruments Incorporated A. C includesprobeandjigcapacitance. L Figure11. Resistive-LoadTestCircuit Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com Parameter Measurement Information (continued) 8 7 6 5 4 3 2 1 SRCK SERIN G RCK 0 CLR 1 DRAIN0 0 DRAIN1 0 DRAIN6 0 DRAIN7 0 Figure12. VoltageWaveforms 10 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 8 Detailed Description 8.1 Overview The TLC6C598-Q1 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive relatively moderate load power such LEDs. The device contains an 8-bit serial-in, parallel-out shift register that feedsan8-bitD-typestorageregister.Thermalshutdownprotectionisalsobuilt-intothedevice. 8.2 Functional Block Diagram G RCK DRAIN0 CLR D D SRCK C1 C1 CLR CLR DRAIN1 SER IN D D C1 C1 CLR CLR DRAIN2 D D C1 C1 CLR CLR DRAIN3 D D C1 C1 CLR CLR DRAIN4 D D C1 C1 CLR CLR DRAIN5 D D C1 C1 CLR CLR DRAIN6 D D C1 C1 CLR CLR DRAIN7 D D C1 C1 CLR CLR GND D C1 CLR SER OUT Copyright © 2016,Texas Instruments Incorporated Figure13. LogicDiagram(Positive)ofTLC6C598-Q1 Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com 8.3 Feature Description 8.3.1 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C (typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds the thermal trip threshold. Once the junction temperature decreases below 160°C (typical), the device begins to operateagain. 8.3.2 Serial-InInterface The TLC6C598-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregisterclear(CLR)ishigh. 8.3.3 ClearRegisters A logic low the CLR pin clears all registers in the device. TI suggests clearing the device during power up or initialization. 8.3.4 OutputChannels DRAIN0–DRAIN7. These pins can survive up to 40-V LED supply voltage. This is quite helpful during automotive load-dumpconditions. 8.3.5 RegisterClock RCK is the storage-register clock. Data in the storage register appears at the output whenever the output enable (G)inputsignalishigh. 8.3.6 CascadeThroughSEROUT By connecting the SER OUT pin to the SER IN input of the next device on the serial bus to cascade, the data transfers to the next device on the falling edge of SRCK. This can improve the cascade application reliability, as itcanavoidtheissuethattheseconddevicereceivesSRCKanddatainputatthesamerisingedgeofSRCK. 8.3.7 OutputControl Holding the output enable (pin G) high holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable ofsinkingcurrent.ThispinalsocanbeusedforglobalPWMdimming. 8.4 Device Functional Modes 8.4.1 OperationWithV <3V CC This device works normally within the range 3 V ≤ V ≤ 5.5 V. When the operating voltage is lower than 3 V, CC correctbehaviorofthedevice,includingcommunicationinterfaceandcurrentcapability,isnotassured. 8.4.2 OperationWith5.5V ≤ V ≤ 8V CC The device works normally in this voltage range, but reliability issues may occur if the device works for a long timeinthisvoltagerange. 12 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The TLC6C598-Q1 device is a serial-in, parallel-out, power and logic, 8-bit shift register with low-side open-drain DMOS output ratings of 40-V and 50-mA continuous sink-current capabilities when V = 5 V. The device is CC designed to drive resistive loads and is particularly well-suited as an interface between a microcontroller and LEDs or lamps. The device also provides up to 2000 V of ESD protection when tested using the human body modeland200Vwhenusingthemachinemodel 9.2 Typical Application Figure 14 shows a typical cascade application circuit with two TLC6C598-Q1 chips configured in cascade topology.TheMCUgeneratesalltheinputsignals. Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com Typical Application (continued) Battery 9 V–40 V 3 V–5.5 V DRAIN0 DRAIN1 DRAIN6 DRAIN7 V CC SER IN GND SRCK MCU G CLR SER OUT RCK DRAIN0 DRAIN1 DRAIN6 DRAIN7 V CC SER IN GND SRCK G CLR SER OUT RCK Copyright © 2016,Texas Instruments Incorporated Figure14. TypicalApplicationCircuit 9.2.1 DesignRequirements DESIGNPARAMETER EXAMPLEVALUE V 9Vto40V Battery V 3.3V CC_1 I(D0),I(D1),I(D2),I(D3),I(D4),I(D5),I(D6),I(D7) 30mA V 5V CC_2 I(D8),I(D9),I(D10),I(D11),I(D12),I(D13),I(D14),I(D15) 50mA 14 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 9.2.2 DetailedDesignProcedure Tobeginthedesignprocess,thedesignermustdecideonafewparameters,asfollows: • V :LEDsupplyvoltage supply • V :LEDforwardvoltage Dx • I:LEDcurrent With these parameters determined, the resistor in series with the LED can be calculated by using the following equation: R =(V -V )/I X Supply Dx (1) 9.2.3 ApplicationCurve Figure15. TLC6C598-Q1ApplicationWaveform Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com 10 Power Supply Recommendations TheTLC6C598-Q1deviceisdesignedtooperatewithaninputvoltagesupplyrangefrom3Vto5.5V.Thisinput supplyshouldbewellregulated.TIrecommendsplacingtheceramicbypasscapacitorsneartheV pin. CC 11 Layout 11.1 Layout Guidelines There are no special layout requirement for the digital signal pins. The only requirement is placing the ceramic bypasscapacitorsnearthecorrespondingpin. MaximizethecoppercoverageonthePCBtoincreasethethermalconductivityoftheboard.Themajorheat-flow path from the package to the ambient is through the cooper on the PCB. Maximizing the copper coverage is extremely important when the design does not include heat sinks attached to the PCB on the other side of the package. Addasmanythermalviasaspossibledirectlyunderthepackagegroundpadtooptimizethethermalconductivity oftheboard. All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent solder voids.Toensurereliabilityandperformance,thesoldercoverageshouldbeatleast85%. 11.2 Layout Example V 1 16 GND CC SERIN 2 15 SRCK DRAIN0 3 DRAIN7 14 DRAIN1 4 13 DRAIN6 DRAIN2 5 12 DRAIN5 DRAIN3 6 11 DRAIN4 CLR 7 10 RCK G 8 9 SER OUT Figure16. TLC6C598-Q1ExampleLayout 16 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 12 Device and Documentation Support 12.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 12.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com 13.1 Package Option Addendum 13.1.1 PackagingInformation OrderableDevice Status(1) PaTcykpaege PDaracwkaingge Pins PaQcktyage EcoPlan(2) LFeinadis/hB(a3l)l MSLPeakTemp(4) OpTemp(°C) DeviceMarking(5)(6) Green(RoHS Level-3-260C-168 TLC6C598QPWRQ1 ACTIVE TSSOP PW 16 2000 CUNIPDAU -40to125 6C598 &noSb/Br) HR Green(RoHS Level-3-260C-168 TLC6C598QDRQ1 ACTIVE SOIC D 16 2500 CUNIPDAU -40to125 TLC6C598 &noSb/Br) HR Green(RoHS Level-3-260C-168 TLC6C598CQDRQ1 ACTIVE SOIC D 16 2500 CUNIPDAU -40to125 TLC6C598C &noSb/Br) HR (1) Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartinanewdesign. PRE_PRODUnannounceddevice,notinproduction,notavailableformassmarket,norontheweb,samplesnotavailable. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. space (2) EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheckhttp://www.ti.com/productcontentforthelatest availabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirementsforall6substances,includingthe requirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesolderedathightemperatures,TIPb-Freeproductsaresuitableforuseinspecified lead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieandpackage,or2)lead-baseddieadhesiveused betweenthedieandleadframe.ThecomponentisotherwiseconsideredPb-Free(RoHScompatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflameretardants(BrorSbdonotexceed0.1%by weightinhomogeneousmaterial) space (3) Lead/BallFinish-OrderableDevicesmayhavemultiplematerialfinishoptions.Finishoptionsareseparatedbyaverticalruledline.Lead/BallFinishvaluesmaywraptotwolinesifthe finishvalueexceedsthemaximumcolumnwidth. space (4) MSL,PeakTemp.--TheMoistureSensitivityLevelratingaccordingtotheJEDECindustrystandardclassifications,andpeaksoldertemperature. space (5) Theremaybeadditionalmarking,whichrelatestothelogo,thelottracecodeinformation,ortheenvironmentalcategoryonthedevice space (6) MultipleDevicemarkingswillbeinsideparentheses.OnlyonDeviceMarkingcontainedinparenthesesandseparatedbya"~"willappearonadevice.Ifalineisindentedthenitisa continuationofthepreviouslineandthetwocombinedrepresenttheentireDeviceMarkingforthatdevice. ImportantInformationandDisclaimer:TheinformationprovidedonthispagerepresentsTI'sknowledgeandbeliefasofthedatethatitisprovided.TIbasesitsknowledgeandbelief oninformationprovidedbythirdparties,andmakesnorepresentationorwarrantyastotheaccuracyofsuchinformation.Effortsareunderwaytobetterintegrateinformationfromthird parties.TIhastakenandcontinuestotakereasonablestepstoproviderepresentativeandaccurateinformationbutmaynothaveconducteddestructivetestingorchemicalanalysison incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimitedinformationmaynotbeavailablefor release. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTItoCustomeronanannualbasis. 18 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 www.ti.com SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 13.1.2 TapeandReelInformation REELDIMENSIONS TAPE DIMENSIONS K0 P1 W B0 Reel Diameter Cavity A0 A0 Dimension designed to accommodate the component width B0 Dimension designed to accommodate the component length K0 Dimension designed to accommodate the component thickness W Overall width of the carrier tape P1 Pitch between successive cavity centers Reel Width (W1) QUADRANTASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants Reel Reel Package Package A0 B0 K0 P1 W Pin1 Device Pins SPQ Diameter WidthW1 Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant (mm) (mm) TLC6C598QPWRQ1 TSSOP PW 16 2000 330 12.4 6.9 5.6 1.6 8 12 Q1 TLC6C598QDRQ1 SOIC D 16 2500 330 16.4 6.5 10.3 2.1 8 16 Q1 TLC6C598CQDRQ1 SOIC D 16 2500 330 16.4 6.5 10.3 2.1 8 16 Q1 Copyright©2012–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TLC6C598-Q1

TLC6C598-Q1 SLIS142D–DECEMBER2012–REVISEDSEPTEMBER2016 www.ti.com TAPEAND REELBOX DIMENSIONS Width (mm) H W L Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC6C598QPWRQ1 TSSOP PW 16 2000 367 367 38 TLC6C598QDRQ1 SOIC D 16 2500 367 367 38 TLC6C598CQDRQ1 SOIC D 16 2500 367 367 38 20 SubmitDocumentationFeedback Copyright©2012–2016,TexasInstrumentsIncorporated ProductFolderLinks:TLC6C598-Q1

None

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated