(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 (cid:1) Dependable Texas Instruments Quality and SN5404 . . . J PACKAGE Reliability SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) description/ordering information These devices contain six independent inverters. 1A 1 14 VCC 1Y 2 13 6A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3Y 6 9 4A GND 7 8 4Y SN5404 . . . W PACKAGE (TOP VIEW) 1A 1 14 1Y 2Y 2 13 6A 2A 3 12 6Y VCC 4 11 GND 3A 5 10 5Y 3Y 6 9 5A 4A 7 8 4Y SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW) C Y A C CA 1 1 N V6 3 2 1 20 19 2A 4 18 6Y NC 5 17 NC 2Y 6 16 5A NC 7 15 NC 3A 8 14 5Y 9 10 11 12 13 Y D CY A 3 N N4 4 G NC − No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:16)(cid:14)(cid:17)(cid:18)(cid:19)(cid:20)(cid:15)(cid:12)(cid:17)(cid:2) (cid:18)(cid:21)(cid:15)(cid:21) (cid:22)(cid:23)(cid:24)(cid:25)(cid:26)(cid:27)(cid:28)(cid:29)(cid:22)(cid:25)(cid:23) (cid:22)(cid:30) (cid:31)!(cid:26)(cid:26)"(cid:23)(cid:29) (cid:28)(cid:30) (cid:25)(cid:24) #!$%(cid:22)(cid:31)(cid:28)(cid:29)(cid:22)(cid:25)(cid:23) &(cid:28)(cid:29)"’ Copyright  2004, Texas Instruments Incorporated (cid:16)(cid:26)(cid:25)&!(cid:31)(cid:29)(cid:30) (cid:31)(cid:25)(cid:23)(cid:24)(cid:25)(cid:26)(cid:27) (cid:29)(cid:25) (cid:30)#"(cid:31)(cid:22)(cid:24)(cid:22)(cid:31)(cid:28)(cid:29)(cid:22)(cid:25)(cid:23)(cid:30) #"(cid:26) (cid:29)(" (cid:29)"(cid:26)(cid:27)(cid:30) (cid:25)(cid:24) (cid:15)")(cid:28)(cid:30) (cid:12)(cid:23)(cid:30)(cid:29)(cid:26)!(cid:27)"(cid:23)(cid:29)(cid:30) (cid:17)(cid:23) #(cid:26)(cid:25)&!(cid:31)(cid:29)(cid:30) (cid:31)(cid:25)(cid:27)#%(cid:22)(cid:28)(cid:23)(cid:29) (cid:29)(cid:25) -(cid:12)(cid:7).(cid:16)(cid:14)/.01(cid:3)0(cid:3)(cid:6) (cid:28)%% #(cid:28)(cid:26)(cid:28)(cid:27)"(cid:29)"(cid:26)(cid:30) (cid:28)(cid:26)" (cid:29)"(cid:30)(cid:29)"& (cid:30)(cid:29)(cid:28)(cid:23)&(cid:28)(cid:26)& *(cid:28)(cid:26)(cid:26)(cid:28)(cid:23)(cid:29)+’ (cid:16)(cid:26)(cid:25)&!(cid:31)(cid:29)(cid:22)(cid:25)(cid:23) #(cid:26)(cid:25)(cid:31)"(cid:30)(cid:30)(cid:22)(cid:23), &(cid:25)"(cid:30) (cid:23)(cid:25)(cid:29) (cid:23)"(cid:31)"(cid:30)(cid:30)(cid:28)(cid:26)(cid:22)%+ (cid:22)(cid:23)(cid:31)%!&" !(cid:23)%"(cid:30)(cid:30) (cid:25)(cid:29)("(cid:26)*(cid:22)(cid:30)" (cid:23)(cid:25)(cid:29)"&’ (cid:17)(cid:23) (cid:28)%% (cid:25)(cid:29)("(cid:26) #(cid:26)(cid:25)&!(cid:31)(cid:29)(cid:30)(cid:6) #(cid:26)(cid:25)&!(cid:31)(cid:29)(cid:22)(cid:25)(cid:23) (cid:29)"(cid:30)(cid:29)(cid:22)(cid:23), (cid:25)(cid:24) (cid:28)%% #(cid:28)(cid:26)(cid:28)(cid:27)"(cid:29)"(cid:26)(cid:30)’ #(cid:26)(cid:25)(cid:31)"(cid:30)(cid:30)(cid:22)(cid:23), &(cid:25)"(cid:30) (cid:23)(cid:25)(cid:29) (cid:23)"(cid:31)"(cid:30)(cid:30)(cid:28)(cid:26)(cid:22)%+ (cid:22)(cid:23)(cid:31)%!&" (cid:29)"(cid:30)(cid:29)(cid:22)(cid:23), (cid:25)(cid:24) (cid:28)%% #(cid:28)(cid:26)(cid:28)(cid:27)"(cid:29)"(cid:26)(cid:30)’ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING Tube SN7404N SN7404N PPDDIIPP −− NN Tube SN74LS04N SN74LS04N Tube SN74S04N SN74S04N Tube SN7404D 77440044 Tape and reel SN7404DR Tube SN74LS04D SSOOIICC −− DD LLSS0044 00°CC ttoo 7700°CC Tape and reel SN74LS04DR Tube SN74S04D SS0044 Tape and reel SN74S04DR Tape and reel SN7404NSR SN7404 SSOOPP −− NNSS Tape and reel SN74LS04NSR 74LS04 Tape and reel SN74S04NSR 74S04 SSOP − DB Tape and reel SN74LS04DBR LS04 Tube SN5404J SN5404J Tube SNJ5404J SNJ5404J Tube SN54LS04J SN54LS04J CCDDIIPP −− JJ Tube SN54S04J SN54S04J Tube SNJ54LS04J SNJ54LS04J −−5555°CC ttoo 112255°CC Tube SNJ54S04J SNJ54S04J Tube SNJ5404W SNJ5404W CCFFPP −− WW Tube SNJ54LS04W SNJ54LS04W Tube SNJ54S04W SNJ54S04W Tube SNJ54LS04FK SNJ54LS04FK LLCCCCCC −− FFKK Tube SNJ54S04FK SNJ54S04FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT OUTPUT A Y H L L H 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 logic diagram (positive logic) 1A 1Y 2A 2Y 3A 3Y 4A 4Y 5A 5Y 6A 6Y Y = A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 schematics (each gate) ’04 VCC 4 kΩ 1.6 kΩ 130 Ω Input A Output Y 1 kΩ GND ’LS04 ’S04 VCC VCC 20 kΩ 8 kΩ 120 Ω 2.8 kΩ 50 Ω 900 Ω Input Input 4 kΩ Output A 3.5 kΩ OYutput A Y 12 kΩ 250 Ω 500 Ω 3 kΩ 1.5 kΩ GND GND Resistor values shown are nominal. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V: ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V I ’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W JA DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. Voltage values are with respect to network ground terminal. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SSNN55440044 SSNN77440044 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 16 16 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN5404 SN7404 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS‡‡ UUNNIITT MIN TYP§ MAX MIN TYP§ MAX VIK VCC = MIN, II = −12 mA −1.5 −1.5 V VOH VCC = MIN, VIL = 0.8 V, IOH = −0.4 mA 2.4 3.4 2.4 3.4 V VOL VCC = MIN, VIH = 2 V, IOL = 16 mA 0.2 0.4 0.2 0.4 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.4 V 40 40 µA IIL VCC = MAX, VI = 0.4 V −1.6 −1.6 mA IOS¶ VCC = MAX −20 −55 −18 −55 mA ICCH VCC = MAX, VI = 0 V 6 12 6 12 mA ICCL VCC = MAX, VI = 4.5 V 18 33 18 33 mA ‡For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. §All typical values are at VCC = 5 V, TA = 25°C. ¶Not more than one output should be shorted at a time. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 switching characteristics, V = 5 V, T = 25°C (see Figure 1) CC A SN5404 FROM TO PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS SN7404 UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX tPLH 12 22 AA YY RRLL == 440000 ΩΩ,, CCLL == 1155 ppFF nnss tPHL 8 15 recommended operating conditions (see Note 3) SSNN5544LLSS0044 SSNN7744LLSS0044 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current −0.4 −0.4 mA IOL Low-level output current 4 8 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS04 SN74LS04 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = MIN, II = −18 mA −1.5 −1.5 V VOH VCC = MIN, VIL = MAX, IOH = −0.4 mA 2.5 3.4 2.7 3.4 V IOL = 4 mA 0.25 0.4 0.4 VVOOLL VVCCCC == MMIINN,, VVIIHH == 22 VV VV IOL = 8 mA 0.25 0.5 II VCC = MAX, VI = 7 V 0.1 0.1 mA IIH VCC = MAX, VI = 2.7 V 20 20 µA IIL VCC = MAX, VI = 0.4 V −0.4 −0.4 mA IOS§ VCC = MAX −20 −100 −20 −100 mA ICCH VCC = MAX, VI = 0 V 1.2 2.4 1.2 2.4 mA ICCL VCC = MAX, VI = 4.5 V 3.6 6.6 3.6 6.6 mA †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, V = 5 V, T = 25°C (see Figure 2) CC A SN54LS04 FROM TO PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS SN74LS04 UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX tPLH 9 15 AA YY RRLL == 22 kkΩΩ,, CCLL == 1155 ppFF nnss tPHL 10 15 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 recommended operating conditions (see Note 3) SSNN5544SS0044 SSNN7744SS0044 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current −1 −1 mA IOL Low-level output current 20 20 mA TA Operating free-air temperature −55 125 0 70 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54S04 SN74S04 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIK VCC = MIN, II = −18 mA −1.2 −1.2 V VOH VCC = MIN, VIL = 0.8 V, IOH = −1 mA 2.5 3.4 2.7 3.4 V VOL VCC = MIN, VIH = 2 V, IOL = 20 mA 0.5 0.5 V II VCC = MAX, VI = 5.5 V 1 1 mA IIH VCC = MAX, VI = 2.7 V 50 50 µA IIL VCC = MAX, VI = 0.5 V −2 −2 mA IOS§ VCC = MAX −40 −100 −40 −100 mA ICCH VCC = MAX, VI = 0 V 15 24 15 24 mA ICCL VCC = MAX, VI = 4.5 V 30 54 30 54 mA †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second. switching characteristics, V = 5 V, T = 25°C (see Figure 1) CC A SN54S04 FROM TO PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS SN74S04 UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX tPLH 3 4.5 AA YY RRLL == 228800 ΩΩ,, CCLL == 1155 ppFF nnss tPHL 3 5 tPLH 4.5 AA YY RRLL == 228800 ΩΩ,, CCLL == 5500 ppFF nnss tPHL 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES VCC Test RL Test Point S1 Point VCC From Output VCC Under Test (see Note B) RL CL From Output RL (see Note A) 1 kΩ Under Test (see Note B) From Output Test CL Under Test Point (see Note A) CL (see Note A) S2 LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V High-Level Timing 1.5 V 1.5 V 1.5 V Pulse Input 0 V tw th tsu 3 V Low-Level Data 1.5 V 1.5 V 1.5 V 1.5 V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1.5 V 1.5 V 3 V (low-level Input 1.5 V 1.5 V enabling) 0 V 0 V tPZL tPLZ tPLH tPHL Waveform 1 ≈1.5 V In-Phase VOH (see Notes C 1.5 V Output 1.5 V 1.5 V and D) VOL + 0.5 V (see Note D) VOL VOL tPZH tPHZ tPHL tPLH VOH Out-of-Phase VOH Waveform 2 VOH − 0.5 V Output 1.5 V 1.5 V (see Notes C 1.5 V ≈1.5 V (see Note D) VOL and D) VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω; tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 ns for Series 54S/74S devices. F. The outputs are measured one at a time, with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:3)(cid:4)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:7)(cid:1)(cid:5)(cid:4)(cid:6) (cid:1)(cid:2)(cid:8)(cid:4)(cid:1)(cid:5)(cid:4) (cid:9)(cid:10)(cid:11) (cid:12)(cid:2)(cid:13)(cid:10)(cid:14)(cid:15)(cid:10)(cid:14)(cid:1) SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test RL Test Point S1 Point VCC From Output VCC Under Test (see Note B) RL CL From Output RL (see Note A) 5 kΩ Under Test (see Note B) From Output Test CL Under Test Point (see Note A) CL (see Note A) S2 LOAD CIRCUIT LOAD CIRCUIT LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3 V High-Level Timing 1.3 V 1.3 V 1.3 V Pulse Input 0 V tw th tsu 3 V Low-Level Data 1.3 V 1.3 V 1.3 V 1.3 V Pulse Input 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATIONS SETUP AND HOLD TIMES Output 3 V Control 1.3 V 1.3 V (low-level 3 V enabling) Input 1.3 V 1.3 V 0 V 0 V tPZL tPLZ tPLH tPHL Waveform 1 ≈1.5 V In-Phase VOH (see Notes C 1.3 V Output 1.3 V 1.3 V and D) VOL + 0.5 V (see Note D) VOL VOL tPZH tPHZ tPHL tPLH VOH Out-of-Phase VOH Waveform 2 VOH − 0.5 V (see Notes C 1.3 V Output 1.3 V 1.3 V ≈1.5 V and D) (see Note D) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. All diodes are 1N3064 or equivalent. C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open for tPZL. E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns, tf ≤ 2.6 ns. G. The outputs are measured one at a time, with one input transition per measurement. Figure 2. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) JM38510/00105BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 00105BCA JM38510/00105BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 00105BDA JM38510/07003BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 07003BCA JM38510/07003BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 07003BDA JM38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A JM38510/30003BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 30003BCA JM38510/30003BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 30003BDA JM38510/30003SCA ACTIVE CDIP J 14 25 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 30003SCA M38510/00105BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 00105BCA M38510/00105BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 00105BDA M38510/07003BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 07003BCA M38510/07003BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 07003BDA M38510/30003B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 30003B2A M38510/30003BCA ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 30003BCA M38510/30003BDA ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 30003BDA M38510/30003SCA ACTIVE CDIP J 14 25 TBD SNPB N / A for Pkg Type -55 to 125 JM38510/ 30003SCA SN5404J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN5404J Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN54LS04J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54LS04J SN54S04J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SN54S04J SN7404D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7404 & no Sb/Br) SN7404DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 7404 & no Sb/Br) SN7404N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN7404N & no Sb/Br) SN7404NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN7404N & no Sb/Br) SN74LS04D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 & no Sb/Br) SN74LS04DBR ACTIVE SSOP DB 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM LS04 & no Sb/Br) SN74LS04DG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 & no Sb/Br) SN74LS04DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 & no Sb/Br) SN74LS04DRG4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 LS04 & no Sb/Br) SN74LS04N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N & no Sb/Br) SN74LS04NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74LS04N & no Sb/Br) SN74LS04NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74LS04 & no Sb/Br) SN74S04D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 S04 & no Sb/Br) SN74S04DR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 S04 & no Sb/Br) SN74S04N ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74S04N & no Sb/Br) SN74S04NE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 SN74S04N & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) SN74S04NSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74S04 & no Sb/Br) SNJ5404J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SNJ5404J SNJ5404W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ5404W SNJ54LS04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54LS 04FK SNJ54LS04J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SNJ54LS04J SNJ54LS04W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54LS04W SNJ54S04FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SNJ54S 04FK SNJ54S04J ACTIVE CDIP J 14 1 TBD SNPB N / A for Pkg Type -55 to 125 SNJ54S04J SNJ54S04W ACTIVE CFP W 14 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54S04W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN5404, SN54LS04, SN54LS04-SP, SN54S04, SN7404, SN74LS04, SN74S04 : •Catalog: SN7404, SN74LS04, SN54LS04, SN74S04 •Military: SN5404, SN54LS04, SN54S04 •Space: SN54LS04-SP NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications •Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN7404DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LS04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74S04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74S04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN7404DR SOIC D 14 2500 367.0 367.0 38.0 SN74LS04DR SOIC D 14 2500 367.0 367.0 38.0 SN74LS04NSR SO NS 14 2000 367.0 367.0 38.0 SN74S04DR SOIC D 14 2500 367.0 367.0 38.0 SN74S04NSR SO NS 14 2000 367.0 367.0 38.0 PackMaterials-Page2

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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