(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:10)(cid:7)(cid:11)(cid:5)(cid:12) (cid:13)(cid:6)(cid:14)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:16) (cid:21)(cid:19)(cid:11)(cid:22) (cid:23)(cid:24)(cid:1)(cid:11)(cid:5)(cid:11)(cid:15) (cid:10)(cid:6)(cid:11)(cid:25)(cid:6)(cid:11)(cid:1) SCES430A − MARCH 2003 − REVISED MARCH 2003 (cid:1) Optimized for 1.8-V Operation and is 3.6-V RGY PACKAGE I/O Tolerant to Support Mixed-Mode Signal (TOP VIEW) Operation E C (cid:1) I Supports Partial-Power-Down Mode 1O VC off Operation 1 20 (cid:1) 1A1 2 19 2OE Sub 1-V Operable (cid:1) 2Y4 3 18 1Y1 Max t of 1.7 ns at 1.8 V pd 1A2 4 17 2A4 (cid:1) Low Power Consumption, 20-µA Max ICC 2Y3 5 16 1Y2 (cid:1) ±8-mA Output Drive at 1.8 V 1A3 6 15 2A3 (cid:1) Latch-Up Performance Exceeds 100 mA Per 2Y2 7 14 1Y3 JESD 78, Class II 1A4 8 13 2A2 (cid:1) 2Y1 9 12 1Y4 ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) 10 11 − 200-V Machine Model (A115-A) D 1 N A − 1000-V Charged-Device Model (C101) G 2 description/ordering information This octal buffer/driver is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V to 1.95-V V CC CC operation. The SN74AUC240 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs, off off preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING −40°C to 85°C QFN − RGY Tape and reel SN74AUC240RGYR MS240 †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. (cid:25)(cid:16)(cid:10)(cid:18)(cid:6)(cid:7)(cid:11)(cid:19)(cid:10)(cid:2) (cid:18)(cid:5)(cid:11)(cid:5) (cid:26)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31)!"(cid:26)(cid:29)(cid:27) (cid:26)# $%(cid:30)(cid:30)&(cid:27)" !# (cid:29)(cid:28) ’%()(cid:26)$!"(cid:26)(cid:29)(cid:27) *!"&+ Copyright  2003, Texas Instruments Incorporated (cid:25)(cid:30)(cid:29)*%$"# $(cid:29)(cid:27)(cid:28)(cid:29)(cid:30)(cid:31) "(cid:29) #’&$(cid:26)(cid:28)(cid:26)$!"(cid:26)(cid:29)(cid:27)# ’&(cid:30) ",& "&(cid:30)(cid:31)# (cid:29)(cid:28) (cid:11)&-!# (cid:19)(cid:27)#"(cid:30)%(cid:31)&(cid:27)"# #"!(cid:27)*!(cid:30)* .!(cid:30)(cid:30)!(cid:27)"/+ (cid:25)(cid:30)(cid:29)*%$"(cid:26)(cid:29)(cid:27) ’(cid:30)(cid:29)$&##(cid:26)(cid:27)0 *(cid:29)&# (cid:27)(cid:29)" (cid:27)&$&##!(cid:30)(cid:26))/ (cid:26)(cid:27)$)%*& "&#"(cid:26)(cid:27)0 (cid:29)(cid:28) !)) ’!(cid:30)!(cid:31)&"&(cid:30)#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:10)(cid:7)(cid:11)(cid:5)(cid:12) (cid:13)(cid:6)(cid:14)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:16) (cid:21)(cid:19)(cid:11)(cid:22) (cid:23)(cid:24)(cid:1)(cid:11)(cid:5)(cid:11)(cid:15) (cid:10)(cid:6)(cid:11)(cid:25)(cid:6)(cid:11)(cid:1) SCES430A − MARCH 2003 − REVISED MARCH 2003 FUNCTION TABLE (each 4-bit buffer/driver) INPUTS OOUUTTPPUUTT OE A Y L H L L L H H X Z logic diagram (positive logic) 1 19 1OE 2OE 2 18 11 9 1A1 1Y1 2A1 2Y1 4 16 13 7 1A2 1Y2 2A2 2Y2 6 14 15 5 1A3 1Y3 2A3 2Y3 8 12 17 3 1A4 1Y4 2A4 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V I Voltage range applied to any output in the high-impedance or power-off state, V O (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V O CC Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA IK I Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA OK O Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA O Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θ (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W JA Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:10)(cid:7)(cid:11)(cid:5)(cid:12) (cid:13)(cid:6)(cid:14)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:16) (cid:21)(cid:19)(cid:11)(cid:22) (cid:23)(cid:24)(cid:1)(cid:11)(cid:5)(cid:11)(cid:15) (cid:10)(cid:6)(cid:11)(cid:25)(cid:6)(cid:11)(cid:1) SCES430A − MARCH 2003 − REVISED MARCH 2003 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 0.8 2.7 V VCC = 0.8 V VCC VVIIHH HHiigghh--lleevveell iinnppuutt vvoollttaaggee VCC = 1.1 V to 1.95 V 0.65 ×VCC VV VCC = 2.3 V to 2.7 V 1.7 VCC = 0.8 V 0 VVIILL LLooww--lleevveell iinnppuutt vvoollttaaggee VCC = 1.1 V to 1.95 V 0.35 ×VCC VV VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 3.6 V Active state 0 VCC VVOO OOuuttppuutt vvoollttaaggee VV 3-state 0 3.6 VCC = 0.8 V −0.7 VCC = 1.1 V −3 IIOOHH HHiigghh--lleevveell oouuttppuutt ccuurrrreenntt VCC = 1.4 V −5 mmAA VCC = 1.65 V −8 VCC = 2.3 V −9 VCC = 0.8 V 0.7 VCC = 1.1 V 3 IIOOLL LLooww--lleevveell oouuttppuutt ccuurrrreenntt VCC = 1.4 V 5 mmAA VCC = 1.65 V 8 VCC = 2.3 V 9 ∆t/∆v Input transition rise or fall rate 20 ns/V TA Operating free-air temperature −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:10)(cid:7)(cid:11)(cid:5)(cid:12) (cid:13)(cid:6)(cid:14)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:16) (cid:21)(cid:19)(cid:11)(cid:22) (cid:23)(cid:24)(cid:1)(cid:11)(cid:5)(cid:11)(cid:15) (cid:10)(cid:6)(cid:11)(cid:25)(cid:6)(cid:11)(cid:1) SCES430A − MARCH 2003 − REVISED MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP† MAX UNIT IOH = −100 µA 0.8 V to 2.7 V VCC−0.1 IOH = −0.7 mA 0.8 V 0.55 IOH = −3 mA 1.1 V 0.8 VVOOHH VV IOH = −5 mA 1.4 V 1 IOH = −8 mA 1.65 V 1.2 IOH = −9 mA 2.3 V 1.8 IOL = 100 µA 0.8 V to 2.7 V 0.2 IOL = 0.7 mA 0.8 V 0.25 IOL = 3 mA 1.1 V 0.3 VVOOLL VV IOL = 5 mA 1.4 V 0.4 IOL = 8 mA 1.65 V 0.45 IOL = 9 mA 2.3 V 0.6 II A and OE inputs VI = VCC or GND 0 to 2.7 V ±5 µA Ioff VI or VO = 2.7 V 0 ±10 µA IOZ VO = VCC or GND 2.7 V ±10 µA ICC VI = VCC or GND, IO = 0 0.8 V to 2.7 V 20 µA Ci VI = VCC or GND 2.5 V 2.5 3 pF Co VO = VCC or GND 2.5 V 5.5 6 pF †All typical values are at TA = 25°C. switching characteristics over recommended operating free-air temperature range, C = 15 pF L (unless otherwise noted) (see Figure 1) VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V PPAARRAAMMEETTEERR FROM TO VCC = 0.8 V ± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX tpd A Y 4.8 1.2 3.3 0.8 2 0.7 1.1 1.7 0.6 1.3 ns ten OE Y 6.4 1.4 4 0.9 2.6 0.8 1.2 2.1 0.7 1.5 ns tdis OE Y 8.7 2 5.8 1.8 3.9 1.8 2.5 4 0.3 3 ns switching characteristics over recommended operating free-air temperature range, C = 30 pF L (unless otherwise noted) (see Figure 1) VCC = 1.8 V VCC = 2.5 V PPAARRAAMMEETTEERR FROM TO ± 0.15 V ± 0.2 V UUNNIITT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX tpd A Y 1 1.4 2.1 0.9 1.6 ns ten OE Y 1.1 1.7 2.7 1 2 ns tdis OE Y 1.9 2.5 4 1 2 ns 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:10)(cid:7)(cid:11)(cid:5)(cid:12) (cid:13)(cid:6)(cid:14)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:16) (cid:21)(cid:19)(cid:11)(cid:22) (cid:23)(cid:24)(cid:1)(cid:11)(cid:5)(cid:11)(cid:15) (cid:10)(cid:6)(cid:11)(cid:25)(cid:6)(cid:11)(cid:1) SCES430A − MARCH 2003 − REVISED MARCH 2003 operating characteristics, TA = 25°C TTEESSTT VCC = 0.8 V VCC = 1.2 V VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V PPAARRAAMMEETTEERR UUNNIITT CONDITIONS TYP TYP TYP TYP TYP Outputs Power enabled 21 21 21 22 25 CCppdd ddiissssiippaattiioonn ff == 1100 MMHHzz ppFF Outputs capacitance 3 3 3 3 5 disabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:4)(cid:9) (cid:10)(cid:7)(cid:11)(cid:5)(cid:12) (cid:13)(cid:6)(cid:14)(cid:14)(cid:15)(cid:16)(cid:17)(cid:18)(cid:16)(cid:19)(cid:20)(cid:15)(cid:16) (cid:21)(cid:19)(cid:11)(cid:22) (cid:23)(cid:24)(cid:1)(cid:11)(cid:5)(cid:11)(cid:15) (cid:10)(cid:6)(cid:11)(cid:25)(cid:6)(cid:11)(cid:1) SCES430A − MARCH 2003 − REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 From Output RL S1 Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC CL tPHZ/tPZH GND (see Note A) RL VCC CL RL V∆ 0.8 V 15 pF 2 kΩ 0.1 V 1.2 V ±0.1 V 15 pF 2 kΩ 0.1 V LOAD CIRCUIT 1.5 V ±0.1 V 15 pF 2 kΩ 0.1 V 1.8 V ±0.15 V 15 pF 2 kΩ 0.15 V 2.5 V ±0.2 V 15 pF 2 kΩ 0.15 V 1.8 V ±0.15 V 30 pF 1 kΩ 0.15 V 2.5 V ±0.2 V 30 pF 500 Ω 0.15 V VCC Timing Input VCC/2 0 V tw tsu th VCC VCC Input VCC/2 VCC/2 Data Input VCC/2 VCC/2 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES VCC VCC Output Input VCC/2 VCC/2 Control VCC/2 VCC/2 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 VCC Output VCC/2 VCC/2 S1 at 2 × VCC VCC/2 VOL + V∆ VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output VOH VOH Output VCC/2 VCC/2 WSa1v eafto GrmN D2 VCC/2 VOH − V∆ VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AUC240RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 MS240 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AUC240RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AUC240RGYR VQFN RGY 20 3000 367.0 367.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGY 20 VQFN - 1 mm max height 3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4225264/A www.ti.com

PACKAGE OUTLINE RGY0020A VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 3.65 B 3.35 PIN 1 INDEX AREA 4.65 4.35 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 2.05 0.1 2X 1.5 (0.2) TYP 10 11 EXPOSED THERMAL PAD 9 12 14X 0.5 2X SYMM 21 3.05 0.1 3.5 2 19 0.30 PIN 1 ID 1 20 20X 0.18 SYMM 0.1 C A B 0.5 0.05 20X 0.3 4225320/A 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (2.05) SYMM 1 20 20X (0.6) 2 19 20X (0.24) (1.275) (4.3) SYMM 21 (3.05) 14X (0.5) (0.775) 9 12 (R0.05) TYP ( 0.2) TYP VIA 10 11 (0.75) TYP (3.3) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL SOLDER MASK EXPOSED METAL UNDER OPENING METAL SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4225320/A 09/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGY0020A VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 4X (0.92) 1 20 (R0.05) TYP 20X (0.6) 2 19 20X (0.24) 4X (1.33) 21 SYMM (4.3) (0.77) 14X (0.5) (0.56) 9 12 METAL TYP 10 11 (0.75) TYP (3.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 21 78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4225320/A 09/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated