SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 (cid:1) State-of-the-Art EPIC-II B BiCMOS Design SN54ABT2952A...JT OR W PACKAGE Significantly Reduces Power Dissipation SN74ABT2952A...DB, DW, PW, OR NT PACKAGE (cid:1) (TOP VIEW) Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions B8 1 24 VCC (cid:1) Noninverting Outputs B7 2 23 A8 (cid:1) Typical V (Output Ground Bounce) < 1 V B6 3 22 A7 OLP at V = 5 V, T = 25°C B5 4 21 A6 CC A (cid:1) B4 5 20 A5 Latch-Up Performance Exceeds 500 mA Per B3 6 19 A4 JESD 17 (cid:1) B2 7 18 A3 ESD Protection Exceeds 2000 V Per B1 8 17 A2 MIL-STD-883, Method 3015; Exceeds 200 V OEAB 9 16 A1 Using Machine Model (C = 200 pF, R = 0) CLKAB 10 15 OEBA (cid:1) Package Options Include Plastic CLKENAB 11 14 CLKBA Small-Outline (DW), Shrink Small-Outline GND 12 13 CLKENBA (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) SN54ABT2952A...FK PACKAGE and Ceramic (JT) DIPs (TOP VIEW) C 6 78 C C87 description B BB N V AA The ’ABT2952A transceivers consist of two 8-bit 4 3 2 1 28 27 26 B5 5 25 A6 back-to-back registers that store data flowing in B4 6 24 A5 both directions between two bidirectional buses. B3 7 23 A4 Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or NC 8 22 NC CLKBA) input provided that the clock-enable B2 9 21 A3 (CLKENAB or CLKENBA) input is low. Taking the B1 10 20 A2 output-enable (OEAB or OEBA) input low OEAB 11 19 A1 12 1314 15 16 1718 accesses the data on either port. B BDC A A A To ensure the high-impedance state during power A ANN B B B K NG N K E up or power down, OE should be tied to VCC CL KE KE CL O through a pullup resistor; the minimum value of CL CL the resistor is determined by the current-sinking NC – No internal connection capability of the driver. The SN54ABT2952A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT2952A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1998, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 FUNCTION TABLE† INPUTS OUTPUT CLKENAB CLKAB OEAB A B H X L X B0‡ X H or L L X B0‡ L ↑ L L L L ↑ L H H X X H X Z †A-to-B data flow is shown; B-to-A data flow is similar, but uses CLKENBA, CLKBA, and OEBA. ‡Level of B before the indicated steady-state input conditions were established logic symbol§ 15 OEBA EN3 13 CLKENBA G1 14 CLKBA 1 C5 9 OEAB EN4 11 CLKENAB G2 10 CLKAB 2 C6 16 8 A1 3 1 5D B1 6D 1 4 17 7 A2 B2 18 6 A3 B3 19 5 A4 B4 20 4 A5 B5 21 3 A6 B6 22 2 A7 B7 23 1 A8 B8 §This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 logic diagram (positive logic) 11 CLKENAB 10 CLKAB 9 OEAB 13 CLKENBA 14 CLKBA 15 OEBA C1 16 8 A1 1D B1 C1 1D To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT2952A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT2952A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, q JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions (see Note 3) SN54ABT2952A SN74ABT2952A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA D t/D v Input transition rise or fall rate Outputs enabled 10 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT2952A SN74ABT2952A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3 VVOOHH VV IOH = –24 mA 2 2 VVCCCC == 44.55 VV IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44.55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV Control inputs ±1 ±1 ±1 IIII VVCCCC == 55.55 VV, VVII == VVCCCC oorr GGNNDD mm AA A or B ports ±100 ±100 ±100 IOZH‡ VCC = 5.5 V, VO = 2.7 V 50* 10 50 m A IOZL‡ VCC = 5.5 V, VO = 0.5 V –50* –10 –50 m A Ioff VCC = 0, VI or VO ≤ 4.5 V ±100* ±100 m A ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 m A IO§ VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –50 –180 –50 –180 mA VCC = 5.5 V, Outputs high 1 250 250 250 m A IIO = 00, ICC A or B ports VVII == VVCCCC oorr Outputs low 24 35 35 35 mA GND Outputs disabled 0.5 250 250 250 m A D ICC¶ VOCthCe r= i n5p.5u tVs ,a Ot nVeC iCn pourt GaNt 3D.4 V, 1.5 1.5 1.5 mA Ci Control inputs VI = 2.5 V or 0.5 V 3.5 pF Cio A or B ports VO = 2.5 V or 0.5 V 7.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡The parameters IOZH and IOZL include the input leakage current. §Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, SN54ABT2952A SN74ABT2952A TA = 25°C UNIT MIN MAX MIN MAX MIN MAX fclock Clock frequency 0 150 0 150 0 150 MHz tw Pulse duration, CLK high or low 3.3 3.3 3.3 ns A or B 2.5 3 2.5 ttsu SSeettuupp ttiimmee bbeeffoorree CCLLKK↑↑ HHiigghh oorr llooww nnss CLKEN 3 3 3 A or B 1.5 1.5 1.5 tthh HHoolldd ttiimmee aafftteerr CCLLKK↑↑ nnss CLKEN 2 2 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L VCC = 5 V, PARAMETER FROM TO TA = 25°C SN54ABT2952A SN74ABT2952A UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN TYP MAX MIN MAX MIN MAX fmax 150 150 150 MHz tPLH 2 3.3 5.2 2 6.3 2 5.9 CCLLKKAABB oorr CCLLKKBBAA BB oorr AA nnss tPHL 2.5 4 6.1 2.5 6.8 2.5 6.3 tPZH 1.5 3.2 4.7 1.5 5.7 1.5 5.6 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPZL 2 3.7 5.7 2 6.7 2 6.6 tPHZ 1.5 3.5 5.1 1.5 6.5 1.5 6.4 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPLZ 1.5 3.4 5.9 1.5 6.7 1.5 6.2 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT2952A, SN74ABT2952A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS203D – AUGUST 1992 – REVISED JANUARY 1998 PARAMETER MEASUREMENT INFORMATION 7 V 500 W S1 Open From Output TEST S1 Under Test GND tPLH/tPHL Open (sCeeL N= o5t0e pAF) 500 W tPLZ/tPZL 7 V tPHZ/tPZH Open LOAD CIRCUIT 3 V Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL Output tPLZ VOH Waveform 1 3.5 V Output 1.5 V 1.5 V S1 at 7 V 1.5 V VOL + 0.3 V VOL (see Note B) VOL tPHZ tPHL tPLH tPZH Output Output 1.5 V 1.5 V VOH WSa1v aetf oOrpme n2 1.5 V VOH – 0.3 V VOH VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9308602QLA ACTIVE CDIP JT 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9308602QL A SNJ54ABT2952AJ T SN74ABT2952ADWR ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT2952A & no Sb/Br) SNJ54ABT2952AJT ACTIVE CDIP JT 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9308602QL A SNJ54ABT2952AJ T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT2952A, SN74ABT2952A : •Catalog: SN74ABT2952A •Military: SN54ABT2952A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT2952ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT2952ADWR SOIC DW 24 2000 350.0 350.0 43.0 PackMaterials-Page2

MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN A PINS ** 24 28 DIM 24 13 1.280 1.460 A MAX (32,51) (37,08) B A MIN 1.240 1.440 (31,50) (36,58) 0.300 0.291 B MAX (7,62) (7,39) 1 12 0.070 (1,78) 0.245 0.285 B MIN 0.030 (0,76) (6,22) (7,24) 0.320 (8,13) 0.100 (2,54) MAX 0.015 (0,38) MIN 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.100 (2,54) 0.008 (0,20) 4040110/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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