SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 (cid:1) Members of the Texas Instruments SN54ABT16640...WD PACKAGE Widebus Family SN74ABT16640...DGG OR DL PACKAGE (cid:1) (TOP VIEW) State-of-the-Art EPIC-II B BiCMOS Design Significantly Reduces Power Dissipation (cid:1) 1DIR 1 48 1OE Latch-Up Performance Exceeds 500 mA Per 1B1 2 47 1A1 JEDEC Standard JESD-17 1B2 3 46 1A2 (cid:1) Typical VOLP (Output Ground Bounce) < 1 V GND 4 45 GND at VCC = 5 V, TA = 25°C 1B3 5 44 1A3 (cid:1) Distributed V and GND Pin Configuration 1B4 6 43 1A4 CC Minimizes High-Speed Switching Noise VCC 7 42 VCC (cid:1) Flow-Through Architecture Optimizes PCB 1B5 8 41 1A5 Layout 1B6 9 40 1A6 (cid:1) GND 10 39 GND High-Drive Outputs (–32-mA I , OH 1B7 11 38 1A7 64-mA I ) OL (cid:1) 1B8 12 37 1A8 Package Options Include Plastic 300-mil 2B1 13 36 2A1 Shrink Small-Outline (DL) and Thin Shrink 2B2 14 35 2A2 Small-Outline (DGG) Packages, and 380-mil GND 15 34 GND Fine-Pitch Ceramic Flat (WD) Package 2B3 16 33 2A3 Using 25-mil Center-to-Center Spacings 2B4 17 32 2A4 description VCC 18 31 VCC 2B5 19 30 2A5 The ’ABT16640 are inverting 16-bit transceivers 2B6 20 29 2A6 designed for asynchronous communication GND 21 28 GND between data buses. 2B7 22 27 2A7 2B8 23 26 2A8 These devices can be used as two 8-bit 2DIR 24 25 2OE transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (1DIR and 2DIR) inputs. The output-enable (1OE and 2OE) inputs can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup CC resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT16640 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT16640 is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each 8-bit section) INPUTS OOPPEERRAATTIIOONN OE DIR L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus and EPIC-II B are trademarks of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 logic symbol† logic diagram (positive logic) 48 48 1OE 1OE G3 1 1DIR 3 EN1 [BA] 3 EN2 [AB] 25 1 2OE G6 1DIR 24 2DIR 6 EN4 [BA] 6 EN5 [AB] 47 2 1A1 1 1 1B1 1 2 47 2 46 3 1A1 1B1 1A2 1B2 44 5 1A3 1B3 43 6 1A4 1B4 41 8 1A5 1B5 To Seven Other Channels 40 9 1A6 1B6 38 11 25 1A7 1B7 2OE 37 12 1A8 1B8 36 13 2A1 4 1 2B1 1 5 24 2DIR 35 14 2A2 2B2 33 16 2A3 2B3 32 17 2A4 2B4 30 19 2A5 2B5 29 20 36 13 2A6 2B6 2A1 2B1 27 22 2A7 2B7 26 23 2A8 2B8 †This symbol is in accordance with ANSI/IEEE Std 91-1984 and To Seven Other Channels IEC Publication 617-12. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT16640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT16640 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, q (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W JA DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 recommended operating conditions (see Note 3) SN54ABT16640 SN74ABT16640 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA D t/D v Input transition rise or fall rate Outputs enabled 10 10 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT16640 SN74ABT16640 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3 VVOOHH VV IOH = –24 mA 2 2 VVCCCC == 44.55 VV IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44.55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV Control ±1 ±1 ±1 III inputs VCCCC = 5.5 V,, VII = VCCCC or GND mm A A or B ports ±100 ±100 ±100 IOZH‡ VCC = 5.5 V, VO = 2.7 V 50 50 50 m A IOZL‡ VCC = 5.5 V, VO = 0.5 V –50 –50 –50 m A Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 m A ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 m A IO§ VCC = 5.5 V, VO = 2.5 V –50 –100 –180 –40 –180 –50 –180 mA Outputs high 2 2 2 VVCCCC == 55..55 VV,, ICC A or B ports IO = 0, Outputs low 32 32 32 mA VI = VCC or GND Outputs disabled 2 2 2 VCC = 5.5 V, Outputs enabled 1 1.5 1 One input at 3.4 V,, DDaattaa iinnpputtss Other inputs at D ICC¶¶ VCC or GND Outputs disabled 0.05 0.05 0.05 mA Control VCC = 5.5 V, One input at 3.4 V, 1.5 1.5 1.5 inputs Other inputs at VCC or GND Control Ci inputs VI = 2.5 V or 0.5 V 3 pF Cio A or B ports VO = 2.5 V or 0.5 V 8 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡The parameters IOZH and IOZL include the input leakage current. §Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN54ABT16640 FROM TO VCC = 5 V, PARAMETER (INPUT) (OUTPUT) TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH 0.5 2.5 4.1 0.5 5.2 AA oorr BB BB oorr AA nnss tPHL 0.5 2.8 4 0.5 4.5 tPZH 0.5 3.5 5.2 0.5 6.2 OOEE AA oorr BB nnss tPZL 0.5 3.9 6 0.5 7.4 tPHZ 0.5 3.8 6.8 0.5 7.9 OOEE AA oorr BB nnss tPLZ 0.5 3 4.5 0.5 5 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN74ABT16640 FROM TO VCC = 5 V, PARAMETER (INPUT) (OUTPUT) TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH 1 2.5 3.4 1 4.3 AA oorr BB BB oorr AA nnss tPHL 1.1 2.8 3.6 1.1 3.9 tPZH 1.2 3.5 4.5 1.2 5.5 OOEE AA oorr BB nnss tPZL 1.5 3.9 5 1.5 6.3 tPHZ 1.8 3.8 4.8 1.8 6.3 OOEE AA oorr BB nnss tPLZ 1.5 3 3.9 1.5 4.2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ABT16640, SN74ABT16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS107C – APRIL 1992 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7 V TEST S1 500 W S1 Open From Output tPLH/tPHL Open Under Test GND tPLZ/tPZL 7 V CL = 50 pF 500 W tPHZ/tPZH Open (see Note A) 3 V LOAD CIRCUIT Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V OOuuttppuutt Input 1.5 V 1.5 V 1.5 V 1.5 V CCoonnttrrooll 0 V 0 V tPZL tPLH tPHL VOH Output tPLZ 3.5 V Output 1.5 V 1.5 V VOL WavSe1f oatr m7 V1 1.5 V VOL + 0.3 V VOL (see Note B) tPHZ tPHL tPLH tPZH Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH – 0.3 V VOL (see Note B) ≈ 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74ABT16640DGGR ACTIVE TSSOP DGG 48 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16640 & no Sb/Br) SN74ABT16640DL ACTIVE SSOP DL 48 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16640 & no Sb/Br) SN74ABT16640DLR ACTIVE SSOP DL 48 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT16640 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT16640DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1 SN74ABT16640DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT16640DGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74ABT16640DLR SSOP DL 48 1000 367.0 367.0 55.0 PackMaterials-Page2

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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,50 0,08 M 0,17 48 25 6,20 8,30 6,00 7,90 0,15 NOM Gage Plane 0,25 1 24 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 48 56 64 DIM A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 4040078/F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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