PIC24FJ128GA204 FAMILY 28/44-Pin, General Purpose, 16-Bit Flash Microcontrollers with Cryptographic Engine, ISO 7816 and XLP Technology Cryptographic Engine Extreme Low-Power Features (Continued) • AES Engine with 128,192 or 256-Bit Key • Alternate Clock modes allow On-the-Fly • Supports ECB, CBC, OFB, CTR and Switching to a Lower Clock Speed for Selective CFB128 modes Power Reduction • DES/Triple DES (TDES) Engine: Supports • Extreme Low-Power Current Consumption for 2-Key and 3-Key EDE or DED TDES Deep Sleep: • Supports up to Three Unique Keys for TDES - WDT: 270nA @ 3.3V typical • Programmatically Secure - RTCC: 400nA @ 32 kHz, 3.3V typical • Pseudorandom Number Generator - Deep Sleep current: 40nA, 3.3V typical • True Random Number Generator Analog Features • Non-Readable, On-Chip, OTP Key Storages • 10/12-Bit, 13-Channel Analog-to-Digital (A/D) Extreme Low-Power Features Converter: - Conversion rate of 500 ksps (10-bit), • Multiple Power Management Options for Extreme 200 ksps (12-bit) Power Reduction: - Conversion available during Sleep and Idle - VBAT allows the device to transition to a • Three Rail-to-Rail, Enhanced Analog Comparators backup battery for the lowest power with Programmable Input/Output Configuration consumption with RTCC • Three On-Chip Programmable Voltage References - Deep Sleep allows near total power-down • Charge Time Measurement Unit (CTMU): with the ability to wake-up on internal or - Used for capacitive touch sensing, up to 13 channels external triggers - Time measurement down to 100 ps resolution - Sleep and Idle modes selectively shut down - Operation in Sleep mode peripherals and/or core for substantial power reduction and fast wake-up - Doze mode allows CPU to run at a lower clock speed than peripherals Analog Memory Digital Peripherals Peripherals hic Device Program Flash (bytes) Data RAM (bytes) Pins 10/12-Bit A/D (ch) Comparators CTMU (ch) Input Capture utput Compare/PWM 2C™I SPI ® 7816UART w/IrDA EPMP/PSP 16-Bit Timers Deep Sleep w/VBAT AES/DES Cryptograp O PIC24FJ128GA204 128K 8K 44 13 3 13 6 6 2 3 4 Y 5 Y Y PIC24FJ128GA202 128K 8K 28 10 3 10 6 6 2 3 4 N 5 Y Y PIC24FJ64GA204 64K 8K 44 13 3 13 6 6 2 3 4 Y 5 Y Y PIC24FJ64GA202 64K 8K 28 10 3 10 6 6 2 3 4 N 5 Y Y  2013-2015 Microchip Technology Inc. DS30010038C-page 1

PIC24FJ128GA204 FAMILY Peripheral Features High-Performance CPU • Up to Five External Interrupt Sources • Modified Harvard Architecture • Peripheral Pin Select (PPS); Allows Independent • Up to 16 MIPS Operation @ 32MHz I/O Mapping of Many Peripherals • 8MHz Internal Oscillator: • Five 16-Bit Timers/Counters with Prescaler: - 96MHz PLL option - Can be paired as 32-bit timers/counters - Multiple clock divide options • Six-Channel DMA supports All Peripheral modules: - Run-time self-calibration capability for - Minimizes CPU overhead and increases data maintaining better than ±0.20% accuracy throughput - Fast start-up • Six Input Capture modules, Each with a • 17-Bit x 17-Bit Single-Cycle Hardware Dedicated 16-Bit Timer Fractional/Integer Multiplier • Six Output Compare/PWM modules, Each with a • 32-Bit by 16-Bit Hardware Divider Dedicated 16-Bit Timer • 16 x 16-Bit Working Register Array • Enhanced Parallel Master/Slave Port (EPMP/EPSP) • C Compiler Optimized Instruction Set • Hardware Real-Time Clock/Calendar (RTCC): Architecture (ISA) - Runs in Sleep, Deep Sleep and VBAT modes • Two Address Generation Units (AGUs) for • Three 3-Wire/4-Wire SPI modules: Separate Read and Write Addressing of - Support four Frame modes Data Memory - Variable FIFO buffer Special Microcontroller Features - I2S mode - Variable width from 2-bit to 32-bit • Supply Voltage Range of 2.0V to 3.6V • Two I2C™ modules Support Multi-Master/Slave • Two On-Chip Voltage Regulators (1.8V and 1.2V) mode and 7-Bit/10-Bit Addressing for Regular and Extreme Low-Power Operation • Four UART modules: • 20,000 Erase/Write Cycle Endurance Flash - Support RS-485, RS-232 and LIN/J2602 Program Memory, Typical - On-chip hardware encoder/decoder for IrDA® • Flash Data Retention: 20 Years Minimum - Smart Card ISO 7816 support on UART1 and • Self-Programmable under Software Control UART2 only: • Programmable Reference Clock Output - T = 0 protocol with automatic error handling • In-Circuit Serial Programming™ (ICSP™) and - T = 1 protocol In-Circuit Emulation (ICE) via 2 Pins - Dedicated Guard Time Counter (GTC) • JTAG Programming and Boundary Scan Support - Dedicated Waiting Time Counter (WTC) • Fail-Safe Clock Monitor (FSCM) Operation: - Auto-wake-up on Auto-Baud Detect (ABD) - Detects clock failure and switches to on-chip, Low-Power RC Oscillator (LPRC) - 4-level deep FIFO buffer • Power-on Reset (POR), Power-up Timer (PWRT) • Programmable 32-Bit Cyclic Redundancy Check and Oscillator Start-up Timer (OST) (CRC) Generator • Separate Brown-out Reset (BOR) and Deep • Digital Signal Modulator provides On-Chip FSK Sleep Brown-out Reset (DSBOR) Circuits and PSK Modulation for a Digital Signal Stream • Programmable High/Low-Voltage Detect (HLVD) • High-Current Sink/Source (18mA/18mA) on All I/O Pins • Flexible Watchdog Timer (WDT) with its Own RC Oscillator for Reliable Operation • Configurable Open-Drain Outputs on Digital I/O Pins • Standard and Ultra Low-Power Watchdog Timers • 5.5V Tolerant Inputs on Most Pins (ULPWs) for Reliable Operation in Standard and Deep Sleep modes DS30010038C-page 2  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY Pin Diagrams 28-Pin SPDIP, SOIC, SSOP(1) 5V tolerant MCLR 1 28 VDD CVREF+/VREF+/AN0/C3INC/CTED1/CN2/RA0 2 27 VSS CVREF-/VREF-/AN1/C3IND/CTED2/CN3/RA1 3 26 AN9/C3INA/RP15/T3CK/T2CK/CTED6/CN11/RB15 P PGD1/AN2/CTCMP/C2INB/RP0/CN4/RB0 4 IC 25 CVREF/AN6/C3INB/RP14/RTCC/CTED5/CN12/RB14 PGC1/AN3/C2INA/RP1/CTED12/CN5/RB1 5 2 24 AN7/C1INC/REFO/RP13/CTPLS/CN13/RB13 4 AN4/C1INB/RP2/SDA2/T5CK/T4CK/CTED13/CN6/RB2 6 F 23 AN8/HLVDIN/RP12/CN14/RB12 AN5/C1INA/RP3/SCL2/CTED8/CN7/RB3 7 JX 22 PGC2/REFI/RP11/CTED9/CN15/RB11 VSS 8 X 21 PGD2/TDI/RP10/CTED11/CN16/RB10 X OSCI/CLKI/C1IND/CN30/RA2 9 G 20 VCAP/VDDCORE OSCO/CLKO/C2IND/CN29/RA3 10 A 19 VBAT SOSCI/RPI4/CN1/RB4 11 20 18 TDO/C1INC/C2INC/C3INC/RP9/SDA1/T1CK/CTED4/CN21/RB9 SOSCO/SCLKI/CN0/RA4 12 2 17 TCK/RP8/SCL1/CTED10/CN22/RB8 VDD 13 16 RP7/CTED3/INT0/CN23/RB7 PGD3/RP5/ASDA1/CN27/RB5 14 15 PGC3/RP6/ASCL1/CN24/RB6 Legend: RPn represents remappable peripheral pins.  2013-2015 Microchip Technology Inc. DS30010038C-page 3

PIC24FJ128GA204 FAMILY Pin Diagrams (Continued) 28-Pin QFN-S(1,2) 5V tolerant 4 15B1 BR 2/CN3/RA1D1/CN2/RA0 TED6/CN11/RCTED5/CN12/ CV-/V-/AN1/C3IND/CTEDREFREF CV+/V+/AN0/C3INC/CTEREFREF MCLRVDD VSSAN9/C3INA/RP15/T3CK/T2CK/CCV/AN6/C3INB/RP14/RTCC/REF 28272625242322 PGD1/AN2/CTCMP/C2INB/RP0/CN4/RB0 1 21 AN7/C1INC/REFO/RP13/CTPLS/CN13/RB13 PGC1/AN3/C2INA/RP1/CTED12/CN5/RB1 2 20 AN8/HLVDIN/RP12/CN14/RB12 AN4/C1INB/RP2/SDA2/T5CK/T4CK/CTED13/CN6/RB2 3 19 PGC2/REFI/RP11/CTED9/CN15/RB11 AN5/C1INA/RP3/SCL2/CTED8/CN7/RB3 4PIC24FJXXXGA20218 PGD2/TDI/RP10/CTED11/CN16/RB10 VSS 5 17 VCAP/VDDCORE OSCI/CLKI/C1IND/CN30/RA2 6 16 VBAT OSCO/CLKO/C2IND/CN29/RA3 7 15 TDO/C1INC/C2INC/C3INC/RP9/SDA1/T1CK/CTED4/CN21/RB9 8 91011121314 RB4RA4VDDRB5 RB6RB7RB8 CN1/CN0/ N27/ N24/N23/N22/ SOSCI/RPI4/SOSCO/SCLKI/ PGD3/RP5/ASDA1/C PGC3/RP6/ASCL1/CRP7/CTED3/INT0/CRP8/SCL1/CTED10/C K/ C T Legend: RPn represents remappable peripheral pins. Note 1: The back pad on QFN devices should be connected to VSS. DS30010038C-page 4  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY Pin Diagrams (Continued) 44-Pin TQFP, 5V tolerant 44-Pin QFN(1,2,3) RB8RB7RB6RB5VDDVSSRC5RC4RC3RA9RA4 43210987654 44444333333 RB9 1 33 RB4 RC6 2 32 RA8 RC7 3 31 RA3 RC8 4 30 RA2 RC9 5 29 VSS VBAT 6 PIC24FJXXXGA204 28 VDD VCAP 7 27 RC2 RB10 8 26 RC1 RB11 9 25 RC0 RB12 10 24 RB3 RB13 11 23 RB2 23456789012 11111111222 0745SDR0101 RA1RARB1RB1/VSSAVDMCLRARARBRB S V A Legend: RPn represents remappable peripheral pins. Note 1: The back pad on QFN devices should be connected to VSS. 2: See Table1 for complete pinout descriptions. TABLE 1: PIC24FJXXGA204 PIN FUNCTION DESCRIPTIONS Pin Function Pin Function 1 C1INC/C2INC/C3INC/RP9/SDA1/T1CK/CTED4/PMD3/CN21/RB9 23 AN4/C1INB/RP2/SDA2/T5CK/T4CK/CTED13/CN6/RB2 2 RP22/PMA1/PMALH/CN18/RC6 24 AN5/C1INA/RP3/SCL2/CTED8/CN7/RB3 3 RP23/PMA0/PMALL/CN17/RC7 25 AN10/RP16/PMBE1/CN8/RC0 4 RP24/PMA5/CN20/RC8 26 AN11/RP17/PMCS2/CN9/RC1 5 RP25/CTED7/PMA6/CN19/RC9 27 AN12/RP18/PMACK1/CN10/RC2 6 VBAT 28 VDD 7 VCAP 29 VSS 8 RP10/CTED11/PMD2/CN16/PGD2/RB10 30 OSCI/CLKI/C1IND/PMCS1/CN30/RA2 9 REFI/RP11/CTED9/PMD1/CN15/PGC2/RB11 31 OSCO/CLKO/C2IND/CN29/RA3 10 AN8/HLVDIN/RP12/PMD0/CN14/RB12 32 TDO/PMA8/CN34/RA8 11 AN7/C1INC/REFO/RP13/CTPLS/PMRD/PMWR/CN13/RB13 33 SOSCI/CN1/RPI4/RB4 12 TMS/PMA2/PMALU/CN36/RA10 34 SOSCO/SCLKI/CN0/RA4 13 TCK/PMA7/CN33/RA7 35 TDI/PMA9/CN35/RA9 14 CVREF/AN6/C3INB/RP14/PMWR/PMNEB/RTCC/CTED5/CN12/RB14 36 RP19/PMBE0/CN28/RC3 15 AN9/C3INA/RP15/T3CK/T2CK/CTED6/PMA14/CN11/PMCS/PMCS1/RB15 37 RP20/PMA4/CN25/RC4 16 AVSS/VSS 38 RP21/PMA3/CN26/RC5 17 AVDD 39 VSS 18 MCLR 40 VDD 19 CVREF+/VREF+/AN0/C3INC/CTED1/CN2/RA0 41 PGD3/RP5/ASDA1(1)/PMD7/CN27/RB5 20 CVREF-/VREF-/AN1/C3IND/CTED2/CN3/RA1 42 PGC3/RP6/ASCL1(1)/PMD6/CN24/RB6 21 AN2/CTCMP/C2INB/RP0/CN4/PGD1/RB0 43 RP7/CTED3/INT0/CN23/PMD5/RB7 22 AN3/C2INA/RP1/CTED12/CN5/PGC1/RB1 44 RP8/SCL1/CTED10/PMD4/CN22/RB8 Legend: RPn represents remappable peripheral pins. Note1: Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.  2013-2015 Microchip Technology Inc. DS30010038C-page 5

PIC24FJ128GA204 FAMILY Table of Contents 1.0 Device Overview..........................................................................................................................................................................9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................21 3.0 CPU ...........................................................................................................................................................................................27 4.0 Memory Organization.................................................................................................................................................................33 5.0 Direct Memory Access Controller (DMA)...................................................................................................................................67 6.0 Flash Program Memory..............................................................................................................................................................75 7.0 Resets........................................................................................................................................................................................81 8.0 Interrupt Controller.....................................................................................................................................................................87 9.0 Oscillator Configuration............................................................................................................................................................141 10.0 Power-Saving Features............................................................................................................................................................155 11.0 I/O Ports...................................................................................................................................................................................167 12.0 Timer1......................................................................................................................................................................................195 13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................199 14.0 Input Capture with Dedicated Timers.......................................................................................................................................205 15.0 Output Compare with Dedicated Timers..................................................................................................................................211 16.0 Serial Peripheral Interface (SPI)...............................................................................................................................................221 17.0 Inter-Integrated Circuit™ (I2C™)..............................................................................................................................................237 18.0 Universal Asynchronous Receiver Transmitter (UART)...........................................................................................................245 19.0 Data Signal Modulator (DSM)..................................................................................................................................................257 20.0 Enhanced Parallel Master Port (EPMP)...................................................................................................................................263 21.0 Real-Time Clock and Calendar (RTCC) ..................................................................................................................................275 22.0 Cryptographic Engine...............................................................................................................................................................289 23.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator .......................................................................................305 24.0 12-Bit A/D Converter with Threshold Detect............................................................................................................................311 25.0 Triple Comparator Module........................................................................................................................................................331 26.0 Comparator Voltage Reference................................................................................................................................................337 27.0 Charge Time Measurement Unit (CTMU)................................................................................................................................339 28.0 High/Low-Voltage Detect (HLVD).............................................................................................................................................347 29.0 Special Features......................................................................................................................................................................349 30.0 Development Support...............................................................................................................................................................363 31.0 Instruction Set Summary..........................................................................................................................................................367 32.0 Electrical Characteristics..........................................................................................................................................................375 33.0 Packaging Information..............................................................................................................................................................407 Appendix A: Revision History.............................................................................................................................................................425 Index..................................................................................................................................................................................................427 The Microchip Web Site.....................................................................................................................................................................433 Customer Change Notification Service..............................................................................................................................................433 Customer Support..............................................................................................................................................................................433 Product Identification System.............................................................................................................................................................435 DS30010038C-page 6  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2013-2015 Microchip Technology Inc. DS30010038C-page 7

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 8  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 1.0 DEVICE OVERVIEW Many of these new low-power modes also support the continuous operation of the low-power, on-chip Real- This document contains device-specific information for Time Clock/Calendar (RTCC), making it possible for an the following devices: application to keep time while the device is otherwise asleep. • PIC24FJ64GA202 • PIC24FJ128GA202 • PIC24FJ64GA204 • PIC24FJ128GA204 Aside from these new features, PIC24FJ128GA204 family devices also include all of the legacy power-saving The PIC24FJ128GA204 family expands the capabilities features of previous PIC24F microcontrollers, such as: of the PIC24F family by adding a complete selection of Cryptographic Engines, ISO 7816 support and I2S sup- • On-the-Fly Clock Switching, allowing the selection of a lower power clock during run time port to its existing features. This combination, along with its ultra low-power features and Direct Memory Access • Doze Mode Operation, for maintaining peripheral (DMA) for peripherals, make this family the new clock speed while slowing the CPU clock standard for mixed-signal PIC® microcontrollers in one • Instruction-Based Power-Saving Modes, for quick economical and power-saving package. invocation of Idle and the many Sleep modes 1.1 Core Features 1.1.3 OSCILLATOR OPTIONS AND FEATURES 1.1.1 16-BIT ARCHITECTURE All of the devices in the PIC24FJ128GA204 family offer Central to all PIC24F devices is the 16-bit modified five different oscillator options, allowing users a range Harvard architecture, first introduced with Microchip’s of choices in developing application hardware. These dsPIC® Digital Signal Controllers (DSCs). The PIC24F include: CPU core offers a wide range of enhancements, such as: • Two Crystal modes • 16-bit data and 24-bit address paths with the • Two External Clock modes ability to move information between data and • A Phase-Locked Loop (PLL) frequency multiplier, memory spaces which allows clock speeds of up to 32MHz • Linear addressing of up to 12 Mbytes (program • A Fast Internal Oscillator (FRC) – nominal 8MHz space) and 32 Kbytes (data) output with multiple frequency divider options and • A 16-element Working register array with built-in automatic frequency self-calibration during software stack support run time • A 17 x 17 hardware multiplier with support for • A separate, Low-Power Internal RC Oscillator integer math (LPRC) – 31 kHz nominal, for low-power, • Hardware support for 32 by 16-bit division timing-insensitive applications. • An instruction set that supports multiple The internal oscillator block also provides a stable ref- addressing modes and is optimized for high-level erence source for the Fail-Safe Clock Monitor (FSCM). languages, such as ‘C’ This option constantly monitors the main clock source • Operational performance up to 16 MIPS against a reference signal provided by the internal oscillator and enables the controller to switch to the 1.1.2 XLP POWER-SAVING internal oscillator, allowing for continued low-speed TECHNOLOGY operation or a safe application shutdown. The PIC24FJ128GA204 family of devices introduces a 1.1.4 EASY MIGRATION greatly expanded range of power-saving operating modes for the ultimate in power conservation. The new Regardless of the memory size, all devices share the modes include: same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. This • Retention Sleep, with essential circuits being extends the ability of applications to grow from the powered from a separate low-voltage regulator relatively simple, to the powerful and complex, yet still • Deep Sleep without RTCC, for the lowest possible selecting a Microchip device. power consumption under software control • VBAT mode (with or without RTCC), to continue limited operation from a backup battery when VDD is removed  2013-2015 Microchip Technology Inc. DS30010038C-page 9

PIC24FJ128GA204 FAMILY 1.2 DMA Controller • Enhanced Parallel Master/Parallel Slave Port: This module allows rapid and transparent access PIC24FJ128GA204 family devices also add a Direct to the microcontroller data bus, and enables the Memory Access (DMA) Controller to the existing CPU to directly address external data memory. PIC24F architecture. The DMA acts in concert with the The parallel port can function in Master or Slave CPU, allowing data to move between data memory and mode, accommodating data widths of 4, 8 or peripherals without the intervention of the CPU, 16bits, and address widths of up to 23 bits in increasing data throughput and decreasing execution Master modes. time overhead. Six independently programmable chan- • Real-Time Clock and Calendar (RTCC): This nels make it possible to service multiple peripherals at module implements a full-featured clock and virtually the same time, with each channel peripheral calendar with alarm functions in hardware, freeing performing a different operation. Many types of data up timer resources and program memory space transfer operations are supported. for use of the core application. • Data Signal Modulator (DSM): The Data Signal 1.3 Cryptographic Engine Modulator (DSM) allows the user to mix a digital The Cryptographic Engine provides a new set of data data stream (the “modulator signal”) with a carrier security options. Using its own free-standing state signal to produce a modulated output. machines, the engine can independently perform NIST standard encryption and decryption of data, 1.5 Details on Individual Family independently of the CPU. Members Support for True Random Number Generation (TRNG) Devices in the PIC24FJ128GA204 family are available and Pseudorandom Number Generation (PRNG); in 28-pin and 44-pin packages. The general block NIST SP800-90 compliant. diagram for all devices is shown in Figure1-1. 1.4 Other Special Features The devices are differentiated from each other in sixways: • Peripheral Pin Select (PPS): The Peripheral Pin 1. Flash program memory (64 Kbytes for Select feature allows most digital peripherals to PIC24FJ64GA2XX devices and 128 Kbytes for be mapped over a fixed set of digital I/O pins. PIC24FJ128GA2XX devices). Users may independently map the input and/or 2. Available I/O pins and ports (21 pins on two output of any one of the many digital peripherals ports for 28-pin devices, 35 pins on three ports to any one of the I/O pins. for 44-pin devices). • Communications: The PIC24FJ128GA204 family 3. Available Input Change Notification (ICN) inputs incorporates a range of serial communication (20 on 28-pin devices and 34 on 44-pin devices). peripherals to handle a range of application requirements. There are two independent I2C™ 4. Available remappable pins (14 pins on 28-pin modules that support both Master and Slave devices and 24 pins on 44-pin devices). modes of operation. Devices also have, through 5. Analog input channels for the A/D Converter the PPS feature, four independent UARTs with (12channels for 44-pin devices and 9 channels built-in IrDA® encoders/decoders, ISO 7816 Smart for 28-pin devices). Card support (UART1 and UART2 only), and three All other features for devices in this family are identical. SPI modules with I2S and variable data width These are summarized in Table1-1 and Table1-2. support. A list of the pin features available on the • Analog Features: All members of the PIC24FJ128GA204 family devices, sorted by function, PIC24FJ128GA204 family include a 12-bit A/D is shown in Table1-3. Note that this table shows the pin Converter module and a triple comparator module. location of individual peripheral features and not how The A/D module incorporates a range of new they are multiplexed on the same pin. This information features that allows the converter to assess and is provided in the pinout diagrams in the beginning of make decisions on incoming data, reducing CPU the data sheet. Multiplexed features are sorted by the overhead for routine A/D conversions. The compar- priority given to a feature, with the highest priority ator module includes three analog comparators that peripheral being listed first. are configurable for a wide range of operations. • CTMU Interface: In addition to their other analog features, members of the PIC24FJ128GA204 family include the CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. DS30010038C-page 10  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA204 FAMILY: 44-PIN DEVICES Features PIC24FJ64GA204 PIC24FJ128GA204 Operating Frequency DC – 32 MHz Program Memory (bytes) 64K 128K Program Memory (instructions) 22,016 44,032 Data Memory (bytes) 8K Interrupt Sources (soft vectors/ 71 (67/4) NMI traps) I/O Ports Ports A, B, C Total I/O Pins 35 Remappable Pins 25 (24 I/Os, 1 Input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture w/Timer Channels 6(1) Output Compare/PWM Channels 6(1) Input Change Notification Interrupt 35 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 2 Digital Signal Modulator (DSM) Yes Parallel Communications (EPMP/PSP) Yes JTAG Boundary Scan Yes 12-Bit SAR Analog-to-Digital 13 Converter (A/D) (input channels) Analog Comparators 3 CTMU Interface 13 Channels Resets (and Delays) Core POR, VDD POR, VBAT POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 44-Pin TQFP and QFN Cryptographic Engine Supports AES with 128, 192 and 256-Bit Key, DES and TDES, True Random and Pseudorandom Number Generator, On-Chip OTP Storage RTCC Yes Note 1: Peripherals are accessible through remappable pins.  2013-2015 Microchip Technology Inc. DS30010038C-page 11

PIC24FJ128GA204 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ128GA204 FAMILY: 28-PIN DEVICES Features PIC24FJ64GA202 PIC24FJ128GA202 Operating Frequency DC – 32 MHz Program Memory (bytes) 64K 128K Program Memory (instructions) 22,016 44,032 Data Memory (bytes) 8K Interrupt Sources (soft vectors/ 71 (67/4) NMI traps) I/O Ports Ports A, B Total I/O Pins 21 Remappable Pins 16 (15 I/Os, 1 Input only) Timers: Total Number (16-bit) 5(1) 32-Bit (from paired 16-bit timers) 2 Input Capture w/Timer Channels 6(1) Output Compare/PWM Channels 6(1) Input Change Notification Interrupt 21 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2C™ 2 Digital Signal Modulator (DSM) Yes JTAG Boundary Scan Yes 12-Bit SAR Analog-to-Digital 10 Converter (A/D) (input channels) Analog Comparators 3 CTMU Interface 10 Channels Resets (and Delays) Core POR, VDD POR, VBAT POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) Instruction Set 76 Base Instructions, Multiple Addressing Mode Variations Packages 28-Pin SPDIP, SSOP, SOIC and QFN-S Cryptographic Engine Supports AES with 128, 192 and 256-Bit Key, DES and TDES, True Random and Pseudorandom Number Generator, On-Chip OTP Storage RTCC Yes Note 1: Peripherals are accessible through remappable pins. DS30010038C-page 12  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 1-1: PIC24FJ128GA204 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 8 16 16 (9 I/Os) EDS and Data Latch Table Data Access Control PCH PCL DataRAM DMA 23 Controller Program Counter Address Stack Repeat Latch Control Control Logic Logic 16 23 16 16 PORTB Address Latch Read AGU Write AGU (16 I/Os) Program Memory/ Extended Data Space Data Latch 16 Address Bus EA MUX 24 Inst Latch 16 16 Literal Data Inst Register DMA PORTC(1) Data Bus Instruction (10 I/Os) Control Signals Decode and Control Divide OSCO/CLKO Support 16 x 16 OSCI/CLKI 17x17 W Reg Array Timing Power-up Multiplier Generation Timer Oscillator REFO FRC/LPRC Start-up Timer Oscillators Power-on 16-Bit ALU BGBUF1 Reset 16 Precision EPMP/PSP Band Gap Watchdog BGBUF2 References Timer Voltage HLVD & BOR Regulators VCAP VBAT VDD, VSS MCLR Timers UARTx 12-Bit Timer1 2/3 & 4/5(2) RTCC DSM Wit1h/ 2IS/3O/4 7(28)16 A/D Converter Comparators(2) SPIx 1-I6C(2) OC1-/P6(W2)M ICNs(1) w1i/t2h/ 3I2(2S) I21C/2™ CTMU CrypEtnoggirnaephic Note1: Not all I/O pins or features are implemented on all device pinout configurations. See Table1-3 for specific implementations by pin count. 2: These peripheral I/Os are only accessible through remappable pins.  2013-2015 Microchip Technology Inc. DS30010038C-page 13

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP AN0 2 27 19 I ANA 12-Bit SAR A/D Converter Inputs. AN1 3 28 20 I ANA AN2 4 1 21 I ANA AN3 5 2 22 I ANA AN4 6 3 23 I ANA AN5 7 4 24 I ANA AN6 25 22 14 I ANA AN7 24 21 11 I ANA AN8 23 20 10 I ANA AN9 26 23 15 I ANA AN10 — — 25 I ANA AN11 — — 26 I ANA AN12 — — 27 I ANA ASCL1 15 12 42 — — ASDA1 2 27 19 — — AVDD — — 17 P ANA Positive Supply for Analog modules. AVSS — 24 16 P ANA Ground Reference for Analog modules. C1INA 7 4 24 I ANA Comparator 1 Input A. C1INB 6 3 23 I ANA Comparator 1 Input B. C1INC 24 15 1 I ANA Comparator 1 Input C. C1IND 9 6 30 I ANA Comparator 1 Input D. C2INA 5 2 22 I ANA Comparator 2 Input A. C2INB 4 1 21 I ANA Comparator 2 Input B. C2INC 18 15 1 I ANA Comparator 2 Input C. C2IND 10 7 31 I ANA Comparator 2 Input D. C3INA 26 23 15 I ANA Comparator 3 Input A. C3INB 25 22 14 I ANA Comparator 3 Input B. C3INC 2 15 1 I ANA Comparator 3 Input C. C3IND 3 28 20 I ANA Comparator 3 Input D. CLKI 9 6 30 I ANA Main Clock Input Connection. CLKO 10 7 31 O — System Clock Output. Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels DS30010038C-page 14  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP CN0 12 9 34 — — Interrupt-on-Change Inputs. CN1 11 8 33 — — CN2 2 27 19 — — CN3 3 28 20 — — CN4 4 1 21 — — CN5 5 2 22 — — CN6 6 3 23 — — CN7 7 4 24 — — CN8 — — 25 — — CN9 — — 26 — — CN10 — — 27 — — CN11 26 23 15 — — CN12 25 22 14 — — CN13 24 21 11 — — CN14 23 20 10 — — CN15 22 19 9 — — CN16 21 18 8 — — CN17 — — 3 — — CN18 — — 2 — — CN19 — — 5 — — CN20 — — 4 — — CN21 18 15 1 — — CN22 17 14 44 — — CN23 16 13 43 — — CN24 15 12 42 — — CN25 — — 37 — — CN26 — — 38 — — CN27 14 11 41 — — CN28 — — 36 — — CN29 10 7 31 — — CN30 9 6 30 — — CN33 — — 13 — — CN34 — — 32 — — CN35 — — 35 — — CN36 — — 12 — — CTCMP 4 1 21 I ANA CTMU Comparator 2 Input (Pulse mode). Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels  2013-2015 Microchip Technology Inc. DS30010038C-page 15

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP CTED1 2 27 19 I ANA CTMU External Edge Inputs. CTED2 3 28 20 I ANA CTED3 16 13 43 I ANA CTED4 18 15 1 I ANA CTED5 25 22 14 I ANA CTED6 26 23 15 I ANA CTED7 — — 5 I ANA CTED8 7 4 24 I ANA CTED9 22 19 9 I ANA CTED10 17 14 44 I ANA CTED11 21 18 8 I ANA CTED12 5 2 22 I ANA CTED13 6 3 23 I ANA CTPLS 24 21 11 O — CTMU Pulse Output. CVREF 25 22 14 O ANA Comparator Voltage Reference Output. CVREF+ 2 27 19 I ANA Comparator Reference Voltage (high) Input. CVREF- 3 28 20 I ANA Comparator Reference Voltage (low) Input. INT0 16 13 43 I ST External Interrupt Input 0. HLVDIN 23 20 10 I ANA High/Low-Voltage Detect Input. MCLR 1 26 18 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 9 6 30 I ANA Main Oscillator Input Connection. OSCO 10 7 31 O — Main Oscillator Output Connection. PGC1 5 2 22 I/O ST In-Circuit Debugger/Emulator/ICSP™ PGC2 22 19 9 I/O ST Programming Clock. PGC3 15 12 42 I/O ST PGD1 4 1 21 I/O ST PGD2 21 18 8 I/O ST PGD3 14 11 41 I/O ST Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels DS30010038C-page 16  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP PMA0/PMALL — — 3 O — Parallel Master Port Address. PMA1/PMALH — — 2 O — PMA14/PMCS/ — — 15 O — PMCS1 PMA2/PMALU — — 12 O — PMA3 — — 38 O — PMA4 — — 37 O — PMA5 — — 4 O — PMA6 — — 5 O — PMA7 — — 13 O — PMA8 — — 32 O — PMA9 — — 35 O — PMACK1 — — 27 I ST/TTL Parallel Master Port Acknowledge Input 1. PMBE0 — — 36 O — Parallel Master Port Byte Enable 0 Strobe. PMBE1 — — 25 O — Parallel Master Port Byte Enable 1 Strobe. PMCS1 — — 30 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe. PMD0 — — 10 I/O ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed PMD1 — — 9 I/O ST/TTL Master modes). PMD2 — — 8 I/O ST/TTL PMD3 — — 1 I/O ST/TTL PMD4 — — 44 I/O ST/TTL PMD5 — — 43 I/O ST/TTL PMD6 — — 42 I/O ST/TTL PMD7 — — 41 I/O ST/TTL PMRD — — 11 O — Parallel Master Port Read Strobe. PMWR — — 14 O — Parallel Master Port Write Strobe. RA0 2 27 19 I/O ST PORTA Digital I/Os. RA1 3 28 20 I/O ST RA2 9 6 30 I/O ST RA3 10 7 31 I/O ST RA4 12 9 34 I ST RA7 — — 13 I/O ST RA8 — — 32 I/O ST RA9 — — 35 I/O ST RA10 — — 12 I/O ST Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels  2013-2015 Microchip Technology Inc. DS30010038C-page 17

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP RB0 4 1 21 I/O ST PORTB Digital I/Os. RB1 5 2 22 I/O ST RB2 6 3 23 I/O ST RB3 7 4 24 I/O ST RB4 11 8 33 I ST RB5 14 11 41 I/O ST RB6 15 12 42 I/O ST RB7 16 13 43 I/O ST RB8 17 14 44 I/O ST RB9 18 15 1 I/O ST RB10 21 18 8 I/O ST RB11 22 19 9 I/O ST RB12 23 20 10 I/O ST RB13 24 21 11 I/O ST RB14 25 22 14 I/O ST RB15 26 23 15 I/O ST RC0 — — 25 I/O ST PORTC Digital I/Os. RC1 — — 26 I/O ST RC2 — — 27 I/O ST RC3 — — 36 I/O ST RC4 — — 37 I/O ST RC5 — — 38 I/O ST RC6 — — 2 I/O ST RC7 — — 3 I/O ST RC8 — — 4 I/O ST RC9 — — 5 I/O ST REFI 22 19 9 — — REFO 24 21 11 — — Reference Clock Output. Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels DS30010038C-page 18  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP RP0 4 1 21 I/O ST Remappable Peripherals (input or output). RP1 5 2 22 I/O ST RP2 6 3 23 I/O ST RP3 7 4 24 I/O ST RP5 14 11 41 I/O ST RP6 3,15 12 42 I/O ST RP7 16 13 43 I/O ST RP8 17 14 44 I/O ST RP9 18 15 1 I/O ST RP10 21 18 8 I/O ST RP11 22 19 9 I/O ST RP12 23 20 10 I/O ST RP13 24 21 11 I/O ST RP14 25 22 14 I/O ST RP15 26 23 15 I/O ST RP16 — — 25 I/O ST RP17 — — 26 I/O ST RP18 — — 27 I/O ST RP19 — — 36 I/O ST RP20 — — 37 I/O ST RP21 — — 38 I/O ST RP22 — — 2 I/O ST RP23 — — 3 I/O ST RP24 — — 4 I/O ST RP25 — — 5 I/O ST RPI4 11 8 33 I ST Remappable Peripheral (input). RTCC 25 22 14 O — Real-Time Clock Alarm/Seconds Pulse Output. SCL1 17 14 44 I/O I2C I2C1 Synchronous Serial Clock Input/Output. SCL2 7 4 24 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SCLKI 12 9 34 I — Secondary Oscillator Digital Clock Input. SDA1 18 15 1 I/O I2C I2C1 Data Input/Output. SDA2 6 3 23 I/O I2C I2C2 Data Input/Output. SOSCI 11 8 33 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 12 9 34 O ANA Secondary Oscillator/Timer1 Clock Output. Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels  2013-2015 Microchip Technology Inc. DS30010038C-page 19

PIC24FJ128GA204 FAMILY TABLE 1-3: PIC24FJ128GA204 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number/Grid Locator Input Pin Function 28-Pin I/O Description 28-Pin 44-Pin Buffer SPDIP/SOIC/ QFN-S TQFP/QFN SSOP T1CK 18 15 1 I ST Timer1 Clock. T2CK 26 23 15 I ST Timer2 Clock. T3CK 26 23 15 I ST Timer3 Clock. T4CK 6 3 23 I ST Timer4 Clock. T5CK 6 3 23 I ST Timer5 Clock. TCK 17 14 13 I ST JTAG Test Clock/Programming Clock Input. TDI 21 18 35 I ST JTAG Test Data/Programming Data Input. TDO 18 15 32 O — JTAG Test Data Output. TMS 22 19 12 I — JTAG Test Mode Select Input. VBAT 19 16 6 P — Backup Battery (B+) Input (1.2V nominal). VCAP 20 17 7 P — External Filter Capacitor Connection. VDD 13,28 25,10 28,40 P — Positive Supply for Peripheral Digital Logic and I/O Pins. VDDCORE 20 17 7 — — Microcontroller Core Supply Voltage. VREF+ 2 27 19 I ANA A/D Reference Voltage Input (+). VREF- 3 28 20 I ANA A/D Reference Voltage Input (-). VSS 8,27 5,24 29,39 P — Ground Reference for Logic and I/O Pins. Legend: ST = Schmitt Trigger input TTL = TTL compatible input I = Input ANA= Analog input O = Output P = Power I2C = ST with I2C™ or SMBus levels DS30010038C-page 20  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 2.0 GUIDELINES FOR GETTING FIGURE 2-1: RECOMMENDED STARTED WITH 16-BIT MINIMUM CONNECTIONS MICROCONTROLLERS C2(2) 2.1 Basic Connection Requirements VDD Getting started with the PIC24FJ128GA204 family of R1 DD SS (1) (1) 16-bit microcontrollers requires attention to a minimal V V R2 set of device pin connections before proceeding with MCLR (EN/DIS)VREG development. VCAP/VDDCORE C1 The following pins must always be connected: C7 PIC24FJXXXX • All VDD and VSS pins (see Section2.2 “Power Supply Pins”) VSS VDD C6(2) C3(2) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used VDD D S VSS D S D S (see Section2.2 “Power Supply Pins”) V V D S A A V V • MCLR pin (see Section2.3 “Master Clear (MCLR) Pin”) C5(2) C4(2) • ENVREG/DISVREG and VCAP/VDDCORE pins (see Section2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”) Key (all values are recommendations): These pins must also be connected if they are being C1 through C6: 0.1 F, 20V ceramic used in the end application: C7: 10 F, 6.3V or greater, tantalum or ceramic • PGECx/PGEDx pins used for In-Circuit Serial R1: 10 kΩ Programming™ (ICSP™) and debugging purposes R2: 100Ω to 470Ω (see Section2.5 “ICSP Pins”) Note 1: See Section2.4 “Voltage Regulator Pins • OSCI and OSCO pins when an external oscillator (ENVREG/DISVREG and VCAP/VDDCORE)” source is used for explanation of the ENVREG/DISVREG (see Section2.6 “External Oscillator Pins”) pin connections. Additionally, the following pins may be required: 2: The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. • VREF+/VREF- pins used when external voltage Other devices may have more or less pairs; reference for analog modules is implemented adjust the number of decoupling capacitors Note: The AVDD and AVSS pins must always be appropriately. connected, regardless of whether any of the analog modules are being used. The minimum mandatory connections are shown in Figure2-1.  2013-2015 Microchip Technology Inc. DS30010038C-page 21

PIC24FJ128GA204 FAMILY 2.2 Power Supply Pins 2.3 Master Clear (MCLR) Pin 2.2.1 DECOUPLING CAPACITORS The MCLR pin provides two specific device func- tions: device Reset, and device programming and The use of decoupling capacitors on every pair of debugging. If programming and debugging are not power supply pins, such as VDD, VSS, AVDD and required in the end application, a direct connection to AVSS, is required. VDD may be all that is required. The addition of other Consider the following criteria when using decoupling components, to help increase the application’s capacitors: resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in • Value and type of capacitor: A 0.1 F (100 nF), Figure2-1. Other circuit designs may be implemented, 10-20V capacitor is recommended. The capacitor depending on the application’s requirements. should be a low-ESR device with a resonance frequency in the range of 200MHz and higher. During programming and debugging, the resistance Ceramic capacitors are recommended. and capacitance that can be added to the pin must • Placement on the printed circuit board: The be considered. Device programmers and debuggers decoupling capacitors should be placed as close drive the MCLR pin. Consequently, specific voltage to the pins as possible. It is recommended to levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values place the capacitors on the same side of the board as the device. If space is constricted, the of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is capacitor can be placed on another layer on the recommended that the capacitor, C1, be isolated PCB using a via; however, ensure that the trace from the MCLR pin during programming and debug- length from the pin to the capacitor is no greater ging operations by using a jumper (Figure2-2). The than 0.25inch (6mm). jumper is replaced for normal run-time operations. • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of Any components associated with the MCLR pin tens of MHz), add a second ceramic type capaci- should be placed within 0.25 inch (6mm) of the pin. tor in parallel to the above described decoupling capacitor. The value of the second capacitor can FIGURE 2-2: EXAMPLE OF MCLR PIN be in the range of 0.01F to 0.001F. Place this CONNECTIONS second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider VDD implementing a decade pair of capacitances as close to the power and ground pins as possible R1 (e.g., 0.1F in parallel with 0.001F). R2 • Maximizing performance: On the board layout MCLR from the power supply circuit, run the power and JP PIC24FXXXX return traces to the decoupling capacitors first, and then to the device pins. This ensures that the C1 decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a Note 1: R110k is recommended. A minimum, thereby reducing PCB trace suggested starting value is 10k. Ensure inductance. that the MCLR pin VIH and VIL specifications are met. 2.2.2 TANK CAPACITORS 2: R2470 will limit any current flowing into On boards with power traces running longer than MCLR from the external capacitor, C, in sixinches in length, it is suggested to use a tank capac- the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical itor for integrated circuits, including microcontrollers, to Overstress (EOS). Ensure that the MCLR supply a local power source. The value of the tank pin VIH and VIL specifications are met. capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7F to 47F. DS30010038C-page 22  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 2.4 Voltage Regulator Pins (ENVREG/ Designers may use Figure2-3 to evaluate ESR DISVREG and VCAP/VDDCORE) equivalence of candidate devices. The placement of this capacitor should be close to Note: This section applies only to PIC24FJ VCAP/VDDCORE. It is recommended that the trace devices with an on-chip voltage regulator. length not exceed 0.25inch (6mm). Refer to Section32.0 “Electrical Characteristics” for The on-chip voltage regulator enable/disable pin additional information. (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a When the regulator is disabled, the VCAP/VDDCORE pin supply voltage or to ground. The particular connection must be tied to a voltage supply at the VDDCORE level. is determined by whether or not the regulator is to be Refer to Section32.0 “Electrical Characteristics” for used: information on VDD and VDDCORE. • For ENVREG, tie to VDD to enable the regulator, FIGURE 2-3: FREQUENCY vs. ESR or to ground to disable the regulator PERFORMANCE FOR • For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator SUGGESTED VCAP 10 Refer to Section29.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. 1 When the regulator is enabled, a low-ESR (<5Ω) csatapbailciziteo rt heis voreltqaugiere rde guolna tothr eo uVtpCuAt Pv/oVltDaDgCeO. RTEh e pVinC AtPo/ SR () 0.1 E VDDCORE pin must not be connected to VDD and must use a capacitor of 10 µF connected to ground. The type 0.01 can be ceramic or tantalum. Suitable examples of capacitors are shown in Table2-1. Capacitors with 0.001 equivalent specifications can be used. 0.01 0.1 1 10 100 1000 10,000 Frequency (MHz) Note: Typical data measurement at +25°C, 0V DC bias. . TABLE 2-1: SUITABLE CAPACITOR EQUIVALENTS Nominal Make Part # Base Tolerance Rated Voltage Temp. Range Capacitance TDK C3216X7R1C106K 10 µF ±10% 16V -55 to +125°C TDK C3216X5R1C106K 10 µF ±10% 16V -55 to +85°C Panasonic ECJ-3YX1C106K 10 µF ±10% 16V -55 to +125°C Panasonic ECJ-4YB1C106K 10 µF ±10% 16V -55 to +85°C Murata GRM32DR71C106KA01L 10 µF ±10% 16V -55 to +125°C Murata GRM31CR61C106KC31L 10 µF ±10% 16V -55 to +85°C  2013-2015 Microchip Technology Inc. DS30010038C-page 23

PIC24FJ128GA204 FAMILY 2.4.1 CONSIDERATIONS FOR CERAMIC FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITORS CAPACITANCE CHARACTERISTICS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic %) 10 e ( 0 capacitors very attractive in many types of applications. ng-10 16V Capacitor ha-20 Ceramic capacitors are suitable for use with the inter- C-30 nal voltage regulator of this microcontroller. However, ance --5400 10V Capacitor some care is needed in selecting the capacitor to cit-60 ensure that it maintains sufficient capacitance over the Capa--8700 6.3V Capacitor intended operating range of the application. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC Bias Voltage (VDC) Typical low-cost, 10 F ceramic capacitors are available in X5R, X7R and Y5V dielectric ratings (other types are also available, but are less common). The initial When selecting a ceramic capacitor to be used with the tolerance specifications for these types of capacitors are internal voltage regulator, it is suggested to select a often specified as ±10% to ±20% (X5R and X7R) or high-voltage rating, so that the operating voltage is a -20%/+80% (Y5V). However, the effective capacitance small percentage of the maximum rated capacitor volt- that these capacitors provide in an application circuit will age. For example, choose a ceramic capacitor rated at also vary based on additional factors, such as the 16V for the 2.5V or 1.8V core voltage. Suggested applied DC bias voltage and the temperature. The total capacitors are shown in Table2-1. in-circuit tolerance is, therefore, much wider than the initial tolerance specification. 2.5 ICSP Pins The X5R and X7R capacitors typically exhibit satisfac- The PGECx and PGEDx pins are used for In-Circuit tory temperature stability (ex: ±15% over a wide Serial Programming (ICSP) and debugging purposes. temperature range, but consult the manufacturer’s data It is recommended to keep the trace length between sheets for exact specifications). However, Y5V capaci- the ICSP connector and the ICSP pins on the device as tors typically have extreme temperature tolerance short as possible. If the ICSP connector is expected to specifications of +22%/-82%. Due to the extreme experience an ESD event, a series resistor is recom- temperature tolerance, a 10 F nominal rated Y5V type mended, with the value in the range of a few tens of capacitor may not deliver enough total capacitance to ohms, not to exceed 100Ω. meet minimum internal voltage regulator stability and Pull-up resistors, series diodes and capacitors on the transient response requirements. Therefore, Y5V PGECx and PGEDx pins are not recommended as they capacitors are not recommended for use with the will interfere with the programmer/debugger communi- internal regulator if the application must operate over a cations to the device. If such discrete components are wide temperature range. an application requirement, they should be removed In addition to temperature tolerance, the effective from the circuit during programming and debugging. capacitance of large value ceramic capacitors can vary Alternatively, refer to the AC/DC characteristics and substantially, based on the amount of DC voltage timing requirements information in the respective applied to the capacitor. This effect can be very signifi- device Flash programming specification for information cant, but is often overlooked or is not always on capacitive loading limits and pin Voltage Input High documented. (VIH) and Voltage Input Low (VIL) requirements. Typical DC bias voltage vs. capacitance graph for X7R For device emulation, ensure that the “Communication type capacitors is shown in Figure2-4. Channel Select” (i.e., PGECx/PGEDx pins), programmed into the device, matches the physical connections for the ICSP to the Microchip debugger/ emulator tool. For more information on available Microchip development tools connection requirements, refer to Section30.0 “Development Support”. DS30010038C-page 24  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: SUGGESTED PLACEMENT OF THE Many microcontrollers have options for at least two OSCILLATOR CIRCUIT oscillators: a high-frequency Primary Oscillator and a low-frequency Secondary Oscillator (refer to Single-Sided and In-Line Layouts: Section9.0 “Oscillator Configuration” for details). Copper Pour Primary Oscillator The oscillator circuit should be placed on the same (tied to ground) Crystal side of the board as the device. Place the oscillator DEVICE PINS circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side Primary OSCI Oscillator of the board. C1 ` OSCO Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The C2 GND grounded copper pour should be routed directly to the ` MCU ground. Do not run any signal traces or power SOSCO traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board Secondary SOSCI where the crystal is placed. Oscillator Crystal ` Layout suggestions are shown in Figure2-5. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With Sec Oscillator: C1 Sec Oscillator: C2 fine-pitch packages, it is not always possible to com- pletely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored Fine-Pitch (Dual-Sided) Layouts: ground layer. In all cases, the guard trace(s) must be returned to ground. Top Layer Copper Pour (tied to ground) In planning the application’s routing and I/O assign- ments, ensure that adjacent port pins, and other Bottom Layer signals in close proximity to the oscillator, are benign Copper Pour (i.e., free of high frequencies, short rise and fall times (tied to ground) and other similar noise). OSCO For additional information and design guidance on oscillator circuits, please refer to these Microchip C2 Application Notes, available at the corporate web site Oscillator (www.microchip.com): GND Crystal • AN826, “Crystal Oscillator Basics and Crystal C1 Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” OSCI • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” DEVICE PINS  2013-2015 Microchip Technology Inc. DS30010038C-page 25

PIC24FJ128GA204 FAMILY 2.7 Configuration of Analog and If your application needs to use certain A/D pins as Digital Pins During ICSP analog input pins during the debug session, the user application must modify the appropriate bits during Operations initialization of the A/D module, as follows: If an ICSP compliant emulator is selected as a debug- • For devices with an ADxPCFG register, clear the ger, it automatically initializes all of the A/D input pins bits corresponding to the pin(s) to be configured (ANx) as “digital” pins. Depending on the particular as analog. Do not change any other bits, particu- device, this is done by setting all bits in the ADxPCFG larly those corresponding to the PGECx/PGEDx register(s) or clearing all bits in the ANSx registers. pair, at any time. All PIC24F devices will have either one or more • For devices with ANSx registers, set the bits ADxPCFG registers or several ANSx registers (one for corresponding to the pin(s) to be configured as each port); no device will have both. Refer to analog. Do not change any other bits, particularly Section11.2 “Configuring Analog Port Pins those corresponding to the PGECx/PGEDx pair, (ANSx)” for more specific information. at any time. The bits in these registers that correspond to the A/D When a Microchip debugger/emulator is used as a pins that initialized the emulator must not be changed programmer, the user application firmware must by the user application firmware; otherwise, correctly configure the ADxPCFG or ANSx registers. communication errors will result between the debugger Automatic initialization of this register is only done and the device. during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.8 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1kΩ to 10kΩ resistor to VSS on unused pins and drive the output to logic low. DS30010038C-page 26  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 3.0 CPU The core supports Inherent (no operand), Relative, Literal and Memory Direct Addressing modes along Note: This data sheet summarizes the features with three groups of addressing modes. All modes sup- of this group of PIC24F devices. It is not port Register Direct and various Register Indirect intended to be a comprehensive refer- modes. Each group offers up to seven addressing ence source. For more information on the modes. Instructions are associated with predefined CPU, refer to the “dsPIC33/PIC24 Family addressing modes depending upon their functional Reference Manual”, “CPU with Extended requirements. Data Space (EDS)” (DS39732). The infor- For most instructions, the core is capable of executing mation in this data sheet supersedes the a data (or program data) memory read, a Working reg- information in the FRM. ister (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a The PIC24F CPU has a 16-bit (data) modified Harvard result, three parameter instructions can be supported, architecture with an enhanced instruction set and a allowing trinary operations (that is, A + B = C) to be 24-bit instruction word with a variable length opcode executed in a single cycle. field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program A high-speed, 17-bit x 17-bit multiplier has been included memory space. A single-cycle instruction prefetch to significantly enhance the core arithmetic capability and mechanism is used to help maintain throughput and throughput. The multiplier supports Signed, Unsigned provides predictable execution. All instructions execute and Mixed mode, 16-bit x 16-bit or 8-bit x 8-bit, integer in a single cycle, with the exception of instructions that multiplication. All multiply instructions execute in a single change the program flow, the double-word move cycle. (MOV.D) instruction and the table instructions. The 16-bit ALU has been enhanced with integer divide Overhead-free program loop constructs are supported assist hardware that supports an iterative non-restoring using the REPEAT instructions, which are interruptible divide algorithm. It operates in conjunction with the at any point. REPEAT instruction looping mechanism and a selection PIC24F devices have sixteen, 16-bit Working registers of iterative divide instructions to support 32-bit (or 16-bit), in the programmer’s model. Each of the Working divided by 16-bit, integer signed and unsigned division. registers can act as a Data, Address or Address Offset All divide operations require 19 cycles to complete but register. The 16th Working register (W15) operates as are interruptible at any cycle boundary. a Software Stack Pointer (SSP) for interrupts and calls. The PIC24F has a vectored exception scheme with up The lower 32 Kbytes of the Data Space (DS) can be to 8 sources of non-maskable traps and up to 118 inter- accessed linearly. The upper 32 Kbytes of the Data rupt sources. Each interrupt source can be assigned to Space are referred to as Extended Data Space to which one of seven priority levels. the extended data RAM, EPMP memory space or A block diagram of the CPU is shown in Figure3-1. program memory can be mapped. The Instruction Set Architecture (ISA) has been 3.1 Programmer’s Model significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibil- The programmer’s model for the PIC24F is shown in ity. All PIC18 instructions and addressing modes are Figure3-2. All registers in the programmer’s model are supported, either directly, or through simple macros. memory-mapped and can be manipulated directly by Many of the ISA enhancements have been driven by instructions. compiler efficiency needs. A description of each register is provided in Table3-1. All registers associated with the programmer’s model are memory-mapped.  2013-2015 Microchip Technology Inc. DS30010038C-page 27

PIC24FJ128GA204 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM EDS and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Data RAM 16 23 Up to 0x7FFF Program Counter Stack Loop Address Control Control Latch Logic Logic 23 16 RAGU Address Latch WAGU Program Memory/ Extended Data Space EA MUX Address Bus Data Latch ROM Latch 24 16 16 Instruction a Decode and Dat Control Instruction Reg al er Lit Control Signals to Various Blocks Hardware Multiplier 16 x 16 W Register Array Divide Support 16 16-Bit ALU 16 To Peripheral Modules TABLE 3-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register RCOUNT REPEAT Loop Counter Register CORCON CPU Control Register DISICNT Disable Interrupt Count Register DSRPAG Data Space Read Page Register DSWPAG Data Space Write Page Register DS30010038C-page 28  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address W8 Registers W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 Stack Pointer Limit SPLIM 0 Value Register 22 0 PC 0 Program Counter 7 0 Table Memory Page TBLPAG Address Register 9 0 DSRPAG Data Space Read Page Register 8 0 DSWPAG Data Space Write Page Register 15 0 REPEAT Loop Counter RCOUNT Register 15 SRH SRL 0 ———————DC2IP1L0RA N OV Z C ALU STATUS Register (SR) 15 0 ———————————— IPL3 ——— CPU Control Register (CORCON) 13 0 DISICNT Disable Interrupt Count Register Registers or bits are shadowed for PUSH.S and POP.S instructions.  2013-2015 Microchip Technology Inc. DS30010038C-page 29

PIC24FJ128GA204 FAMILY 3.2 CPU Control Registers REGISTER 3-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2) IPL1(2) IPL0(2) RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was not negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation, which affects the Z bit, has set it at some time in the past 0 = The most recent operation, which affects the Z bit, has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit (MSb) of the result occurred 0 = No carry out from the Most Significant bit of the result occurred Note 1: The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1. 2: The IPLx Status bits are concatenated with the IPL3 Status (CORCON<3>) bit to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS30010038C-page 30  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 3-2: CORCON: CPU CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 r-1 U-0 U-0 — — — — IPL3(1) r — — bit 7 bit 0 Legend: C = Clearable bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 Reserved: Read as ‘1’ bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level; see Register3-1 for bit description.  2013-2015 Microchip Technology Inc. DS30010038C-page 31

PIC24FJ128GA204 FAMILY 3.3 Arithmetic Logic Unit (ALU) 3.3.2 DIVIDER The PIC24F ALU is 16 bits wide and is capable of addi- The divide block supports 32-bit/16-bit and 16-bit/16-bit tion, subtraction, bit shifts and logic operations. Unless signed and unsigned integer divide operations with the otherwise mentioned, arithmetic operations are 2’s following data sizes: complement in nature. Depending on the operation, the 1. 32-bit signed/16-bit signed divide ALU may affect the values of the Carry (C), Zero (Z), 2. 32-bit unsigned/16-bit unsigned divide Negative (N), Overflow (OV) and Digit Carry (DC) 3. 16-bit signed/16-bit signed divide Status bits in the SR register. The C and DC Status bits 4. 16-bit unsigned/16-bit unsigned divide operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The quotient for all divide instructions ends up in W0 and the remainder in W1. The 16-bit signed and The ALU can perform 8-bit or 16-bit operations, unsigned DIV instructions can specify any W register depending on the mode of the instruction that is used. for both the 16-bit divisor (Wn), and any W register Data for the ALU operation can come from the W (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. register array, or data memory, depending on the The divide algorithm takes one cycle per bit of divisor, addressing mode of the instruction. Likewise, output so both 32-bit/16-bit and 16-bit/16-bit instructions take data from the ALU can be written to the W register array the same number of cycles to execute. or a data memory location. The PIC24F CPU incorporates hardware support for 3.3.3 MULTI-BIT SHIFT SUPPORT both multiplication and division. This includes a The PIC24F ALU supports both single bit and single- dedicated hardware multiplier and support hardware cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts for 16-bit divisor division. are implemented using a shifter block, capable of per- 3.3.1 MULTIPLIER forming up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift The ALU contains a high-speed, 17-bit x 17-bit instructions only support Register Direct Addressing for multiplier. It supports unsigned, signed or mixed sign both the operand source and result destination. operation in several multiplication modes: A full summary of instructions that use the shift • 16-bit x 16-bit signed operation is provided in Table3-2. • 16-bit x 16-bit unsigned • 16-bit signed x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit unsigned • 16-bit unsigned x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit signed • 8-bit unsigned x 8-bit unsigned TABLE 3-2: INSTRUCTIONS THAT USE THE SINGLE BIT AND MULTI-BIT SHIFT OPERATION Instruction Description ASR Arithmetic Shift Right Source register by one or more bits. SL Shift Left Source register by one or more bits. LSR Logical Shift Right Source register by one or more bits. DS30010038C-page 32  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 4.0 MEMORY ORGANIZATION from either the 23-bit Program Counter (PC) during pro- gram execution, or from table operation or Data Space As Harvard architecture devices, PIC24F micro- remapping, as described in Section4.3 “Interfacing controllers feature separate program and data memory Program and Data Memory Spaces”. spaces and buses. This architecture also allows direct User access to the program memory space is restricted access of program memory from the Data Space (DS) to the lower half of the address range (000000h to during code execution. 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to 4.1 Program Memory Space the Configuration bits and Device ID sections of the The program address memory space of the configuration memory space. PIC24FJ128GA204 family devices is 4M instructions. Memory maps for the PIC24FJ128GA204 family of The space is addressable by a 24-bit value derived devices are shown in Figure4-1. FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA204 FAMILY DEVICES PIC24FJ64GA2XX PIC24F128GA2XX 000000h GOTO Instruction GOTO Instruction 000002h Reset Address Reset Address 000004h Interrupt Vector Table Interrupt Vector Table 0000FEh Reserved Reserved 000100h 000104h Alternate Vector Table Alternate Vector Table 0001FEh 000200h User Flash Program Memory (22K instructions) User Flash Program Memory Flash Config Words (44K instructions) 00ABFEh 00AC00h e c a p 0157F7h S ory Flash Config Words 0157F8h m 0157FEh Me 015800h er s U Unimplemented Read ‘0’ Unimplemented Read ‘0’ 7FFFFEh 800000h Reserved Reserved e c a p S y F7FFFEh mor F80000h Me Device Config Registers Device Config Registers F8000Eh n F80010h o ati ur g Confi Reserved Reserved FEFFFEh FF0000h DEVID (2) DEVID (2) FFFFFEh Note: Memory areas are not shown to scale.  2013-2015 Microchip Technology Inc. DS30010038C-page 33

PIC24FJ128GA204 FAMILY 4.1.1 PROGRAM MEMORY 4.1.3 FLASH CONFIGURATION WORDS ORGANIZATION In PIC24FJ128GA204 family devices, the top four words The program memory space is organized in word- of on-chip program memory are reserved for configura- addressable blocks. Although it is treated as 24 bits tion information. On device Reset, the configuration wide, it is more appropriate to think of each address of information is copied into the appropriate Configuration the program memory as a lower and upper word, with register. The addresses of the Flash Configuration Word the upper byte of the upper word being unimplemented. for devices in the PIC24FJ128GA204 family are shown The lower word always has an even address, while the in Table4-1. Their location in the memory map is shown upper word has an odd address (Figure4-2). with the other memory vectors in Figure4-1. Program memory addresses are always word-aligned The Configuration Words in program memory are a on the lower word and addresses are incremented or compact format. The actual Configuration bits are decremented by two during code execution. This mapped in several different registers in the configuration arrangement also provides compatibility with data memory space. Their order in the Flash Configuration memory space addressing and makes it possible to Words does not reflect a corresponding arrangement in access data in the program memory space. the configuration space. Additional details on the device Configuration Words are provided in Section29.0 4.1.2 HARD MEMORY VECTORS “Special Features”. All PIC24F devices reserve the addresses between TABLE 4-1: FLASH CONFIGURATION 000000h and 000200h for hard-coded program execu- tion vectors. A hardware Reset vector is provided to WORDS FOR PIC24FJ128GA204 redirect code execution from the default value of the FAMILY DEVICES PC on device Reset to the actual start of code. A GOTO Program instruction is programmed by the user at 000000h with Configuration Word Device Memory the actual address for the start of code at 000002h. Addresses (Words) PIC24F devices also have two Interrupt Vector Tables, PIC24FJ64GA2XX 22,016 00ABF8h:00ABFEh (IVTs), located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the PIC24FJ128GA2XX 44,032 0157F8h:0157FEh many device interrupt sources to be handled by sepa- rate ISRs. A more detailed discussion of the Interrupt Vector Tables is provided in Section8.1 “Interrupt Vector Table”. FIGURE 4-2: PROGRAM MEMORY ORGANIZATION msw most significant word least significant word PC Address Address (lsw Address) 23 16 8 0 0x000001 00000000 0x000000 0x000003 00000000 0x000002 0x000005 00000000 0x000004 0x000007 00000000 0x000006 Program Memory Instruction Width ‘Phantom’ Byte (read as ‘0’) DS30010038C-page 34  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 4.2 Data Memory Space The upper half of data memory address space (8000h to FFFFh) is used as a window into the Extended Data Note: This data sheet summarizes the features of Space (EDS). This allows the microcontroller to directly this group of PIC24F devices. It is not access a greater range of data beyond the standard intended to be a comprehensive reference 16-bit address range. EDS is discussed in detail in source. For more information, refer to Section4.2.5 “Extended Data Space (EDS)”. the “dsPIC33/PIC24 Family Reference The lower half of DS is compatible with previous PIC24F Manual”, “Data Memory with Extended microcontrollers without EDS. All PIC24FJ128GA204 Data Space (EDS)” (DS39733). The family devices implement 8 Kbytes of data RAM in the information in this data sheet supersedes lower half of DS, from 0800h to 27FFh. the information in the FRM. 4.2.1 DATA SPACE WIDTH The PIC24F core has a 16-bit wide data memory space, addressable as a single linear range. The Data The data memory space is organized in byte- Space (DS) is accessed using two Address Generation addressable, 16-bit wide blocks. Data is aligned in data Units (AGUs), one each for read and write operations. memory and registers as 16-bit words, but all Data The Data Space memory map is shown in Figure4-3. Space Effective Addresses (EAs) resolve to bytes. The Least Significant Bytes (LSBs) of each word have even The 16-bit wide data addresses in the data memory addresses, while the Most Significant Bytes (MSBs) space point to bytes within the Data Space. This gives have odd addresses. a DS address range of 64 Kbytes or 32K words. The lower half (0000h to 7FFFh) is used for implemented (on-chip) memory addresses. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA204 FAMILY DEVICES MSB LSB Address MSB LSB Address 0001h SFR Space 0000h SFR 07FFh 07FEh Space Near 0801h 0800h Data Space 1FFFh 1FFEh 8 Kbytes Data RAM 2001h 2000h Lower 32 Kbytes 27FFh 27FEh EDS Page 0x1 Data Space 2801h 2800h (32 Kbytes) Unimplemented EDS Page 0x2 (32 Kbytes) 7FFFh 7FFEh EPMP Memory Space 8001h 8000h EDS Page 0x3 EDS Page 0x4 EDS Window Upper 32 Kbytes Data Space EDS Page 0x1FF EDS Page 0x200 Program Space Visibility Area to Access Lower Word of Program Memory EDS Page 0x2FF FFFFh FFFEh EDS Page 0x300 Program Space Visibility Area to Access Upper Word of Program Memory EDS Page 0x3FF Note: Memory areas not shown to scale.  2013-2015 Microchip Technology Inc. DS30010038C-page 35

PIC24FJ128GA204 FAMILY 4.2.2 DATA MEMORY ORGANIZATION A Sign-Extend (SE) instruction is provided to allow AND ALIGNMENT users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users To maintain backward compatibility with PIC® MCUs can clear the MSB of any W register by executing a and improve Data Space memory usage efficiency, the Zero-Extend (ZE) instruction on the appropriate PIC24F instruction set supports both word and byte address. operations. As a consequence of byte accessibility, all Effective Address (EA) calculations are internally Although most instructions are capable of operating on scaled to step through word-aligned memory. For word or byte data sizes, it should be noted that some example, the core recognizes that Post-Modified Reg- instructions operate only on words. ister Indirect Addressing mode [Ws++] will result in a 4.2.3 NEAR DATA SPACE value of Ws + 1 for byte operations and Ws + 2 for word operations. The 8-Kbyte area between 0000h and 1FFFh is referred to as the Near Data Space. Locations in this Data byte reads will read the complete word, which space are directly addressable via a 13-bit absolute contains the byte, using the LSB of any EA to deter- address field within all memory direct instructions. The mine which byte to select. The selected byte is placed remainder of the Data Space is addressable indirectly. onto the LSB of the data path. That is, data memory Additionally, the whole Data Space is addressable and registers are organized as two parallel, byte-wide entities with shared (word) address decode but using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. separate write lines. Data byte writes only write to the corresponding side of the array or register which 4.2.4 SPECIAL FUNCTION REGISTER matches the byte address. (SFR) SPACE All word accesses must be aligned to an even address. The first 2 Kbytes of the Near Data Space, from 0000h Misaligned word data fetches are not supported, so to 07FFh, are primarily occupied with Special Function care must be taken when mixing byte and word Registers (SFRs). These are used by the PIC24F core operations or translating from 8-bit MCU code. If a and peripheral modules for controlling the operation of misaligned read or write is attempted, an address error the device. trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on SFRs are distributed among the modules that they con- a write, the instruction will be executed but the write will trol and are generally grouped together by the module. not occur. In either case, a trap is then executed, allow- Much of the SFR space contains unused addresses; ing the system and/or user to examine the machine these are read as ‘0’. A diagram of the SFR space, state prior to execution of the address Fault. showing where the SFRs are actually implemented, is shown in Table4-2. Each implemented area indicates a All byte loads into any W register are loaded into the 32-byte region where at least one address is imple- LSB. The Most Significant Byte (MSB) is not modified. mented as an SFR. A complete list of implemented SFRs, including their addresses, is shown in Tables4-3 through4-32. TABLE 4-2: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 xx40 xx60 xx80 xxA0 xxC0 xxE0 000h Core ICN Interrupts 100h System NVM/RTCC PMP CRC PMD I/O Crypto 200h A/D/CTMU CMP TMR OC IC I2C™/DSM 300h SPI PPS 400h — DMA 500h UART — 600h — 700h — Legend: — = No implemented SFRs in this block DS30010038C-page 36  2013-2015 Microchip Technology Inc.

 TABLE 4-3: CPU CORE REGISTERS MAP 2 0 1 3 File All -2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 5 M WREG0 0000 Working Register 0 0000 ic WREG1 0002 Working Register 1 0000 ro ch WREG2 0004 Working Register 2 0000 ip T WREG3 0006 Working Register 3 0000 ec WREG4 0008 Working Register 4 0000 h no WREG5 000A Working Register 5 0000 lo g WREG6 000C Working Register 6 0000 y In WREG7 000E Working Register 7 0000 c . WREG8 0010 Working Register 8 0000 WREG9 0012 Working Register 9 0000 WREG10 0014 Working Register 10 0000 WREG11 0016 Working Register 11 0000 WREG12 0018 Working Register 12 0000 P WREG13 001A Working Register 13 0000 I C WREG14 001C Working Register 14 0000 WREG15 001E Working Register 15 0800 2 SPLIM 0020 Stack Pointer Limit Value Register xxxx 4 PCL 002E Program Counter Low Word Register 0000 F PCH 0030 — — — — — — — — Program Counter High Word Register 0000 J DSRPAG 0032 — — — — — — Extended Data Space Read Page Address Register 0001 1 DSWPAG 0034 — — — — — — — Extended Data Space Write Page Address Register 0001 2 RCOUNT 0036 REPEAT Loop Counter Register xxxx 8 SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000 G CORCON 0044 — — — — — — — — — — — — IPL3 r — — 0004 A DISICNT 0052 — — Disable Interrupts Counter Register xxxx TBLPAG 0054 — — — — — — — — Table Memory Page Address Register 0000 2 Legend: — = unimplemented, read as ‘0’; r = reserved, do not modify; x = unknown value on Reset. Reset values are shown in hexadecimal. 0 4 DS F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 3 Y 7

DS TABLE 4-4: ICN REGISTER MAP P 3 0 I 0 File All C 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 0 3 2 8C CNPD1 0056 CN15PDE CN14PDE CN13PDE CN12PDE CN11PDE CN10PDE(1) CN9PDE(1) CN8PDE(1) CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE 0000 4 -pag CNPD2 0058 — CN30PDE CN29PDE CN28PDE(1) CN27PDE CN26PDE(1) CN25PDE(1) CN24PDE CN23PDE CN22PDE CN21PDE CN20PDE(1) CN19PDE(1) CN18PDE(1) CN17PDE(1) CN16PDE 0000 F e CNPD3 005A — — — — — — — — — — — CN36PDE(1) CN35PDE(1) CN34PDE(1) CN33PDE(1) — 0000 3 J 8 CNEN1 0062 CN15IE CN14IE CN13IE CN12IE CN11IE CN10IE(1) CN9IE(1) CN8IE(1) CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000 1 CNEN2 0064 — CN30IE CN29IE CN28IE(1) CN27IE CN26IE(1) CN25IE(1) CN24IE CN23IE CN22IE CN21IE CN20IE(1) CN19IE(1) CN18IE(1) CN17IE(1) CN16IE 0000 2 CNEN3 0066 — — — — — — — — — — — CN36IE(1) CN35IE(1) CN34IE(1) CN33IE(1) — 0000 8 CNPU1 006E CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 G CNPU2 0070 — CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE 0000 CNPU3 0072 — — — — — — — — — — — CN36PUE(1) CN35PUE(1) CN34PUE(1) CN33PUE(1) — 0000 A Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 Note 1: These bits are unimplemented in 28-pin devices, read as ‘0’. 0 4 F A M I L Y  2 0 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP 2 0 1 3 File All -2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 5 M INTCON1 0080 NSTDIS — — — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — 0000 ic INTCON2 0082 ALTIVT DISI — — — — — — — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 ro c IFS0 0084 — DMA1IF AD1IF U1TXIF U1RXIF SPI1TXIF SPI1IF T3IF T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF 0000 h ip T IFS1 0086 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF 0000 ec IFS2 0088 — DMA4IF PMPIF — — OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF DMA3IF CRYROLLIF CRYFREEIF SPI2TXIF SPI2IF 0000 h no IFS3 008A — RTCIF DMA5IF SPI3RXIF SPI2RXIF SPI1RXIF — KEYSTRIF CRYDNIF INT4IF INT3IF — — MI2C2IF SI2C2IF — 0000 log IFS4 008C — — CTMUIF — — — — HLVDIF — — — — CRCIF U2ERIF U1ERIF — 0000 y In IFS5 008E — — — — SPI3TXIF SPI3IF U4TXIF U4RXIF U4ERIF — I2C2BCIF I2C1BCIF U3TXIF U3RXIF U3ERIF — 0000 c . IFS6 0090 — — — — — FSTIF — — — — — — — — — — 0000 IFS7 0092 — — — — — — — — — — JTAGIF — — — — — 0000 IEC0 0094 — DMA1IE AD1IE U1TXIE U1RXIE SPI1TXIE SPI1IE T3IE T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE 0000 IEC1 0096 U2TXIE U2RXIE INT2IE T5IE T4IE OC4IE OC3IE DMA2IE — — — INT1IE CNIE CMIE MI2C1IE SI2C1IE 0000 IEC2 0098 — DMA4IE PMPIE — — OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE DMA3IE CRYROLLIE CRYFREEIE SPI2TXIE SPI2IE 0000 P IEC3 009A — RTCIE DMA5IE SPI3RXIE SPI2RXIE SPI1RXIE — KEYSTRIE CRYDNIE INT4IE INT3IE — — MI2C2IE SI2C2IE — 0000 I C IEC4 009C — — CTMUIE — — — — HLVDIE — — — — CRCIE U2ERIE U1ERIE — 0000 IEC5 009E — — — — SPI3TXIE SPI3IE U4TXIE U4RXIE U4ERIE — I2C2BCIE I2C1BCIE U3TXIE U3RXIE U3ERIE — 0000 2 IEC6 00A0 — — — — — FSTIE — — — — — — — — — — 0000 4 IEC7 00A2 — — — — — — — — — — JTAGIE — — — — — 0000 F IPC0 00A4 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 4444 J IPC1 00A6 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 4444 1 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1TXIP2 SPI1TXIP1 SPI1TXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 — T3IP2 T3IP1 T3IP0 4444 2 IPC3 00AA — — — — — DMA1IP2 DMA1IP1 DMA1IP0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 0444 8 IPC4 00AC — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 4444 G IPC5 00AE — — — — — — — — — — — — — INT1IP<2:0> 0004 A IPC6 00B0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 4444 IPC7 00B2 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 4444 2 IPC8 00B4 — CRYROLLIP2 CRYROLLIP1 CRYROLLIP0 — CRYFREEIP2 CRYFREEIP1 CRYFREEIP0 — SPI2TXIP2 SPI2TXIP1 SPI2TXIP0 — SPI2IP2 SPI2IP1 SPI2IP0 4444 0 IPC9 00B6 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 4444 4 DS IPC10 00B8 — — — — — OC6IP2 OC6IP1 OC6IP0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 0444 F 3 IPC11 00BA — — — — — DMA4IP2 DMA4IP1 DMA4IP0 — PMPIP2 PMPIP1 PMPIP0 — — — — 0440 0 A 01 IPC12 00BC — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — 0440 0 0 IPC13 00BE — CRYDNIP2 CRYDNIP1 CRYDNIP0 — INT4IP2 INT4IP1 INT4IP0 — INT3IP2 INT3IP1 INT3IP0 — — — — 4440 M 3 8C IPC14 00CO — SPI2RXIP2 SPI2RXIP1 SPI2RXIP0 — SPI1RXIP2 SPI1RXIP1 SPI1RXIP0 — — — — — KEYSTRIP2 KEYSTRIP1 KEYSTRIP0 4404 -pa IPC15 00C2 — — — — — RTCIP2 RTCIP1 RTCIP0 — DMA5IP2 DMA5IP1 DMA5IP0 — SPI3RXIP2 SPI3RXIP1 SPI3RXIP0 0444 IL g e 3 Legend: — = unimplemented, read as ‘0’; r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal. Y 9

D TABLE 4-5: INTERRUPT CONTROLLER REGISTER MAP (CONTINUED) P S 3 0 I 0 File All C 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 0 3 2 8C IPC16 00C4 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — 4440 4 -p IPC18 00C8 — — — — — — — — — — — — — HLVDIP<2:0> 0004 ag F e IPC19 00CA — — — — — — — — — CTMUIP<2:0> — — — — 0040 4 J 0 IPC20 00CC — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — 4440 1 IPC21 00CE — U4ERIP2 U4ERIP1 U4ERIP0 — — — — — I2C2BCIP2 I2C2BCIP1 I2C2BCIP0 — I2C1BCIP2 I2C1BCIP1 I2C1BCIP0 4044 2 IPC22 00D0 — SPI3TXIP2 SPI3TXIP1 SPI3TXIP0 — SPI3IP2 SPI3IP1 SPI3IP0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 4444 8 IPC26 00D8 — — — — — FSTIP<2:0> — — — — — — — — 0400 G IPC29 00DE — — — — — — — — — JTAGIP<2:0> — — — — 0040 INTTREG 00E0 CPUIRQ r VHOLD — ILR3 ILR2 ILR1 ILR0 VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 0000 A Legend: — = unimplemented, read as ‘0’; r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal. 2 0 4 F A M I L Y  2 0 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 2 TABLE 4-6: TIMER REGISTER MAP 0 1 3-2 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All 0 Name Resets 1 5 M TMR1 024C Timer1 Register 0000 icro PR1 024E Timer1 Period Register FFFF c h T1CON 0250 TON — TSIDL — — — TECS1 TECS0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — 0000 ip T TMR2 0252 Timer2 Register 0000 e ch TMR3HLD 0254 Timer3 Holding Register (for 32-bit timer operations only) 0000 n o TMR3 0256 Timer3 Register 0000 lo gy PR2 0258 Timer2 Period Register FFFF Inc PR3 025A Timer3 Period Register FFFF . T2CON 025C TON — TSIDL — — — TECS1 TECS0 — TGATE TCKPS1 TCKPS0 T32 — TCS — 0000 T3CON 025E TON — TSIDL — — — TECS1 TECS0 — TGATE TCKPS1 TCKPS0 — — TCS — 0000 TMR4 0260 Timer4 Register 0000 TMR5HLD 0262 Timer5 Holding Register (for 32-bit operations only) 0000 P TMR5 0264 Timer5 Register 0000 PR4 0266 Timer4 Period Register FFFF IC PR5 0268 Timer5 Period Register FFFF 2 T4CON 026A TON — TSIDL — — — TECS1 TECS0 — TGATE TCKPS1 TCKPS0 T45 — TCS — 0000 4 T5CON 026C TON — TSIDL — — — TECS1 TECS0 — TGATE TCKPS1 TCKPS0 — — TCS — 0000 F Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. J 1 2 8 G A 2 0 4 DS F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 4 Y 1

D P S TABLE 4-7: INPUT CAPTURE REGISTER MAP 3 0 I 0 C 1 File All 0 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 3 2 8 C IC1CON1 02AA — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 4 -p ag IC1CON2 02AC — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D F e 4 IC1BUF 02AE Input Capture 1 Buffer Register 0000 J 2 IC1TMR 02B0 Timer Value 1 Register xxxx 1 IC2CON1 02B2 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 2 IC2CON2 02B4 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 8 IC2BUF 02B6 Input Capture 2 Buffer Register 0000 G IC2TMR 02B8 Timer Value 2 Register xxxx A IC3CON1 02BA — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC3CON2 02BC — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D 2 IC3BUF 02BE Input Capture 3 Buffer Register 0000 0 IC3TMR 02C0 Timer Value 3 Register xxxx 4 IC4CON1 02C2 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 F IC4CON2 02C4 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D A IC4BUF 02C6 Input Capture 4 Buffer Register 0000 IC4TMR 02C8 Timer Value 4 Register xxxx M IC5CON1 02CA — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 I IC5CON2 02CC — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D L IC5BUF 02CE Input Capture 5 Buffer Register 0000 Y IC5TMR 02D0 Timer Value 5 Register xxxx IC6CON1 02D2 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 0000 IC6CON2 02D4 — — — — — — — IC32 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000D IC6BUF 02D6 Input Capture 6 Buffer Register 0000  IC6TMR 02D8 Timer Value 6 Register xxxx 20 Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-8: OUTPUT COMPARE REGISTER MAP 2 0 1 3 File All -2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 5 M OC1CON1 026E — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 ic OC1CON2 0270 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C ro ch OC1RS 0272 Output Compare 1 Secondary Register 0000 ip T OC1R 0274 Output Compare 1 Register 0000 ec OC1TMR 0276 Timer Value 1 Register xxxx h no OC2CON1 0278 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 lo g OC2CON2 027A FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C y In OC2RS 027C Output Compare 2 Secondary Register 0000 c . OC2R 027E Output Compare 2 Register 0000 OC2TMR 0280 Timer Value 2 Register xxxx OC3CON1 0282 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 OC3CON2 0284 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C OC3RS 0286 Output Compare 3 Secondary Register 0000 P OC3R 0288 Output Compare 3 Register 0000 I C OC3TMR 028A Timer Value 3 Register xxxx OC4CON1 028C — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 OC4CON2 028E FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 4 OC4RS 0290 Output Compare 4 Secondary Register 0000 F OC4R 0292 Output Compare 4 Register 0000 J OC4TMR 0294 Timer Value 4 Register xxxx 1 OC5CON1 0296 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT1 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 OC5CON2 0298 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 8 OC5RS 029A Output Compare 5 Secondary Register 0000 G OC5R 029C Output Compare 5 Register 0000 A OC5TMR 029E Timer Value 5 Register xxxx OC6CON1 02A0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2 ENFLT1 ENFLT0 OCFLT2 OCFLT1 OCFLT0 TRIGMODE OCM2 OCM1 OCM0 0000 2 OC6CON2 02A2 FLTMD FLTOUT FLTTRIEN OCINV — DCB1 DCB0 OC32 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 000C 0 OC6RS 02A4 Output Compare 6 Secondary Register 0000 4 DS OC6R 02A6 Output Compare 6 Register 0000 F 3 OC6TMR 02A8 Timer Value 6 Register xxxx 0 A 01 Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. 0 0 M 3 8 C -pa IL g e 4 Y 3

DS TABLE 4-9: I2C™ REGISTER MAP P 3 0 I 0100 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts C 3 2 8 C I2C1RCV 02DA — — — — — — — — I2C1 Receive Register 0000 4 -p ag I2C1TRN 02DC — — — — — — — — I2C1 Transmit Register 00FF F e 4 I2C1BRG 02DE — — — — Baud Rate Generator Register 0000 J 4 I2C1CONL 02E0 I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 1 I2C1CONH 02E2 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 2 I2C1STAT 02E4 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 8 I2C1ADD 02E6 — — — — — — I2C1 Address Register 0000 G I2C1MSK 02E8 — — — — — — I2C1 Address Mask Register 0000 I2C2RCV 02EA — — — — — — — — I2C2 Receive Register 0000 A I2C2TRN 02EC — — — — — — — — I2C2 Transmit Register 00FF 2 I2C2BRG 02EE — — — — Baud Rate Generator Register 0000 0 I2C2CONL 02F0 I2CEN — I2CSIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000 4 I2C2CONH 02F2 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 F I2C2STAT 02F4 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 A I2C2ADD 02F6 — — — — — — I2C2 Address Register 0000 I2C2MSK 02F8 — — — — — — I2C2 Address Mask Register 0000 M Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. I L Y  2 0 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 T ABLE 4-10: UART REGISTER MAP 2 0 1 3 File All -2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 5 M U1MODE 0500 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 ic U1STA 0502 UTXISEL1 UTXINV UTXISEL0 URXEN UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 ro c U1TXREG 0504 LAST — — — — — — U1TXREG<8:0> xxxx h ip T U1RXREG 0506 — — — — — — — U1RXREG<8:0> 0000 ec U1BRG 0508 U1BRG<15:0> 0000 h no U1ADMD 050A ADMMASK<7:0> ADMADDR<7:0> 0000 log U1SCCON 050C — — — — — — — — — — TXRPT1 TXRPT0 CONV T0PD PTRCL SCEN 0000 y In U1SCINT 050E — — RXRPTIF TXRPTIF — — WTCIF GTCIF — PARIE RXRPTIE TXRPTIE — — WTCIE GTCIE 0000 c . U1GTC 0510 — — — — — — — GTC<8:0> 0000 U1WTCL 0512 WTC<15:0> 0000 U1WTCH 0514 — — — — — — — — WTC<23:16> 0000 U2MODE 0516 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 U2STA 0518 UTXISEL1 UTXINV UTXISEL0 URXEN UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 P U2TXREG 051A LAST — — — — — — U2TXREG<8:0> xxxx I C U2RXREG 051C — — — — — — — U2RXREG<8:0> 0000 U2BRG 051E U2BRG<15:0> 0000 2 U2ADMD 0520 ADMMASK<7:0> ADMADDR<7:0> 0000 4 U2SCCON 0522 — — — — — — — — — — TXRPT1 TXRPT0 CONV T0PD PTRCL SCEN 0000 F U2SCINT 0524 — — RXRPTIF TXRPTIF — — WTCIF GTCIF — PARIE RXRPTIE TXROTIE — — WTCIE GTCIE 0000 J U2GTC 0526 — — — — — — — GTC<8:0> 0000 1 U2WTCL 0528 WTC<15:0> 0000 2 U2WTCH 052A — — — — — — — — WTC<23:16> 0000 8 U3MODE 052C UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 G U3STA 052E UTXISEL1 UTXINV UTXISEL0 URXEN UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 A U3TXREG 0530 LAST — — — — — — U3TXREG<8:0> xxxx U3RXREG 0532 — — — — — — — U3RXREG<8:0> 0000 2 U3BRG 0534 U3BRG<15:0> 0000 0 U3ADMD 0536 ADMMASK<7:0> ADMADDR<7:0> 0000 4 DS U4MODE 0538 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000 F 3 U4STA 053A UTXISEL1 UTXINV UTXISEL0 URXEN UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110 0 A 01 U4TXREG 053C LAST — — — — — — U4TXREG<8:0> xxxx 0 0 U4RXREG 053E — — — — — — — U4RXREG<8:0> 0000 M 3 8C U4BRG 0540 U4BRG<15:0> 0000 -pa U4ADMD 0542 ADMMASK<7:0> ADMADDR<7:0> 0000 IL g e 4 Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. Y 5

D TABLE 4-11: SPI1 REGISTER MAP P S 3 0 File All I 0 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 C 1 Name Resets 0 0 38 SPI1CON1L 0300 SPIEN — SPISIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI DISSCK MCLKEN SPIFE ENHBUF 0000 2 C-p SPI1CON1H 0302 AUDEN SPISGNEXT IGNROV IGNTUR AUDMONO URDTEN AUDMOD1 AUDMOD0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT2 FRMCNT1 FRMCNT0 0000 4 ag SPI1CON2L 0304 — — — — — — — — — — — WLENGTH<4:0> 0000 F e 4 SPI1STATL 0308 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0028 J 6 SPI1STATH 030A — — RXELM5 RXELM4 RXELM3 RXELM2 RXELM1 RXELM0 — — TXELM5 TXELM4 TXELM3 TXELM2 TXELM1 TXELM0 0000 1 SPI1BUFL 030C SPI1BUFL<15:0> 0000 2 SPI1BUFH 030E SPI1BUFH<31:16> 0000 8 SPI1BRGL 0310 — — — SPI1BRG<12:0> 0000 G SPI1IMSKL 0314 — — — FRMERREN BUSYEN — — SPITUREN SRMTEN SPIROVEN SPIRBEN — SPITBEN — SPITBFEN SPIRBFEN 0000 SPI1IMSKH 0316 RXWIEN — RXMSK5 RXMSK4 RXMSK3 RXMSK2 RXMSK1 RXMSK0 TXWIEN — TXMSK5 TXMSK4 TXMSK3 TXMSK2 TXMSK1 TXMSK0 0000 A SPI1URDTL 0318 SPI1URDTL<15:0> 0000 2 SPI1URDTH 031A SPI1URDTH<31:16> 0000 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 4 F TABLE 4-12: SPI2 REGISTER MAP A File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets M SPI2CON1L 031C SPIEN — SPISIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI DISSCK MCLKEN SPIFE ENHBUF 0000 I SPI2CON1H 031E AUDEN SPISGNEXT IGNROV IGNTUR AUDMONO URDTEN AUDMOD1 AUDMOD0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT2 FRMCNT1 FRMCNT0 0000 L SPI2CON2L 0320 — — — — — — — — — — — WLENGTH<4:0> 0000 Y SPI2STATL 0324 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0028 SPI2STATH 0326 — — RXELM5 RXELM4 RXELM3 RXELM2 RXELM1 RXELM0 — — TXELM5 TXELM4 TXELM3 TXELM2 TXELM1 TXELM0 0000 SPI2BUFL 0328 SPI2BUFL<15:0> 0000 SPI2BUFH 032A SPI2BUFH<31:16> 0000  SPI2BRGL 032C — — — SPI2BRG<12:0> 0000 2 SPI2IMSKL 0330 — — — FRMERREN BUSYEN — — SPITUREN SRMTEN SPIROVEN SPIRBEN — SPITBEN — SPITBFEN SPIRBFEN 0000 0 1 3 SPI2IMSKH 0332 RXWIEN — RXMSK5 RXMSK4 RXMSK3 RXMSK2 RXMSK1 RXMSK0 TXWIEN — TXMSK5 TXMSK4 TXMSK3 TXMSK2 TXMSK1 TXMSK0 0000 -2 0 SPI2URDTL 0334 SPI2URDTL<15:0> 0000 1 5 M SPI2URDTH 0336 SPI2URDTH<31:16> 0000 ic Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. ro c h ip T e c h n o lo g y In c .

 TABLE 4-13: SPI3 REGISTER MAP 2 013-2 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslelts 0 1 SPI3CON1L 0338 SPIEN — SPISIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN DISSDI DISSCK MCLKEN SPIFE ENHBUF 0000 5 M SPI3CON1H 033A AUDEN SPISGNEXT IGNROV IGNTUR AUDMONO URDTEN AUDMOD1 AUDMOD0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT2 FRMCNT1 FRMCNT0 0000 ic ro SPI3CON2L 033C — — — — — — — — — — — WLENGTH<4:0> 0000 c h SPI3STATL 0340 — — — FRMERR SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0028 ip T SPI3STATH 0342 — — RXELM5 RXELM4 RXELM3 RXELM2 RXELM1 RXELM0 — — TXELM5 TXELM4 TXELM3 TXELM2 TXELM1 TXELM0 0000 e ch SPI3BUFL 0344 SPI3BUFL<15:0> 0000 n o SPI3BUFH 0346 SPI3BUFH<31:16> 0000 lo gy SPI3BRGL 0348 — — — SPI3BRG<12:0> 0000 In SPI3IMSKL 034C — — — FRMERREN BUSYEN — — SPITUREN SRMTEN SPIROVEN SPIRBEN — SPITBEN — SPITBFEN SPIRBFEN 0000 c . SPI3IMSKH 034E RXWIEN — RXMSK5 RXMSK4 RXMSK3 RXMSK2 RXMSK1 RXMSK0 TXWIEN — TXMSK5 TXMSK4 TXMSK3 TXMSK2 TXMSK1 TXMSK0 0000 SPI3URDTL 0350 SPI3URDTL<15:0> 0000 SPI3URDTH 0352 SPI3URDTH<31:16> 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C 2 4 F J 1 2 8 G A 2 0 4 DS F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 4 Y 7

D TABLE 4-14: PORTA REGISTER MAP P S 3 0 I 01 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10(1,3) Bit 9(1,3) Bit 8(1,3) Bit 7(1,3) Bit 6 Bit 5 Bit 4 Bit 3 Bit2 Bit 1 Bit 0 All C 0 Name Resets 0 3 2 8 TRISA 0180 — — — — — TRISA<10:7> — — — TRISA<3:0> 078F(2) C 4 -p PORTA 0182 — — — — — RA<10:7> — — RA<4:0> xxxx age LATA 0184 — — — — — LATA<10:7> — — — LATA<3:0> xxxx F 48 ODCA 0186 — — — — — ODA<10:7> — — — ODA<3:0> 0000 J 1 Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. Reset values shown are for 44-pin devices. Note 1: These bits are not available on 28-pin devices; read as ‘0’. 2 2: Reset value for the 44-pin devices is shown; 001F for the 28-pin devices. 8 3: The RA<10:7> bits are multiplexed with the JTAG pins. In order to use these pins as I/Os, JTAG should be disabled in the Configuration Fuse bits. G A TABLE 4-15: PORTB REGISTER MAP 2 File All Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 4 TRISB 018A TRISB<15:5> — TRISB<3:0> FFEF PORTB 018C RB<15:0> xxxx F LATB 018E LATB<15:5> — LATB<3:0> xxxx A ODCB 0190 ODB<15:5> — ODB<3:0> 0000 M Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. I L TABLE 4-16: PORTC REGISTER MAP Y File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 8(1) Bit 7(1) Bit 6(1) Bit 5(1) Bit 4(1) Bit 3(1) Bit 2(1) Bit 1(1) Bit 0(1) All Name Resets TRISC 0194 — — — — — — TRISC<9:0> 03FF(2) PORTC 0196 — — — — — — RC<9:0> xxxx(2)  LATC 0198 — — — — — — LATC<9:0> xxxx(2) 20 ODCC 019A — — — — — — ODC<9:0> 0000(2) 1 3-2 Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. 0 Note 1: These bits are not available on 28-pin devices; read as ‘0’. 1 5 2: The Reset value for 44-pin devices is shown. M ic ro c TABLE 4-17: PAD CONFIGURATION REGISTER MAP (PADCFG1) h ip T File All e Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 c Name Resets h n olo PADCFG1 01A0 — — — — — — — — — — — — — — — PMPTTL 0000 g y Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. In c .

 TABLE 4-18: A/D CONVERTER REGISTER MAP 2 0 1 3 File All -2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 1 5 M ADC1BUF0 0200 A/D Data Buffer 0/Threshold for Channel 0 xxxx ic ADC1BUF1 0202 A/D Data Buffer 1/Threshold for Channel 1 xxxx ro ch ADC1BUF2 0204 A/D Data Buffer 2/Threshold for Channel 2 xxxx ip T ADC1BUF3 0206 A/D Data Buffer 3/Threshold for Channel 3 xxxx ec ADC1BUF4 0208 A/D Data Buffer 4/Threshold for Channel 4 xxxx h no ADC1BUF5 020A A/D Data Buffer 5/Threshold for Channel 5 xxxx lo g ADC1BUF6 020C A/D Data Buffer 6/Threshold for Channel 6 xxxx y In ADC1BUF7 020E A/D Data Buffer 7/Threshold for Channel 7 xxxx c . ADC1BUF8 0210 A/D Data Buffer 8/Threshold for Channel 8/Threshold for Channel 0 in Windowed Compare mode xxxx ADC1BUF9 0212 A/D Data Buffer 9/Threshold for Channel 9/Threshold for Channel 1 in Windowed Compare mode xxxx ADC1BUF10 0214 A/D Data Buffer 10/Threshold for Channel 10/Threshold for Channel 2 in Windowed Compare mode(1) xxxx ADC1BUF11 0216 A/D Data Buffer 11/Threshold for Channel 11/Threshold for Channel 3 in Windowed Compare mode(1) xxxx ADC1BUF12 0218 A/D Data Buffer 12/Threshold for Channel 12/Threshold for Channel 4 in Windowed Compare mode(1) xxxx P ADC1BUF13 021A A/D Data Buffer 13 xxxx I C ADC1BUF14 021C A/D Data Buffer 14 xxxx ADC1BUF15 021E A/D Data Buffer 15 xxxx 2 AD1CON1 0220 ADON — ADSIDL DMABM DMAEN MODE12 FORM1 FORM0 SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE 0000 4 AD1CON2 0222 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — BUFS SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS 0000 F AD1CON3 0224 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 0000 J AD1CHS 0228 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 0000 1 AD1CSSH 022A CSS<31:27> — — — — — — — — — — — 0000 2 AD1CSSL 022C — CSS<14:0>(1) 0000 8 AD1CON4 022E — — — — — — — — — — — — — DMABL<2:0> 0000 G AD1CON5 0230 ASEN LPEN CTMREQ BGREQ — — ASINT1 ASINT0 — — — — WM1 WM0 CM1 CM0 0000 A AD1CHITL 0234 — — — CHH<12:0>(1) 0000 AD1CTMENL 0238 — — — CTMEN<12:0>(1) 0000 2 AD1DMBUF 023A A/D Conversion Data Buffer (Extended Buffer mode) xxxx 0 Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. 4 Note 1: The CSS<12:10>, CHH<12:10> and CTMEN<12:10> bits are unimplemented in 28-pin devices, read as ‘0’. DS F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 4 Y 9

DS TABLE 4-19: CTMU REGISTER MAP P 3 0 I 0 File All C 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 0 3 2 8C CTMUCON1 023C CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG — — — — — — — — 0000 4 -pag CTMUCON2 023E EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — 0000 F e CTMUICON 0240 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — 0000 5 J 0 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1 2 TABLE 4-20: ANALOG CONFIGURATION REGISTER MAP 8 G File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets A ANCFG 019E — — — — — — — — — — — — — — VBG2EN VBGEN 0000 2 ANSA 0188 — — — — — — — — — — — — ANSA<3:0> 000F 0 ANSB 0192 ANSB<15:12> — — ANSB9 — — ANSB6 — — ANSB<3:0> F24F 4 ANSC 019C — — — — — — — — — — — — — ANSC<2:0>(1) 0007 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. F Note 1: These bits are unimplemented in 28-pin devices, read as ‘0’. A M I L Y  2 0 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-21: DMA REGISTER MAP 2 0 13-2 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts 0 1 5 DMACON 0450 DMAEN — — — — — — — — — — — — — — PRSSEL 0000 M ic DMABUF 0452 DMA Transfer Data Buffer 0000 ro c DMAL 0454 DMA High Address Limit Register 0000 h ip DMAH 0456 DMA Low Address Limit Register 0000 T ec DMACH0 0458 — — — r — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 h n DMAINT0 045A DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 o log DMASRC0 045C DMA Channel 0 Source Address Register 0000 y In DMADST0 045E DMA Channel 0 Destination Address Register 0000 c . DMACNT0 0460 DMA Channel 0 Transaction Count Register 0001 DMACH1 0462 — — — r — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 DMAINT1 0464 DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 DMASRC1 0466 DMA Channel 1 Source Address Register 0000 DMADST1 0468 DMA Channel 1 Destination Address Register 0000 P DMACNT1 046A DMA Channel 1 Transaction Count Register 0001 I C DMACH2 046C — — — r — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 DMAINT2 046E DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 2 DMASRC2 0470 DMA Channel 2 Source Address Register 0000 4 DMADST2 0472 DMA Channel 2 Destination Address Register 0000 F DMACNT2 0474 DMA Channel 2 Transaction Count Register 0001 J DMACH3 0476 — — — r — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 1 DMAINT3 0478 DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 2 DMASRC3 047A DMA Channel 3 Source Address Register 0000 8 DMADST3 047C DMA Channel 3 Destination Address Register 0000 G DMACNT3 047E DMA Channel 3 Transaction Count Register 0001 A DMACH4 0480 — — — r — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 DMAINT4 0482 DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 2 DMASRC4 0484 DMA Channel 4 Source Address Register 0000 0 DMADST4 0486 DMA Channel 4 Destination Address Register 0000 4 DMACNT4 0488 DMA Channel 4 Transaction Count Register 0001 DS3 DMACH5 048A — — — r — NULLW RELOAD CHREQ SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN 0000 F 0 A 0 DMAINT5 048C DBUFWF — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 HIGHIF LOWIF DONEIF HALFIF OVRUNIF — — HALFEN 0000 1 00 DMASRC5 048E DMA Channel 5 Source Address Register 0000 M 3 8C DMADST5 0490 DMA Channel 5 Destination Address Register 0000 -pa DMACNT5 0492 DMA Channel 5 Transaction Count Register 0001 IL g e 5 Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. Y 1

DS TABLE 4-22: ENHANCED PARALLEL MASTER/SLAVE PORT REGISTER MAP P 3 0 I 0 File All C 1 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 0 3 2 8C PMCON1 0128 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 0000 4 -pag PMCON2 012A PMPBUSY — ERROR TIMEOUT — — — — RADDR23 RADDR22 RADDR21 RADDR20 RADDR19 RADDR18 RADDR17 RADDR16 0000 F e PMCON3 012C PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE — — — — — — — — 0000 5 J 2 PMCON4 012E — PTEN14 — — — — PTEN<9:0> 0000 1 PMCS1CF 0130 CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000 2 PMCS1BS 0132 BASE<23:15> — — — BASE11 — — — 0200 8 PMCS1MD 0134 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000 G PMCS2CF 0136 CSDIS CSP CSPTEN BEP — WRSP RDSP SM ACKP PTSZ1 PTSZ0 — — — — — 0000 PMCS2BS 0138 BASE<23:15> — — — BASE11 — — — 0600 A PMCS2MD 013A ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 0000 2 PMDOUT1 013C EPMP Data Out Register 1<15:8> EPMP Data Out Register 1<7:0> xxxx 0 PMDOUT2 013E EPMP Data Out Register 2<15:8> EPMP Data Out Register 2<7:0> xxxx 4 PMDIN1 0140 EPMP Data In Register 1<15:8> EPMP Data In Register 1<7:0> xxxx PMDIN2 0142 EPMP Data In Register 2<15:8> EPMP Data In Register 2<7:0> xxxx F PMSTAT 0144 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F A Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. M I L Y  2 0 1 3 -2 0 1 5 M ic ro c h ip T e c h n o lo g y In c .

 2 TABLE 4-23: REAL-TIME CLOCK AND CALENDAR (RTCC) REGISTER MAP 0 1 3 File All -2 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 1 5 M ALRMVAL 011E Alarm Value Register Window Based on ALRMPTR<1:0> xxxx icro ALCFGRPT 0120 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 0000 ch RTCVAL 0122 RTCC Value Register Window Based on RTCPTR<1:0> xxxx ip T RCFGCAL 0124 RTCEN — RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 Note1 e c RTCPWC 0126 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1 RTCLK0 RTCOUT1 RTCOUT0 — — — — — — — — Note1 h n o Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. lo g Note 1: The status of the RCFGCAL and RTCPWC registers on POR is ‘0000’ and on other Resets, it is unchanged. y In c . TABLE 4-24: DATA SIGNAL MODULATOR (DSM) REGISTER MAP File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets MDCON 02FA MDEN — MDSIDL — — — — — — MDOE MDSLR MDOPOL — — — MDBIT 0020 P MDSRC 02FC — — — — — — — — SODIS — — — MS3 MS2 MS1 MS0 0000 I MDCAR 02FE CHODIS CHPOL CHSYNC — CH3 CH2 CH1 CH0 CLODIS CLPOL CLSYNC — CL3 CL2 CL1 CL0 0000 C Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 2 4 TABLE 4-25: COMPARATOR REGISTER MAP F J File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 1 2 CMSTAT 0242 CMIDL — — — — C3EVT C2EVT C1EVT — — — — — C3OUT C2OUT C1OUT 0000 8 CVRCON 0244 — — — — — CVREFP CVREFM1 CVREFM0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 0000 G CM1CON 0246 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 CM2CON 0248 CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 A CM3CON 024A CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 0000 2 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0 4 DS F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 5 Y 3

D P S TABLE 4-26: CRC REGISTER MAP 3 0 I 0 C 1 File All 0 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Name Resets 3 2 8 C CRCCON1 0158 CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0040 4 -p ag CRCCON2 015A — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 0000 F e 5 CRCXORL 015C X<15:1> — 0000 J 4 CRCXORH 015E X<31:16> 0000 1 CRCDATL 0160 CRC Data Input Register Low xxxx 2 CRCDATH 0162 CRC Data Input Register High xxxx 8 CRCWDATL 0164 CRC Result Register Low xxxx G CRCWDATH 0166 CRC Result Register High xxxx Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. A 2 0 TABLE 4-27: PERIPHERAL PIN SELECT REGISTER MAP 4 File Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Name Resets F RPINR0 038C — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — OCTRIG1R5 OCTRIG1R4 OCTRIG1R3 OCTRIG1R2 OCTRIG1R1 OCTRIG1R0 3F3F A RPINR1 038E — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 3F3F M RPINR2 0390 — — OCTRIG2R5 OCTRIG2R4 OCTRIG2R3 OCTRIG2R2 OCTRIG2R1 OCTRIG2R0 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 3F3F RPINR7 039A — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 3F3F I L RPINR8 039C — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 3F3F Y RPINR9 039E — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 3F3F RPINR11 03A2 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 3F3F RPINR17 03AE — — U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 — — — — — — — — 3F00 RPINR18 03B0 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 3F3F RPINR19 03B2 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 3F3F  RPINR20 03B4 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 3F3F 2 0 RPINR21 03B6 — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 3F3F 1 3 -2 RPINR22 03B8 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 3F3F 0 1 RPINR23 03BA — — TMRCKR5 TMRCKR4 TMRCKR3 TMRCKR2 TMRCKR1 TMRCKR0 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 3F3F 5 M RPINR27 03C2 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 3F3F icro RPINR28 03C4 — — SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 — — SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 3F3F ch RPINR29 03C6 — — — — — — — — — — SS3R<5:0> 003F ip T RPINR30 03C8 — — — — — — — — — — MDMIR<5:0> 003F e c RPINR31 03CA — — MDC2R5 MDC2R4 MDC2R3 MDC2R2 MDC2R1 MDC2R0 — — MDC1R5 MDC1R4 MDC1R3 MDC1R2 MDC1R1 MDC1R0 3F3F h no Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. lo g y In c .

 TABLE 4-27: PERIPHERAL PIN SELECT REGISTER MAP (CONTINUED) 2 0 1 File All 3-2 Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 0 15 RPOR0 03D6 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 0000 M RPOR1 03D8 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 0000 ic ro RPOR2 03DA — — RP5R<5:0> — — — — — — — — 0000 c hip RPOR3 03DC — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 0000 T RPOR4 03DE — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 0000 e ch RPOR5 03E0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 0000 n o RPOR6 03E2 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 0000 lo gy RPOR7 03E4 — — RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 0000 In RPOR8 03E6 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 0000 c . RPOR9 03E8 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 0000 RPOR10 03EA — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 0000 RPOR11 03EC — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 0000 RPOR12 03EE — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 0000 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. P I C TABLE 4-28: SYSTEM CONTROL (CLOCK AND RESET) REGISTER MAP 2 File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 Name Resets F RCON 0108 TRAPR IOPUWR — RETEN — DPSLP CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Note1 J OSCCON 0100 — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN Note2 1 CLKDIV 0102 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — PLLEN — — — — — 0100 2 OSCTUN 0106 STEN — STSIDL STSRC STLOCK STLPOL STOR STORPOL — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000 8 REFOCONL 0168 ROEN — ROSIDL ROOUT ROSLP — ROSWEN ROACTIVE — — — — ROSEL3 ROSEL2 ROSEL1 ROSEL0 0000 G REFOCONH 016A — RODIV<14:0> 0000 REFOTRIML 016C ROTRIM<15:7> — — — — — — — 0000 A HLVDCON 010C HLVDEN — LSIDL — — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 0000 2 RCON2 010A — — — — — — — — — — — r VDDBOR VDDPOR VBPOR VBAT Note1 0 Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. 4 Note 1: The Reset value of the RCON (or RCON2) register is dependent on the type of Reset event. For more information, refer to Section7.0 “Resets”. DS 2: The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. For more information, refer to Section9.0 “Oscillator Configuration”. F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 5 Y 5

D P S TABLE 4-29: DEEP SLEEP REGISTER MAP 3 0 I 0100 NFaimlee Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ReAslel ts C 3 2 8C DSCON 010E DSEN — — — — — — — — — — — — r DSBOR RELEASE 0000(1) 4 -pag DSWAKE 0110 — — — — — — — DSINT0 DSFLT — — DSWDT DSRTCC DSMCLR — — 0000(1) F e 5 DSGPR0 0112 Deep Sleep Semaphore Data 0 Register 0000(1) J 6 DSGPR1 0114 Deep Sleep Semaphore Data 1 Register 0000(1) 1 Legend: — = unimplemented, read as ‘0’; r = reserved. Reset values are shown in hexadecimal. 2 Note 1: These registers are only reset on a VDD POR event. 8 G TABLE 4-30: CRYPTOGRAPHIC ENGINE REGISTER MAP A File All Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Resets 2 CRYCONL 01A4 CRYON — CRYSIDL ROLLIE DONEIE FREEIE — CRYGO OPMOD3 OPMOD2 OPMOD1 OPMOD0 CPHRSEL CPHRMOD2 CPHRMOD1 CPHRMOD0 0000 0 4 CRYCONH 01A6 — CTRSIZE6 CTRSIZE5 CTRSIZE4 CTRSIZE3 CTRSIZE2 CTRSIZE1 CTRSIZE0 SKEYSEL KEYMOD1 KEYMOD0 — KEYSRC3 KEYSRC2 KEYSRC1 KEYSRC0 0000 CRYSTAT 01A8 — — — — — — — — CRYBSY TXTABSY CRYABRT ROLLOVR — MODFAIL KEYFAIL PGMFAIL 0000 F CRYOTP 01AC — — — — — — — — PGMTST OTPIE CRYREAD KEYPG3 KEYPG2 KEYPG1 KEYPG0 CRYWR 0020 A CRYTXTA 01B0 Cryptographic Text Register A (128 bits wide) xxxx M CRYKEY 01C0 Cryptographic Key Register (256 bits wide, write-only) xxxx CRYTXTB 01E0 Cryptographic Text Register B (128 bits wide) xxxx I L CRYTXTC 01F0 Cryptographic Text Register C (128 bits wide) xxxx Legend: — = unimplemented, read as ‘0’; x = unknown value on Reset. Reset values are shown in hexadecimal. Y TABLE 4-31: NVM REGISTER MAP File All  Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Resets 2 01 NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 3 -2 NVMKEY 0766 — — — — — — — — NVMKEY Register<7:0> 0000 0 1 5 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. M Note 1: The Reset value shown is for POR only. The value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. ic ro c h ip T e c h n o lo g y In c .

 TABLE 4-32: PERIPHERAL MODULE DISABLE (PMD) REGISTER MAP 2 0 1 File All 3 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 -2 Name Resets 0 1 5 PMD1 0170 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — — ADC1MD 0000 M ic PMD2 0172 — — IC6MD IC5MD IC4MD IC3MD IC2MD IC1MD — — OC6MD OC5MD OC4MD OC3MD OC2MD OC1MD 0000 roc PMD3 0174 — — — — DSMMD CMPMD RTCCMD PMPMD CRCMD — — — U3MD — I2C2MD — 0000 h ip PMD4 0176 — — — — — — — — — UPWMMD U4MD — REFOMD CTMUMD HLVDMD — 0000 T e PMD6 017A — — — — — — — — — — — — — — — SPI3MD 0000 c h n PMD7 017C — — — — — — — — — — DMA1MD DMA0MD — — — — 0000 o lo PMD8 017E — — — — — — — — — — — — — — — CRYMD 0000 g y In Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. c . P I C 2 4 F J 1 2 8 G A 2 0 4 DS F 3 0 A 0 1 0 0 M 3 8 C -pa IL g e 5 Y 7

PIC24FJ128GA204 FAMILY 4.2.5 EXTENDED DATA SPACE (EDS) The data addressing range of PIC24FJ128GA204 family devices depends on the version of the Enhanced The Extended Data Space (EDS) allows PIC24F Parallel Master Port implemented on a particular device; devices to address a much larger range of data than this is, in turn, a function of device pin count. Table4-33 would otherwise be possible with a 16-bit address lists the total memory accessible by each of the devices range. EDS includes any additional internal data in this family. For more details on accessing external memory not directly accessible by the lower 32-Kbyte memory using EPMP, refer to the “dsPIC33/PIC24 data address space and any external memory through Family Reference Manual”, “Enhanced Parallel the Enhanced Parallel Master Port (EPMP). Master Port (EPMP)” (DS39730). In addition, EDS also allows read access to the . program memory space. This feature is called Program TABLE 4-33: TOTAL ACCESSIBLE DATA Space Visibility (PSV) and is discussed in detail in MEMORY Section4.3.3 “Reading Data from Program Memory External RAM Using EDS”. Internal Family Access Using RAM Figure4-4 displays the entire EDS space. The EDS is EPMP organized as pages, called EDS pages, with one page PIC24FJXXXGA204 8K Up to 16 Mbytes equal to the size of the EDS window (32 Kbytes). A particular EDS page is selected through the Data PIC24FJXXXGA202 8K Up to 64K Space Read register (DSRPAG) or Data Space Write register (DSWPAG). For PSV, only the DSRPAG regis- Note: Accessing Page 0 in the EDS window will ter is used. The combination of the DSRPAG register generate an address error trap as Page 0 value and the 16-bit wide data address forms a 24-bit is the base data memory (data locations, Effective Address (EA). 0800h to 7FFFh, in the lower Data Space). FIGURE 4-4: EXTENDED DATA SPACE (EDS) Special 0000h Function Registers 0800h Internal Data Memory Space (up to 30 Kbytes) EDS Pages 8000h 008000h FF8000h 000000h 7F8000h 000001h 7F8001h 32-Kbyte External External Program Program Program Program EDS Memory Memory Space Space Space Space Window Access Access Access Access Access Access Using Using (Lower (Lower (Upper (Upper EPMP(1) EPMP(1) Word) Word) Word) Word) FFFEh 00FFFEh FFFFFEh 007FFEh 7FFFFEh 007FFFh 7FFFFFh DSxPAG = DSx PAG = DSRPAG = DSRPAG = DSRPAG = DSRPAG = 001h 1FFh 00h 2FFh 300h 3FFh EPMP Memory Space(1) Program Memory Note1: The range of addressable memory available is dependent on the device pin count and EPMP implementation. DS30010038C-page 58  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 4.2.5.1 Data Read from EDS Example4-1 shows how to read a byte, word and double-word from EDS. In order to read the data from the EDS space first, an Address Pointer is set up by loading the required EDS Note: All read operations from EDS space have page number into the DSRPAG register and assigning an overhead of one instruction cycle. the offset address to one of the W registers. Once the Therefore, a minimum of two instruction above assignment is done, the EDS window is enabled cycles are required to complete an EDS by setting bit 15 of the Working register assigned with read. EDS reads under the REPEAT the offset address; then, the contents of the pointed instruction; the first two accesses take EDS location can be read. three cycles and the subsequent Figure4-5 illustrates how the EDS space address is accesses take one cycle. generated for read operations. When the Most Significant bit of the EA is ‘1’ and DSRPAG<9> = 0, the lower 9 bits of DSRPAG are con- catenated to the lower 15 bits of the EA to form a 24-bit EDS space address for read operations. FIGURE 4-5: EDS ADDRESS GENERATION FOR READ OPERATIONS Select 1 Wn 9 8 0 DSRPAG Reg 9 Bits 15 Bits 24-Bit EA 0 = Extended SRAM and EPMP Wn<0> is Byte Select EXAMPLE 4-1: EDS READ CODE IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0002, w0 mov w0, DSRPAG ;page 2 is selected for read mov #0x0800, w1 ;select the location (0x800) to be read bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++], w2 ;read Low byte mov.b [w1++], w3 ;read High byte ;Read a word from the selected location mov [w1], w2 ; ;Read Double - word from the selected location mov.d [w1], w2 ;two word read, stored in w2 and w3  2013-2015 Microchip Technology Inc. DS30010038C-page 59

PIC24FJ128GA204 FAMILY 4.2.5.2 Data Write into EDS 0x8000. While developing code in assembly, care must be taken to update the Data Space Page registers when In order to write data to EDS space, such as in EDS an Address Pointer crosses the page boundary. The ‘C’ reads, an Address Pointer is set up by loading the compiler keeps track of the addressing, and increments required EDS page number into the DSWPAG register or decrements the DS Page registers accordingly, while and assigning the offset address to one of the W regis- accessing contiguous data memory locations. ters. Once the above assignment is done, then the EDS window is enabled by setting bit 15 of the Working Note1: All write operations to EDS are executed register, assigned with the offset address, and the in a single cycle. accessed location can be written. 2: Use of Read-Modify-Write operation on Figure4-2 illustrates how the EDS space address is any EDS location under a REPEAT instruc- generated for write operations. tion is not supported. For example, BCLR, When the MSBs of EA are ‘1’, the lower 9 bits of BSW, BTG, RLC f, RLNC f, RRC f, RRNC DSWPAG are concatenated to the lower 15 bits of the f, ADD f, SUB f, SUBR f, AND f, IOR EA to form a 24-bit EDS address for write operations. f, XOR f, ASR f and ASL f. Example4-2 shows how to write a byte, word and 3: Use the DSRPAG register while double-word to EDS. performing Read-Modify-Write operations. The Data Space Page registers (DSRPAG/DSWPAG) do not update automatically while crossing a page boundary when the rollover happens from 0xFFFF to FIGURE 4-6: EDS ADDRESS GENERATION FOR WRITE OPERATIONS Select 1 Wn 8 0 DSWPAG Register 9 Bits 15 Bits 24-Bit EA Wn<0> is Byte Select EXAMPLE 4-2: EDS WRITE CODE IN ASSEMBLY ; Set the EDS page where the data to be written mov #0x0002, w0 mov w0, DSWPAG ;page 2 is selected for write mov #0x0800, w1 ;select the location (0x800) to be written bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Write a byte to the selected location mov #0x00A5, w2 mov #0x003C, w3 mov.b w2, [w1++] ;write Low byte mov.b w3, [w1++] ;write High byte ;Write a word to the selected location mov #0x1234, w2 ; mov w2, [w1] ; ;Write a Double - word to the selected location mov #0x1122, w2 mov #0x4455, w3 mov.d w2, [w1] ;2 EDS writes DS30010038C-page 60  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 4-34: EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES Source/Destination DSRPAG DSWPAG Address While 24-Bit EA (Data Space Read (Data Space Write Comment Indirect Pointing to EDS Register) Register) Addressing 000000h to 0000h to 1FFFh Near Data Space(2) 001FFFh x(1) x(1) 002000h to 2000h to 7FFFh 007FFFh 008000h to 001h 001h 00FFFEh 010000h to 002h 002h 017FFEh 018000h to 003h 003h 0187FEh • • EPMP Memory Space 8000h to FFFFh • • • • • • • • • • • • FF8000h to 1FFh 1FFh FFFFFEh 000h 000h Invalid Address Address Error Trap(3) Note 1: If the source/destination address is below 8000h, the DSRPAG and DSWPAG registers are not considered. 2: This Data Space can also be accessed by Direct Addressing. 3: When the source/destination address is above 8000h and DSRPAG/DSWPAG are ‘0’, an address error trap will occur. 4.2.6 SOFTWARE STACK desirable to cause a stack error trap when the stack grows beyond address, 2000h in RAM, initialize the Apart from its use as a Working register, the W15 SPLIM with the value, 1FFEh. register in PIC24F devices is also used as a Software Stack Pointer (SSP). The pointer always points to the Similarly, a Stack Pointer underflow (stack error) trap is first available free word and grows from lower to higher generated when the Stack Pointer address is found to addresses. It predecrements for stack pops and post- be less than 0800h. This prevents the stack from increments for stack pushes, as shown in Figure4-7. interfering with the SFR space. Note that for a PC push during any CALL instruction, A write to the SPLIM register should not be immediately the MSB of the PC is zero-extended before the push, followed by an indirect read operation using W15. ensuring that the MSB is always clear. Note: A PC push during exception processing FIGURE 4-7: CALL STACK FRAME will concatenate the SRL Register to the 0000h 15 0 MSB of the PC prior to the push. The Stack Pointer Limit Value (SPLIM) register, associ- s d abtoeudn dwairthy fothre th Se tsatcakc kP. oSiPntLeIrM, sise tusn iannit iaulipzpeedr aat dRderseests. Towardress AfaSolsoirgc uneirsecd ed t .hto oWer ‘Dh0ceae’ nssaeetisvn eafaortl irlao nntsh tEPaecA okSi ni sttao egcprek,e n trhaPeetroia oirntneetssed ur u,ml tsinSuingsPgt L a WbIdMed1 <r5ew0 sa>oss r d iiass- ack Grows Higher Ad 00000<0FP0rC0e<e01 WP5C:o0<r>d2>2:16> WW1155 ((abfeteforr Ce ACLALL)L) compared with the value in SPLIM. If the contents of St POP : [--W15] the Stack Pointer (W15) and the SPLIM register are PUSH: [W15++] equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is  2013-2015 Microchip Technology Inc. DS30010038C-page 61

PIC24FJ128GA204 FAMILY 4.3 Interfacing Program and Data 4.3.1 ADDRESSING PROGRAM SPACE Memory Spaces Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is The PIC24F architecture uses a 24-bit wide program needed to create a 23-bit or 24-bit program address space and 16-bit wide Data Space. The architecture is from 16-bit Data registers. The solution depends on the also a modified Harvard scheme, meaning that data interface method to be used. can also be present in the program space. To use this data successfully, it must be accessed in a way that For table operations, the 8-bit Table Memory Page preserves the alignment of information in both spaces. Address register (TBLPAG) is used to define a 32Kword region within the program space. This is Aside from normal execution, the PIC24F architecture concatenated with a 16-bit EA to arrive at a full 24-bit provides two methods by which program space can be program space address. In this format, the MSbs of accessed during operation: TBLPAG are used to determine if the operation occurs in • Using table instructions to access individual bytes the user memory (TBLPAG<7> = 0) or the configuration or words anywhere in the program space memory (TBLPAG<7> = 1). • Remapping a portion of the program space into For remapping operations, the 10-bit Extended Data the Data Space (Program Space Visibility) Space Read register (DSRPAG) is used to define a Table instructions allow an application to read or write 16Kword page in the program space. When the Most to small areas of the program memory. This makes the Significant bit (MSb) of the EA is ‘1’ and the MSb (bit9) method ideal for accessing data tables that need to be of DSRPAG is ‘1’, the lower 8 bits of DSRPAG are updated from time to time. It also allows access to all concatenated with the lower 15 bits of the EA to form a bytes of the program word. The remapping method 23-bit program space address. The DSRPAG<8> bit allows an application to access a large block of data on decides whether the lower word (when the bit is ‘0’) or a read-only basis, which is ideal for look-ups from a the higher word (when the bit is ‘1’) of program memory large table of static data. It can only access the least is mapped. Unlike table operations, this strictly limits significant word of the program word. remapping operations to the user memory area. Table4-35 and Figure4-8 show how the program EA is created for table operations and remapping accesses from the data EA. Here, the P<23:0> bits refer to a pro- gram space word, whereas the D<15:0> bits refer to a Data Space word. TABLE 4-35: PROGRAM SPACE ADDRESS CONSTRUCTION Access Program Space Address Access Type Space <23> <22:16> <15> <14:1> <0> Instruction Access User 0 PC<22:1> 0 (Code Execution) 0xx xxxx xxxx xxxx xxxx xxx0 TBLRD/TBLWT User TBLPAG<7:0> Data EA<15:0> (Byte/Word Read/Write) 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx Program Space Visibility User 0 DSRPAG<7:0>(2) Data EA<14:0>(1) (Block Remap/Read) 0 xxxx xxxx xxx xxxx xxxx xxxx Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is DSRPAG<0>. 2: DSRPAG<9> is always ‘1’ in this case. DSRPAG<8> decides whether the lower word or higher word of program memory is read. When DSRPAG<8> is ‘0’, the lower word is read and when it is ‘1’, the higher word is read. DS30010038C-page 62  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter 0 Program Counter 0 23 Bits EA 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select 1 EA 1/0 Program Space Visibility(1) 0 DSRPAG<7:0> (Remapping) 1-Bit 8 Bits 15 Bits 23 Bits User/Configuration Byte Select Space Select Note 1: DSRPAG<8> acts as word select. DSRPAG<9> should always be ‘1’ to map program memory to data memory. 2: The instructions, TBLRDH/TBLWTH/TBLRDL/TBLWTL, decide if the higher or lower word of program memory is accessed. TBLRDH/TBLWTH instructions access the higher word and TBLRDL/TBLWTL instructions access the lower word. Table Read operations are permitted in the configuration memory space.  2013-2015 Microchip Technology Inc. DS30010038C-page 63

PIC24FJ128GA204 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM 2. TBLRDH (Table Read High): In Word mode, it MEMORY USING TABLE maps the entire upper word of a program address INSTRUCTIONS (P<23:16>) to a data address. Note that D<15:8>, the ‘phantom’ byte, will always be ‘0’. The TBLRDL and TBLWTL instructions offer a direct In Byte mode, it maps the upper or lower byte of method of reading or writing the lower word of any the program word to D<7:0> of the data address within the program space without going through address, as above. Note that the data will Data Space. The TBLRDH and TBLWTH instructions are always be ‘0’ when the upper ‘phantom’ byte is the only method to read or write the upper 8 bits of a selected (Byte Select = 1). program space word as data. In a similar fashion, two table instructions, TBLWTH The PC is incremented by two for each successive and TBLWTL, are used to write individual bytes or 24-bit program word. This allows program memory words to a program space address. The details of addresses to directly map to Data Space addresses. their operation are described in Section6.0 “Flash Program memory can thus be regarded as two, 16-bit Program Memory”. word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL For all table operations, the area of program memory access the space which contains the least significant space to be accessed is determined by the Table data word, and TBLRDH and TBLWTH access the space Memory Page Address register (TBLPAG). TBLPAG which contains the upper data byte. covers the entire program memory space of the device, including user and configuration spaces. When Two table instructions are provided to move byte or TBLPAG<7> = 0, the table page is located in the user word-sized (16-bit) data to and from program space. memory space. When TBLPAG<7> = 1, the page is Both function as either byte or word operations. located in configuration space. 1. TBLRDL (Table Read Low): In Word mode, it Note: Only Table Read operations will execute maps the lower word of the program space in the configuration memory space where location (P<15:0>) to a data address (D<15:0>). Device IDs are located; Table Write In Byte mode, either the upper or lower byte of operations are not allowed. the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. FIGURE 4-9: ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG Data EA<15:0> 02 23 15 0 000000h 23 16 8 0 00000000 00000000 020000h 00000000 030000h 00000000 ‘Phantom’ Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. 800000h Only read operations are shown; write operations are also valid in the user memory area. DS30010038C-page 64  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 4.3.3 READING DATA FROM PROGRAM Table4-36 provides the corresponding 23-bit EDS MEMORY USING EDS address for program memory with EDS page and source addresses. The upper 32 Kbytes of Data Space may optionally be mapped into any 16K word page of the program space. For operations that use PSV and are executed outside This provides transparent access of stored constant a REPEAT loop, the MOV and MOV.D instructions will data from the Data Space without the need to use require one instruction cycle in addition to the specified special instructions (i.e., TBLRDL/H). execution time. All other instructions will require two instruction cycles in addition to the specified execution Program space access through the Data Space occurs time. when the MSb of EA is ‘1’ and the DSRPAG<9> bit is also ‘1’. The lower 8 bits of DSRPAG are concatenated For operations that use PSV, which are executed inside to the Wn<14:0> bits to form a 23-bit EA to access pro- a REPEAT loop, there will be some instances that gram memory. The DSRPAG<8> bit decides which word require two instruction cycles in addition to the should be addressed; when the bit is ‘0’, the lower word specified execution time of the instruction: and when ‘1’, the upper word of the program memory is • Execution in the first iteration accessed. • Execution in the last iteration The entire program memory is divided into 512 EDS • Execution prior to exiting the loop due to an pages, from 200h to 3FFh, each consisting of 16K words interrupt of data. Pages, 200h to 2FFh, correspond to the lower • Execution upon re-entering the loop after an words of the program memory, while 300h to 3FFh interrupt is serviced correspond to the upper words of the program memory. Any other iteration of the REPEAT loop will allow the Using this EDS technique, the entire program memory instruction accessing data, using PSV, to execute in a can be accessed. Previously, the access to the upper single cycle. word of the program memory was not supported. TABLE 4-36: EDS PROGRAM ADDRESS WITH DIFFERENT PAGES AND ADDRESSES DSRPAG Source Address While 23-Bit EA Pointing to Comment (Data Space Read Register) Indirect Addressing EDS 200h 000000h to 007FFEh • • Lower words of 4M program • • instructions (8 Mbytes); for • • read operations only 2FFh 7F8000h to 7FFFFEh 300h 8000h to FFFFh 000001h to 007FFFh Upper words of 4M program • • instructions (4 Mbytes remaining, • • 4Mbytes are phantom bytes); for • • read operations only 3FFh 7F8001h to 7FFFFFh 000h Invalid Address Address error trap(1) Note 1: When the source/destination address is above 8000h and DSRPAG/DSWPAG is ‘0’, an address error trap will occur. EXAMPLE 4-3: EDS READ CODE FROM PROGRAM MEMORY IN ASSEMBLY ; Set the EDS page from where the data to be read mov #0x0202, w0 mov w0, DSRPAG ;page 0x202, consisting lower words, is selected for read mov #0x000A, w1 ;select the location (0x0A) to be read bset w1, #15 ;set the MSB of the base address, enable EDS mode ;Read a byte from the selected location mov.b [w1++], w2 ;read Low byte mov.b [w1++], w3 ;read High byte ;Read a word from the selected location mov [w1], w2 ; ;Read Double - word from the selected location mov.d [w1], w2 ;two word read, stored in w2 and w3  2013-2015 Microchip Technology Inc. DS30010038C-page 65

PIC24FJ128GA204 FAMILY FIGURE 4-10: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS LOWER WORD When DSRPAG<9:8> = 10 and EA<15> = 1: Program Space Data Space DSRPAG 23 15 0 202h 000000h 0000h Data EA<14:0> 010000h 017FFEh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window ...while the lower 15bits of the EA specify an exact FFFFh address within the EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program 7FFFFEh space address. FIGURE 4-11: PROGRAM SPACE VISIBILITY OPERATION TO ACCESS UPPER WORD When DSRPAG<9:8> = 11 and EA<15> = 1: Program Space Data Space DSRPAG 23 15 0 302h 000000h 0000h Data EA<14:0> 010001h 017FFFh The data in the page designated by DSRPAG is mapped into the upper half of the data memory space.... 8000h EDS Window ...while the lower 15bits of the EA specify an exact FFFFh address within the EDS area. This corre- sponds exactly to the same lower 15 bits of the actual program 7FFFFEh space address. DS30010038C-page 66  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 5.0 DIRECT MEMORY ACCESS The controller also monitors CPU instruction process- CONTROLLER (DMA) ing directly, allowing it to be aware of when the CPU requires access to peripherals on the DMA bus and Note: This data sheet summarizes the features of automatically relinquishing control to the CPU as this group of PIC24F devices. It is not needed. This increases the effective bandwidth for intended to be a comprehensive reference handling data without DMA operations causing a source. For more information, refer to processor stall. This makes the controller essentially the “dsPIC33/PIC24 Family Reference transparent to the user. Manual”, “Direct Memory Access The DMA Controller has these features: Controller (DMA)” (DS39742). The infor- • Six multiple independent and independently mation in this data sheet supersedes the programmable channels information in the FRM. • Concurrent operation with the CPU (no DMA The Direct Memory Access (DMA) Controller is caused Wait states) designed to service high data throughput peripherals • DMA bus arbitration operating on the SFR bus, allowing them to access • Five Programmable Address modes data memory directly and alleviating the need for CPU • Four Programmable Transfer modes intensive management. By allowing these data- • Four Flexible Internal Data Transfer modes intensive peripherals to share their own data path, the main data bus is also deloaded, resulting in additional • Byte or word support for data transfer power savings. • 16-Bit Source and Destination Address register for each channel, dynamically updated and The DMA Controller functions both as a peripheral reloadable and a direct extension of the CPU. It is located on the microcontroller data bus between the CPU and • 16-Bit Transaction Count register, dynamically DMA-enabled peripherals, with direct access to updated and reloadable SRAM. This partitions the SFR bus into two buses, • Upper and Lower Address Limit registers allowing the DMA Controller access to the DMA • Counter half-full level interrupt capable peripherals located on the new DMA SFR bus. • Software triggered transfer The controller serves as a master device on the DMA • Null Write mode for symmetric buffer operations SFR bus, controlling data flow from DMA capable peripherals. A simplified block diagram of the DMA Controller is shown in Figure5-1. FIGURE 5-1: DMA FUNCTIONAL BLOCK DIAGRAM CPU Execution Monitoring To DMA-Enabled To I/O Ports Peripherals and Peripherals DMACON Control DMAH Logic DMAL DMABUF Data Bus DMACH0 DMACH1 DMACH4 DMACH5 DMAINT0 DMAINT1 DMAINT4 DMAINT5 DMASRC0 DMASRC1 DMASRC4 DMASRC5 DMADST0 DMADST1 DMADST4 DMADST5 DMACNT0 DMACNT1 DMACNT4 DMACNT5 Channel 0 Channel 1 Channel 4 Channel 5 Data RAM Data RAM Address Generation  2013-2015 Microchip Technology Inc. DS30010038C-page 67

PIC24FJ128GA204 FAMILY 5.1 Summary of DMA Operations Since the source and destination addresses for any transaction can be programmed independently of the The DMA Controller is capable of moving data between trigger source, the DMA Controller can use any trigger addresses according to a number of different parame- to perform an operation on any peripheral. This also ters. Each of these parameters can be independently allows DMA channels to be cascaded to perform more configured for any transaction. In addition, any or all of complex transfer operations. the DMA channels can independently perform a different transaction at the same time. Transactions are classified 5.1.4 TRANSFER MODE by these parameters: The DMA Controller supports four types of data • Source and destination (SFRs and data RAM) transfers, based on the volume of data to be moved for • Data size (byte or word) each trigger: • Trigger source • One-Shot: A single transaction occurs for each • Transfer mode (One-Shot, Repeated or trigger. Continuous) • Continuous: A series of back-to-back transactions • Addressing modes (Fixed Address or occur for each trigger; the number of transactions Address Blocks with or without Address is determined by the DMACNTn transaction Increment/Decrement) counter. In addition, the DMA Controller provides channel priority • Repeated One-Shot: A single transaction is per- arbitration for all channels. formed repeatedly, once per trigger, until the DMA channel is disabled. 5.1.1 SOURCE AND DESTINATION • Repeated Continuous: A series of transactions Using the DMA Controller, data may be moved between are performed repeatedly, one cycle per trigger, any two addresses in the Data Space. The SFR space until the DMA channel is disabled. (0000h to 07FFh), or the data RAM space (0800h to All Transfer modes allow the option to have the source FFFFh) can serve as either the source or the destina- and destination addresses, and counter value, auto- tion. Data can be moved between these areas in either matically reloaded after the completion of a transaction; direction or between addresses in either area. The four Repeated mode transfers do this automatically. different combinations are shown in Figure5-2. 5.1.5 ADDRESSING MODES If it is necessary to protect areas of data RAM, the DMA Controller allows the user to set upper and lower address The DMA Controller also supports transfers between boundaries for operations in the Data Space above the single addresses or address ranges. The four basic SFR space. The boundaries are set by the DMAH and options are: DMAL High/Low Address Limit registers. If a DMA • Fixed-to-Fixed: Between two constant addresses channel attempts an operation outside of the address • Fixed-to-Block: From a constant source address boundaries, the transaction is terminated and an to a range of destination addresses interrupt is generated. • Block-to-Fixed: From a range of source 5.1.2 DATA SIZE addresses to a single, constant destination address The DMA Controller can handle both 8-bit and 16-bit • Block-to-Block: From a range of source transactions. Size is user-selectable using the SIZE bit addresses to a range of destination addresses (DMACHn<1>). By default, each channel is configured for word-size transactions. When byte-size transac- The option to select auto-increment or auto-decrement tions are chosen, the LSb of the source and/or of source and/or destination addresses is available for destination address determines if the data represents Block Addressing modes. the upper or lower byte of the data RAM location. In addition to the four basic modes, the DMA Controller also supports Peripheral Indirect Addressing (PIA) 5.1.3 TRIGGER SOURCE mode, where the source or destination address is gen- The DMA Controller can use 63 of the device’s interrupt erated jointly by the DMA Controller and a PIA capable sources to initiate a transaction. The DMA trigger peripheral. When enabled, the DMA channel provides sources occur in reverse order than their natural a base source and/or destination address, while the interrupt priority and are shown in Table5-1. peripheral provides a fixed range offset address. For PIC24FJ128GA204 family devices, the 12-bit A/D Converter module is the only PIA capable peripheral. Details for its use in PIA mode are provided in Section24.0 “12-Bit A/D Converter with Threshold Detect”. DS30010038C-page 68  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 5-2: TYPES OF DMA DATA TRANSFERS Peripheral to Memory Memory to Peripheral SFR Area SFR Area DMASRCn DMADSTn 07FFh 07FFh 0800h 0800h Data RAM Data RAM DMAL DMAL DMA RAM Area DMA RAM Area DMADSTn DMASRCn DMAH DMAH Peripheral to Peripheral Memory to Memory SFR Area SFR Area DMASRCn DMADSTn 07FFh 07FFh 0800h 0800h Data RAM Data RAM DMAL DMAL DMA RAM Area DMA RAM Area DMASRCn DMADSTn DMAH DMAH Note: Relative sizes of memory areas are not shown to scale.  2013-2015 Microchip Technology Inc. DS30010038C-page 69

PIC24FJ128GA204 FAMILY 5.1.6 CHANNEL PRIORITY 5.3 Peripheral Module Disable Each DMA channel functions independently of the Unlike other peripheral modules, the channels of the others, but also competes with the others for access to DMA Controller cannot be individually powered down the data and DMA buses. When access collisions using the Peripheral Module Disable x (PMDx) occur, the DMA Controller arbitrates between the registers. Instead, the channels are controlled as two channels using a user-selectable priority scheme. Two groups. The DMA0MD bit (PMD7<4>) selectively schemes are available: controls DMACH0 through DMACH3. The DMA1MD bit • Round Robin: When two or more channels col- (PMD7<5>) controls DMACH4 and DMACH5. Setting lide, the lower numbered channel receives priority both bits effectively disables the DMA Controller. on the first collision. On subsequent collisions, the higher numbered channels each receive priority 5.4 Registers based on their channel number. The DMA Controller uses a number of registers to con- • Fixed Priority: When two or more channels trol its operation. The number of registers depends on collide, the lowest numbered channel always the number of channels implemented for a particular receives priority, regardless of past history. device. 5.2 Typical Setup There are always four module-level registers (one control and three buffer/address): To set up a DMA channel for a basic data transfer: • DMACON: DMA Control Register (Register5-1) 1. Enable the DMA Controller (DMAEN = 1) and • DMAH and DMAL: DMA High and Low Address select an appropriate channel priority scheme Limit Registers by setting or clearing PRSSEL. • DMABUF: DMA Transfer Data Buffer 2. Program DMAH and DMAL with appropriate Each of the DMA channels implements five registers upper and lower address boundaries for data (two control and three buffer/address): RAM operations. 3. Select the DMA channel to be used and disable • DMACHn: DMA Channel n Control Register its operation (CHEN = 0). (Register5-2) 4. Program the appropriate source and destination • DMAINTn: DMA Channel n Interrupt Control addresses for the transaction into the channel’s Register (Register5-3) DMASRCn and DMADSTn registers. For PIA • DMASRCn: DMA Data Source Address Pointer Addressing mode, use the base address value. for Channel n Register 5. Program the DMACNTn register for the number • DMADSTn: DMA Data Destination Source for of triggers per transfer (One-Shot or Continuous Channel n Register modes) or the number of words (bytes) to be • DMACNTn: DMA Transaction Counter for transferred (Repeated modes). Channel n Register 6. Set or clear the SIZE bit to select the data size. For PIC24FJ128GA204 family devices, there are a 7. Program the TRMODE<1:0> bits to select the total of 34 registers. Data Transfer mode. 8. Program the SAMODE<1:0> and DAMODE<1:0> bits to select the addressing mode. 9. Enable the DMA channel by setting CHEN. 10. Enable the trigger source interrupt. DS30010038C-page 70  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 5-1: DMACON: DMA ENGINE CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DMAEN — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PRSSEL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DMAEN: DMA Module Enable bit 1 = Enables module 0 = Disables module and terminates all active DMA operation(s) bit 14-1 Unimplemented: Read as ‘0’ bit 0 PRSSEL: Channel Priority Scheme Selection bit 1 = Round robin scheme 0 = Fixed priority scheme  2013-2015 Microchip Technology Inc. DS30010038C-page 71

PIC24FJ128GA204 FAMILY REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER U-0 U-0 U-0 r-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — NULLW RELOAD(1) CHREQ(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SAMODE1 SAMODE0 DAMODE1 DAMODE0 TRMODE1 TRMODE0 SIZE CHEN bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 Reserved: Maintain as ‘0’ bit 11 Unimplemented: Read as ‘0’ bit 10 NULLW: Null Write Mode bit 1 = A dummy write is initiated to DMASRCn for every write to DMADSTn 0 = No dummy write is initiated bit 9 RELOAD: Address and Count Reload bit(1) 1 = DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the start of the next operation 0 = DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation(2) bit 8 CHREQ: DMA Channel Software Request bit(3) 1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer 0 = No DMA request is pending bit 7-6 SAMODE<1:0>: Source Address Mode Selection bits 11 = DMASRCn is used in Peripheral Indirect Addressing and remains unchanged 10 = DMASRCn is decremented based on the SIZE bit after a transfer completion 01 = DMASRCn is incremented based on the SIZE bit after a transfer completion 00 = DMASRCn remains unchanged after a transfer completion bit 5-4 DAMODE<1:0>: Destination Address Mode Selection bits 11 = DMADSTn is used in Peripheral Indirect Addressing and remains unchanged 10 = DMADSTn is decremented based on the SIZE bit after a transfer completion 01 = DMADSTn is incremented based on the SIZE bit after a transfer completion 00 = DMADSTn remains unchanged after a transfer completion bit 3-2 TRMODE<1:0>: Transfer Mode Selection bits 11 = Repeated Continuous mode 10 = Continuous mode 01 = Repeated One-Shot mode 00 = One-Shot mode bit 1 SIZE: Data Size Selection bit 1 = Byte (8-bit) 0 = Word (16-bit) bit 0 CHEN: DMA Channel Enable bit 1 = The corresponding channel is enabled 0 = The corresponding channel is disabled Note 1: Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn values. 2: DMACNTn will always be reloaded in Repeated mode transfers, regardless of the state of the RELOAD bit. 3: The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>. DS30010038C-page 72  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 5-3: DMAINTn: DMA CHANNEL n INTERRUPT REGISTER R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DBUFWF(1) — CHSEL5 CHSEL4 CHSEL3 CHSEL2 CHSEL1 CHSEL0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 HIGHIF(1,2) LOWIF(1,2) DONEIF(1) HALFIF(1) OVRUNIF(1) — — HALFEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DBUFWF: DMA Buffered Data Write Flag bit(1) 1 = The content of the DMA buffer has not been written to the location specified in DMADSTn or DMASRCn in Null Write mode 0 = The content of the DMA buffer has been written to the location specified in DMADSTn or DMASRCn in Null Write mode bit 14 Unimplemented: Read as ‘0’ bit 13-8 CHSEL<5:0>: DMA Channel Trigger Selection bits See Table5-1 for a complete list. bit 7 HIGHIF: DMA High Address Limit Interrupt Flag bit(1,2) 1 = The DMA channel has attempted to access an address higher than DMAH or the upper limit of the data RAM space 0 = The DMA channel has not invoked the high address limit interrupt bit 6 LOWIF: DMA Low Address Limit Interrupt Flag bit(1,2) 1 = The DMA channel has attempted to access the DMA SFR address lower than DMAL, but above the SFR range (07FFh) 0 = The DMA channel has not invoked the low address limit interrupt bit 5 DONEIF: DMA Complete Operation Interrupt Flag bit(1) If CHEN = 1: 1 = The previous DMA session has ended with completion 0 = The current DMA session has not yet completed If CHEN = 0: 1 = The previous DMA session has ended with completion 0 = The previous DMA session has ended without completion bit 4 HALFIF: DMA 50% Watermark Level Interrupt Flag bit(1) 1 = DMACNTn has reached the halfway point to 0000h 0 = DMACNTn has not reached the halfway point bit 3 OVRUNIF: DMA Channel Overrun Flag bit(1) 1 = The DMA channel is triggered while it is still completing the operation based on the previous trigger 0 = The overrun condition has not occurred bit 2-1 Unimplemented: Read as ‘0’ bit 0 HALFEN: DMA Halfway Completion Watermark bit 1 = Interrupts are invoked when DMACNTn has reached its halfway point and at completion 0 = An interrupt is invoked only at the completion of the transfer Note 1: Setting these flags in software does not generate an interrupt. 2: Testing for address limit violations (DMASRCn or DMADSTn is either greater than DMAH or less than DMAL) is NOT done before the actual access.  2013-2015 Microchip Technology Inc. DS30010038C-page 73

PIC24FJ128GA204 FAMILY TABLE 5-1: DMA CHANNEL TRIGGER SOURCES CHSEL<5:0> Trigger (Interrupt) CHSEL<5:0> Trigger (Interrupt) 000000 (Unimplemented) 100000 UART2 Transmit 000001 SPI3 General Event 100001 UART2 Receive 000010 I2C1 Slave Event 100010 External Interrupt 2 000011 UART4 Transmit 100011 Timer5 000100 UART4 Receive 100100 Timer4 000101 UART4 Error 100101 Output Compare 4 000110 UART3 Transmit 100110 Output Compare 3 000111 UART3 Receive 100111 DMA Channel 2 001000 UART3 Error 101000 I2C2 Slave Event 001001 CTMU Event 101001 External Interrupt 1 001010 HLVD 101010 Interrupt-on-Change 001011 CRC Done 101011 Comparators Event 001100 UART2 Error 101100 SPI3 Receive Event 001101 UART1 Error 101101 I2C1 Master Event 001110 RTCC 101110 DMA Channel 1 001111 DMA Channel 5 101111 A/D Converter 010000 External Interrupt 4 110000 UART1 Transmit 010001 External Interrupt 3 110001 UART1 Receive 010010 SPI2 Receive Event 110010 SPI1 Transmit Event 010011 I2C2 Master Event 110011 SPI1 General Event 010100 DMA Channel 4 110100 Timer3 010101 EPMP 110101 Timer2 010110 SPI1 Receive Event 110110 Output Compare 2 010111 Output Compare 6 110111 Input Capture 2 011000 Output Compare 5 111000 DMA Channel 0 011001 Input Capture 6 111001 Timer1 011010 Input Capture 5 111010 Output Compare 1 011011 Input Capture 4 111011 Input Capture 1 011100 Input Capture 3 111100 External Interrupt 0 011101 DMA Channel 3 111101 Reserved 011110 SPI2 Transmit Event 111110 SPI3 Transmit Event 011111 SPI2 General Event 111111 Cryptographic Done DS30010038C-page 74  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 6.0 FLASH PROGRAM MEMORY microcontroller just before shipping the product. This also allows the most recent firmware or a custom Note: This data sheet summarizes the features of firmware to be programmed. this group of PIC24F devices. It is not RTSP is accomplished using TBLRD (Table Read) and intended to be a comprehensive reference TBLWT (Table Write) instructions. With RTSP, the user source. For more information, refer to may write program memory data in blocks of 64 instruc- the “dsPIC33/PIC24 Family Reference tions (192 bytes) at a time and erase program memory Manual”, “Program Memory” (DS39715). in blocks of 512 instructions (1536 bytes) at a time. The information in this data sheet supersedes the information in the FRM. 6.1 Table Instructions and Flash The PIC24FJ128GA204 family of devices contains Programming internal Flash program memory for storing and execut- Regardless of the method used, all programming of ing application code. The program memory is readable, Flash memory is done with the Table Read and Table writable and erasable. The Flash memory can be Write instructions. These allow direct read and write programmed in four ways: access to the program memory space from the data • In-Circuit Serial Programming™ (ICSP™) memory while the device is in normal operating mode. • Run-Time Self-Programming (RTSP) The 24-bit target address in the program memory is • JTAG formed using the TBLPAG<7:0> bits and the Effective • Enhanced In-Circuit Serial Programming Address (EA) from a W register, specified in the table (Enhanced ICSP) instruction, as shown in Figure6-1. ICSP allows a PIC24FJ128GA204 family device to be The TBLRDL and the TBLWTL instructions are used to serially programmed while in the end application circuit. read or write to bits<15:0> of program memory. This is simply done with two lines for the programming TBLRDL and TBLWTL can access program memory in clock and programming data (named PGECx and both Word and Byte modes. PGEDx, respectively), and three other lines for power The TBLRDH and TBLWTH instructions are used to read (VDD), ground (VSS) and Master Clear (MCLR). This or write to bits<23:16> of program memory. TBLRDH allows customers to manufacture boards with and TBLWTH can also access program memory in Word unprogrammed devices and then program the or Byte mode. FIGURE 6-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program 0 Program Counter 0 Counter Working Register EA Using Table 1/0 TBLPAG Register Instruction 8 Bits 16 Bits User/Configuration Byte Space Select 24-Bit EA Select  2013-2015 Microchip Technology Inc. DS30010038C-page 75

PIC24FJ128GA204 FAMILY 6.2 RTSP Operation 6.3 JTAG Operation The PIC24F Flash program memory array is organized The PIC24F family supports JTAG boundary scan. into rows of 64 instructions or 192 bytes. RTSP allows Boundary scan can improve the manufacturing the user to erase blocks of eight rows (512 instructions) process by verifying pin to PCB connectivity. at a time and to program one row at a time. It is also possible to program single words. 6.4 Enhanced In-Circuit Serial The 8-row erase blocks and single row write blocks are Programming edge-aligned, from the beginning of program memory on Enhanced In-Circuit Serial Programming uses an boundaries of 1536 bytes and 192 bytes, respectively. on-board bootloader, known as the Program Executive When data is written to program memory using TBLWT (PE), to manage the programming process. Using an instructions, the data is not written directly to memory. SPI data frame format, the Program Executive can Instead, data written using Table Writes is stored in erase, program and verify program memory. For more holding latches until the programming sequence is information on Enhanced ICSP, see the device executed. programming specification. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 6.5 Control Registers 64TBLWT instructions are required to write the full row There are two SFRs used to read and write the of memory. program Flash memory: NVMCON and NVMKEY. To ensure that no data is corrupted during a write, The NVMCON register (Register6-1) controls which any unused address should be programmed with blocks are to be erased, which memory type is to be FFFFFFh. This is because the holding latches reset to programmed and when the programming cycle starts. an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows NVMKEY is a write-only register that is used for write which were not rewritten. protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the The basic sequence for RTSP programming is to set up NVMKEY register. For more information, refer to a Table Pointer, then do a series of TBLWT instructions Section6.6 “Programming Operations”. to load the buffers. Programming is performed by setting the control bits in the NVMCON register. 6.6 Programming Operations Data can be loaded in any order and the holding regis- ters can be written to multiple times before performing A complete programming sequence is necessary for a write operation. Subsequent writes, however, will programming or erasing the internal Flash in RTSP wipe out any previous writes. mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Note: Writing to a location multiple times without Setting the WR bit (NVMCON<15>) starts the opera- erasing is not recommended. tion and the WR bit is automatically cleared when the All of the Table Write operations are single-word writes operation is finished. (2 instruction cycles), because only the buffers are writ- ten. A programming cycle is required for programming each row. DS30010038C-page 76  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 6-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/S-0, HC(1) R/W-0(1) R-0, HSC(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — ERASE — — NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: S = Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HSC = Hardware Settable/Clearable bit bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program/erase operations 0 = Inhibits Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as ‘0’ bit 6 ERASE: Erase/Program Enable bit(1) 1 = Performs the erase operation specified by the NVMOP<3:0> bits on the next WR command 0 = Performs the program operation specified by the NVMOP<3:0> bits on the next WR command bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP<3:0>: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) Note 1: These bits can only be reset on a Power-on Reset. 2: All other combinations of NVMOP<3:0> are unimplemented. 3: Available in ICSP™ mode only; refer to the device programming specification.  2013-2015 Microchip Technology Inc. DS30010038C-page 77

PIC24FJ128GA204 FAMILY 6.6.1 PROGRAMMING ALGORITHM FOR 4. Write the first 64 instructions from data RAM into FLASH PROGRAM MEMORY the program memory buffers (see Example6-3). 5. Write the program block to Flash memory: The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row a) Set the NVMOPx bits to ‘0001’ to configure erase block containing the desired row. The general for row programming. Clear the ERASE bit process is: and set the WREN bit. b) Write 55h to NVMKEY. 1. Read eight rows of program memory (512instructions) and store in data RAM. c) Write AAh to NVMKEY. 2. Update the program data in RAM with the d) Set the WR bit. The programming cycle desired new data. begins and the CPU stalls for the duration of the write cycle. When the write to Flash 3. Erase the block (see Example6-1): memory is done, the WR bit is cleared a) Set the NVMOPx bits (NVMCON<3:0>) to automatically. ‘0010’ to configure for block erase. Set the 6. Repeat Steps 4 and 5, using the next available ERASE (NVMCON<6>) and WREN 64instructions from the block in data RAM by (NVMCON<14>) bits. incrementing the value in TBLPAG, until all b) Write the starting address of the block to be 512instructions are written back to Flash erased into the TBLPAG and W registers. memory. c) Write 55h to NVMKEY. For protection against accidental operations, the write d) Write AAh to NVMKEY. initiate sequence for NVMKEY must be used to allow e) Set the WR bit (NVMCON<15>). The erase any erase or program operation to proceed. After the cycle begins and the CPU stalls for the programming command has been executed, the user duration of the erase cycle. When the erase must wait for the programming time until programming is done, the WR bit is cleared automatically. is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example6-4. EXAMPLE 6-1: ERASING A PROGRAM MEMORY BLOCK (ASSEMBLY LANGUAGE CODE) ; Set up NVMCON for block erase operation MOV #0x4042, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ; Initialize Program Memory (PM) Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ; Initialize in-page EA<15:0> pointer TBLWTL W0, [W0] ; Set base address of erase block DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the erase sequence NOP ; Insert two NOPs after the erase NOP ; command is asserted DS30010038C-page 78  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY EXAMPLE 6-2: ERASING A PROGRAM MEMORY BLOCK (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned long progAddr = 0xXXXXXX; // Address of row to write unsigned int offset; //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // check function to perform unlock // sequence and set WR EXAMPLE 6-3: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch • • • ; 63rd_program_word MOV #LOW_WORD_63, W2 ; MOV #HIGH_BYTE_63, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0] ; Write PM high byte into program latch EXAMPLE 6-4: INITIATING A PROGRAMMING SEQUENCE DISI #5 ; Block all interrupts with priority <7 ; for next 5 instructions MOV.B #0x55, W0 MOV W0, NVMKEY ; Write the 0x55 key MOV.B #0xAA, W1 ; MOV W1, NVMKEY ; Write the 0xAA key BSET NVMCON, #WR ; Start the programming sequence NOP ; Required delays NOP BTSC NVMCON, #15 ; and wait for it to be BRA $-2 ; completed  2013-2015 Microchip Technology Inc. DS30010038C-page 79

PIC24FJ128GA204 FAMILY 6.6.2 PROGRAMMING A SINGLE WORD latches and specify the lower 16 bits of the program OF FLASH PROGRAM MEMORY memory address to write to. To configure the NVMCON register for a word write, set the NVMOPx bits If a Flash location has been erased, it can be (NVMCON<3:0>) to ‘0011’. The write is performed by programmed using Table Write instructions to write an executing the unlock sequence and setting the WR bit instruction word (24-bit) into the write latch. The (see Example6-5). An equivalent procedure in ‘C’ com- TBLPAG register is loaded with the 8 Most Significant piler language, using the MPLAB® C30 compiler and Bytes (MSBs) of the Flash address. The TBLWTL and built-in hardware functions, is shown in Example6-6. TBLWTH instructions write the desired data into the write EXAMPLE 6-5: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY ; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV #LOW_WORD_N, W2 ; MOV #HIGH_BYTE_N, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI #5 ; Disable interrupts while the KEY sequence is written MOV.B #0x55, W0 ; Write the key sequence MOV W0, NVMKEY MOV.B #0xAA, W0 MOV W0, NVMKEY BSET NVMCON, #WR ; Start the write cycle NOP ; Required delays NOP EXAMPLE 6-6: PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY (‘C’ LANGUAGE CODE) // C example using MPLAB C30 unsigned int offset; unsigned long progAddr = 0xXXXXXX; // Address of word to program unsigned int progDataL = 0xXXXX; // Data to program lower word unsigned char progDataH = 0xXX; // Data to program upper byte //Set up NVMCON for word programming NVMCON = 0x4003; // Initialize NVMCON //Set up pointer to the first memory location to be written TBLPAG = progAddr>>16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); // Write to address low word __builtin_tblwth(offset, progDataH); // Write to upper byte asm(“DISI #5”); // Block interrupts with priority <7 // for next 5 instructions __builtin_write_NVM(); // C30 function to perform unlock // sequence and set WR DS30010038C-page 80  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 7.0 RESETS Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU Note: This data sheet summarizes the features of and peripherals are forced to a known Reset state. this group of PIC24F devices. It is not Most registers are unaffected by a Reset; their status is intended to be a comprehensive reference unknown on POR and unchanged by all other Resets. source. For more information, refer to the “dsPIC33/PIC24 Family Reference Note: Refer to the specific peripheral or CPU section of this manual for register Reset Manual”, “Reset” (DS39712). The infor- mation in this data sheet supersedes the states. information in the FRM. All types of device Resets will set a corresponding The Reset module combines all Reset sources and status bit in the RCON register to indicate the type of controls the device Master Reset Signal, SYSRST. The Reset (see Register7-1). In addition, Reset events following is a list of device Reset sources: occurring while an extreme power-saving feature is in use (such as VBAT) will set one or more status bits in • POR: Power-on Reset the RCON2 register (Register7-2). A POR will clear all • MCLR: Master Clear Pin Reset bits, except for the BOR and POR (RCON<1:0>) bits, • SWR: RESET Instruction which are set. The user may set or clear any bit at any • WDT: Watchdog Timer Reset time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in • BOR: Brown-out Reset software will not cause a device Reset to occur. • CM: Configuration Mismatch Reset The RCON register also has other bits associated with • TRAPR: Trap Conflict Reset the Watchdog Timer and device power-saving states. • IOPUWR: Illegal Opcode Reset The function of these bits is discussed in other sections • UWR: Uninitialized W Register Reset of this data sheet. A simplified block diagram of the Reset module is Note: The status bits in the RCON registers shown in Figure7-1. should be cleared after they are read so that the next RCON register values after a device Reset will be meaningful. FIGURE 7-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise POR Detect SYSRST VDD Brown-out BOR Reset Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2013-2015 Microchip Technology Inc. DS30010038C-page 81

PIC24FJ128GA204 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 TRAPR(1) IOPUWR(1) — RETEN(2) — DPSLP(1) CM(1) VREGS(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR(1) SWR(1) SWDTEN(4) WDTO(1) SLEEP(1) IDLE(1) BOR(1) POR(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit(1) 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit(1) 1 = An illegal opcode detection, an illegal address mode or Uninitialized W register is used as an Address Pointer and caused a Reset 0 = An illegal opcode or Uninitialized W register Reset has not occurred bit 13 Unimplemented: Read as ‘0’ bit 12 RETEN: Retention Mode Enable bit(2) 1 = Retention mode is enabled while device is in Sleep modes (1.2V regulator supplies to the core) 0 = Retention mode is disabled; normal voltage levels are present bit 11 Unimplemented: Read as ‘0’ bit 10 DPSLP: Deep Sleep Flag bit(1) 1 = Device has been in Deep Sleep mode 0 = Device has not been in Deep Sleep mode bit 9 CM: Configuration Word Mismatch Reset Flag bit(1) 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred bit 8 VREGS: Program Memory Power During Sleep bit(3) 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep bit 7 EXTR: External Reset (MCLR) Pin bit(1) 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit(1) 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN bit has no effect. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. 4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS30010038C-page 82  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 7-1: RCON: RESET CONTROL REGISTER (CONTINUED) bit 5 SWDTEN: Software Enable/Disable of WDT bit(4) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit(1) 1 = WDT time-out has occurred 0 = WDT time-out has not occurred bit 3 SLEEP: Wake from Sleep Flag bit(1) 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake from Idle Flag bit(1) 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit(1) 1 = A Brown-out Reset has occurred (also set after a Power-on Reset) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit(1) 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the LPCFG Configuration bit is ‘1’ (unprogrammed), the retention regulator is disabled and the RETEN bit has no effect. 3: Re-enabling the regulator after it enters Standby mode will add a delay, TVREG, when waking up from Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from occurring. 4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting.  2013-2015 Microchip Technology Inc. DS30010038C-page 83

PIC24FJ128GA204 FAMILY REGISTER 7-2: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 r-0 R/CO-1 R/CO-1 R/CO-1 R/CO-0 — — — — VDDBOR(1) VDDPOR(1,2) VBPOR(1,3) VBAT(1) bit 7 bit 0 Legend: CO = Clearable Only bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Maintain as ‘0’ bit 3 VDDBOR: VDD Brown-out Reset Flag bit(1) 1 = A VDD Brown-out Reset has occurred (set by hardware) 0 = A VDD Brown-out Reset has not occurred bit 2 VDDPOR: VDD Power-on Reset Flag bit(1,2) 1 = A VDD Power-on Reset has occurred (set by hardware) 0 = A VDD Power-on Reset has not occurred bit 1 VBPOR: VBPOR Flag bit(1,3) 1 = A VBAT POR has occurred (no battery is connected to the VBAT pin or VBAT power below the Deep Sleep Semaphore register retention level is set by hardware) 0 = A VBAT POR has not occurred bit 0 VBAT: VBAT Flag bit(1) 1 = A POR exit has occurred while power was applied to the VBAT pin (set by hardware) 0 = A POR exit from VBAT has not occurred Note 1: This bit is set in hardware only; it can only be cleared in software. 2: This bit indicates a VDD Power-on Reset. Setting the POR bit (RCON<0>) indicates a VCORE Power-on Reset. 3: This bit is set when the device is originally powered up, even if power is present on VBAT. TABLE 7-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out CLRWDT, PWRSAV Instruction, POR SLEEP (RCON<3>) PWRSAV #0 Instruction POR DPSLP (RCON<10>) PWRSAV #0 Instruction while DSEN bit is Set POR IDLE (RCON<2>) PWRSAV #1 Instruction POR BOR (RCON<1>) POR, BOR — POR (RCON<0>) POR — Note: All Reset flag bits may be set or cleared by the user software. DS30010038C-page 84  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 7.1 Special Function Register Reset 7.3 Brown-out Reset (BOR) States PIC24FJ128GA204 family devices implement a BOR Most of the Special Function Registers (SFRs) associ- circuit that provides the user with several configuration ated with the PIC24F CPU and peripherals are reset to a and power-saving options. The BOR is controlled by particular value at a device Reset. The SFRs are the BOREN (CW3<12>) Configuration bit. grouped by their peripheral or CPU function and their When BOR is enabled, any drop of VDD below the BOR Reset values are specified in each section of this manual. threshold results in a device BOR. Threshold levels are The Reset value for each SFR does not depend on the described in Section32.1 “DC Characteristics” type of Reset, with the exception of four registers. The (Parameter DC17A). Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value 7.4 Clock Source Selection at Reset for the Oscillator Control register, OSCCON, will If clock switching is enabled, the system clock source at depend on the type of Reset and the programmed device Reset is chosen, as shown in Table7-2. If clock values of the FNOSC<2:0> bits in Flash Configuration switching is disabled, the system clock source is always Word2 (CW2); see Table7-2. The RCFGCAL and selected according to the Oscillator Configuration bits. For NVMCON registers are only affected by a POR. more information, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Oscillator” (DS39700). 7.2 Device Reset Times The Reset times for various types of device Reset are TABLE 7-2: OSCILLATOR SELECTION vs. summarized in Table7-3. Note that the Master Reset TYPE OF RESET (CLOCK Signal, SYSRST, is released after the POR delay time SWITCHING ENABLED) expires. Reset Type Clock Source Determinant The time at which the device actually begins to execute code will also depend on the system oscillator delays, POR FNOSC<2:0> Configuration bits which include the Oscillator Start-up Timer (OST) and BOR (CW2<10:8>) the PLL lock time. The OST and PLL lock times occur MCLR in parallel with the applicable SYSRST delay times. COSC<2:0> Control bits WDTO The Fail-Safe Clock Monitor (FSCM) delay determines (OSCCON<14:12>) SWR the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released.  2013-2015 Microchip Technology Inc. DS30010038C-page 85

PIC24FJ128GA204 FAMILY TABLE 7-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS System Clock Reset Type Clock Source SYSRST Delay Notes Delay POR EC TPOR + TSTARTUP + TRST — 1, 2, 3 ECPLL TPOR + TSTARTUP + TRST TLOCK 1, 2, 3, 5 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST 1, 2, 3, 4 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK 1, 2, 3, 4, 5 FRC, FRCDIV TPOR + TSTARTUP + TRST TFRC 1, 2, 3, 6, 7 FRCPLL TPOR + TSTARTUP + TRST TFRC + TLOCK 1, 2, 3, 5, 6 LPRC TPOR + TSTARTUP + TRST TLPRC 1, 2, 3, 6 BOR EC TSTARTUP + TRST — 2, 3 ECPLL TSTARTUP + TRST TLOCK 2, 3, 5 XT, HS, SOSC TSTARTUP + TRST TOST 2, 3, 4 XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK 2, 3, 4, 5 FRC, FRCDIV TSTARTUP + TRST TFRC 2, 3, 6, 7 FRCPLL TSTARTUP + TRST TFRC + TLOCK 2, 3, 5, 6 LPRC TSTARTUP + TRST TLPRC 2, 3, 6 MCLR Any Clock TRST — 3 WDT Any Clock TRST — 3 Software Any clock TRST — 3 Illegal Opcode Any Clock TRST — 3 Uninitialized W Any Clock TRST — 3 Trap Conflict Any Clock TRST — 3 Note 1: TPOR = Power-on Reset Delay (10 s nominal). 2: TSTARTUP = TVREG. 3: TRST = Internal State Reset Time (2s nominal). 4: TOST = Oscillator Start-up Timer (OST). A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. 5: TLOCK = PLL Lock Time. 6: TFRC and TLPRC = RC Oscillator Start-up Times. 7: If Two-Speed Start-up is enabled, regardless of the Primary Oscillator selected, the device starts with FRC so the system clock delay is just TFRC, and in such cases, FRC start-up time is valid; it switches to the Primary Oscillator after its respective clock delay. 7.4.1 POR AND LONG OSCILLATOR The device will not begin to execute code until a valid START-UP TIMES clock source has been released to the system. There- fore, the oscillator and PLL start-up delays must be The oscillator start-up circuitry and its associated delay considered when the Reset delay time must be known. timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially 7.4.2 FAIL-SAFE CLOCK MONITOR low-frequency crystals) will have a relatively long (FSCM) AND DEVICE RESETS start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a • The oscillator circuit has not begun to oscillate. valid clock source is not available at this time, the • The Oscillator Start-up Timer has not expired (if a device will automatically switch to the FRC Oscillator crystal oscillator is used). and the user can switch to the desired crystal oscillator • The PLL has not achieved a lock (if PLL is used). in the Trap Service Routine (TSR). DS30010038C-page 86  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 8.0 INTERRUPT CONTROLLER 8.1.1 ALTERNATE INTERRUPT VECTOR TABLE Note: This data sheet summarizes the features The Alternate Interrupt Vector Table (AIVT) is located of this group of PIC24F devices. It is not after the IVT, as shown in Figure8-1. The ALTIVT intended to be a comprehensive refer- (INTCON2<15>) control bit provides access to the ence source. For more information, refer AIVT. If the ALTIVT bit is set, all interrupt and exception to the “dsPIC33/PIC24 Family Reference processes will use the alternate vectors instead of the Manual”, “Interrupts” (DS70000600). default vectors. The alternate vectors are organized in The information in this data sheet the same manner as the default vectors. supersedes the information in the FRM. The AIVT supports emulation and debugging efforts by The PIC24F interrupt controller reduces the numerous providing a means to switch between an application peripheral interrupt request signals to a single interrupt and a support environment without requiring the inter- request signal to the PIC24F CPU. It has the following rupt vectors to be reprogrammed. This feature also features: enables switching between applications for evaluation • Up to 8 processor exceptions and software traps of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with • Seven user-selectable priority levels the same addresses used in the IVT. • Interrupt Vector Table (IVT) with up to 118 vectors • Unique vector for each interrupt or exception 8.2 Reset Sequence source • Fixed priority within a specified user priority level A device Reset is not a true exception because the • Alternate Interrupt Vector Table (AIVT) for debug interrupt controller is not involved in the Reset process. support The PIC24F devices clear their registers in response to a Reset, which forces the PC to zero. The micro- • Fixed interrupt entry and return latencies controller then begins program execution at location, 000000h. The user programs a GOTO instruction at the 8.1 Interrupt Vector Table Reset address, which redirects program execution to The Interrupt Vector Table (IVT) is shown in Figure8-1. the appropriate start-up routine. The IVT resides in program memory, starting at location, Note: Any unimplemented or unused vector 000004h. The IVT contains 126 vectors, consisting of locations in the IVT and AIVT should be 8non-maskable trap vectors, plus up to 118 sources of programmed with the address of a default interrupt. In general, each interrupt source has its own interrupt handler routine that contains a vector. Each interrupt vector contains a 24-bit wide RESET instruction. address. The value programmed into each interrupt vec- tor location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt asso- ciated with Vector 0 will take priority over interrupts at any other vector address. PIC24FJ128GA204 family devices implement non- maskable traps and unique interrupts. These are summarized in Table8-1 and Table8-2.  2013-2015 Microchip Technology Inc. DS30010038C-page 87

PIC24FJ128GA204 FAMILY FIGURE 8-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction 000000h Reset – GOTO Address 000002h Reserved 000004h Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000014h Interrupt Vector 1 — — — Interrupt Vector 52 00007Ch Interrupt Vector 53 00007Eh Interrupt Vector Table (IVT)(1) Interrupt Vector 54 000080h y orit — Pri — er — d Interrupt Vector 116 0000FCh Or al Interrupt Vector 117 0000FEh ur Reserved 000100h at Reserved 000102h N g Reserved sin Oscillator Fail Trap Vector ea Address Error Trap Vector cr Stack Error Trap Vector e D Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 000114h Interrupt Vector 1 — — — Interrupt Vector 52 00017Ch Interrupt Vector 53 00017Eh Alternate Interrupt Vector Table (AIVT)(1) Interrupt Vector 54 000180h — — — Interrupt Vector 116 Interrupt Vector 117 0001FEh Start of Code 000200h Note 1: See Table8-2 for the interrupt vector list. TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h Reserved 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved DS30010038C-page 88  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector IRQ IVT AIVT Interrupt Source # # Address Address Flag Enable Priority ADC1 Interrupt 21 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 26 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 75 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 85 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> Cryptographic Operation Done 63 55 000082h 000182h IFS3<7> IEC3<7> IPC13<14:12> Cryptographic Key Store Program Done 64 56 000084h 000184h IFS3<8> IEC3<8> IPC14<2:0> Cryptographic Buffer Ready 42 34 000058h 000158h IFS2<2> IEC2<2> IPC8<10:8> Cryptographic Rollover 43 35 00005Ah 00015Ah IFS2<3> IEC2<3> IPC8<14:12> DMA Channel 0 12 4 00001Ch 00011Ch IFS0<4> IEC0<4> IPC1<2:0> DMA Channel 1 22 14 000030h 000130h IFS0<14> IEC0<14> IPC3<10:8> DMA Channel 2 32 24 000044h 000144h IFS1<8> IEC1<8> IPC6<2:0> DMA Channel 3 44 36 00005Ch 00015Ch IFS2<4> IEC2<4> IPC9<2:0> DMA Channel 4 54 46 000070h 000170h IFS2<14> IEC2<14> IPC11<10:8> DMA Channel 5 69 61 00008Eh 00018Eh IFS3<13> IEC3<13> IPC15<6:4> External Interrupt 0 8 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 28 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0> External Interrupt 2 37 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4> External Interrupt 3 61 53 00007Eh 00017Eh IFS3<5> IEC3<5> IPC13<6:4> External Interrupt 4 62 54 000080h 000180h IFS3<6> IEC3<6> IPC13<10:8> FRC Self-Tune 114 106 0000E8h 0001E8h IFS6<10> IEC6<10> IPC26<10:8> I2C1 Master Event 25 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4> I2C1 Slave Event 24 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0> I2C1 Bus Collision 92 84 0000BC 0001BC IFS5<4> IEC5<4> IPC21<2:0> I2C2 Master Event 58 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8> I2C2 Slave Event 57 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4> I2C2 Bus Collision. 93 85 0000BE 0001BE IFS5<5> IEC5<5> IPC21<6:4> Input Capture 1 9 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4> Input Capture 2 13 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4> Input Capture 3 45 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4> Input Capture 4 46 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8> Input Capture 5 47 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12> Input Capture 6 48 40 000064h 000164h IFS2<8> IEC2<8> IPC10<2:0> JTAG 125 117 0000FEh 0001FEh IFS7<5> IEC7<5> IPC29<6:4> Input Change Notification (ICN) 27 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12> High/Low-Voltage Detect (HLVD) 80 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC18<2:0> Output Compare 1 10 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8> Output Compare 2 14 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8> Output Compare 3 33 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4> Output Compare 4 34 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8> Output Compare 5 49 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4> Output Compare 6 50 42 000068h 000168h IFS2<10> IEC2<10> IPC10<10:8> Enhanced Parallel Master Port (EPMP) 53 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4> Real-Time Clock and Calendar (RTCC) 70 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8>  2013-2015 Microchip Technology Inc. DS30010038C-page 89

PIC24FJ128GA204 FAMILY TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector IRQ IVT AIVT Interrupt Source # # Address Address Flag Enable Priority SPI1 General 17 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4> SPI1 Transmit 18 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8> SPI1 Receive 66 58 000088h 000188h IFS3<10> IEC3<10> IPC14<10:8> SPI2 General 40 32 000054h 000154h IFS2<0> IEC2<0> IPC8<2:0> SPI2 Transmit 41 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4> SPI2 Receive 67 59 00008Ah 00018Ah IFS3<11> IEC3<11> IPC14<14:12> SPI3 General 98 90 0000C8h 0001C8h IFS5<10> IEC5<10> IPC22<10:8> SPI3 Transmit 99 91 0000CAh 0001CAh IFS5<11> IEC5<11> IPC22<14:12> SPI3 Receive 68 60 000054h 000154h IFS3<12> IEC3<12> IPC15<2:0> Timer1 11 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 15 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 16 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 35 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer5 36 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0> UART1 Error 73 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 19 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12> UART1 Transmitter 20 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0> UART2 Error 74 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8> UART2 Receiver 38 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2 Transmitter 39 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12> UART3 Error 89 81 0000B6h 0001B6h IFS5<1> IEC5<1> IPC20<6:4> UART3 Receiver 90 82 0000B8h 0001B8h IFS5<2> IEC5<2> IPC20<10:8> UART3 Transmitter 91 83 0000BAh 0001BAh IFS5<3> IEC5<3> IPC20<14:12> UART4 Error 95 87 0000C2h 0001C2h IFS5<7> IEC5<7> IPC21<14:12> UART4 Receiver 96 88 0000C4h 0001C4h IFS5<8> IEC5<8> IPC22<2:0> UART4 Transmitter 97 89 0000C6h 0001C6h IFS5<9> IEC5<9> IPC22<6:4> DS30010038C-page 90  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 8.3 Interrupt Control and Status The interrupt sources are assigned to the IFSx, IECx Registers and IPCx registers in the order of their vector numbers, as shown in Table8-2. For example, the INT0 (External The PIC24FJ128GA204 family of devices implements Interrupt 0) is shown as having a vector number and a a total of 43 registers for the interrupt controller: natural order priority of 0. Thus, the INT0IF status bit is • INTCON1 found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the INT0IP<2:0> priority bits in the first position of • INTCON2 IPC0 (IPC0<2:0>). • IFS0 through IFS7 Although they are not specifically part of the interrupt • IEC0 through IEC7 control hardware, two of the CPU Control registers con- • IPC0 through IPC16, IPC18 through IPC22, tain bits that control interrupt functionality. The ALU IPC26 and IPC29 STATUS Register (SR) contains the IPL<2:0> bits • INTTREG (SR<7:5>). These indicate the current CPU Interrupt Global interrupt control functions are controlled from Priority Level. The user can change the current CPU INTCON1 and INTCON2. INTCON1 contains the Inter- priority level by writing to the IPLx bits. rupt Nesting Disable (NSTDIS) bit, as well as the The CORCON register contains the IPL3 bit, which control and status flags for the processor trap sources. together with the IPL<2:0> bits, indicates the current The INTCON2 register controls the external interrupt CPU priority level. IPL3 is a read-only bit so that trap request signal behavior and the use of the Alternate events cannot be masked by the user software. Interrupt Vector Table (AIVT). The interrupt controller has the Interrupt Controller Test The IFSx registers maintain all of the interrupt request register, INTTREG, which displays the status of the flags. Each source of interrupt has a status bit, which is interrupt controller. When an interrupt request occurs, set by the respective peripherals or an external signal its associated vector number and the new Interrupt and is cleared via software. Priority Level are latched into INTTREG. This informa- The IECx registers maintain all of the interrupt enable tion can be used to determine a specific interrupt bits. These control bits are used to individually enable source if a generic ISR is used for multiple vectors interrupts from the peripherals or external signals. (such as when ISR remapping is used in bootloader applications) or to check if another interrupt is pending The IPCx registers are used to set the Interrupt Priority while in an ISR. Level (IPL) for each source of interrupt. Each user interrupt source can be assigned to one of eight priority All Interrupt registers are described in Register8-1 levels. through Register8-45 in the succeeding pages. The INTTREG register contains the associated interrupt vector number and the new CPU Interrupt Priority Level, which are latched into the Vector Number (VECNUM<7:0>) and the Interrupt Priority Level (ILR<3:0>) bit fields in the INTTREG register. The new Interrupt Priority Level is the priority of the pending interrupt.  2013-2015 Microchip Technology Inc. DS30010038C-page 91

PIC24FJ128GA204 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — DC(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL2(2,3) IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) Note 1: See Register3-1 for the description of the remaining bits (bits 8, 4, 3, 2, 1 and 0) that are not dedicated to interrupt control functions. 2: The IPLx bits are concatenated with the IPL3 (CORCON<3>) bit to form the CPU Interrupt Priority Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1. 3: The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1. DS30010038C-page 92  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-2: CORCON: CPU CORE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 r-1 U-0 U-0 — — — — IPL3(1) — — — bit 7 bit 0 Legend: r = Reserved bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU Interrupt Priority Level is greater than 7 0 = CPU Interrupt Priority Level is 7 or less bit 2 Reserved: Read as PSV bit bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level; see Register3-2 for bit description.  2013-2015 Microchip Technology Inc. DS30010038C-page 93

PIC24FJ128GA204 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as ‘0’ bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS30010038C-page 94  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses Alternate Interrupt Vector Table 0 = Uses standard (default) Interrupt Vector Table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 3 INT3EP: External Interrupt 3 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge  2013-2015 Microchip Technology Inc. DS30010038C-page 95

PIC24FJ128GA204 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IF AD1IF U1TXIF U1RXIF SPI1TXIF SPI1IF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF DMA0IF T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IF: DMA Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 AD1IF: A/D Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1TXIF: SPI1 Transmit Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 SPI1IF: SPI1 General Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA0IF: DMA Channel 0 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30010038C-page 96  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 2 OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2013-2015 Microchip Technology Inc. DS30010038C-page 97

PIC24FJ128GA204 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF T5IF T4IF OC4IF OC3IF DMA2IF bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF CMIF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 DMA2IF: DMA Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30010038C-page 98  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED) bit 2 CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2013-2015 Microchip Technology Inc. DS30010038C-page 99

PIC24FJ128GA204 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — DMA4IF PMPIF — — OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF DMA3IF CRYROLLIF CRYFREEIF SPI2TXIF SPI2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IF: DMA Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-11 Unimplemented: Read as ‘0’ bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 DMA3IF: DMA Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 CRYROLLIF: Cryptographic Rollover Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 CRYFREEIF: Cryptographic Buffer Free Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS30010038C-page 100  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 (CONTINUED) bit 1 SPI2TXIF: SPI2 Transmit Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPI2IF: SPI2 General Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred  2013-2015 Microchip Technology Inc. DS30010038C-page 101

PIC24FJ128GA204 FAMILY REGISTER 8-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 — RTCIF DMA5IF SPI3RXIF SPI2RXIF SPI1RXIF — KEYSTRIF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 CRYDNIF INT4IF INT3IF — — MI2C2IF SI2C2IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13 DMA5IF: DMA Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 SPI3RXIF: SPI3 Receive Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 SPI2RXIF: SPI2 Receive Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI1RXIF: SPI1 Receive Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 Unimplemented: Read as ‘0’ bit 8 KEYSTRIF: Cryptographic Key Store Program Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 CRYDNIF: Cryptographic Operation Done Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS30010038C-page 102  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIF: High/Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 103

PIC24FJ128GA204 FAMILY REGISTER 8-10: IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SPI3TXIF SPI3IF U4TXIF U4RXIF bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIF — I2C2BCIF I2C1BCIF U3TXIF U3RXIF U3ERIF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 SPI3TXIF: SPI3 Transmit Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 SPI3IF: SPI3 General Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 Unimplemented: Read as ‘0’ bit 5 I2C2BCIF: I2C2 Bus Collision Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4 I2C1BCIF: I2C1 Bus Collision Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 3 U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ DS30010038C-page 104  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-11: IFS6: INTERRUPT FLAG STATUS REGISTER 6 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — FSTIF — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 FSTIF: FRC Self-Tune Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9-0 Unimplemented: Read as ‘0’ REGISTER 8-12: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — JTAGIF — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 JTAGIF: JTAG Controller Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 105

PIC24FJ128GA204 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DMA1IE AD1IE U1TXIE U1RXIE SPI1TXIE SPI1IE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE DMA0IE T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA1IE: DMA Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 AD1IE: A/D Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1TXIE: SPI1 Transmit Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 SPI1IE: SPI1 General Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 DMA0IE: DMA Channel 0 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS30010038C-page 106  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-13: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2013-2015 Microchip Technology Inc. DS30010038C-page 107

PIC24FJ128GA204 FAMILY REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE(1) T5IE T4IE OC4IE OC3IE DMA2IE bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE(1) CNIE CMIE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 14 U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 DMA2IE: DMA Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. DS30010038C-page 108  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-14: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) bit 2 CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2013-2015 Microchip Technology Inc. DS30010038C-page 109

PIC24FJ128GA204 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — DMA4IE PMPIE — — OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE DMA3IE CRYROLLIE CRYFREEIE SPI2TXIE SPI2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 DMA4IE: DMA Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-11 Unimplemented: Read as ‘0’ bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 DMA3IE: DMA Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 CRYROLLIE: Cryptographic Rollover Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 CRYFREEIE: Cryptographic Buffer Free Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS30010038C-page 110  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-15: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 (CONTINUED) bit 1 SPI2TXIE: SPI2 Transmit Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 SPI2IE: SPI2 General Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled  2013-2015 Microchip Technology Inc. DS30010038C-page 111

PIC24FJ128GA204 FAMILY REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 — RTCIE DMA5IE SPI3RXIE SPI2RXIE SPI1RXIE — KEYSTRIE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 CRYDNIE INT4IE(1) INT3IE(1) — — MI2C2IE SI2C2IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 13 DMA5IE: DMA Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12 SPI3RXIE: SPI3 Receive Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 11 SPI2RXIE: SPI2 Receive Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI1RXIE: SPI1 Receive Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 Unimplemented: Read as ‘0’ bit 8 KEYSTRIE: Cryptographic Key Store Program Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 CRYDNIE: Cryptographic Operation Done Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 5 INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-3 Unimplemented: Read as ‘0’ bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. DS30010038C-page 112  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-16: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 (CONTINUED) bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ Note 1: If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2013-2015 Microchip Technology Inc. DS30010038C-page 113

PIC24FJ128GA204 FAMILY REGISTER 8-17: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-9 Unimplemented: Read as ‘0’ bit 8 HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7-4 Unimplemented: Read as ‘0’ bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’ DS30010038C-page 114  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-18: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — SPI3TXIE SPI3IE U4TXIE U4RXIE bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U4ERIE — I2C2BCIE I2C1BCIE U3TXIE U3RXIE U3ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 Unimplemented: Read as ‘0’ bit 11 SPI3TXIE: SPI3 Transmit Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 10 SPI3IE: SPI3 General Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9 U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 8 U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 7 U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 6 Unimplemented: Read as ‘0’ bit 5 I2C2BCIE: I2C2 Bus Collision Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4 I2C1BCIE: I2C1 Bus Collision Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 3 U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 2 U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 1 U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 115

PIC24FJ128GA204 FAMILY REGISTER 8-19: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — FSTIE — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 FSTIE: FRC Self-Tune Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 9-0 Unimplemented: Read as ‘0’ REGISTER 8-20: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — JTAGIE — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5 JTAGIE: JTAG Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 4-0 Unimplemented: Read as ‘0’ DS30010038C-page 116  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-21: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 INT0IP<2:0>: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 117

PIC24FJ128GA204 FAMILY REGISTER 8-22: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T2IP2 T2IP1 T2IP0 — OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC2IP2 IC2IP1 IC2IP0 — DMA0IP2 DMA0IP1 DMA0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA0IP<2:0>: DMA Channel 0 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 118  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-23: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1TXIP2 SPI1TXIP1 SPI1TXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI1IP2 SPI1IP1 SPI1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1TXIP<2:0>: SPI1 Transmit Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI1IP<2:0>: SPI1 General Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T3IP<2:0>: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 119

PIC24FJ128GA204 FAMILY REGISTER 8-24: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA1IP2 DMA1IP1 DMA1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA1IP<2:0>: DMA Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 AD1IP<2:0>: A/D Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 120  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-25: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1IP2 MI2C1IP1 MI2C1IP0 — SI2C1IP2 SI2C1IP1 SI2C1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Input Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CMIP<2:0>: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 MI2C1IP<2:0>: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SI2C1IP<2:0>: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 121

PIC24FJ128GA204 FAMILY REGISTER 8-26: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 122  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-27: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T4IP2 T4IP1 T4IP0 — OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC3IP2 OC3IP1 OC3IP0 — DMA2IP2 DMA2IP1 DMA2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 T4IP<2:0>: Timer4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA2IP<2:0>: DMA Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 123

PIC24FJ128GA204 FAMILY REGISTER 8-28: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — INT2IP2 INT2IP1 INT2IP0 — T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 T5IP<2:0>: Timer5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 124  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-29: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRYROLLIP2 CRYROLLIP1 CRYROLLIP0 — CRYFREEIP2 CRYFREEIP1 CRYFREEIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2TXIP2 SPI2TXIP1 SPI2TXIP0 — SPI2IP2 SPI2IP1 SPI2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRYROLLIP<2:0>: Cryptographic Rollover Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 CRYFREEIP<2:0>: Cryptographic Buffer Free Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SPI2TXIP<2:0>: SPI2 Transmit Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI2IP<2:0>: SPI2 General Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 125

PIC24FJ128GA204 FAMILY REGISTER 8-30: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC5IP2 IC5IP1 IC5IP0 — IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC3IP2 IC3IP1 IC3IP0 — DMA3IP2 DMA3IP1 DMA3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 IC5IP<2:0>: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 IC4IP<2:0>: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 IC3IP<2:0>: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 DMA3IP<2:0>: DMA Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 126  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-31: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — OC5IP2 OC5IP1 OC5IP0 — IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 OC6IP<2:0>: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 OC5IP<2:0>: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 IC6IP<2:0>: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 127

PIC24FJ128GA204 FAMILY REGISTER 8-32: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — DMA4IP2 DMA4IP1 DMA4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — PMPIP2 PMPIP1 PMPIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 DMA4IP<2:0>: DMA Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 PMPIP<2:0>: Parallel Master Port Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30010038C-page 128  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-33: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — MI2C2IP2 MI2C2IP1 MI2C2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — SI2C2IP2 SI2C2IP1 SI2C2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 MI2C2IP<2:0>: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 SI2C2IP<2:0>: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 129

PIC24FJ128GA204 FAMILY REGISTER 8-34: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRYDNIP2 CRYDNIP1 CRYDNIP0 — INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT3IP2 INT3IP1 INT3IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRYDNIP<2:0>: Cryptographic Operation Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 INT4IP<2:0>: External Interrupt 4 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 INT3IP<2:0>: External Interrupt 3 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30010038C-page 130  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-35: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI2RXIP2 SPI2RXIP1 SPI2RXIPO — SPI1RXIP2 SPI1RXIP1 SPI1RXIPO bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — KEYSTRIP2 KEYSTRIP1 KEYSTRIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 SPI2RXIP<2:0>: SPI2 Receive Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI1RXIP<2:0>: SPI1 Receive Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 KEYSTRIP<2:0>: Cryptographic Key Store Program Done Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 131

PIC24FJ128GA204 FAMILY REGISTER 8-36: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — DMA5IP2 DMA5IP1 DMA5IP0 — SPI3RXIP2 SPI3RXIP1 SPI3RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 DMA5IP<2:0>: DMA Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 SPI3RXIP<2:0>: SPI3 Receive Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 132  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-37: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC Generator Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U2ERIP<2:0>: UART2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U1ERIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 133

PIC24FJ128GA204 FAMILY REGISTER 8-38: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 8-39: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — CTMUIP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 CTMUIP<2:0>: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30010038C-page 134  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-40: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U3TXIP2 U3TXIP1 U3TXIP0 — U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U3ERIP2 U3ERIP1 U3ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U3TXIP<2:0>: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 U3RXIP<2:0>: UART3 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U3ERIP<2:0>: UART3 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 135

PIC24FJ128GA204 FAMILY REGISTER 8-41: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U4ERIP2 U4ERIP1 U4ERIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — I2C2BCIP2 I2C2BCIP1 I2C2BCIP0 — I2C1BCIP2 I2C1BCIP1 I2C1BCIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 U4ERIP<2:0>: UART4 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11-7 Unimplemented: Read as ‘0’ bit 6-4 I2C2BCIP<2:0>: I2C2 Bus Collision Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 I2C1BCIP<2:0>: I2C1 Bus Collision Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled DS30010038C-page 136  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-42: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPI3TXIP2 SPI3TXIP1 SPI3TXIP0 — SPI3IP2 SPI3IP1 SPI3IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U4TXIP2 U4TXIP1 U4TXIP0 — U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 SPI3TXIP<2:0>: SPI3 Transmit Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-8 SPI3IP<2:0>: SPI3 General Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as ‘0’ bit 6-4 U4TXIP<2:0>: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U4RXIP<2:0>: UART4 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2013-2015 Microchip Technology Inc. DS30010038C-page 137

PIC24FJ128GA204 FAMILY REGISTER 8-43: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — FSTIP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 FSTIP<2:0>: FRC Self-Tune Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as ‘0’ REGISTER 8-44: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — JTAGIP<2:0> — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 JTAGIP<2:0>: JTAG Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS30010038C-page 138  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 8-45: INTTREG: INTERRUPT CONTROLLER TEST REGISTER R-0 r-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VECNUM7 VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: CPU Interrupt Request from Interrupt Controller bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU 0 = No interrupt request is unacknowledged bit 14 Reserved: Maintain as ‘0’ bit 13 VHOLD: Vector Number Capture Configuration bit 1 = VECNUM<7:0> contain the value of the highest priority pending interrupt 0 = VECNUM<7:0> contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) bit 12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 bit 7-0 VECNUM<7:0>: Vector Number of Pending Interrupt or Last Acknowledged Interrupt bits When VHOLD = 1: Indicates the vector number (from 0 to 118) of the last interrupt to occur. When VHOLD = 0: Indicates the vector number (from 0 to 118) of the interrupt request currently being handled.  2013-2015 Microchip Technology Inc. DS30010038C-page 139

PIC24FJ128GA204 FAMILY 8.4 Interrupt Setup Procedures 8.4.3 TRAP SERVICE ROUTINE (TSR) A Trap Service Routine (TSR) is coded like an ISR, 8.4.1 INITIALIZATION except that the appropriate trap status flag in the To configure an interrupt source: INTCON1 register must be cleared to avoid re-entry into the TSR. 1. Set the NSTDIS (INTCON1<15>) control bit if nested interrupts are not desired. 8.4.4 INTERRUPT DISABLE 2. Select the user-assigned priority level for the interrupt source by writing the control bits in the All user interrupts can be disabled using the following appropriate IPCx register. The priority level will procedure: depend on the specific application and type of 1. Push the current SR value onto the software interrupt source. If multiple priority levels are not stack using the PUSH instruction. desired, the IPCx register control bits for all 2. Force the CPU to Priority Level 7 by inclusive enabled interrupt sources may be programmed ORing the value, 0Eh, with SRL. to the same non-zero value. To enable user interrupts, the POP instruction may be Note: At a device Reset, the IPCx registers are used to restore the previous SR value. initialized, such that all user interrupt Note that only user interrupts with a priority level of 7 or sources are assigned to Priority Level 4. less can be disabled. Trap sources (Levels8-15) 3. Clear the interrupt flag status bit associated with cannot be disabled. the peripheral in the associated IFSx register. The DISI instruction provides a convenient way to 4. Enable the interrupt source by setting the disable interrupts of Priority Levels 1-6 for a fixed interrupt enable control bit associated with the period of time. Level 7 interrupt sources are not source in the appropriate IECx register. disabled by the DISI instruction. 8.4.2 INTERRUPT SERVICE ROUTINE (ISR) The method that is used to declare an Interrupt Service Routine (ISR) and initialize the IVT with the correct vec- tor address will depend on the programming language (i.e., ‘C’ or assembler), and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles; otherwise, the ISR will be re- entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS30010038C-page 140  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 9.0 OSCILLATOR CONFIGURATION • Software-controllable switching between various clock sources Note: This data sheet summarizes the features of • Software-controllable postscaler for selective this group of PIC24F devices. It is not clocking of CPU for system power savings intended to be a comprehensive reference • A Fail-Safe Clock Monitor (FSCM) that detects source. For more information, refer to clock failure and permits safe application recovery the “dsPIC33/PIC24 Family Reference or shutdown Manual”, “Oscillator” (DS39700). • A separate and independently configurable system The oscillator system for PIC24FJ128GA204 family clock output for synchronizing external hardware devices has the following features: A simplified diagram of the oscillator system is shown in • A total of four external and internal oscillator options Figure9-1. as clock sources, providing 15 different Clock modes • An on-chip PLL (x4, x6, x8) block available for the Primary Oscillator (POSC) source or FRCDIV (see Section9.7 “On-Chip PLL”) FIGURE 9-1: PIC24FJ128GA204 FAMILY CLOCK DIAGRAM PIC24FJXXXGA2XX Family Primary Oscillator REFOCON<15:8> XT, HS, EC OSCO Reference Clock Generator OSCI PLL(2) XTxPLL, HSxPLL, REFO x4 ECxPLL, FRCxPLL(1) x6 x8 8 MHz 8 MHz er 4 MHz FRC (nominal) al FRCDIV c Oscillator sts Peripherals o P CLKDIV<10:8> Reference FRC FRC Self-Tune SOSC CLKO Control er al CPU LPRC 31 kHz (nominal) LPRC sc Oscillator st o P Secondary Oscillator CLKDIV<14:12> SOSC SOSCO SOSCEN Clock Control Logic Enable Fail-Safe SOSCI Oscillator Clock Monitor WDT, PWRT Clock Source Option for Other Modules Note 1: x denotes 4, 6 or 8. 2: The on-chip PLL can be configured using the PLLDIV<3:0> Configuration bits.  2013-2015 Microchip Technology Inc. DS30010038C-page 141

PIC24FJ128GA204 FAMILY 9.1 CPU Clocking Scheme 9.2 Initial Configuration on POR The system clock source can be provided by one of The oscillator source (and operating mode) that is used four sources: at a device Power-on Reset event is selected using Configuration bit settings. The Oscillator Configuration • Primary Oscillator (POSC) on the OSCI and bit settings are located in the Configuration registers in OSCO pins program memory (for more information, refer to • Secondary Oscillator (SOSC) on the SOSCI and Section29.1 “Configuration Bits”). The Primary SOSCO pins Oscillator Configuration bits, POSCMD<1:0> (Configu- • Fast Internal RC (FRC) Oscillator ration Word 2<1:0>), and the Initial Oscillator Select • Low-Power Internal RC (LPRC) Oscillator Configuration bits, FNOSC<2:0> (Configuration The internal FRC provides an 8 MHz clock source. It Word2<10:8>), select the oscillator source that is used at a Power-on Reset. The FRC Primary Oscillator with can optionally be reduced by the programmable clock Postscaler (FRCDIV) is the default (unprogrammed) divider to provide a range of system clock frequencies. selection. The Secondary Oscillator, or one of the inter- The selected clock source generates the processor nal oscillators, may be chosen by programming these bit and peripheral clock sources. The processor clock locations. source is divided by two to produce the internal instruc- tion cycle clock, FCY. In this document, the instruction The Configuration bits allow users to choose between cycle clock is also denoted by FOSC/2. The internal the various clock modes, as shown in Table9-1. instruction cycle clock, FOSC/2, can be provided on the 9.2.1 CLOCK SWITCHING MODE OSCO I/O pin for some operating modes of the Primary CONFIGURATION BITS Oscillator. The FCKSM<1:0> Configuration bits (Configuration Word2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when FCKSM<1:0> are both programmed (‘00’). TABLE 9-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Notes Fast RC Oscillator with Postscaler Internal 11 111 1, 2 (FRCDIV) (Reserved) Internal xx 110 1 Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary (Timer1) Oscillator Secondary 11 100 1 (SOSC) Primary Oscillator (XT) with PLL Primary 01 011 Module (XTPLL) Primary Oscillator (EC) with PLL Primary 00 011 Module (ECPLL) Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module Internal 11 001 1 (FRCPLL) Fast RC Oscillator (FRC) Internal 11 000 1 Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. DS30010038C-page 142  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 9.3 Control Registers The CLKDIV register (Register9-2) controls the features associated with Doze mode, as well as the The operation of the oscillator is controlled by three postscaler for the FRC Oscillator. Special Function Registers: The OSCTUN register (Register9-3) allows the user to • OSCCON fine-tune the FRC Oscillator over a range of approxi- • CLKDIV mately ±1.5%. It also controls the FRC self-tuning • OSCTUN features described in Section9.5 “FRC Self-Tuning”. The OSCCON register (Register9-1) is the main con- trol register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1) — COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 R/W-0 R/W-0 R/W-0 CLKLOCK IOLOCK(2) LOCK — CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clearable Only bit SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC<2:0>: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC<2:0>: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits. 2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.  2013-2015 Microchip Technology Inc. DS30010038C-page 143

PIC24FJ128GA204 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enable bit If FSCM is Enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is Disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator (POSC) Sleep Enable bit 1 = Primary Oscillator continues to operate during Sleep mode 0 = Primary Oscillator is disabled during Sleep mode bit 1 SOSCEN: 32kHz Secondary Oscillator (SOSC) Enable bit 1 = Enables Secondary Oscillator 0 = Disables Secondary Oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiates an oscillator switch to a clock source specified by the NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: Reset values for these bits are determined by the FNOSCx Configuration bits. 2: The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. 3: This bit also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. DS30010038C-page 144  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — PLLEN — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE<2:0>: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: Doze Mode Enable bit(1) 1 = DOZE<2:0> bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio is set to 1:1 bit 10-8 RCDIV<2:0>: FRC Postscaler Select bits 111 = 31.25kHz (divide-by-256) 110 = 125kHz (divide-by-64) 101 = 250kHz (divide-by-32) 100 = 500kHz (divide-by-16) 011 = 1MHz (divide-by-8) 010 = 2MHz (divide-by-4) 001 = 4MHz (divide-by-2) 000 = 8MHz (divide-by-1) bit 7-6 Unimplemented: Read as ‘0’ bit 5 PLLEN: PLL Enable bit 1 = PLL is enabled 0 = PLL is disabled bit 4-0 Unimplemented: Read as ‘0’ Note 1: This bit is automatically cleared when the ROI bit is set and an interrupt occurs.  2013-2015 Microchip Technology Inc. DS30010038C-page 145

PIC24FJ128GA204 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER R/W-0 U-0 R/W-0 R/W-0 R-0 R/W-0 R-0 R/W-0 STEN — STSIDL STSRC(1) STLOCK STLPOL STOR STORPOL bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 STEN: FRC Self-Tune Enable bit 1 = FRC self-tuning is enabled; TUNx bits are controlled by hardware 0 = FRC self-tuning is disabled; application may optionally control TUNx bits bit 14 Unimplemented: Read as ‘0’ bit 13 STSIDL: FRC Self-Tune Stop in Idle bit 1 = Self-tuning stops during Idle mode 0 = Self-tuning continues during Idle mode bit 12 STSRC: FRC Self-Tune Reference Clock Source bit(1) 1 = Reserved 0 = FRC is tuned to approximately match the 32.768kHz SOSC tolerance bit 11 STLOCK: FRC Self-Tune Lock Status bit 1 = FRC accuracy is currently within ±0.2% of the STSRC reference accuracy 0 = FRC accuracy may not be within ±0.2% of the STSRC reference accuracy bit 10 STLPOL: FRC Self-Tune Lock Interrupt Polarity bit 1 = A self-tune lock interrupt is generated when STLOCK = 0 0 = A self-tune lock interrupt is generated when STLOCK = 1 bit 9 STOR: FRC Self-Tune Out of Range Status bit 1 = STSRC reference clock error is beyond the range of TUN<5:0>; no tuning is performed 0 = STSRC reference clock is within the tunable range; tuning is performed bit 8 STORPOL: FRC Self-Tune Out of Range Interrupt Polarity bit 1 = A self-tune out of range interrupt is generated when STOR is = 0 0 = A self-tune out of range interrupt is generated when STOR is = 1 bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Maximum frequency deviation 011110 = • • • 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 = • • • 100001 = 100000 = Minimum frequency deviation Note 1: Use of either clock recovery source has specific application requirements. For more information, see Section9.5 “FRC Self-Tuning”. DS30010038C-page 146  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 9.4 Clock Switching Operation Once the basic sequence is completed, the system clock hardware responds automatically as follows: With few limitations, applications are free to switch 1. The clock switching hardware compares the between any of the four clock sources (POSC, SOSC, COSCx bits with the new value of the NOSCx FRC and LPRC) under software control and at any bits. If they are the same, then the clock switch time. To limit the possible side effects that could result is a redundant operation. In this case, the from this flexibility, PIC24F devices have a safeguard OSWEN bit is cleared automatically and the lock built into the switching process. clock switch is aborted. Note: The Primary Oscillator mode has three 2. If a valid clock switch has been initiated, the different submodes (XT, HS and EC), LOCK (OSCCON<5>) and CF (OSCCON<3>) which are determined by the POSCMDx bits are cleared. Configuration bits. While an application 3. The new oscillator is turned on by the hardware can switch to and from Primary Oscillator if it is not currently running. If a crystal oscillator mode in software, it cannot switch must be turned on, the hardware will wait until between the different primary submodes the OST expires. If the new source is using the without reprogramming the device. PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). 9.4.1 ENABLING CLOCK SWITCHING 4. The hardware waits for 10 clock cycles from the To enable clock switching, the FCKSM1 Configuration new clock source and then performs the clock bit in CW2 must be programmed to ‘0’. (For more infor- switch. mation, refer to Section29.1 “Configuration Bits”.) If 5. The hardware clears the OSWEN bit to indicate a the FCKSM1 Configuration bit is unprogrammed (‘1’), successful clock transition. In addition, the NOSCx the clock switching function and Fail-Safe Clock bit values are transferred to the COSCx bits. Monitor function are disabled; this is the default setting. 6. The old clock source is turned off at this time, The NOSCx control bits (OSCCON<10:8>) do not control with the exception of LPRC (if WDT or FSCM is the clock selection when clock switching is disabled. enabled) or SOSC (if SOSCEN remains set). However, the COSC<2:0> bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSCx Note1: The processor will continue to execute Configuration bits. code throughout the clock switching sequence. Timing-sensitive code should The OSWEN control bit (OSCCON<0>) has no effect not be executed during this time. when clock switching is disabled; it is held at ‘0’ at all times. 2: Direct clock switches between any Primary Oscillator mode with PLL and 9.4.2 OSCILLATOR SWITCHING FRCPLL mode are not permitted. This SEQUENCE applies to clock switches in either direc- tion. In these instances, the application At a minimum, performing a clock switch requires this must switch to FRC mode as a transitional basic sequence: clock source between the two PLL modes. 1. If desired, read the COSCx bits (OSCCON<14:12>) to determine the current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON register high byte. 3. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. 4. Perform the unlock sequence to allow a write to the OSCCON register low byte. 5. Set the OSWEN bit to initiate the oscillator switch.  2013-2015 Microchip Technology Inc. DS30010038C-page 147

PIC24FJ128GA204 FAMILY A recommended code sequence for a clock switch 9.5 FRC Self-Tuning includes the following: PIC24FJ128GA204 family devices include an automatic 1. Disable interrupts during the OSCCON register mechanism to calibrate the FRC during run time. This unlock and write sequence. system uses clock recovery from a source of known 2. Execute the unlock sequence for the OSCCON accuracy to maintain the FRC within a very narrow high byte by writing 78h and 9Ah to margin of its nominal 8MHz frequency. This allows for a OSCCON<15:8> in two back-to-back instructions. frequency accuracy that exceeds 0.25%, which is well 3. Write the new oscillator source to the NOSCx within the requirements. bits in the instruction immediately following the The self-tune system is controlled by the bits in the unlock sequence. upper half of the OSCTUN register. Setting the STEN 4. Execute the unlock sequence for the OSCCON bit (OSCTUN<15>) enables the system, causing it to low byte by writing 46h and 57h to recover a calibration clock from a source selected by OSCCON<7:0> in two back-to-back instructions. the STSRC bit (OSCTUN<12>). When STSRC = 0, the 5. Set the OSWEN bit in the instruction system uses the crystal controlled SOSC for its calibra- immediately following the unlock sequence. tion source. Regardless of the source, the system uses 6. Continue to execute code that is not clock- sensitive the TUN<5:0> bits (OSCTUN<5:0>) to change the (optional). FRC’s frequency. Frequency monitoring and adjust- ment is dynamic, occurring continuously during run 7. Invoke an appropriate amount of software delay time. While the system is active, the TUNx bits cannot (cycle counting) to allow the selected oscillator be written to by software. and/or PLL to start and stabilize. 8. Check to see if OSWEN is ‘0’. If it is, the switch Note: If the SOSC is to be used as the clock was successful. If OSWEN is still set, then recovery source (STSRC = 0), the SOSC check the LOCK bit to determine the cause of must always be enabled. the failure. The self-tune system can generate a hardware inter- The core sequence for unlocking the OSCCON register rupt, FSTIF. The interrupt can result from a drift of the and initiating a clock switch is shown in Example9-1. FRC from the reference by greater than 0.2% in either direction or whenever the frequency deviation is EXAMPLE 9-1: BASIC CODE SEQUENCE beyond the ability of the TUNx bits to correct (i.e., FOR CLOCK SWITCHING greater than 1.5%). The STLOCK and STOR status bits (OSCTUN<11,9>) are used to indicate these ;Place the new oscillator selection in W0 conditions. ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 The STLPOL and STORPOL bits (OSCTUN<10,8>) MOV #0x78, w2 configure the FSTIF interrupt to occur in the presence MOV #0x9A, w3 or the absence of the conditions. It is the user’s respon- MOV.b w2, [w1] sibility to monitor both the STLOCK and STOR bits to MOV.b w3, [w1] determine the exact cause of the interrupt. ;Set new oscillator selection MOV.b WREG, OSCCONH Note: The STLPOL and STORPOL bits should ;OSCCONL (low byte) unlock sequence be ignored when the self-tune system is MOV #OSCCONL, w1 disabled (STEN = 0). MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 DS30010038C-page 148  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 9.6 Reference Clock Output The ROTRIMx and RODIVx bits can be changed on- the-fly. Follow the below mentioned steps before In addition to the CLKO output (FOSC/2) available in changing the ROTRIMx and RODIVx bits. certain Oscillator modes, the device clock in the • REFO is not actively performing the divider switch PIC24FJ128GA204 family devices can also be config- (ROSWEN = 0). ured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configura- • Update the ROTRIMx and RODIVx bits with the tions and allows the user to select a greater range of latest values. clock submultiples to drive external devices in the • Set the ROSWEN bit. application. • Wait for the ROSWEN bit to be cleared by hardware. This reference clock output is controlled by the The ROTRIMx bits allow a fractional divisor to be added REFOCONL, REFOCONH and REFOTRIML registers to the integer divisor, specified in the RODIVx bits. (Register9-4, Register9-5 and Register9-6). Setting the ROEN bit (REFOCONL<15>) enables the module. EQUATION 9-1: FRACTIONAL DIVISOR Setting the ROOUT bit (REFOCONL<12>) makes the FOR ROTRIMx BITS clock signal available on the REFO pin. For RODIV<14:0> = 0, No Divide: The RODIVx bits (REFOCONH<14:0>) enable the RODIV<14:0> > 0, Period = 2 * (RODIVx + ROTRIMx) selection of 32768 different clock divider options. 9.6.3 OPERATION IN SLEEP MODE 9.6.1 CLOCK SOURCE REQUEST The ROSLP and ROSELx bits (REFOCONL<11,3:0>) The ROSEL<3:0> bits determine different base clock control the availability of the reference output during sources for the module. Sleep mode. If the selected clock source has a global device enable The ROSLP bit determines if the reference source is (via device Configuration Fuse settings), the user must available on the REFO pin when the device is in Sleep enable the clock source before selecting it as a base mode. clock source. To use the reference clock output in Sleep mode, the The ROACTIVE bit (REFOCONL<8>) synchronizes ROSLP bit must be set and the reference base clock the REFO module during the turn on and turn off of the should not be the system clock or peripheral clock module. (ROSELx bits should not be ‘0b0000’ or ‘0b0001’). Note: Once the ROEN bit is set, it should not be The device clock must also be configured for either: cleared until the ROACTIVE bit is read as ‘1’. • One of the Primary modes (EC, HS or XT); the POSCEN bit should be set 9.6.2 CLOCK SWITCHING • The Secondary Oscillator bit (SOSCEN) should be set The base clock to the module can be switched. First, • The LPRC Oscillator turn off the module by clearing the ROEN bit (REFOCONL<15> = 0) and wait for the ROACTIVE If one of the above conditions is not met, then the oscil- (REFOCONL<8>) bit to be cleared by the hardware. lators on OSC1, OSC2 and SOSCI will be powered down when the device enters Sleep mode. This avoids a glitch in the REFO output.  2013-2015 Microchip Technology Inc. DS30010038C-page 149

PIC24FJ128GA204 FAMILY REGISTER 9-4: REFOCONL: REFERENCE OSCILLATOR CONTROL LOW REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ROEN — ROSIDL ROOUT ROSLP — ROSWEN ROACTIVE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — ROSEL3 ROSEL2 ROSEL1 ROSEL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled 0 = Reference oscillator is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 ROSIDL: Reference Oscillator Output in Idle Mode bit 1 = Reference oscillator is disabled in Idle mode 0 = Reference oscillator continues to run in Idle mode bit 12 ROOUT: Reference Clock Output Enable bit 1 = REFO clock output is driven on the REFO pin 0 = REFO clock output is disabled bit 11 ROSLP: Reference Oscillator Output in Sleep Mode bit 1 = Reference oscillator output continues to run in Sleep mode 0 = Reference oscillator output is disabled in Sleep mode bit 10 Unimplemented: Read as ‘0’ bit 9 ROSWEN: Reference Oscillator Clock Source Switch Enable bit 1 = Reference clock source switching is currently in progress 0 = Reference clock source switching has completed bit 8 ROACTIVE: Reference Clock Request Status bit 1 = Reference clock request is active (user should not update the REFOCONL register) 0 = Reference clock request is not active (user can update the REFOCONL register) bit 7-4 Unimplemented: Read as ‘0’ (Reserved for additional ROSELx bits.) bit 3-0 ROSEL<3:0>: Reference Clock Source Select bits Selects one of the various clock sources to be used as the reference clock: 1001-1111 = Reserved 1000 = REFI (Reference Clock Input) 0111 = Reserved 0110 = 8x PLL 0101 = Secondary Oscillator (SOSC) 0100 = Low-Power RC Oscillator (LPRC) 0011 = Fast RC Oscillator (FRC) 0010 = Primary Oscillator (XT, HS, EC) 0001 = Peripheral Clock (PBCLK) – internal instruction cycle clock, FCY 0000 = System Clock (FOSC) DS30010038C-page 150  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 9-5: REFOCONH: REFERENCE OSCILLATOR CONTROL HIGH REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RODIV<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RODIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 RODIV<14:0>: Reference Oscillator Divisor Select bits (Specifies the 1/2 period of the reference clock in the source clocks.) For example: Period of ref_clk_output  [Reference Source * 2] * RODIV<14:0> 111111111111111 = REFO clock is the base clock frequency divided by 65,534 (32,767 * 2) 111111111111110 = REFO clock is the base clock frequency divided by 65,532 (32,766 * 2) • • • 000000000000011 = REFO clock is the base clock frequency divided by 6 (3 * 2) 000000000000010 = REFO clock is the base clock frequency divided by 4 (2 * 2) 000000000000001 = REFO clock is the base clock frequency divided by 2 (1 * 2) 000000000000000 = REFO clock is the same frequency as the base clock (no divider)(1) Note 1: The ROTRIMx values are ignored.  2013-2015 Microchip Technology Inc. DS30010038C-page 151

PIC24FJ128GA204 FAMILY REGISTER 9-6: REFOTRIML: REFERENCE OSCILLATOR TRIM REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROTRIM<15:8> bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 ROTRIM7 — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 ROTRIM<15:7>: Reference Oscillator Trim bits Provides fractional additive to the RODIVx value for the 1/2 period of the REFO clock. 111111111 = 511/512 (0.998046875) divisor added to RODIVx value 111111110 = 510/512 (0.99609375) divisor added to RODIVx value • • • 100000000 = 256/512 (0.5000) divisor added to RODIVx value • • • 000000010 = 2/512 (0.00390625) divisor added to RODIVx value 000000001 = 1/512 (0.001953125) divisor added to RODIVx value 000000000 = 0/512 (0.0) divisor added to RODIVx value bit 6-0 Unimplemented: Read as ‘0’ DS30010038C-page 152  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 9.7 On-Chip PLL Using the internal FRC source, the PLL module can generate the following frequencies, as shown in An on-chip PLL (x4, x6, x8) can be selected by the Table9-2. Configuration Fuse bits, PLLDIV<3:0>. The Primary Oscillator and FRC sources (FRCDIV) have the option of using this PLL. TABLE 9-2: VALID FRC CONFIGURATION FOR ON-CHIP PLL(1) RCDIV<2:0> FRC x4 PLL x6 PLL x8 PLL (FRCDIV) 8 MHz 000 (divide-by-1) 32 MHz — — 8 MHz 001 (divide-by-2) 16 MHz 24 MHz 32 MHz 8 MHz 010 (divide-by-4) 8 MHz 12 MHz 16 MHz Note 1: The minimum frequency input to the on-chip PLL is 2 MHz.  2013-2015 Microchip Technology Inc. DS30010038C-page 153

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 154  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 10.0 POWER-SAVING FEATURES 10.1 Overview of Power-Saving Modes Note: This data sheet summarizes the features In addition to full-power operation, otherwise known as of this group of PIC24F devices. It is Run mode, the PIC24FJ128GA204 family of devices not intended to be a comprehensive offers three instruction-based, power-saving modes reference source. For more information, and one hardware-based mode: refer to the “dsPIC33/PIC24 Family • Idle Reference Manual”, “Power-Saving • Sleep (Sleep and Low-Voltage Sleep) Features with Deep Sleep” (DS39727). • Deep Sleep The PIC24FJ128GA204 family of devices provides the • VBAT (with and without RTCC) ability to manage power consumption by selectively man- All four modes can be activated by powering down aging clocking to the CPU and the peripherals. In general, different functional areas of the microcontroller, allow- a lower clock frequency and a reduction in the number of ing progressive reductions of operating and Idle power circuits being clocked reduce consumed power. consumption. In addition, three of the modes can be PIC24FJ128GA204 family devices manage power tailored for more power reduction at a trade-off of some consumption with five strategies: operating features. Table10-1 lists all of the operating modes in order of increasing power savings. Table10-2 • Instruction-Based Power Reduction Modes summarizes how the microcontroller exits the different • Hardware-Based Power Reduction Features modes. Specific information is provided in the following • Clock Frequency Control sections. • Software Controlled Doze Mode • Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications. TABLE 10-1: OPERATING MODES FOR PIC24FJ128GA204 FAMILY DEVICES Active Systems Mode Entry DSGPR0/ Data RAM Core Peripherals RTCC(1) DSGPR1 Retention Retention Run (default) N/A Y Y Y Y Y Idle Instruction N Y Y Y Y Sleep: Sleep Instruction N S(2) Y Y Y Low-Voltage Sleep Instruction + N S(2) Y Y Y RETEN bit Deep Sleep: Deep Sleep Instruction + N N N Y Y DSEN bit VBAT: with RTCC Hardware N N N Y Y Note 1: If RTCC is otherwise enabled in firmware. 2: A select peripheral can operate during this mode from LPRC or an external clock.  2013-2015 Microchip Technology Inc. DS30010038C-page 155

PIC24FJ128GA204 FAMILY TABLE 10-2: EXITING POWER-SAVING MODES Exit Conditions Code Mode Interrupts Resets Execution RTCC VDD Alarm WDT Restore(2) Resumes All INT0 All POR MCLR Idle Y Y Y Y Y Y Y N/A Next instruction Sleep (all modes) Y Y Y Y Y Y Y N/A Deep Sleep N Y N Y Y Y Y(1) N/A Reset vector VBAT N N N N N N N Y Reset vector Note 1: Deep Sleep WDT. 2: A POR or POR like Reset results whenever VDD is removed and restored in any mode except for Retention Deep Sleep mode. 10.1.1 INSTRUCTION-BASED The features enabled with the low-voltage/retention POWER-SAVING MODES regulator results in some changes to the way that Sleep and Deep Sleep modes behave. See Section10.3 Three of the power-saving modes are entered through “Sleep Mode” and Section10.4 “Deep Sleep Mode” the execution of the PWRSAV instruction. Sleep mode for additional information. stops clock operation and halts all code execution. Idle mode halts the CPU and code execution, but allows 10.1.1.1 Interrupts Coincident with peripheral modules to continue operation. Deep Sleep Power Save Instructions mode stops clock operation, code execution, and all peripherals, except RTCC and DSWDT. It also freezes Any interrupt that coincides with the execution of a I/O states and removes power to Flash memory, and PWRSAV instruction will be held off until entry into Sleep may remove power to SRAM. or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. The assembly syntax of the PWRSAV instruction is shown in Example10-1. Sleep and Idle modes are For Deep Sleep mode, interrupts that coincide with the entered directly with a single assembler command. execution of the PWRSAV instruction may be lost. If the Deep Sleep requires an additional sequence to unlock low-voltage/retention regulator is not enabled, the and enable the entry into Deep Sleep, which is microcontroller resets on leaving Deep Sleep and the described in Section10.4.1 “Entering Deep Sleep interrupt will be lost. Mode”. Interrupts that occur during the Deep Sleep unlock sequence will interrupt the mandatory five-instruction Note: SLEEP_MODE and IDLE_MODE are cycle sequence timing and cause a failure to enter constants defined in the assembler Deep Sleep. For this reason, it is recommended to include file for the selected device. disable all interrupts during the Deep Sleep unlock Sleep and Idle modes can be exited as a result of an sequence. enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. EXAMPLE 10-1: PWRSAV INSTRUCTION SYNTAX // Syntax to enter Sleep mode: PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode // //Synatx to enter Idle mode: PWRSAV #IDLE_MODE ; Put the device into IDLE mode // // Syntax to enter Deep Sleep mode: // First use the unlock sequence to set the DSEN bit (see Example10-2) BSET DSCON, #DSEN ; Enable Deep Sleep BSET DSCON, #DSEN ; Enable Deep Sleep(repeat the command) PWRSAV #SLEEP_MODE ; Put the device into Deep SLEEP mode DS30010038C-page 156  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 10.1.2 HARDWARE-BASED 10.3 Sleep Mode POWER-SAVING MODE Sleep mode includes these features: The hardware-based VBAT mode does not require any • The system clock source is shut down. If an action by the user during code development. Instead, it on-chip oscillator is used, it is turned off. is a hardware design feature that allows the micro- controller to retain critical data (using the DSGPRx • The device current consumption will be reduced registers) and maintain the RTCC when VDD is removed to a minimum provided that no I/O pin is sourcing from the application. This is accomplished by supplying current. a backup power source to a specific power pin. VBAT • The I/O pin directions and states are frozen. mode is described in more detail in Section10.5 “VBAT • The Fail-Safe Clock Monitor does not operate Mode”. during Sleep mode since the system clock source is disabled. 10.1.3 LOW-VOLTAGE/RETENTION • The LPRC clock will continue to run in Sleep REGULATOR mode if the WDT or RTCC, with LPRC as the PIC24FJ128GA204 family devices incorporate a clock source, is enabled. second on-chip voltage regulator, designed to provide • The WDT, if enabled, is automatically cleared power to select microcontroller features at 1.2V nomi- prior to entering Sleep mode. nal. This regulator allows features, such as data RAM • Some device features or peripherals may and the WDT, to be maintained in power-saving modes continue to operate in Sleep mode. This includes where they would otherwise be inactive, or maintain items, such as the Input Change Notification on them at a lower power than would otherwise be the the I/O ports or peripherals that use an external case. clock input. Any peripheral that requires the The low-voltage/retention regulator is only available system clock source for its operation will be when Sleep mode is invoked. It is controlled by the disabled in Sleep mode. LPCFG Configuration bit (CW1<10>) and in firmware The device will wake-up from Sleep mode on any of by the RETEN bit (RCON<12>). LPCFG must be these events: programmed (= 0) and the RETEN bit must be set (= 1) • On any interrupt source that is individually for the regulator to be enabled. enabled 10.2 Idle Mode • On any form of device Reset • On a WDT time-out Idle mode includes these features: On wake-up from Sleep, the processor will restart with • The CPU will stop executing instructions. the same clock source that was active when Sleep • The WDT is automatically cleared. mode was entered. • The system clock source remains active. By 10.3.1 LOW-VOLTAGE/RETENTION SLEEP default, all peripheral modules continue to operate MODE normally from the system clock source, but can also be selectively disabled (see Section10.8 Low-Voltage/Retention Sleep mode functions as Sleep “Selective Peripheral Module Control”). mode with the same features and wake-up triggers. • If the WDT or FSCM is enabled, the LPRC will The difference is that the low-voltage/retention regula- also remain active. tor allows core digital logic voltage (VCORE) to drop to 1.2V nominal. This permits an incremental reduction of The device will wake from Idle mode on any of these power consumption over what would be required if events: VCORE was maintained at a 1.8V (minimum) level. • Any interrupt that is individually enabled Low-Voltage Sleep mode requires a longer wake-up • Any device Reset time than Sleep mode, due to the additional time • A WDT time-out required to bring VCORE back to 1.8V (known as TREG). On wake-up from Idle, the clock is reapplied to the CPU In addition, the use of the low-voltage/retention regula- and instruction execution begins immediately, starting tor limits the amount of current that can be sourced to with the instruction following the PWRSAV instruction or any active peripherals, such as the RTCC, etc. the first instruction in the Interrupt Service Routine (ISR).  2013-2015 Microchip Technology Inc. DS30010038C-page 157

PIC24FJ128GA204 FAMILY 10.4 Deep Sleep Mode The sequence to enter Deep Sleep mode is: 1. If the application requires the Deep Sleep WDT, Deep Sleep mode provides the lowest levels of power enable it and configure its clock source. For consumption available from the instruction-based more information on Deep Sleep WDT, see modes. Section10.4.5 “Deep Sleep WDT”. Deep Sleep mode has these features: 2. If the application requires Deep Sleep BOR, • The system clock source is shut down. If an enable it by programming the DSBOREN on-chip oscillator is used, it is turned off. Configuration bit (CW4<6>). • The device current consumption will be reduced 3. If the application requires wake-up from Deep to a minimum. Sleep on RTCC alarm, enable and configure the • The I/O pin directions and states are frozen. RTCC module. For more information on RTCC, • The Fail-Safe Clock Monitor does not operate see Section21.0 “Real-Time Clock and during Sleep mode since the system clock source Calendar (RTCC)”. is disabled. 4. If needed, save any critical application context • The LPRC clock will continue to run in Deep data by writing it to the DSGPR0 and DSGPR1 Sleep mode if the WDT or RTCC, with LPRC as registers (optional). the clock source, is enabled. 5. Enable Deep Sleep mode by setting the DSEN • The dedicated Deep Sleep WDT and BOR bit (DSCON<15>). systems, if enabled, are used. Note: A repeat sequence is required to set the • The RTCC and its clock source continue to run, if DSEN bit. The repeat sequence (repeating enabled. All other peripherals are disabled. the instruction twice) is required to write Entry into Deep Sleep mode is completely under into any of the Deep Sleep registers software control. Exiting from the Deep Sleep mode (DSCON, DSWAKE, DSGPR0, DSGPR1). can be triggered from any of the following events: This is required to prevent the user from entering Deep Sleep by mistake. Any • POR event write to these registers has to be done • MCLR event twice to actually complete the write (see • RTCC alarm (If the RTCC is present) Example10-2). • External Interrupt 0 6. Enter Deep Sleep mode by issuing 3 NOP • Deep Sleep Watchdog Timer (DSWDT) time-out commands and then a PWRSAV #0 instruction. 10.4.1 ENTERING DEEP SLEEP MODE Any time the DSEN bit is set, all bits in the DSWAKE Deep Sleep mode is entered by setting the DSEN bit in register will be automatically cleared. the DSCON register and then executing a Sleep command (PWRSAV #SLEEP_MODE), within one instruc- EXAMPLE 10-2: THE REPEAT SEQUENCE tion cycle, to minimize the chance that Deep Sleep will Example 1: be spuriously entered. mov #8000, w2 ; enable DS If the PWRSAV command is not given within one mov w2, DSCON instruction cycle, the DSEN bit will be cleared by the mov w2, DSCON ; second write required to hardware and must be set again by the software before actually write to DSCON entering Deep Sleep mode. The DSEN bit is also Example 2: automatically cleared when exiting Deep Sleep mode. bset DSCON, #15 Note: To re-enter Deep Sleep after a Deep Sleep nop wake-up, allow a delay of at least 3 TCY nop after clearing the RELEASE bit. nop bset DSCON, #15 ; enable DS (two writes required) DS30010038C-page 158  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 10.4.2 EXITING DEEP SLEEP MODE 10.4.3 SAVING CONTEXT DATA WITH THE DSGPRx REGISTERS Deep Sleep mode exits on any one of the following events: As exiting Deep Sleep mode causes a POR, most • POR event on VDD supply. If there is no DSBOR Special Function Registers reset to their default POR circuit to rearm the VDD supply POR circuit, the values. In addition, because VCORE power is not external VDD supply must be lowered to the supplied in Deep Sleep mode, information in data RAM natural arming voltage of the POR circuit. may be lost when exiting this mode. • DSWDT time-out. When the DSWDT times out, Applications which require critical data to be saved the device exits Deep Sleep. prior to Deep Sleep, may use the Deep Sleep General • RTCC alarm (if RTCEN = 1). Purpose registers, DSGPR0 and DSGPR1, or data EEPROM (if available). Unlike other SFRs, the • Assertion (‘0’) of the MCLR pin. contents of these registers are preserved while the • Assertion of the INT0 pin (if the interrupt was device is in Deep Sleep mode. After exiting Deep enabled before Deep Sleep mode was entered). Sleep, software can restore the data by reading the The polarity configuration is used to determine the registers and clearing the RELEASE bit (DSCON<0>). assertion level (‘0’ or ‘1’) of the pin that will cause an exit from Deep Sleep mode. Exiting from Deep Note: User software should enable the Sleep mode requires a change on the INT0 pin DSSWEN (CW4<8>) Configuration Fuse while in Deep Sleep mode. bit for saving critical data in the DSGPRx Note: Any interrupt pending when entering registers. Deep Sleep mode is cleared. 10.4.4 I/O PINS IN DEEP SLEEP MODE Exiting Deep Sleep generally does not retain the state During Deep Sleep, the general purpose I/O pins retain of the device and is equivalent to a Power-on Reset their previous states and the Secondary Oscillator (POR) of the device. Exceptions to this include the (SOSC) will remain running, if enabled. Pins that are RTCC (if present), which remains operational through configured as inputs (TRISx bit is set), prior to entry into the wake-up, the DSGPRx registers and the DSWDT. Deep Sleep, remain high-impedance during Deep Sleep. Wake-up events that occur from the time Deep Sleep Pins that are configured as outputs (TRISx bit is clear), exits until the time the POR sequence completes are prior to entry into Deep Sleep, remain as output pins not ignored. The DSWAKE register will capture ALL during Deep Sleep. While in this mode, they continue to wake-up events, from setting the DSEN bit to clearing drive the output level determined by their corresponding the RELEASE bit. LATx bit at the time of entry into Deep Sleep. The sequence for exiting Deep Sleep mode is: Once the device wakes back up, all I/O pins continue to 1. After a wake-up event, the device exits Deep maintain their previous states, even after the device Sleep and performs a POR. The DSEN bit is has finished the POR sequence and is executing cleared automatically. Code execution resumes application code again. Pins configured as inputs at the Reset vector. during Deep Sleep remain high-impedance and pins 2. To determine if the device exited Deep Sleep, configured as outputs continue to drive their previous read the Deep Sleep bit, DPSLP (RCON<10>). value. After waking up, the TRISx and LATx registers, This bit will be set if there was an exit from Deep and the SOSCEN bit (OSCCON<1>) are reset. If Sleep mode. If the bit is set, clear it. firmware modifies any of these bits or registers, the I/O will not immediately go to the newly configured states. 3. Determine the wake-up source by reading the Once the firmware clears the RELEASE bit DSWAKE register. (DSCON<0>), the I/O pins are “released”. This causes 4. Determine if a DSBOR event occurred during the I/O pins to take the states configured by their Deep Sleep mode by reading the DSBOR bit respective TRISx and LATx bit values. (DSCON<1>). This means that keeping the SOSC running after 5. If application context data has been saved, read waking up requires the SOSCEN bit to be set before it back from the DSGPR0 and DSGPR1 clearing RELEASE. registers. 6. Clear the RELEASE bit (DSCON<0>). If the Deep Sleep BOR (DSBOR) is enabled, and a DSBOR or a true POR event occurs during Deep Sleep, the I/O pins will be immediately released, similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents.  2013-2015 Microchip Technology Inc. DS30010038C-page 159

PIC24FJ128GA204 FAMILY If a MCLR Reset event occurs during Deep Sleep, the On power-up, the software should read this status bit to DSGPRx, DSCON and DSWAKE registers will remain determine if the Reset was due to an exit from Deep valid, and the RELEASE bit will remain set. The state Sleep mode and clear the bit if it is set. Of the four of the SOSC will also be retained. The I/O pins, possible combinations of DPSLP and POR bit states, however, will be reset to their MCLR Reset state. Since the following three cases can be considered: RELEASE is still set, changes to the SOSCEN bit • Both the DPSLP and POR bits are cleared. In this (OSCCON<1>) cannot take effect until the RELEASE case, the Reset was due to some event other bit is cleared. than a Deep Sleep mode exit. In all other Deep Sleep wake-up cases, application • The DPSLP bit is clear, but the POR bit is set; this firmware must clear the RELEASE bit in order to is a normal Power-on Reset. reconfigure the I/O pins. • Both the DPSLP and POR bits are set. This means that Deep Sleep mode was entered, the 10.4.5 DEEP SLEEP WDT device was powered down and Deep Sleep mode To enable the DSWDT in Deep Sleep mode, program was exited. the Configuration bit, DSWDTEN (CW4<7>). The device WDT need not be enabled for the DSWDT to 10.4.7 POWER-ON RESETS (PORs) function. Entry into Deep Sleep modes automatically VDD voltage is monitored to produce PORs. Since resets the DSWDT. exiting from Deep Sleep mode functionally looks like a The DSWDT clock source is selected by the POR, the technique described in Section10.4.6 DSWDTOSC Configuration bit (CW4<5>). The postscaler “Checking and Clearing the Status of Deep Sleep” options are programmed by the DSWDTPS<4:0> Config- should be used to distinguish between Deep Sleep and uration bits (CW4<4:0>). The minimum time-out period a true POR event. When a true POR occurs, the entire that can be achieved is 1 ms and the maximum is device, including all Deep Sleep logic (Deep Sleep 25.7days. For more information on the CW4 Configura- registers, RTCC, DSWDT, etc.) is reset. tion register and DSWDT configuration options, refer to Section29.0 “Special Features”. 10.5 VBAT Mode 10.4.5.1 Switching Clocks in Deep Sleep This mode represents the lowest power state that the Mode microcontroller can achieve and still resume operation. VBAT mode is automatically triggered when the micro- Both the RTCC and the DSWDT may run from either controller’s main power supply on VDD fails. When this SOSC or the LPRC clock source. This allows both the happens, the microcontroller’s on-chip power switch RTCC and DSWDT to run without requiring both the connects to a backup power source, such as a battery, LPRC and SOSC to be enabled together, reducing supplied to the VBAT pin. This maintains a few key power consumption. systems at an extremely low-power draw until VDD is Running the RTCC from LPRC will result in a loss of restored. accuracy in the RTCC of approximately 5 to 10%. If a The power supplied on VBAT only runs two systems: more accurate RTCC is required, it must be run from the the RTCC and the Deep Sleep Semaphore registers SOSC clock source. The RTCC clock source is selected (DSGPR0 and DSGPR1). To maintain these systems with the RTCLK<1:0> bits (RTCPWC<11:10>). during a sudden loss of VDD, it is essential to connect Under certain circumstances, it is possible for the a power source, other than VDD or AVDD, to the VBAT DSWDT clock source to be off when entering Deep pin. Sleep mode. In this case, the clock source is turned on When the RTCC is enabled, it continues to operate with automatically (if DSWDT is enabled), without the need the same clock source (SOSC or LPRC) that was for software intervention. However, this can cause a selected prior to entering VBAT mode. There is no delay in the start of the DSWDT counters. In order to provision to switch to a lower power clock source after avoid this delay when using SOSC as a clock source, the mode switch. the application can activate SOSC prior to entering Deep Sleep mode. Since the loss of VDD is usually an unforeseen event, it is recommended that the contents of the Deep Sleep 10.4.6 CHECKING AND CLEARING THE Semaphore registers be loaded with the data to be STATUS OF DEEP SLEEP retained at an early point in code execution. Upon entry into Deep Sleep mode, the status bit, 10.5.1 VBAT MODE WITH NO RTCC DPSLP (RCON<10>), becomes set and must be cleared by the software. By disabling RTCC operation during VBAT mode, power consumption is reduced to the lowest of all power- saving modes. In this mode, only the Deep Sleep Semaphore registers are maintained. DS30010038C-page 160  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 10.5.2 WAKE-UP FROM VBAT MODES 10.5.3 I/O PINS DURING VBAT MODES When VDD is restored to a device in VBAT mode, it auto- All I/O pins switch to Input mode during VBAT mode. matically wakes. Wake-up occurs with a POR, after The only exceptions are the SOSCI and SOSCO pins, which, the device starts executing code from the Reset which maintain their states if the Secondary Oscillator vector. All SFRs, except the Deep Sleep Semaphores, is being used as the RTCC clock source. It is the user’s are reset to their POR values. If the RTCC was not con- responsibility to restore the I/O pins to their proper figured to run during VBAT mode, it will remain disabled states, using the TRISx and LATx bits, once VDD has and RTCC will not run. Wake-up timing is similar to that been restored. for a normal POR. 10.5.4 SAVING CONTEXT DATA WITH THE To differentiate a wake-up from VBAT mode from other DSGPRx REGISTERS POR states, check the VBAT status bit (RCON2<0>). If this bit is set while the device is starting to execute the As with Deep Sleep mode (i.e., without the low-voltage/ code from the Reset vector, it indicates that there has retention regulator), all SFRs are reset to their POR been an exit from VBAT mode. The application must values after VDD has been restored. Only the Deep clear the VBAT bit to ensure that future VBAT wake-up Sleep Semaphore registers are preserved. Applica- events are captured. tions which require critical data to be saved should save it in DSGPR0 and DSGPR1. If a POR occurs without a power source connected to the VBAT pin, the VBPOR bit (RCON2<1>) is set. If this Note: If the VBAT mode is not used, it is bit is set on a Power-on Reset, it indicates that a battery recommended to connect the VBAT pin needs to be connected to the VBAT pin. to VDD. In addition, if the VBAT power source falls below the The POR should be enabled for the reliable operation level needed for Deep Sleep Semaphore operation while in VBAT mode (e.g., the battery has been of the VBAT. drained), the VBPOR bit will be set. VBPOR is also set when the microcontroller is powered up the very first time, even if power is supplied to VBAT.  2013-2015 Microchip Technology Inc. DS30010038C-page 161

PIC24FJ128GA204 FAMILY REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1) R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 r-0 R/W-0 R/C-0, HS — — — — — — DSBOR(2) RELEASE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit r = Reserved bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enable bit 1 = Enters Deep Sleep on execution of PWRSAV #0 0 = Enters normal Sleep on execution of PWRSAV #0 bit 14-3 Unimplemented: Read as ‘0’ bit 2 Reserved: Maintain as ‘0’ bit 1 DSBOR: Deep Sleep BOR Event bit(2) 1 = The DSBOR was active and a BOR event was detected during Deep Sleep 0 = The DSBOR was not active, or was active, but did not detect a BOR event during Deep Sleep bit 0 RELEASE: I/O Pin State Release bit 1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to the Deep Sleep entry 0 = Releases I/O pins from their state previous to Deep Sleep entry and allows their respective TRISx and LATx bits to control their states Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode. 2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms the POR. DS30010038C-page 162  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 10-2: DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 U-0 DSFLT — — DSWDT DSRTCC DSMCLR — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 DSINT0: Deep Sleep Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep bit 7 DSFLT: Deep Sleep Fault Detect bit 1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep bit 6-5 Unimplemented: Read as ‘0’ bit 4 DSWDT: Deep Sleep Watchdog Timer Time-out bit 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep bit 3 DSRTCC: Deep Sleep Real-Time Clock and Calendar Alarm bit 1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep bit 2 DSMCLR: Deep Sleep MCLR Event bit 1 = The MCLR pin was active and was asserted during Deep Sleep 0 = The MCLR pin was not active, or was active, but not asserted during Deep Sleep bit 1-0 Unimplemented: Read as ‘0’ Note 1: All register bits are cleared when the DSEN (DSCON<15>) bit is set.  2013-2015 Microchip Technology Inc. DS30010038C-page 163

PIC24FJ128GA204 FAMILY REGISTER 10-3: RCON2: RESET AND SYSTEM CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 r-0 R/CO-1 R/CO-1 R/CO-1 R/CO-0 — — — — VDDBOR(1) VDDPOR(1,2) VBPOR(1,3) VBAT(1) bit 7 bit 0 Legend: CO = Clearable Only bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 Reserved: Maintain as ‘0’ bit 3 VDDBOR: VDD Brown-out Reset Flag bit(1) 1 = A VDD Brown-out Reset has occurred (set by hardware) 0 = A VDD Brown-out Reset has not occurred bit 2 VDDPOR: VDD Power-on Reset Flag bit(1,2) 1 = A VDD Power-on Reset has occurred (set by hardware) 0 = A VDD Power-on Reset has not occurred bit 1 VBPOR: VBAT Power-on Reset Flag bit(1,3) 1 = A VBAT POR has occurred (no battery connected to the VBAT pin or VBAT power is below Deep Sleep Semaphore retention level; set by hardware) 0 = A VBAT POR has not occurred bit 0 VBAT: VBAT Flag bit(1) 1 = A POR exit has occurred while power is applied to the VBAT pin (set by hardware) 0 = A POR exit from VBAT has not occurred Note 1: This bit is set in hardware only; it can only be cleared in software. 2: This bit indicates a VDD Power-on Reset. Setting the POR bit (RCON<0>) indicates a VCORE Power-on Reset. 3: This bit is set when the device is originally powered up, even if power is present on VBAT. DS30010038C-page 164  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 10.6 Clock Frequency and Clock 10.8 Selective Peripheral Module Switching Control In Run and Idle modes, all PIC24FJ devices allow for a Idle and Doze modes allow users to substantially wide range of clock frequencies to be selected under reduce power consumption by slowing or stopping the application control. If the system clock configuration is CPU clock. Even so, peripheral modules still remain not locked, users can choose low-power or high- clocked, and thus, consume power. There may be precision oscillators by simply changing the NOSCx cases where the application needs what these modes bits. The process of changing a system clock during do not provide: the allocation of power resources to operation, as well as limitations to the process, are CPU processing with minimal power consumption from discussed in more detail in Section9.0 “Oscillator the peripherals. Configuration”. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing 10.7 Doze Mode or eliminating their power consumption. This can be done with two control bits: Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies • The Peripheral Enable bit, generically named, for reducing power consumption. There may be circum- “XXXEN”, located in the module’s main control stances, however, where this is not practical. For SFR. example, it may be necessary for an application to • The Peripheral Module Disable (PMD) bit, maintain uninterrupted synchronous communication, generically named, “XXXMD”, located in one of even while it is doing nothing else. Reducing system the PMDx Control registers (XXXMD bits are in clock speed may introduce communication errors, the PMD1, PMD2, PMD3, PMD4, PMD6, PMD7, while using a power-saving mode may stop PMD8 registers). communications completely. Both bits have similar functions in enabling or disabling Doze mode is a simple and effective alternative method its associated module. Setting the PMDx bit for a module to reduce power consumption while the device is still disables all clock sources to that module, reducing its executing code. In this mode, the system clock con- power consumption to an absolute minimum. In this tinues to operate from the same source and at the state, the control and status registers associated with the same speed. Peripheral modules continue to be peripheral will also be disabled, so writes to those regis- clocked at the same speed, while the CPU clock speed ters will have no effect and read values will be invalid. is reduced. Synchronization between the two clock Many peripheral modules have a corresponding domains is maintained, allowing the peripherals to PMDxbit. access the SFRs while the CPU executes code at a In contrast, disabling a module by clearing its XXXEN slower rate. bit disables its functionality, but leaves its registers Doze mode is enabled by setting the DOZEN bit available to be read and written to. Power consumption (CLKDIV<11>). The ratio between peripheral and is reduced, but not by as much as the use of the PMDx core clock speed is determined by the DOZE<2:0> bits. Most peripheral modules have an enable bit; bits (CLKDIV<14:12>). There are eight possible exceptions include capture, compare and RTCC. configurations, from 1:1 to 1:128, with 1:1 being the To achieve more selective power savings, peripheral default. modules can also be selectively disabled when the It is also possible to use Doze mode to selectively device enters Idle mode. This is done through the con- reduce power consumption in event driven applica- trol bit of the generic name format, “XXXSIDL”. By tions. This allows clock-sensitive functions, such as default, all modules that can operate during Idle mode synchronous communications, to continue without will do so. Using the disable on Idle feature disables the interruption while the CPU Idles, waiting for something module while in Idle mode, allowing further reduction of to invoke an interrupt routine. Enabling the automatic power consumption during Idle mode, enhancing return to full-speed CPU operation on interrupts is power savings for extremely critical power applications. enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation.  2013-2015 Microchip Technology Inc. DS30010038C-page 165

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 166  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 11.0 I/O PORTS When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as Note: This data sheet summarizes the features of a general purpose output pin is disabled. The I/O pin this group of PIC24F devices. It is not may be read, but the output driver for the parallel port intended to be a comprehensive reference bit will be disabled. If a peripheral is enabled, but the source. For more information, refer to peripheral is not actively driving a pin, that pin may be the “dsPIC33/PIC24 Family Reference driven by a port. Manual”, “I/O Ports with Peripheral Pin All port pins have three registers directly associated Select (PPS)” (DS39711). The informa- with their operation as digital I/Os and one register tion in this data sheet supersedes the associated with their operation as analog inputs. The information in the FRM. Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a All of the device pins (except VDD, VSS, MCLR and ‘1’, then the pin is an input. All port pins are defined as OSCI/CLKI) are shared between the peripherals and inputs after a Reset. Reads from the Output Latch the Parallel I/O ports. All I/O input ports feature Schmitt register (LATx), read the latch; writes to the latch, write Trigger (ST) inputs for improved noise immunity. the latch. Reads from the PORTx register, read the port 11.1 Parallel I/O (PIO) Ports pins; writes to the port pins, write the latch. Any bit and its associated data and control registers, A Parallel I/O port that shares a pin with a peripheral is, that are not valid for a particular device, will be in general, subservient to the peripheral. The periph- disabled. That means the corresponding LATx and eral’s output buffer data and control signals are TRISx registers, and the port pin, will read as zeros. provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port When a pin is shared with another peripheral or func- has ownership of the output data and control signals of tion that is defined as an input only, it is regarded as a the I/O pin. The logic also prevents “loop through”, in dedicated port because there is no other competing which a port’s digital output can drive the input of a source of inputs. peripheral that shares the same pin. Figure11-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable I/O Peripheral Output Enable 1 Output Enable Peripheral Output Data 0 PIO Module 1 Output Data Read TRISx 0 Data Bus D Q I/O Pin WR TRISx CK TRISx Latch D Q WR LATx + CK WR PORTx Data Latch Read LATx Input Data Read PORTx  2013-2015 Microchip Technology Inc. DS30010038C-page 167

PIC24FJ128GA204 FAMILY 11.1.1 I/O PORT WRITE/READ TIMING 11.2 Configuring Analog Port Pins (ANSx) One instruction cycle is required between a port direction change or port write operation and a read The ANSx and TRISx registers control the operation of operation of the same port. Typically, this instruction the pins with analog function. Each port pin with analog would be a NOP. function is associated with one of the ANSx bits (see Register11-1 through Register11-3), which decides if 11.1.2 OPEN-DRAIN CONFIGURATION the pin function should be analog or digital. Refer to In addition to the PORTx, LATx and TRISx registers for Table11-1 for detailed behavior of the pin for different data control, each port pin can also be individually ANSx and TRISx bit settings. configured for either a digital or open-drain output. This When reading the PORTx register, all pins configured as is controlled by the Open-Drain Control register, ODCx, analog input channels will read as cleared (a low level). associated with each port. Setting any of the bits con- figures the corresponding pin to act as an open-drain 11.2.1 ANALOG INPUT PINS AND output. VOLTAGE CONSIDERATIONS The open-drain feature allows the generation of The voltage tolerance of pins used as device inputs is outputs higher than VDD (e.g., 5V) on any desired dependent on the pin’s input function. Most input pins digital only pins by using external pull-up resistors. The are able to handle DC voltages of up to 5.5V, a level typ- maximum open-drain voltage allowed is the same as ical for digital logic circuits. However, several pins can the maximum VIH specification. only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should always be avoided. Table11-2 summarizes the different voltage toler- ances. For more information, refer to Section32.0 “Electrical Characteristics” for more details. TABLE 11-1: CONFIGURING ANALOG/DIGITAL FUNCTION OF AN I/O PIN Pin Function ANSx Setting TRISx Setting Comments Analog Input 1 1 It is recommended to keep ANSx = 1. Analog Output 1 1 It is recommended to keep ANSx = 1. Digital Input 0 1 Firmware must wait at least one instruction cycle after configuring a pin as a digital input before a valid input value can be read. Digital Output 0 0 Make sure to disable the analog output function on the pin if any is present. TABLE 11-2: INPUT VOLTAGE LEVELS FOR PORT OR PIN TOLERATED DESCRIPTION INPUT Port or Pin Tolerated Input Description PORTA<10:7,4>(1) Tolerates input levels above VDD; useful PORTB<11:10,8:4> 5.5V for most standard logic. PORTC<9:3>(1) PORTA<3:0> PORTB<15:13,9,3:0> VDD Only VDD input levels are tolerated. PORTC<2:0>(1) Note 1: Not all of these pins are implemented in 28-pin devices. Refer to Section1.0 “Device Overview” for a complete description of port pin implementation. DS30010038C-page 168  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-1: ANSA: PORTA ANALOG FUNCTION SELECTION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANSA<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-4 Unimplemented: Read as ‘0’ bit 3-0 ANSA<3:0>: PORTA Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled REGISTER 11-2: ANSB: PORTB ANALOG FUNCTION SELECTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 ANSB<15:12> — — ANSB9 — bit 15 bit 8 U-0 R/W-1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — ANSB6 — — ANSB<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 ANSB<15:12>: PORTB Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 11-10 Unimplemented: Read as ‘0’ bit 9 ANSB9: PORTB Analog Function Selection bit 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 8-7 Unimplemented: Read as ‘0’ bit 6 ANSB6: PORTB Analog Function Selection bit 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 ANSB<3:0>: PORTB Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled  2013-2015 Microchip Technology Inc. DS30010038C-page 169

PIC24FJ128GA204 FAMILY REGISTER 11-3: ANSC: PORTC ANALOG FUNCTION SELECTION REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSC<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ANSC<2:0>: PORTC Analog Function Selection bits 1 = Pin is configured in Analog mode; I/O port read is disabled 0 = Pin is configured in Digital mode; I/O port read is enabled Note 1: These pins are not available in 28-pin devices. DS30010038C-page 170  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 11.3 Input Change Notification (ICN) Each CN pin has both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current The Input Change Notification function of the I/O ports source that is connected to the pin, while the pull-downs allows the PIC24FJ128GA204 family of devices to gen- act as a current sink that is connected to the pin. These erate interrupt requests to the processor in response to eliminate the need for external resistors when push but- a Change-of-State (COS) on selected input pins. This ton or keypad devices are connected. The pull-ups and feature is capable of detecting input Change-of-States, pull-downs are separately enabled using the CNPU1 even in Sleep mode, when the clocks are disabled. through CNPU3 registers (for pull-ups), and the CNPD1 Depending on the device pin count, there are up to through CNPD3 registers (for pull-downs). Each CN pin 82external inputs that may be selected (enabled) for has individual control bits for its pull-up and pull-down. generating an interrupt request on a Change-of-State. Setting a control bit enables the weak pull-up or Registers, CNEN1 through CNEN3, contain the inter- pull-down for the corresponding pin. rupt enable control bits for each of the CN input pins. When the internal pull-up is selected, the pin pulls up to Setting any of these bits enables a CN interrupt for the VDD – 1.1V (typical). When the internal pull-down is corresponding pins. selected, the pin pulls down to VSS. Note: Pull-ups on Input Change Notification pins should always be disabled whenever the port pin is configured as a digital output. EXAMPLE 11-1: PORT READ/WRITE IN ASSEMBLY MOV 0xFF00, W0 ; Configure PORTB<15:8> as inputs MOV W0, TRISB ; and PORTB<7:0> as outputs NOP ; Delay 1 cycle BTSS PORTB, #13 ; Next Instruction EXAMPLE 11-2: PORT READ/WRITE IN ‘C’ TRISB = 0xFF00; // Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Nop(); // Delay 1 cycle If (PORTBbits.RB13){ }; // Next Instruction  2013-2015 Microchip Technology Inc. DS30010038C-page 171

PIC24FJ128GA204 FAMILY 11.4 Peripheral Pin Select (PPS) PPS is not available for these peripherals: • I2C™ (input and output) A major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while • Change Notification Inputs minimizing the conflict of features on I/O pins. In an • RTCC Alarm Output(s) application that needs to use more than one peripheral • EPMP Signals (input and output) multiplexed on a single pin, inconvenient work arounds • Analog (inputs and outputs) in application code, or a complete redesign, may be the • INT0 only option. A key difference between pin select and non-pin select The Peripheral Pin Select (PPS) feature provides an peripherals is that pin select peripherals are not asso- alternative to these choices by enabling the user’s ciated with a default I/O pin. The peripheral must peripheral set selection and its placement on a wide always be assigned to a specific I/O pin before it can be range of I/O pins. By increasing the pinout options used. In contrast, non-pin select peripherals are always available on a particular device, users can better tailor available on a default pin, assuming that the peripheral the microcontroller to their entire application, rather is active and not conflicting with another peripheral. than trimming the application to fit the device. The Peripheral Pin Select feature operates over a fixed 11.4.2.1 Peripheral Pin Select Function subset of digital I/O pins. Users may independently Priority map the input and/or output of any one of many digital Pin-selectable peripheral outputs (e.g., output com- peripherals to any one of these I/O pins. PPS is per- pare, UART transmit) will take priority over general formed in software and generally does not require the purpose digital functions on a pin, such as EPMP and device to be reprogrammed. Hardware safeguards are port I/O. Specialized digital outputs will take priority included that prevent accidental or spurious changes to over PPS outputs on the same pin. The pin diagrams the peripheral mapping once it has been established. list peripheral outputs in the order of priority. Refer to 11.4.1 AVAILABLE PINS them for priority concerns on a particular pin. Unlike PIC24F devices with fixed peripherals, pin- The PPS feature is used with a range of up to 44 pins, selectable peripheral inputs will never take ownership depending on the particular device and its pin count. of a pin. The pin’s output buffer will be controlled by the Pins that support the Peripheral Pin Select feature TRISx setting or by a fixed peripheral on the pin. If the include the designation, “RPn” or “RPIn”, in their full pin pin is configured in Digital mode, then the PPS input will designation, where “n” is the remappable pin number. operate correctly. If an analog function is enabled on “RP” is used to designate pins that support both remap- the pin, the PPS input will be disabled. pable input and output functions, while “RPI” indicates pins that support remappable input functions only. 11.4.3 CONTROLLING PERIPHERAL PIN PIC24FJ128GA204 family devices support a larger SELECT number of remappable input only pins than remappable PPS features are controlled through two sets of Special input/output pins. In this device family, there are up to Function Registers (SFRs): one to map peripheral 25 remappable input/output pins, depending on the pin inputs and one to map outputs. Because they are count of the particular device selected. These pins are separately controlled, a particular peripheral’s input numbered, RP0 through RP25. and output (if the peripheral has both) can be placed on See Table1-3 for a summary of pinout options in each any selectable function pin without constraint. package offering. The association of a peripheral to a peripheral-selectable 11.4.2 AVAILABLE PERIPHERALS pin is handled in two different ways, depending on if an input or an output is being mapped. The peripherals managed by the PPS are all digital only peripherals. These include general serial commu- nications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and out- put compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. DS30010038C-page 172  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 11.4.3.1 Input Mapping Each register contains two sets of 6-bit fields, with each set associated with one of the pin-selectable peripher- The inputs of the Peripheral Pin Select options are als. Programming a given peripheral’s bit field with an mapped on the basis of the peripheral; that is, a control appropriate 6-bit value maps the RPn/RPIn pin with register associated with a peripheral dictates the pin it that value to that peripheral. For any given device, the will be mapped to. The RPINRx registers are used to valid range of values for any of the bit fields configure peripheral input mapping (see Register11-4 corresponds to the maximum number of Peripheral Pin through Register11-22). Selections supported by the device. TABLE 11-3: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Mapping Input Name Function Name Register Bits DSM Modulation Input MDMIN RPINR30 MDMIR<5:0> DSM Carrier 1 Input MDCIN1 RPINR31 MDC1R<5:0> DSM Carrier 2 Input MDCIN2 RPINR31 MDC2R<5:0> External Interrupt 1 INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> External Interrupt 3 INT3 RPINR1 INT3R<5:0> External Interrupt 4 INT4 RPINR2 INT4R<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Input Capture 3 IC3 RPINR8 IC3R<5:0> Input Capture 4 IC4 RPINR8 IC4R<5:0> Input Capture 5 IC5 RPINR9 IC5R<5:0> Input Capture 6 IC6 RPINR9 IC6R<5:0> Output Compare Fault A OCFA RPINR11 OCFAR<5:0> Output Compare Fault B OCFB RPINR11 OCFBR<5:0> Output Compare Trigger 1 OCTRIG1 RPINR0 OCTRIG1R<5:0> Output Compare Trigger 2 OCTRIG2 RPINR2 OCTRIG2R<5:0> SPI1 Clock Input SCK1IN RPINR20 SCK1R<5:0> SPI1 Data Input SDI1 RPINR20 SDI1R<5:0> SPI1 Slave Select Input SS1IN RPINR21 SS1R<5:0> SPI2 Clock Input SCK2IN RPINR22 SCK2R<5:0> SPI2 Data Input SDI2 RPINR22 SDI2R<5:0> SPI2 Slave Select Input SS2IN RPINR23 SS2R<5:0> SPI3 Clock Input SCK3IN RPINR28 SCK3R<5:0> SPI3 Data Input SDI3 RPINR28 SDI3R<5:0> SPI3 Slave Select Input SS3IN RPINR29 SS3R<5:0> Generic Timer External Clock TMRCK RPINR23 TMRCKR<5:0> UART1 Clear-to-Send U1CTS RPINR18 U1CTSR<5:0> UART1 Receive U1RX RPINR18 U1RXR<5:0> UART2 Clear-to-Send U2CTS RPINR19 U2CTSR<5:0> UART2 Receive U2RX RPINR19 U2RXR<5:0> UART3 Clear-to-Send U3CTS RPINR21 U3CTSR<5:0> UART3 Receive U3RX RPINR17 U3RXR<5:0> UART4 Clear-to-Send U4CTS RPINR27 U4CTSR<5:0> UART4 Receive U4RX RPINR27 U4RXR<5:0> Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger (ST) input buffers.  2013-2015 Microchip Technology Inc. DS30010038C-page 173

PIC24FJ128GA204 FAMILY 11.4.3.2 Output Mapping through Register11-35). The value of the bit field corresponds to one of the peripherals and that In contrast to inputs, the outputs of the Peripheral Pin peripheral’s output is mapped to the pin (see Table11-4). Select options are mapped on the basis of the pin. In this case, a control register associated with a particular Because of the mapping technique, the list of peripherals pin dictates the peripheral output to be mapped. The for output mapping also includes a null value of ‘000000’. RPORx registers are used to control output mapping. This permits any given pin to remain disconnected from Each register contains two 6-bit fields, with each field the output of any of the pin-selectable peripherals. being associated with one RPn pin (see Register11-23 TABLE 11-4: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function Output Name 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS(3) UART1 Request-to-Send 5 U2TX UART2 Transmit 6 U2RTS(3) UART2 Request-to-Send 7 SDO1 SPI1 Data Output 8 SCK1OUT SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock Output 12 SS2OUT SPI2 Slave Select Output 13 OC1 Output Compare 1 14 OC2 Output Compare 2 15 OC3 Output Compare 3 16 OC4 Output Compare 4 17 OC5 Output Compare 5 18 OC6 Output Compare 6 19 U3TX UART3 Transmit 20 U3RTS UART3 Request-to-Send 21 U4TX UART4 Transmit 22 U4RTS(3) UART4 Request-to-Send 23 SDO3 SPI3 Data Output 24 SCK3OUT SPI3 Clock Output 25 SS3OUT SPI3 Slave Select Output 26 C3OUT Comparator 3 Output 27 MDOUT DSM Modulator Output Note 1: Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. 3: IrDA® BCLKx functionality uses this output. DS30010038C-page 174  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 11.4.3.3 Mapping Limitations 11.4.4.1 Control Register Lock The control schema of the Peripheral Pin Select is Under normal operation, writes to the RPINRx and extremely flexible. Other than systematic blocks that RPORx registers are not allowed. Attempted writes will prevent signal contention caused by two physical pins appear to execute normally, but the contents of the being configured as the same functional input or two registers will remain unchanged. To change these reg- functional outputs configured as the same pin, there isters, they must be unlocked in hardware. The register are no hardware enforced lockouts. The flexibility lock is controlled by the IOLOCK bit (OSCCON<6>). extends to the point of allowing a single input to drive Setting IOLOCK prevents writes to the control multiple peripherals or a single functional output to registers; clearing IOLOCK allows writes. drive multiple output pins. To set or clear IOLOCK, a specific command sequence must be executed: 11.4.3.4 Mapping Exceptions for PIC24FJ128GA204 Family Devices 1. Write 46h to OSCCON<7:0>. 2. Write 57h to OSCCON<7:0>. Although the PPS registers theoretically allow for up to 24 remappable I/O pins, not all of these are imple- 3. Clear (or set) IOLOCK as a single operation. mented in all devices. For PIC24FJ128GA204 family Unlike the similar sequence with the oscillator’s LOCK devices, the maximum number of remappable pins bit, IOLOCK remains in one state until changed. This available is 24, which includes one input only pin. The allows all of the Peripheral Pin Selects to be configured differences in available remappable pins are with a single unlock sequence, followed by an update summarized in Table11-5. to all control registers, then locked with a second lock When developing applications that use remappable sequence. pins, users should also keep these things in mind: 11.4.4.2 Continuous State Monitoring • For the RPINRx registers, bit combinations corre- In addition to being protected from direct writes, the con- sponding to an unimplemented pin for a particular tents of the RPINRx and RPORx registers are constantly device are treated as invalid; the corresponding monitored in hardware by shadow registers. If an unex- module will not have an input mapped to it. pected change in any of the registers occurs (such as cell • For RPORx registers, the bit fields corresponding disturbances caused by ESD or other external events), a to an unimplemented pin will also be Configuration Mismatch Reset will be triggered. unimplemented; writing to these fields will have no effect. 11.4.4.3 Configuration Bit Pin Select Lock 11.4.4 CONTROLLING CONFIGURATION As an additional level of safety, the device can be con- CHANGES figured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY Because peripheral remapping can be changed during (CW4<15>) Configuration bit blocks the IOLOCK bit run time, some restrictions on peripheral remapping from being cleared after it has been set once. If are needed to prevent accidental configuration IOLOCK remains set, the register unlock procedure will changes. PIC24F devices include three features to not execute and the Peripheral Pin Select Control prevent alterations to the peripheral map: registers cannot be written to. The only way to clear the • Control register lock sequence bit and re-enable peripheral remapping is to perform a • Continuous state monitoring device Reset. • Configuration bit remapping lock In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. TABLE 11-5: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ128GA204 FAMILY DEVICES RPn Pins (I/O) RPIn Pins Device Total Unimplemented Total Unimplemented PIC24FJXXXGA202 14 RP4, RP12 1 — PIC24FJXXXGA204 24 RP4, RP12 1 —  2013-2015 Microchip Technology Inc. DS30010038C-page 175

PIC24FJ128GA204 FAMILY 11.4.5 CONSIDERATIONS FOR Along these lines, configuring a remappable pin for a PERIPHERAL PIN SELECTION specific peripheral does not automatically turn that feature on. The peripheral must be specifically config- The ability to control Peripheral Pin Selection intro- ured for operation and enabled as if it were tied to a duces several considerations into application design fixed pin. Where this happens in the application code that could be overlooked. This is particularly true for (immediately following a device Reset and peripheral several common peripherals that are available only as configuration or inside the main application routine) remappable peripherals. depends on the peripheral and its use in the The main consideration is that the Peripheral Pin application. Selects are not available on default pins in the device’s A final consideration is that Peripheral Pin Select func- default (Reset) state. Since all RPINRx registers reset tions neither override analog inputs nor reconfigure to ‘111111’ and all RPORx registers reset to ‘000000’, pins with analog functions for digital I/O. If a pin is all Peripheral Pin Select inputs are tied to VSS, and all configured as an analog input on device Reset, it must Peripheral Pin Select outputs are disconnected. be explicitly reconfigured as a digital I/O when used This situation requires the user to initialize the device with a Peripheral Pin Select. with the proper peripheral configuration before any Example11-3 shows a configuration for bidirectional other application code is executed. Since the IOLOCK communication with flow control using UART1. The bit resets in the unlocked state, it is not necessary to following input and output functions are used: execute the unlock sequence after the device has come out of Reset. For application safety, however, it is • Input Functions: U1RX, U1CTS best to set IOLOCK and lock the configuration after • Output Functions: U1TX, U1RTS writing to the control registers. EXAMPLE 11-3: CONFIGURING UART1 Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the INPUT AND OUTPUT same manner as changes to the oscillator configura- FUNCTIONS tion. If the bulk of the application is written in ‘C’, or // Unlock Registers another high-level language, the unlock sequence asm volatile ("MOV #OSCCON, w1 \n" should be performed by writing in-line assembly. "MOV #0x46, w2 \n" "MOV #0x57, w3 \n" Choosing the configuration requires the review of all "MOV.b w2, [w1] \n" Peripheral Pin Selects and their pin assignments, "MOV.b w3, [w1] \n" especially those that will not be used in the application. "BCLR OSCCON, #6") ; In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should // or use C30 built-in macro: have their inputs assigned to an unused RPn/RPIn pin // __builtin_write_OSCCONL(OSCCON & 0xbf); function. I/O pins with unused RPn functions should be configured with the null peripheral output. // Configure Input Functions (Table11-3) // Assign U1RX To Pin RP0 The assignment of a peripheral to a particular pin does RPINR18bits.U1RXR = 0; not automatically perform any other configuration of the pin’s I/O circuitry. In theory, this means adding a pin- // Assign U1CTS To Pin RP1 selectable output to a pin may mean inadvertently RPINR18bits.U1CTSR = 1; driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of // Configure Output Functions (Table11-4) other fixed peripherals that share a remappable pin and // Assign U1TX To Pin RP2 know when to enable or disable them. To be safe, fixed RPOR1bits.RP2R = 3; digital peripherals that share the same pin should be // Assign U1RTS To Pin RP3 disabled when not in use. RPOR1bits.RP3R = 4; // Lock Registers asm volatile ("MOV #OSCCON, w1 \n" "MOV #0x46, w2 \n" "MOV #0x57, w3 \n" "MOV.b w2, [w1] \n" "MOV.b w3, [w1] \n" "BSET OSCCON, #6") ; // or use C30 built-in macro: // __builtin_write_OSCCONL(OSCCON | 0x40); DS30010038C-page 176  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 11.4.6 PERIPHERAL PIN SELECT Note: Input and output register values can only REGISTERS be changed if IOLOCK (OSCCON<6>) = 0. The PIC24FJ128GA204 family of devices implements See Section11.4.4.1 “Control Register a total of 32 registers for remappable peripheral Lock” for a specific command sequence. configuration: • Input Remappable Peripheral Registers (19) • Output Remappable Peripheral Registers (13) REGISTER 11-4: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCTRIG1R5 OCTRIG1R4 OCTRIG1R3 OCTRIG1R2 OCTRIG1R1 OCTRIG1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT1R<5:0>: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCTRIG1R<5:0>: Assign Output Compare Trigger 1 to Corresponding RPn or RPIn Pin bits REGISTER 11-5: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 INT3R<5:0>: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits  2013-2015 Microchip Technology Inc. DS30010038C-page 177

PIC24FJ128GA204 FAMILY REGISTER 11-6: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCTRIG2R5 OCTRIG2R4 OCTRIG2R3 OCTRIG2R2 OCTRIG2R1 OCTRIG2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 OCTRIG2R<5:0>: Assign Output Compare Trigger 2 to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INT4R<5:0>: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits REGISTER 11-7: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R<5:0>: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits DS30010038C-page 178  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-8: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC4R<5:0>: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC3R<5:0>: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits REGISTER 11-9: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC6R<5:0>: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IC5R<5:0>: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits  2013-2015 Microchip Technology Inc. DS30010038C-page 179

PIC24FJ128GA204 FAMILY REGISTER 11-10: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 OCFBR<5:0>: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits REGISTER 11-11: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3RXR<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3RXR<5:0>: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as ‘0’ DS30010038C-page 180  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-12: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:0>: Assign UART1 Clear-to-Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U1RXR<5:0>: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 11-13: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U2CTSR<5:0>: Assign UART2 Clear-to-Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U2RXR<5:0>: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2013-2015 Microchip Technology Inc. DS30010038C-page 181

PIC24FJ128GA204 FAMILY REGISTER 11-14: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI1R<5:0>: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 11-15: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U3CTSR<5:0>: Assign UART3 Clear-to-Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits DS30010038C-page 182  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-16: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK2R<5:0>: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI2R<5:0>: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 11-17: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — TMRCKR5 TMRCKR4 TMRCKR3 TMRCKR2 TMRCKR1 TMRCKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 TMRCKR<5:0>: Assign General Timer External Input (TMRCK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SS2R<5:0>: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2013-2015 Microchip Technology Inc. DS30010038C-page 183

PIC24FJ128GA204 FAMILY REGISTER 11-18: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U4CTSR<5:0>: Assign UART4 Clear-to-Send Input (U4CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 U4RXR<5:0>: Assign UART4 Receive Input (U4RX) to Corresponding RPn or RPIn Pin bits REGISTER 11-19: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK3R<5:0>: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 SDI3R<5:0>: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits DS30010038C-page 184  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-20: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — SS3R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS3R<5:0>: Assign SPI3 Slave Select Input (SS3IN) to Corresponding RPn or RPIn Pin bits REGISTER 11-21: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDMIR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 MDMIR<5:0>: Assign TX Modulation Input (MDMI) to Corresponding RPn or RPIn Pin bits  2013-2015 Microchip Technology Inc. DS30010038C-page 185

PIC24FJ128GA204 FAMILY REGISTER 11-22: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDC2R5 MDC2R4 MDC2R3 MDC2R2 MDC2R1 MDC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — MDC1R5 MDC1R4 MDC1R3 MDC1R2 MDC21R1 MDC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 MDC2R<5:0>: Assign TX Carrier 2 Input (MDCIN2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 MDC1R<5:0>: Assign TX Carrier 1 Input (MDCIN1) to Corresponding RPn or RPIn Pin bits DS30010038C-page 186  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-23: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R<5:0>: RP1 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP1 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP0R<5:0>: RP0 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP0 (see Table11-4 for peripheral function numbers). REGISTER 11-24: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R<5:0>: RP3 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP3 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP2R<5:0>: RP2 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP2 (see Table11-4 for peripheral function numbers).  2013-2015 Microchip Technology Inc. DS30010038C-page 187

PIC24FJ128GA204 FAMILY REGISTER 11-25: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP5R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R<5:0>: RP5 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP5 (see Table11-4 for peripheral function numbers). bit 7-0 Unimplemented: Read as ‘0’ REGISTER 11-26: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R<5:0>: RP7 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP7 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP6R<5:0>: RP6 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP6 (see Table11-4 for peripheral function numbers). DS30010038C-page 188  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-27: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R<5:0>: RP9 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP9 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP8R<5:0>: RP8 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP8 (see Table11-4 for peripheral function numbers). REGISTER 11-28: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R<5:0>: RP11 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP11 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP10R<5:0>: RP10 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP10 (see Table11-4 for peripheral function numbers).  2013-2015 Microchip Technology Inc. DS30010038C-page 189

PIC24FJ128GA204 FAMILY REGISTER 11-29: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R<5:0>: RP13 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP13 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP12R<5:0>: RP12 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP12 (see Table11-4 for peripheral function numbers). REGISTER 11-30: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP15R5 RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R<5:0>: RP15 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP15 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP14R<5:0>: RP14 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP14 (see Table11-4 for peripheral function numbers). DS30010038C-page 190  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-31: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP17R<5:0>: RP17 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP17 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP16R<5:0>: RP16 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP16 (see Table11-4 for peripheral function numbers). Note 1: These pins are not available in 28-pin devices. REGISTER 11-32: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R<5:0>: RP19 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP19 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP18R<5:0>: RP18 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP18 (see Table11-4 for peripheral function numbers). Note 1: These pins are not available in 28-pin devices.  2013-2015 Microchip Technology Inc. DS30010038C-page 191

PIC24FJ128GA204 FAMILY REGISTER 11-33: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP21R<5:0>: RP21 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP21 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP20R<5:0>: RP20 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP20 (see Table11-4 for peripheral function numbers). Note 1: These pins are not available in 28-pin devices. REGISTER 11-34: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R<5:0>: RP23 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP23 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP22R<5:0>: RP22 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP22 (see Table11-4 for peripheral function numbers). Note 1: These pins are not available in 28-pin devices. DS30010038C-page 192  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 11-35: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP25R<5:0>: RP25 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP25 (see Table11-4 for peripheral function numbers). bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RP24R<5:0>: RP24 Output Pin Mapping bits Peripheral Output Number n is assigned to pin, RP24 (see Table11-4 for peripheral function numbers). Note 1: These pins are not available in 28-pin devices.  2013-2015 Microchip Technology Inc. DS30010038C-page 193

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 194  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 12.0 TIMER1 Figure12-1 shows a block diagram of the 16-bit timer module. Note: This data sheet summarizes the features of To configure Timer1 for operation: this group of PIC24F devices. It is not intended to be a comprehensive reference 1. Set the TON bit (= 1). source. For more information, refer to 2. Select the timer prescaler ratio using the the “dsPIC33/PIC24 Family Reference TCKPS<1:0> bits. Manual”, “Timers” (DS39704). The infor- 3. Set the Clock and Gating modes using the TCS, mation in this data sheet supersedes the TECS<1:0> and TGATE bits. information in the FRM. 4. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. The Timer1 module is a 16-bit timer, which can serve as the time counter for the Real-Time Clock (RTC) or 5. Load the timer period value into the PR1 operate as a free-running, interval timer/counter. register. Timer1 can operate in three modes: 6. If interrupts are required, set the Timer1 Inter- rupt Enable bit, T1IE. Use the Timer1 Interrupt • 16-Bit Timer Priority bits, T1IP<2:0>, to set the interrupt • 16-Bit Synchronous Counter priority. • 16-Bit Asynchronous Counter Timer1 also supports these features: • Timer Gate Operation • Selectable Prescaler Settings • Timer Operation during CPU Idle and Sleep modes • Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 12-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TGATE LPRC Clock SOSCO D Q 1 Input Select Set T1IF CK Q 0 Reset SOSCI TMR1 SOSCSEL Comparator Equal SOSCEN PR1 Clock Input Select Detail SOSC Gate Input Output TCKPS<1:0> T1CK Input TON 2 TMRCK Input LPRC Input Gate Prescaler 0 Sync 1, 8, 64, 256 Clock Output 2 to TMR1 Sync 1 TCY TECS<1:0> TSYNC TGATE TCS  2013-2015 Microchip Technology Inc. DS30010038C-page 195

PIC24FJ128GA204 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — TECS1 TECS0 bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timer1 Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TECS<1:0>: Timer1 Extended Clock Source Select bits (selected when TCS = 1) When TCS = 1: 11 = Generic Timer (TMRCK) External Input 10 = LPRC Oscillator 01 = T1CK External Clock Input 00 = SOSC When TCS = 0: These bits are ignored; the Timer is clocked from the internal system clock (FOSC/2). bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as ‘0’ Note 1: Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS30010038C-page 196  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER(1) (CONTINUED) bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronizes external clock input 0 = Does not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = Extended clock selected by the TECS<1:0> bits 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of T1CON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended.  2013-2015 Microchip Technology Inc. DS30010038C-page 197

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 198  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 13.0 TIMER2/3 AND TIMER4/5 To configure Timer2/3 or Timer4/5 for 32-bit operation: 1. Set the T32 or T45 bit (T2CON<3> or Note: This data sheet summarizes the features of T4CON<3> = 1). this group of PIC24F devices. It is not 2. Select the prescaler ratio for Timer2 or Timer4 intended to be a comprehensive reference using the TCKPS<1:0> bits. source. For more information, refer to 3. Set the Clock and Gating modes using the TCS the “dsPIC33/PIC24 Family Reference and TGATE bits. If TCS is set to an external Manual”, “Timers” (DS39704). The infor- clock, RPINRx (TxCK) must be configured to mation in this data sheet supersedes the an available RPn/RPIn pin. For more informa- information in the FRM. tion, see Section 11.4“Peripheral Pin Select The Timer2/3 and Timer4/5 modules are 32-bit timers, (PPS)”. which can also be configured as four independent, 16-bit 4. Load the timer period value. PR3 (or PR5) will timers with selectable operating modes. contain the most significant word (msw) of the As 32-bit timers, Timer2/3 and Timer4/5 can each value, while PR2 (or PR4) contains the least operate in three modes: significant word (lsw). 5. If interrupts are required, set the interrupt enable • Two Independent 16-Bit Timers with all 16-Bit bit, T3IE or T5IE. Use the priority bits, T3IP<2:0> Operating modes (except Asynchronous Counter or T5IP<2:0>, to set the interrupt priority. Note mode) that while Timer2 or Timer4 controls the timer, the • Single 32-Bit Timer interrupt appears as a Timer3 or Timer5 interrupt. • Single 32-Bit Synchronous Counter 6. Set the TON bit (= 1). They also support these features: The timer value, at any point, is stored in the register • Timer Gate Operation pair, TMR<3:2> (or TMR<5:4>). TMR3 (TMR5) always • Selectable Prescaler Settings contains the most significant word of the count, while • Timer Operation during Idle and Sleep modes TMR2 (TMR4) contains the least significant word. • Interrupt on a 32-Bit Period Register Match To configure any of the timers for individual 16-bit • A/D Event Trigger (only on Timer2/3 in 32-bit operation: mode and Timer3 in 16-bit mode) 1. Clear the T32 bit corresponding to that timer Individually, all four of the 16-bit timers can function as (T2CON<3> for Timer2 and Timer3 or synchronous timers or counters. They also offer the T4CON<3> for Timer4 and Timer5). features listed above, except for the A/D Event Trigger. 2. Select the timer prescaler ratio using the This trigger is implemented only on Timer2/3 in 32-bit TCKPS<1:0> bits. mode and Timer3 in 16-bit mode. The operating modes 3. Set the Clock and Gating modes using the TCS and enabled features are determined by setting the and TGATE bits. See Section 11.4“Peripheral appropriate bit(s) in the T2CON, T3CON, T4CON and Pin Select (PPS)” for more information. T5CON registers. T2CON and T4CON are shown in 4. Load the timer period value into the PRx register. generic form in Register13-1; T3CON and T5CON are 5. If interrupts are required, set the interrupt enable shown in Register13-2. bit, TxIE. Use the priority bits, TxIP<2:0>, to set For 32-bit timer/counter operation, Timer2 and Timer4 the interrupt priority. are the least significant word; Timer3 and Timer5 are 6. Set the TON (TxCON<15> = 1) bit. the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags.  2013-2015 Microchip Technology Inc. DS30010038C-page 199

PIC24FJ128GA204 FAMILY FIGURE 13-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TCY TCKPS<1:0> TMRCK 2 SOSC Input LPRC Input Gate Prescaler 1, 8, 64, 256 Sync TECS<1:0> TGATE TGATE(2) TCS(2) 1 Q D Set T3IF (T5IF) 0 Q CK PR3 PR2 (PR5) (PR4) Equal Comparator A/D Event Trigger(3) MSB LSB TMR3 TMR2 Sync Reset (TMR5) (TMR4) 16 Read TMR2 (TMR4)(1) Write TMR2 (TMR4)(1) 16 16 TMR3HLD (TMR5HLD) Data Bus<15:0> Note 1: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. 2: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4“Peripheral Pin Select (PPS)” for more information. 3: The A/D Event Trigger is available only on Timer2/3 in 32-bit mode and Timer3 in 16-bit mode. DS30010038C-page 200  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 13-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK TCY (T4CK) TCKPS<1:0> TMRCK TON 2 SOSC Input Prescaler LPRC Input Gate 1, 8, 64, 256 Sync TECS<1:0> TGATE TGATE(1) TCS(1) 1 Q D Set T2IF (T4IF) 0 Q CK Reset TMR2 (TMR4) Sync Comparator Equal PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. FIGURE 13-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK TCY (T5CK) TCKPS<1:0> TMRCK TON 2 SOSC Input Prescaler LPRC Input Gate 1, 8, 64, 256 Sync TECS<1:0> TGATE TGATE(1) TCS(1) 1 Q D Set T3IF (T5IF) Q CK 0 Reset TMR3 (TMR5) A/D Event Trigger(2) Comparator Equal PR3 (PR5) Note 1: The timer clock input must be assigned to an available RPn/RPIn pin before use. See Section 11.4“Peripheral Pin Select (PPS)” for more information. 2: The A/D Event Trigger is available only on Timer3.  2013-2015 Microchip Technology Inc. DS30010038C-page 201

PIC24FJ128GA204 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON — TSIDL — — — TECS1(2) TECS0(2) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(3) — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timerx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TECS<1:0>: Timerx Extended Clock Source Select bits (selected when TCS = 1)(2) When TCS = 1: 11 = Generic Timer (TMRCK) External Input 10 = LPRC Oscillator 01 = TxCK External Clock Input 00 = SOSC When TCS = 0: These bits are ignored; the Timer is clocked from the internal system clock (FOSC/2). bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TMRCK or TxCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.4“Peripheral Pin Select (PPS)”. 3: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. DS30010038C-page 202  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 13-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(1) (CONTINUED) bit 3 T32: 32-Bit Timer Mode Select bit(3) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timerx Clock Source Select bit(2) 1 = Timer source is selected by TECS<1:0> 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TMRCK or TxCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.4“Peripheral Pin Select (PPS)”. 3: In T4CON, the T45 bit is implemented instead of T32 to select 32-bit mode. In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation.  2013-2015 Microchip Technology Inc. DS30010038C-page 203

PIC24FJ128GA204 FAMILY REGISTER 13-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 TON(2) — TSIDL(2) — — — TECS1(2,3) TECS0(2,3) bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(2) TCKPS1(2) TCKPS0(2) — — TCS(2,3) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as ‘0’ bit 13 TSIDL: Timery Stop in Idle Mode bit(2) 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-10 Unimplemented: Read as ‘0’ bit 9-8 TECS<1:0>: Timery Extended Clock Source Select bits (selected when TCS = 1)(2,3) 11 = Generic Timer (TMRCK) External Input 10 = LPRC Oscillator 01 = TxCK External Clock Input 00 = SOSC bit 7 Unimplemented: Read as ‘0’ bit 6 TGATE: Timery Gated Time Accumulation Enable bit(2) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 5-4 TCKPS<1:0>: Timery Input Clock Prescale Select bits(2) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as ‘0’ bit 1 TCS: Timery Clock Source Select bit(2,3) 1 = External clock from pin, TyCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as ‘0’ Note 1: Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. 2: When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. 3: If TCS = 1 and TECS<1:0> = x1, the selected external timer input (TyCK) must be configured to an available RPn/RPIn pin. For more information, see Section 11.4“Peripheral Pin Select (PPS)”. DS30010038C-page 204  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 14.0 INPUT CAPTURE WITH 14.1 General Operating Modes DEDICATED TIMERS 14.1.1 SYNCHRONOUS AND TRIGGER Note: This data sheet summarizes the features of MODES this group of PIC24F devices. It is not When the input capture module operates in a Free- intended to be a comprehensive reference Running mode, the internal 16-bit counter, ICxTMR, source. For more information, refer to counts up continuously, wrapping around from FFFFh the “dsPIC33/PIC24 Family Reference to 0000h on each overflow. Its period is synchronized Manual”, “Input Capture with Dedicated to the selected external clock source. When a capture Timer” (DS39722). The information in this event occurs, the current 16-bit value of the internal data sheet supersedes the information in counter is written to the FIFO buffer. the FRM. In Synchronous mode, the module begins capturing Devices in the PIC24FJ128GA204 family contain six events on the ICx pin as soon as its selected clock independent input capture modules. Each of the modules source is enabled. Whenever an event occurs on the offers a wide range of configuration and operating selected sync source, the internal counter is reset. In options for capturing external pulse events and Trigger mode, the module waits for a sync event from generating interrupts. another internal module to occur before allowing the internal counter to run. Key features of the input capture module include: Standard, free-running operation is selected by setting • Hardware-configurable for 32-bit operation in all the SYNCSEL<4:0> bits (ICxCON2<4:0>) to ‘00000’ modes by cascading two adjacent modules and clearing the ICTRIG bit (ICxCON2<7>). Synchro- • Synchronous and Trigger modes of output nous and Trigger modes are selected any time the compare operation with up to 30 user-selectable SYNCSELx bits are set to any value except ‘00000’. The sync/trigger sources available ICTRIG bit selects either Synchronous or Trigger mode; • A 4-level FIFO buffer for capturing and holding setting the bit selects Trigger mode operation. In both timer values for several events modes, the SYNCSELx bits determine the sync/trigger • Configurable interrupt generation source. • Up to 6 clock sources available for each module, When the SYNCSELx bits are set to ‘00000’ and driving a separate, internal 16-bit counter ICTRIG is set, the module operates in Software Trigger The module is controlled through two registers: ICxCON1 mode. In this case, capture operations are started by (Register14-1) and ICxCON2 (Register14-2). A general manually setting the TRIGSTAT bit (ICxCON2<6>). block diagram of the module is shown in Figure14-1. FIGURE 14-1: INPUT CAPTURE x BLOCK DIAGRAM ICM<2:0> ICI<1:0> Prescaler Edge Detect Logic Event and Set ICxIF Counter and Interrupt 1:1/4/16 Clock Synchronizer Logic ICx Pin(1) ICTSEL<2:0> Increment ICx Clock Clock 16 4-Level FIFO Buffer 16 Sources Select ICxTMR 16 Sync and Reset ICxBUF Sync and Trigger Trigger Sources Logic SYNCSEL<4:0> Trigger ICOV, ICBNE System Bus Note 1: The ICx inputs must be assigned to an available RPn/RPIn pin before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information.  2013-2015 Microchip Technology Inc. DS30010038C-page 205

PIC24FJ128GA204 FAMILY 14.1.2 CASCADED (32-BIT) MODE For 32-bit cascaded operations, the setup procedure is slightly different: By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent 1. Set the IC32 bits for both modules (ICyCON2<8> even and odd modules can be configured to function as and ICxCON2<8>), enabling the even numbered a single 32-bit module. (For example, Modules 1 and 2 module first. This ensures that the modules will are paired, as are Modules 3 and 4, and so on.) The start functioning in unison. odd numbered module, Input Capture x (ICx), provides 2. Set the ICTSELx and SYNCSELx bits for both the Least Significant 16 bits of the 32-bit register pairs modules to select the same sync/trigger and and the even numbered module, Input Capture y (ICy), time base source. Set the even module first, provides the Most Significant 16 bits. Wrap arounds then the odd module. Both modules must use of the ICx registers cause an increment of their the same ICTSELx and SYNCSELx bit settings. corresponding ICy registers. 3. Clear the ICTRIG bit of the even module Cascaded operation is configured in hardware by (ICyCON2<7>). This forces the module to run in setting the IC32 bits (ICxCON2<8>) for both modules. Synchronous mode with the odd module, regardless of its trigger setting. 14.2 Capture Operations 4. Use the odd module’s ICIx bits (ICxCON1<6:5>) to set the desired interrupt frequency. The input capture module can be configured to capture 5. Use the ICTRIG bit of the odd module timer values and generate interrupts on rising edges on (ICxCON2<7>) to configure Trigger or ICx or all transitions on ICx. Captures can be config- Synchronous mode operation. ured to occur on all rising edges or just some (every 4th or 16th). Interrupts can be independently configured to Note: For Synchronous mode operation, enable generate on each event or a subset of events. the sync source as the last step. Both input capture modules are held in Reset To set up the module for capture operations: until the sync source is enabled. 1. Configure the ICx input for one of the available Peripheral Pin Select pins. 6. Use the ICMx bits of the odd module (ICxCON1<2:0>) to set the desired Capture 2. If Synchronous mode is to be used, disable the mode. sync source before proceeding. 3. Make sure that any previous data has been The module is ready to capture events when the time removed from the FIFO by reading ICxBUF until base and the sync/trigger source are enabled. When the ICBNE bit (ICxCON1<3>) is cleared. the ICBNE bit (ICxCON1<3>) becomes set, at least one capture value is available in the FIFO. Read input 4. Set the SYNCSELx bits (ICxCON2<4:0>) to the capture values from the FIFO until the ICBNE clears desired sync/trigger source. to‘0’. 5. Set the ICTSELx bits (ICxCON1<12:10>) for the desired clock source. For 32-bit operation, read both the ICxBUF and ICyBUF for the full 32-bit timer value (ICxBUF for the 6. Set the ICIx bits (ICxCON1<6:5>) to the desired lsw, ICyBUF for the msw). At least one capture value is interrupt frequency available in the FIFO buffer when the odd module’s 7. Select Synchronous or Trigger mode operation: ICBNE bit (ICxCON1<3>) becomes set. Continue to a) Check that the SYNCSELx bits are not set read the buffer registers until ICBNE is cleared to ‘00000’. (performed automatically by hardware). b) For Synchronous mode, clear the ICTRIG bit (ICxCON2<7>). c) For Trigger mode, set ICTRIG and clear the TRIGSTAT bit (ICxCON2<6>). 8. Set the ICMx bits (ICxCON1<2:0>) to the desired operational mode. 9. Enable the selected sync/trigger source. DS30010038C-page 206  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 — — bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 — ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-10 ICTSEL<2:0>: Input Capture x Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 bit 9-7 Unimplemented: Read as ‘0’ bit 6-5 ICI<1:0>: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow has occurred 0 = No input capture overflow has occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM<2:0>: Input Capture x Mode Select bits(1) 111 = Interrupt mode: Input capture functions as an interrupt pin only when the device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module is disabled) 101 = Prescaler Capture mode: Capture on every 16th rising edge 100 = Prescaler Capture mode: Capture on every 4th rising edge 011 = Simple Capture mode: Capture on every rising edge 010 = Simple Capture mode: Capture on every falling edge 001 = Edge Detect Capture mode: Capture on every edge (rising and falling); ICI<1:0> bits do not control interrupt generation for this mode 000 = Input capture module is turned off Note 1: The ICx input must also be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2013-2015 Microchip Technology Inc. DS30010038C-page 207

PIC24FJ128GA204 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC32 bit 15 bit 8 R/W-0 R/W-0, HS U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ICTRIG TRIGSTAT — SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module bit 7 ICTRIG: Input Capture x Sync/Trigger Select bit 1 = Triggers ICx from the source designated by the SYNCSELx bits 0 = Synchronizes ICx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear bit 5 Unimplemented: Read as ‘0’ Note 1: Use these inputs as trigger sources only and never as sync sources. 2: Never use an ICx module as its own trigger source by selecting this mode. DS30010038C-page 208  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Synchronization/Trigger Source Selection bits 1111x = Reserved 11101 = Reserved 11100 = CTMU(1) 11011 = A/D(1) 11010 = Comparator 3(1) 11001 = Comparator 2(1) 11000 = Comparator 1(1) 10111 = Reserved 10110 = Reserved 10101 = Input Capture 6(2) 10100 = Input Capture 5(2) 10011 = Input Capture 4(2) 10010 = Input Capture 3(2) 10001 = Input Capture 2(2) 10000 = Input Capture 1(2) 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Reserved 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Output Compare 6 00101 = Output Compare 5 00100 = Output Compare 4 00011 = Output Compare 3 00010 = Output Compare 2 00001 = Output Compare 1 00000 = Not synchronized to any other module Note 1: Use these inputs as trigger sources only and never as sync sources. 2: Never use an ICx module as its own trigger source by selecting this mode.  2013-2015 Microchip Technology Inc. DS30010038C-page 209

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 210  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 15.0 OUTPUT COMPARE WITH In Synchronous mode, the module begins performing DEDICATED TIMERS its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on Note: This data sheet summarizes the features of the selected sync source, the module’s internal counter is reset. In Trigger mode, the module waits for a sync this group of PIC24F devices. It is not intended to be a comprehensive reference event from another internal module to occur before allowing the counter to run. source. For more information, refer to the “dsPIC33/PIC24 Family Reference Free-Running mode is selected by default or any time Manual”, “Output Compare with that the SYNCSEL<4:0> bits (OCxCON2<4:0>) are set Dedicated Timer” (DS70005159). The to ‘00000’. Synchronous or Trigger modes are selected information in this data sheet supersedes any time the SYNCSELx bits are set to any value except the information in the FRM. ‘00000’. The OCTRIG bit (OCxCON2<7>) selects either Synchronous or Trigger mode; setting the bit selects Devices in the PIC24FJ128GA204 family all feature six Trigger mode operation. In both modes, the SYNCSELx independent output compare modules. Each of these bits determine the sync/trigger source. modules offers a wide range of configuration and operating options for generating pulse trains on internal 15.1.2 CASCADED (32-BIT) MODE device events, and can produce Pulse-Width Modulated By default, each module operates independently with (PWM) waveforms for driving power applications. its own set of 16-bit Timer and Duty Cycle registers. To Key features of the output compare module include: increase resolution, adjacent even and odd modules • Hardware-configurable for 32-bit operation in all can be configured to function as a single 32-bit module. modes by cascading two adjacent modules (For example, Modules 1 and 2 are paired, as are Modules 3 and 4, and so on.) The odd numbered • Synchronous and Trigger modes of output module, Output Compare x (OCx), provides the Least compare operation, with up to 31 user-selectable Significant 16 bits of the 32-bit register pairs and the trigger/sync sources available even numbered module, Output Compare y (OCy), • Two separate Period registers (a main register, provides the Most Significant 16 bits. Wrap arounds of OCxR, and a secondary register, OCxRS) for the OCx registers cause an increment of their greater flexibility in generating pulses of varying corresponding OCy registers. widths • Configurable for single pulse or continuous pulse Cascaded operation is configured in hardware by set- generation on an output event, or continuous ting the OC32 bit (OCxCON2<8>) for both modules. PWM waveform generation For more information on cascading, refer to the “dsPIC33/PIC24 Family Reference Manual”, “Output • Up to 6 clock sources available for each module, Compare with Dedicated Timer” (DS70005159). driving a separate internal 16-bit counter 15.1 General Operating Modes 15.1.1 SYNCHRONOUS AND TRIGGER MODES When the output compare module operates in a Free- Running mode, the internal 16-bit counter, OCxTMR, runs counts up continuously, wrapping around from 0xFFFF to 0x0000 on each overflow. Its period is synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the Period registers occurs.  2013-2015 Microchip Technology Inc. DS30010038C-page 211

PIC24FJ128GA204 FAMILY FIGURE 15-1: OUTPUT COMPARE x BLOCK DIAGRAM (16-BIT MODE) OCM<2:0> OCINV OCxCON1 OCTRIS OCTSEL<2:0> FLTOUT OCxCON2 SYNCSEL<4:0> FLTTRIEN TRIGSTAT FLTMD TRIGMODE ENFLT<2:0> OCTRIG OCxR and OCFLT<2:0> DCB<1:0> DCB<1:0> Match Event OCx Pin(1) Comparator Increment OCx Clock Clock Sources Select OC Output and OCxTMR Reset Fault Logic Match Event OCFA/OCFB(2) Comparator Match Event Trigger and Trigger and OCxRS Sync Sources Sync Logic Reset OCx Interrupt Note 1: The OCx outputs must be assigned to an available RPn pin before use. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 15.2 Compare Operations 3. Write the rising edge value to OCxR and the falling edge value to OCxRS. In Compare mode (Figure15-1), the output compare 4. Set the Timer Period register, PRy, to a value module can be configured for single-shot or continuous equal to or greater than the value in OCxRS. pulse generation. It can also repeatedly toggle an 5. Set the OCM<2:0> bits for the appropriate output pin on each timer event. compare operation (‘0xx’). To set up the module for compare operations: 6. For Trigger mode operations, set OCTRIG to 1. Configure the OCx output for one of the enable Trigger mode. Set or clear TRIGMODE available Peripheral Pin Select pins. to configure trigger operation and TRIGSTAT to 2. Calculate the required values for the OCxR and select a hardware or software trigger. For (for Double Compare modes) OCxRS Duty Synchronous mode, clear OCTRIG. Cycle registers: 7. Set the SYNCSEL<4:0> bits to configure the a) Determine the instruction clock cycle time. trigger or synchronization source. If free-running Take into account the frequency of the timer operation is required, set the SYNCSELx external clock to the timer source (if one is bits to ‘00000’ (no sync/trigger source). used) and the timer prescaler settings. 8. Select the time base source with the b) Calculate the time to the rising edge of the OCTSEL<2:0> bits. If necessary, set the TON bit output pulse relative to the timer start value for the selected timer, which enables the com- (0000h). pare time base to count. Synchronous mode c) Calculate the time to the falling edge of the operation starts as soon as the time base is pulse based on the desired pulse width and enabled; Trigger mode operation starts after a the time to the rising edge of the pulse. trigger source event occurs. DS30010038C-page 212  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY For 32-bit cascaded operation, these steps are also 15.3 Pulse-Width Modulation (PWM) necessary: Mode 1. Set the OC32 bits for both registers In PWM mode, the output compare module can be (OCyCON2<8>) and (OCxCON2<8>). Enable configured for edge-aligned or center-aligned pulse the even numbered module first to ensure the waveform generation. All PWM operations are double- modules will start functioning in unison. buffered (buffer registers are internal to the module and 2. Clear the OCTRIG bit of the even module are not mapped into SFR space). (OCyCON2<7>), so the module will run in To configure the output compare module for PWM Synchronous mode. operation: 3. Configure the desired output and Fault settings for OCy. 1. Configure the OCx output for one of the 4. Force the output pin for OCx to the output state available Peripheral Pin Select pins. by clearing the OCTRIS bit. 2. Calculate the desired duty cycles and load them 5. If Trigger mode operation is required, configure into the OCxR register. the trigger options in OCx by using the OCTRIG 3. Calculate the desired period and load it into the (OCxCON2<7>), TRIGMODE (OCxCON1<3>) OCxRS register. and SYNCSELx (OCxCON2<4:0>) bits. 4. Select the current OCx as the synchronization 6. Configure the desired Compare or PWM mode source by writing ‘0x1F’ to the SYNCSEL<4:0> of operation (OCM<2:0>) for OCy first, then for bits (OCxCON2<4:0>) and ‘0’ to the OCTRIG bit OCx. (OCxCON2<7>). Depending on the output mode selected, the module 5. Select a clock source by writing to the holds the OCx pin in its default state and forces a tran- OCTSEL<2:0> bits (OCxCON1<12:10>). sition to the opposite state when OCxR matches the 6. Enable interrupts, if required, for the timer and timer. In Double Compare modes, OCx is forced back output compare modules. The output compare to its default state when a match with OCxRS occurs. interrupt is required for PWM Fault pin The OCxIF interrupt flag is set after an OCxR match in utilization. Single Compare modes and after each OCxRS match 7. Select the desired PWM mode in the OCM<2:0> in Double Compare modes. bits (OCxCON1<2:0>). Single-shot pulse events only occur once, but may 8. Appropriate Fault inputs may be enabled by be repeated by simply rewriting the value of the using the ENFLT<2:0> bits as described in OCxCON1 register. Continuous pulse events continue Register15-1. indefinitely until terminated. 9. If a timer is selected as a clock source, set the selected timer prescale value. The selected timer’s prescaler output is used as the clock input for the OCx timer and not the selected timer output. Note: This peripheral contains input and output functions that may need to be configured by the Peripheral Pin Select. For more infor- mation, see Section11.4 “Peripheral Pin Select (PPS)”.  2013-2015 Microchip Technology Inc. DS30010038C-page 213

PIC24FJ128GA204 FAMILY FIGURE 15-2: OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCM<2:0> OCxCON2 OCINV OCTSEL<2:0> OCTRIS SYNCSEL<4:0> OCxR and FLTOUT TRIGSTAT DCB<1:0> FLTTRIEN TRIGMODE FLTMD OCTRIG Rollover/Reset ENFLT<2:0> OCFLT<2:0> OCxR and DCB<1:0> DCB<1:0> Buffers OCx Pin(1) Comparator Increment Match OCx Clock Clock Event Sources Select OCx Output and OCxTMR Rollover Fault Logic Reset OCFA/OCFB(2) Comparator Match Event Match Trigger and Trigger and Event Sync Sources Sync Logic OCxRS Buffer Rollover/Reset OCxRS OCx Interrupt Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 15.3.1 PWM PERIOD The PWM period is specified by writing to PRy, the Timery Period register. The PWM period can be calculated using Equation15-1. EQUATION 15-1: CALCULATING THE PWM PERIOD(1) PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] Note1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled. Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7, written into the PRy register, will yield a period consisting of 8 time base cycles. DS30010038C-page 214  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 15.3.2 PWM DUTY CYCLE Some important boundary parameters of the PWM duty cycle include: The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR • If OCxR, OCxRS and PRy are all loaded with registers can be written to at any time, but the duty 0000h, the OCx pin will remain low (0% duty cycle). cycle value is not latched until a match between PRy • If OCxRS is greater than PRy, the pin will remain and TMRy occurs (i.e., the period is complete). This high (100% duty cycle). provides a double buffer for the PWM duty cycle and is See Example15-1 for PWM mode timing details. essential for glitchless PWM operation. Table15-1 and Table15-2 show example PWM frequencies and resolutions for a device operating at 4MIPS and 10 MIPS, respectively. EQUATION 15-2: CALCULATION FOR MAXIMUM PWM RESOLUTION(1) log10( FCY ) FPWM • (Timer Prescale Value) Maximum PWM Resolution (bits) = bits log 10 Note1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. EXAMPLE 15-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2ms PWM Period = (PR2 + 1) • TCY • (Timer2 Prescale Value) 19.2s = (PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32MHz device clock rate: PWM Resolution = log10(FCY/FPWM)/log102) bits = (log (16 MHz/52.08 kHz)/log 2) bits 10 10 = 8.3 bits Note1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh Resolution (bits) 16 16 15 12 10 7 5 Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.  2013-2015 Microchip Technology Inc. DS30010038C-page 215

PIC24FJ128GA204 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OCSIDL OCTSEL2 OCTSEL1 OCTSEL0 ENFLT2(2) ENFLT1(2) bit 15 bit 8 R/W-0 R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0 R/W-0 R/W-0 R/W-0 ENFLT0(2) OCFLT2(2,3) OCFLT1(2,4) OCFLT0(2,4) TRIGMODE OCM2(1) OCM1(1) OCM0(1) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 OCSIDL: Output Compare x Stop in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode bit 12-10 OCTSEL<2:0>: Output Compare x Timer Select bits 111 = Peripheral clock (FCY) 110 = Reserved 101 = Reserved 100 = Timer1 clock (only synchronous clock is supported) 011 = Timer5 clock 010 = Timer4 clock 001 = Timer3 clock 000 = Timer2 clock bit 9 ENFLT2: Fault Input 2 Enable bit(2) 1 = Fault 2 (Comparator 1/2/3 out) is enabled(3) 0 = Fault 2 is disabled bit 8 ENFLT1: Fault Input 1 Enable bit(2) 1 = Fault 1 (OCFB pin) is enabled(4) 0 = Fault 1 is disabled bit 7 ENFLT0: Fault Input 0 Enable bit(2) 1 = Fault 0 (OCFA pin) is enabled(4) 0 = Fault 0 is disabled bit 6 OCFLT2: Output Compare x PWM Fault 2 (Comparator 1/2/3) Condition Status bit(2,3) 1 = PWM Fault 2 has occurred 0 = No PWM Fault 2 has occurred bit 5 OCFLT1: Output Compare x PWM Fault 1 (OCFB pin) Condition Status bit(2,4) 1 = PWM Fault 1 has occurred 0 = No PWM Fault 1 has occurred Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC2 channels; Comparator 2 output controls the OC3-OC4 channels; Comparator 3 output controls the OC5-OC6 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. DS30010038C-page 216  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED) bit 4 OCFLT0: Output Compare x PWM Fault 0 (OCFA pin) Condition Status bit(2,4) 1 = PWM Fault 0 has occurred 0 = No PWM Fault 0 has occurred bit 3 TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software bit 2-0 OCM<2:0>: Output Compare x Mode Select bits(1) 111 = Center-Aligned PWM mode on OCx(2) 110 = Edge-Aligned PWM mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initializes the OCx pin low; toggles the OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initializes the OCx pin low; toggles the OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin 010 = Single Compare Single-Shot mode: Initializes OCx pin high; compare event forces the OCx pin low 001 = Single Compare Single-Shot mode: Initializes OCx pin low; compare event forces the OCx pin high 000 = Output compare channel is disabled Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110. 3: The Comparator 1 output controls the OC1-OC2 channels; Comparator 2 output controls the OC3-OC4 channels; Comparator 3 output controls the OC5-OC6 channels. 4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2013-2015 Microchip Technology Inc. DS30010038C-page 217

PIC24FJ128GA204 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV — DCB1(3) DCB0(3) OC32 bit 15 bit 8 R/W-0 R/W-0, HS R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault bit 12 OCINV: Output Compare x Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11 Unimplemented: Read as ‘0’ bit 10-9 DCB<1:0>: PWM Duty Cycle Least Significant bits(3) 11 = Delays OCx falling edge by ¾ of the instruction cycle 10 = Delays OCx falling edge by ½ of the instruction cycle 01 = Delays OCx falling edge by ¼ of the instruction cycle 00 = OCx falling edge occurs at the start of the instruction cycle bit 8 OC32: Cascade Two Output Compare Modules Enable bit (32-bit operation) 1 = Cascade module operation is enabled 0 = Cascade module operation is disabled bit 7 OCTRIG: Output Compare x Trigger/Sync Select bit 1 = Triggers OCx from the source designated by the SYNCSELx bits 0 = Synchronizes OCx with the source designated by the SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: Output Compare x Output Pin Direction Select bit 1 = OCx pin is tri-stated 0 = Output Compare Peripheral x is connected to an OCx pin Note 1: Never use an OCx module as its own trigger source, either by selecting this mode or another equivalent SYNCSELx setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: The DCB<1:0> bits are double-buffered in PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110). DS30010038C-page 218  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED) bit 4-0 SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = OCTRIG1 external input 11101 = OCTRIG2 external input 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Reserved 10110 = Reserved 10101 = Input Capture 6(2) 10100 = Input Capture 5(2) 10011 = Input Capture 4(2) 10010 = Input Capture 3(2) 10001 = Input Capture 2(2) 10000 = Input Capture 1(2) 01111 = Timer5 01110 = Timer4 01101 = Timer3 01100 = Timer2 01011 = Timer1 01010 = Reserved 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Note 1: Never use an OCx module as its own trigger source, either by selecting this mode or another equivalent SYNCSELx setting. 2: Use these inputs as trigger sources only and never as sync sources. 3: The DCB<1:0> bits are double-buffered in PWM modes only (OCM<2:0> (OCxCON1<2:0>) = 111, 110).  2013-2015 Microchip Technology Inc. DS30010038C-page 219

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 220  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 16.0 SERIAL PERIPHERAL The SPI serial interface consists of four pins: INTERFACE (SPI) • SDIx: Serial Data Input • SDOx: Serial Data Output Note: This data sheet summarizes the features • SCKx: Shift Clock Input or Output of the PIC24FJ128GA204 family of • SSx: Active-Low Slave Select or Frame devices. It is not intended to be a compre- Synchronization I/O Pulse hensive reference source. To complement the information in this data sheet, refer to The SPI module can be configured to operate using 2, the “dsPIC33/PIC24 Family Reference 3 or 4 pins. In the 3-pin mode, SSx is not used. In the Manual”, “Serial Peripheral Interface 2-pin mode, both SDOx and SSx are not used. (SPI) with Audio Codec Support” The SPI module has the ability to generate three inter- (DS70005136) which is available from the rupts, reflecting the events that occur during the data Microchip web site (www.microchip.com). communication. The following types of interrupts can be generated: The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating 1. Receive interrupts are signalled by SPIxRXIF. with other peripheral or microcontroller devices. These This event occurs when: peripheral devices may be serial EEPROMs, shift - RX watermark interrupt registers, display drivers, A/D Converters, etc. The SPI - SPIROV = 1 module is compatible with the Motorola® SPI and SIOP - SPIRBF = 1 interfaces. All devices in the PIC24FJ128GA204 family include three SPI modules. - SPIRBE = 1 The module supports operation in two buffer modes. In provided the respective mask bits are enabled in Standard Buffer mode, data is shifted through a single SPIxIMSKL/H. serial buffer. In Enhanced Buffer mode, data is shifted 2. Transmit interrupts are signalled by SPIxTXIF. through a FIFO buffer. The FIFO level depends on the This event occurs when: configured mode. - TX watermark interrupt Variable length data can be transmitted and received, - SPITUR = 1 from 2 to 32-bits. - SPITBF = 1 Note: Do not perform Read-Modify-Write opera- - SPITBE = 1 tions (such as bit-oriented instructions) on provided the respective mask bits are enabled in the SPIxBUF register in either Standard or SPIxIMSKL/H. Enhanced Buffer mode. 3. General interrupts are signalled by SPIxIF. This The module also supports a basic framed SPI protocol event occurs when while operating in either Master or Slave mode. A total - FRMERR = 1 of four framed SPI configurations are supported. - SPIBUSY = 1 The module also supports Audio modes. Four different - SRMT = 1 Audio modes are available. provided the respective mask bits are enabled in • I2S mode SPIxIMSKL/H. • Left Justified Block diagrams of the module in Standard and Enhanced • Right Justified modes are shown in Figure16-1 and Figure16-2. • PCM/DSP Note: In this section, the SPI modules are In each of these modes, the serial clock is free-running referred to together as SPIx, or separately and audio data is always transferred. as SPI1, SPI2 or SPI3. Special Function If an audio protocol data transfer takes place between Registers will follow a similar notation. For two devices, then usually one device is the master and example, SPIxCON1L and SPIxCON1H the other is the slave. However, audio data can be refer to the control registers for any of the transferred between two slaves. Because the audio three SPI modules. protocols require free-running clocks, the master can be a third party controller. In either case, the master generates two free-running clocks: SCKx and LRC (Left, Right Channel Clock/SSx/FSYNC).  2013-2015 Microchip Technology Inc. DS30010038C-page 221

PIC24FJ128GA204 FAMILY 16.1 Standard Master Mode 16.2 Standard Slave Mode To set up the SPIx module for the Standard Master To set up the SPIx module for the Standard Slave mode mode of operation: of operation: 1. If using interrupts: 1. Clear the SPIxBUF registers. a) Clear the interrupt flag bits in the respective 2. If using interrupts: IFSx register. a) Clear the SPIxBUFL and SPIxBUFH b) Set the interrupt enable bits in the registers. respective IECx register. b) Set the interrupt enable bits in the c) Write the SPIxIP<2:0> bits in the respective respective IECx register. IPCx register to set the interrupt priority. c) Write the SPIxIP<2:0> bits in the respective 2. Write the desired settings to the SPIxCON1L IPCx register to set the interrupt priority. and SPIxCON1H registers with the MSTEN bit 3. Write the desired settings to the SPIxCON1L, (SPIxCON1L<5>) = 1. SPIxCON1H and SPIxCON2L registers with 3. Clear the SPIROV bit (SPIxSTATL<6>). the MSTEN bit (SPIxCON1L<5>) = 0. 4. Enable SPIx operation by setting the SPIEN bit 4. Clear the SMP bit. (SPIxCON1L<15>). 5. If the CKE bit (SPIxCON1L<8>) is set, then the 5. Write the data to be transmitted to the SPIxBUFL SSEN bit (SPIxCON1L<7>) must be set to and SPIxBUFH registers. Transmission (and enable the SSx pin. reception) will start as soon as data is written to 6. Clear the SPIROV bit (SPIxSTATL<6>). the SPIxBUFL and SPIxBUFH registers. 7. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L<15>). FIGURE 16-1: SPIx MODULE BLOCK DIAGRAM (STANDARD MODE) Internal Data Bus Read Write SPIxRXB SPIxTXB SPIxURDT MSB Receive Transmit SPIxRXSR SPIxTXSR SDIx MSB 0 SDOx Shift 1 Control TXELM<5:0> = 6’b0 URDTEN SSx & FSYNC Clock Edge Control Control Select MCLKEN SSx/FSYNC MCLK Baud Rate Generator PBCLK SCKx Edge Clock Select Control Enable Master Clock DS30010038C-page 222  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 16.3 Enhanced Master Mode 16.4 Enhanced Slave Mode To set up the SPIx module for the Enhanced Buffer To set up the SPIx module for the Enhanced Buffer Slave mode of operation: Master mode of operation: 1. Clear the SPIxBUFL and SPIxBUFH registers. 1. If using interrupts: 2. If using interrupts: a) Clear the interrupt flag bits in the respective a) Clear the interrupt flag bits in the respective IFSx register. IFSx register. b) Set the interrupt enable bits in the b) Set the interrupt enable bits in the respective IECx register. respective IECx register. c) Write the SPIxIP<2:0> bits in the respective c) Write the SPIxIP<2:0> bits in the respective IPCx register. IPCx register to set the interrupt priority. 2. Write the desired settings to the SPIxCON1L, 3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with SPIxCON1H and SPIxCON2L registers with the MSTEN (SPIxCON1L<5>) = 1. MSTEN bit (SPIxCON1L<5>) = 0. 3. Clear the SPIROV bit (SPIxSTATL<6>). 4. Clear the SMP bit. 4. Select Enhanced Buffer mode by setting the 5. If the CKE bit is set, then the SSEN bit must be ENHBUF bit (SPIxCON1L<0>). set, thus enabling the SSx pin. 5. Enable SPIx operation by setting the SPIEN bit 6. Clear the SPIROV bit (SPIxSTATL<6>). (SPIxCON1L<15>). 7. Select Enhanced Buffer mode by setting the 6. Write the data to be transmitted to the ENHBUF bit (SPIxCON1L<0>). SPIxBUFL and SPIxBUFH registers. Transmis- sion (and reception) will start as soon as data is 8. Enable SPIx operation by setting the SPIEN bit written to the SPIxBUFL and SPIxBUFH (SPIxCON1L<15>). registers. FIGURE 16-2: SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) Internal Data Bus Read Write SPIxRXB SPIxTXB SPIxURDT MSB Transmit Receive SPIxRXSR SPIxTXSR SDIx MSB 0 SDOx Shift 1 Control TXELM<5:0> = 6’b0 URDTEN SSx & FSYNC Clock Edge Control Control Select MCLKEN SSx/FSYNC MCLK Baud Rate Generator PBCLK SCKx Edge Clock Select Control Enable Master Clock  2013-2015 Microchip Technology Inc. DS30010038C-page 223

PIC24FJ128GA204 FAMILY 16.5 Audio Mode 16.6 Registers To set up the SPIx module for Audio mode: The SPI module consists of the following Special Function Registers (SFRs): 1. Clear the SPIxBUFL and SPIxBUFH registers. 2. If using interrupts: • SPIxCON1L, SPIxCON1H and SPIxCON2L: SPIx Control Registers (Register16-1, Register16-2 a) Clear the interrupt flag bits in the respective and Register16-3) IFSx register. • SPIxSTATL and SPIxSTATH: SPIx Status Registers b) Set the interrupt enable bits in the (Register16-4 and Register16-5) respective IECx register. • SPIxBUFL and SPIxBUFH: SPIx Buffer Registers a) Write the SPIxIP<2:0> bits in the respective IPCx register to set the interrupt priority. • SPIxBRGL and SPIxBRGH: SPIx Baud Rate Registers 3. Write the desired settings to the SPIxCON1L, SPIxCON1H and SPIxCON2L registers with • SPIxIMSKL and SPIxIMSKH: SPIx Interrupt Mask AUDEN (SPIxCON1H<15>) = 1. Registers (Register16-6 and Register16-7) 4. Clear the SPIROV bit (SPIxSTATL<6>). • SPIxURDTL and SPIxURDTH: SPIx Underrun Data Registers 5. Enable SPIx operation by setting the SPIEN bit (SPIxCON1L<15>). 6. Write the data to be transmitted to the SPIxBUFL and SPIxBUFH registers. Transmission (and reception) will start as soon as data is written to the SPIxBUFL and SPIxBUFH registers. REGISTER 16-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPIEN — SPISIDL DISSDO MODE32(1,4) MODE16(1,4) SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN(2) CKP MSTEN DISSDI DISSCK MCLKEN(3) SPIFE ENHBUF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx On bit 1 = Enables module 0 = Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR modifications bit 14 Unimplemented: Read as ‘0’ bit 13 SPISIDL: SPIx Stop in Idle Mode bit 1 = Halts in CPU Idle mode 0 = Continues to operate in CPU Idle mode bit 12 DISSDO: Disable SDOx Output Port bit 1 = SDOx pin is not used by the module; pin is controlled by the port function 0 = SDOx pin is controlled by the module Note 1: When AUDEN=1, this module functions as if CKE=0, regardless of its actual value. 2: When FRMEN=1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit=0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW. DS30010038C-page 224  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 16-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED) bit 11-10 MODE<32,16>: Serial Word Length bits(1,4) AUDEN=0: MODE32 MODE16 COMMUNICATION 1 x 32-Bit 0 1 16-Bit 0 0 8-Bit AUDEN=1: MODE32 MODE16 COMMUNICATION 1 1 24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 1 0 32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame 0 1 16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame 0 0 16-Bit Data, 16-Bit FIFO, 16-Bit Channel/32-Bit Frame bit 9 SMP: SPIx Data Input Sample Phase bit Master Mode: 1 = Input data is sampled at the end of data output time 0 = Input data is sampled at the middle of data output time Slave Mode: Input data is always sampled at the middle of data output time, regardless of the SMP bit setting. bit 8 CKE: SPIx Clock Edge Select bit(1) 1 = Transmit happens on transition from active clock state to Idle clock state 0 = Transmit happens on transition from Idle clock state to active clock state bit 7 SSEN: Slave Select Enable bit (Slave mode)(2) 1 = SSx pin is used by the macro in Slave mode; SSx pin is used as the slave select input 0 = SSx pin is not used by the macro (SSx pin will be controlled by the port I/O) bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode bit 4 DISSDI: Disable SDIx Input Port bit 1 = SDIx pin is not used by the module; pin is controlled by the port function 0 = SDIx pin is controlled by the module bit 3 DISSCK: Disable SCKx Output Port bit 1 = SCKx pin is not used by the module; pin is controlled by the port function 0 = SCKx pin is controlled by the module bit 2 MCLKEN: Master Clock Enable bit(3) 1 = MCLK is used by the BRG 0 = PBCLK is used by the BRG bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock 0 = Frame Sync pulse (Idle-to-active edge) precedes the first bit clock bit 0 ENHBUF: Enhanced Buffer Mode Enable bit 1 = Enhanced Buffer Mode is enabled 0 = Enhanced Buffer Mode is disabled Note 1: When AUDEN=1, this module functions as if CKE=0, regardless of its actual value. 2: When FRMEN=1, SSEN is not used. 3: MCLKEN can only be written when the SPIEN bit=0. 4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.  2013-2015 Microchip Technology Inc. DS30010038C-page 225

PIC24FJ128GA204 FAMILY REGISTER 16-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AUDEN(1) SPISGNEXT IGNROV IGNTUR AUDMONO(2) URDTEN(3) AUDMOD1(4) AUDMOD0(4) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT2 FRMCNT1 FRMCNT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 AUDEN: Audio Codec Support Enable bit(1) 1 = Audio protocol is enabled; MSTEN controls the direction of both SCKx and Frame (a.k.a. LRC), and this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT<2:0> = 001 and SMP =0, regardless of their actual values 0 = Audio protocol is disabled bit 14 SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit 1 = Data from RX FIFO is sign-extended 0 = Data from RX FIFO is not sign-extended bit 13 IGNROV: Ignore Receive Overflow bit 1 = A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO is not overwritten by the receive data 0 = A ROV is a critical error that stops SPI operation bit 12 IGNTUR: Ignore Transmit Underrun bit 1 = A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN is transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error that stops SPI operation bit 11 AUDMONO: Audio Data Format Transmit bit(2) 1 = Audio data is mono (i.e., each data word is transmitted on both left and right channels) 0 = Audio data is stereo bit 10 URDTEN: Transmit Underrun Data Enable bit(3) 1 = Transmits data out of SPIxURDT register during Transmit Underrun (TUR) conditions 0 = Transmits the last received data during Transmit Underrun conditions bit 9-8 AUDMOD<1:0>: Audio Protocol Mode Selection bits(4) 11 = PCM/DSP mode 10 = Right Justified mode: This module functions as if SPIFE=1, regardless of its actual value 01 = Left Justified Mode: This module functions as if SPIFE=1, regardless of its actual value 00 = I2S mode: This module functions as if SPIFE=0, regardless of its actual value bit 7 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output) 0 = Framed SPIx support is disabled Note 1: AUDEN can only be written when the SPIEN bit = 0. 2: AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN=1. 3: URDTEN is only valid when IGNTUR=1. 4: AUDMOD<1:0> bits can only be written when the SPIEN bit=0 and are only valid when AUDEN=1. When NOT in PCM/DSP mode, this module functions as if FRMSYPW=1, regardless of its actual value. DS30010038C-page 226  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 16-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED) bit 6 FRMSYNC: Frame Sync Pulse Direction Control bit 1 = Frame Sync pulse input (slave) 0 = Frame Sync pulse output (master) bit 5 FRMPOL: Frame Sync/Slave Select Polarity bit 1 = Frame Sync pulse/slave select is active-high 0 = Frame Sync pulse/slave select is active-low bit 4 MSSEN: Master Mode Slave Select Enable bit 1 = SPIx slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically driven during transmission in Master mode) 0 = Slave select SPIx support is disabled (SSx pin will be controlled by port I/O) bit 3 FRMSYPW: Frame Sync Pulse-Width bit 1 = Frame Sync pulse is one serial word length wide (as defined by MODE<32,16>/WLENGTH<4:0>) 0 = Frame Sync pulse is one clock (SCK) wide bit 2-0 FRMCNT<2:0>: Frame Sync Pulse Counter bits Controls the number of serial words transmitted per Sync pulse. 111 = Reserved 110 = Reserved 101 = Generates a Frame Sync pulse on every 32 serial words 100 = Generates a Frame Sync pulse on every 16 serial words 011 = Generates a Frame Sync pulse on every 8 serial words 010 = Generates a Frame Sync pulse on every 4 serial words 001 = Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols) 000 = Generates a Frame Sync pulse on each serial word Note 1: AUDEN can only be written when the SPIEN bit = 0. 2: AUDMONO can only be written when the SPIEN bit = 0 and is only valid for AUDEN=1. 3: URDTEN is only valid when IGNTUR=1. 4: AUDMOD<1:0> bits can only be written when the SPIEN bit=0 and are only valid when AUDEN=1. When NOT in PCM/DSP mode, this module functions as if FRMSYPW=1, regardless of its actual value.  2013-2015 Microchip Technology Inc. DS30010038C-page 227

PIC24FJ128GA204 FAMILY REGISTER 16-3: SPIxCON2L: SPIx CONTROL REGISTER 2 LOW U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — WLENGTH<4:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 WLENGTH<4:0>: Variable Word Length bits(1,2) 11111 = 32-bit data 11110 = 31-bit data 11101 = 30-bit data 11100 = 29-bit data 11011 = 28-bit data 11010 = 27-bit data 11001 = 26-bit data 11000 = 25-bit data 10111 = 24-bit data 10110 = 23-bit data 10101 = 22-bit data 10100 = 21-bit data 10011 = 20-bit data 10010 = 19-bit data 10001 = 18-bit data 10000 = 17-bit data 01111 = 16-bit data 01110 = 15-bit data 01101 = 14-bit data 01100 = 13-bit data 01011 = 12-bit data 01010 = 11-bit data 01001 = 10-bit data 01000 = 9-bit data 00111 = 8-bit data 00110 = 7-bit data 00101 = 6-bit data 00100 = 5-bit data 00011 = 4-bit data 00010 = 3-bit data 00001 = 2-bit data 00000 = See the MODE<32,16> bits in SPIxCON1L<11:10> Note 1: These bits are effective when AUDEN = 0 only. 2: Varying the length by changing these bits does not affect the depth of the TX/RX FIFO. DS30010038C-page 228  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 16-4: SPIxSTATL: SPIx STATUS REGISTER LOW U-0 U-0 U-0 R/C-0, HS R-0, HSC U-0 U-0 R-0, HSC — — — FRMERR SPIBUSY — — SPITUR(1) bit 15 bit 8 R-0, HSC R/C-0, HS R-1, HSC U-0 R-1, HSC U-0 R-0, HSC R-0, HSC SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware Settable bit bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERR: SPIx Frame Error Status bit 1 = Frame error is detected 0 = No frame error is detected bit 11 SPIBUSY: SPIx Activity Status bit 1 = Module is currently busy with some transactions 0 = No ongoing transactions (at time of read) bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUR: SPIx Transmit Underrun Status bit(1) 1 = Transmit buffer has encountered a Transmit Underrun (TUR) condition 0 = Transmit buffer does not have a Transmit Underrun condition bit 7 SRMT: SPIx Shift Register Empty Status bit 1 = No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit) 0 = Current or pending transactions bit 6 SPIROV: SPIx Receive Overflow Status bit 1 = A new byte/half-word/word has been completely received when the SPIxRXB was full 0 = No overflow bit 5 SPIRBE: SPIx RX Buffer Empty Status bit 1 = RX buffer is empty 0 = RX buffer is not empty Standard Buffer Mode: Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Enhanced Buffer Mode: Indicates RXELM<5:0>=6’b000000. bit 4 Unimplemented: Read as ‘0’ bit 3 SPITBE: SPIx Transmit Buffer Empty Status bit 1 = SPIxTXB is empty 0 = SPIxTXB is not empty Standard Buffer Mode: Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically cleared in hardware when SPIxBUF is written, loading SPIxTXB. Enhanced Buffer Mode: Indicates TXELM<5:0>=6’b000000. Note 1: SPITUR is cleared when SPIEN =0. When IGNTUR=1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software.  2013-2015 Microchip Technology Inc. DS30010038C-page 229

PIC24FJ128GA204 FAMILY REGISTER 16-4: SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED) bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = SPIxTXB is full 0 = SPIxTXB not full Standard Buffer Mode: Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Enhanced Buffer Mode: Indicates TXELM<5:0>=6’b111111. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = SPIxRXB is full 0 = SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Indicates RXELM<5:0>=6’b111111. Note 1: SPITUR is cleared when SPIEN =0. When IGNTUR=1, SPITUR provides dynamic status of the Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by software. DS30010038C-page 230  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 16-5: SPIxSTATH: SPIx STATUS REGISTER HIGH U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — — RXELM5(3) RXELM4(2) RXELM3(1) RXELM2 RXELM1 RXELM0 bit 15 bit 8 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC — — TXELM5(3) TXELM4(2) TXELM3(1) TXELM2 TXELM1 TXELM0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RXELM<5:0>: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TXELM<5:0>: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3) Note 1: RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher. 2: RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher. 3: RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.  2013-2015 Microchip Technology Inc. DS30010038C-page 231

PIC24FJ128GA204 FAMILY REGISTER 16-6: SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW U-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 — — — FRMERREN BUSYEN — — SPITUREN bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 SRMTEN SPIROVEN SPIRBEN — SPITBEN — SPITBFEN SPIRBFEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame error generates an interrupt event 0 = Frame error does not generate an interrupt event bit 11 BUSYEN: Enable Interrupt Events via SPIBUSY bit 1 = SPIBUSY generates an interrupt event 0 = SPIBUSY does not generate an interrupt event bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun (TUR) generates an interrupt event 0 = Transmit Underrun does not generate an interrupt event bit 7 SRMTEN: Enable Interrupt Events via SRMT bit 1 = Shift Register Empty (SRMT) generates an interrupt events 0 = Shift Register Empty does not generate an interrupt events bit 6 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = SPIx Receive Overflow generates an interrupt event 0 = SPIx Receive Overflow does not generate an interrupt event bit 5 SPIRBEN: Enable Interrupt Events via SPIRBE bit 1 = SPIx RX buffer empty generates an interrupt event 0 = SPIx RX buffer empty does not generate an interrupt event bit 4 Unimplemented: Read as ‘0’ bit 3 SPITBEN: Enable Interrupt Events via SPITBE bit 1 = SPIx transmit buffer empty generates an interrupt event 0 = SPIx transmit buffer empty does not generate an interrupt event bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBFEN: Enable Interrupt Events via SPITBF bit 1 = SPIx transmit buffer full generates an interrupt event 0 = SPIx transmit buffer full does not generate an interrupt event bit 0 SPIRBFEN: Enable Interrupt Events via SPIRBF bit 1 = SPIx receive buffer full generates an interrupt event 0 = SPIx receive buffer full does not generate an interrupt event DS30010038C-page 232  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 16-7: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXWIEN — RXMSK5(1) RXMSK4(1,4) RXMSK3(1,3) RXMSK2(1,2) RXMSK1(1) RXMSK0(1) bit 15 bit 8 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXWIEN — TXMSK5(1) TXMSK4(1,4) TXMSK3(1,3) TXMSK2(1,2) TXMSK1(1) TXMSK0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RXWIEN: Receive Watermark Interrupt Enable bit 1 = Triggers receive buffer element watermark interrupt when RXMSK<5:0>RXELM<5:0> 0 = Disables receive buffer element watermark interrupt bit 14 Unimplemented: Read as ‘0’ bit 13-8 RXMSK<5:0>: RX Buffer Mask bits(1,2,3,4) RX mask bits; used in conjunction with the RXWIEN bit. bit 7 TXWIEN: Transmit Watermark Interrupt Enable bit 1 = Triggers transmit buffer element watermark interrupt when TXMSK<5:0>=TXELM<5:0> 0 = Disables transmit buffer element watermark interrupt bit 6 Unimplemented: Read as ‘0’ bit 5-0 TXMSK<5:0>: TX Buffer Mask bits(1,2,3,4) TX mask bits; used in conjunction with the TXWIEN bit. Note 1: Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in this case. 2: RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher. 3: RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher. 4: RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.  2013-2015 Microchip Technology Inc. DS30010038C-page 233

PIC24FJ128GA204 FAMILY FIGURE 16-3: SPIx MASTER/SLAVE CONNECTION (STANDARD MODE) Processor 1 (SPIx Master) Processor 2 (SPIx Slave) SDOx SDIx Serial Receive Buffer Serial Transmit Buffer (SPIxRXB)(2) (SPIxTXB)(2) Shift Register SDIx SDOx Shift Register (SPIxRXSR) (SPIxTXSR) MSb LSb SDOx SDIx MSb LSb Shift Register Shift Register (SPIxTXSR) (SPIxRXSR) MSb LSb MSb LSb Serial Clock Serial Transmit Buffer SCKx SCKx Serial Receive Buffer (SPIxTXB)(2) (SPIxRXB)(2) SSx(1) SPIx Buffer SPIx Buffer (SPIxBUF)(2) (SPIxBUF)(2) MSTEN (SPIxCON1L<5>) = 1 MSSEN (SPIxCON1H<4>) = 1 and MSTEN (SPIxCON1L<5>) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF. DS30010038C-page 234  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 16-4: SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) Processor 1 (SPIx Master) Processor 2 (SPIx Slave) SDOx SDIx Serial Receive FIFO Serial Transmit FIFO (SPIxRXB)(2) (SPIxTXB)(2) Shift Register SDIx SDOx Shift Register (SPIxRXSR) (SPIxTXSR) MSb LSb SDOx SDIx MSb LSb Shift Register Shift Register (SPIxTXSR) (SPIxRXSR) MSb LSb MSb LSb Serial Clock Serial Transmit FIFO SCKx SCKx Serial Receive FIFO (SPIxTXB)(2) (SPIxRXB)(2) SSx(1) SPIx Buffer SPIx Buffer (SPIxBUF)(2) (SPIxBUF)(2) MSTEN (SPIxCON1L<5>) = 1 MSSEN (SPIxCON1H<4>) = 1 and MSTEN (SPIxCON1L<5>) = 0 Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory-mapped to SPIxBUF. FIGURE 16-5: SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F Processor 2 (SPIx Master, Frame Master) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse  2013-2015 Microchip Technology Inc. DS30010038C-page 235

PIC24FJ128GA204 FAMILY FIGURE 16-6: SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F Processor 2 SPIx Master, Frame Slave) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse FIGURE 16-7: SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F Processor 2 (SPIx Slave, Frame Master) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync. Pulse FIGURE 16-8: SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24F Processor 2 (SPIx Slave, Frame Slave) SDOx SDIx SDIx SDOx Serial Clock SCKx SCKx SSx SSx Frame Sync Pulse EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED FPB Baud Rate = (2 * (SPIxBRG + 1)) Where: FPB is the Peripheral Bus Clock Frequency. DS30010038C-page 236  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 17.0 INTER-INTEGRATED 17.1 Communicating as a Master in a CIRCUIT™ (I2C™) Single Master Environment The details of sending a message in Master mode Note: This data sheet summarizes the features of depends on the communication protocols for the device this group of PIC24F devices. It is not being communicated with. Typically, the sequence of intended to be a comprehensive reference events is as follows: source. For more information, refer to the “dsPIC33/PIC24 Family Reference 1. Assert a Start condition on SDAx and SCLx. Manual”, “Inter-Integrated Circuit™ 2. Send the I2C device address byte to the slave (I2C™)” (DS70000195). The information in with a write indication. this data sheet supersedes the information 3. Wait for and verify an Acknowledge from the in the FRM. slave. The Inter-Integrated Circuit™ (I2C™) module is a serial 4. Send the first data byte (sometimes known as interface useful for communicating with other periph- the command) to the slave. eral or microcontroller devices. These peripheral 5. Wait for and verify an Acknowledge from the devices may be serial EEPROMs, display drivers, A/D slave. Converters, etc. 6. Send the serial memory address low byte to the The I2C module supports these features: slave. 7. Repeat Steps 4 and 5 until all data bytes are • Independent master and slave logic sent. • 7-bit and 10-bit device addresses 8. Assert a Repeated Start condition on SDAx and • General call address as defined in the I2C protocol SCLx. • Clock stretching to provide delays for the 9. Send the device address byte to the slave with processor to respond to a slave data request a read indication. • Both 100kHz and 400kHz bus specifications 10. Wait for and verify an Acknowledge from the • Configurable address masking slave. • Multi-Master modes to prevent loss of messages 11. Enable master reception to receive serial in arbitration memory data. • Bus Repeater mode, allowing the acceptance of 12. Generate an ACK or NACK condition at the end all messages as a slave regardless of the address of a received byte of data. • Automatic SCL 13. Generate a Stop condition on SDAx and SCLx. A block diagram of the module is shown in Figure17-1.  2013-2015 Microchip Technology Inc. DS30010038C-page 237

PIC24FJ128GA204 FAMILY FIGURE 17-1: I2Cx BLOCK DIAGRAM Internal Data Bus I2CxRCV Read Shift SCLx Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Write Start and Stop Bit Detect I2CxSTAT Start and Stop Read Bit Generation Write c gi o CDoellitseicotn ol L I2CxCONL ntr o Read C Write Acknowledge Generation I2CxCONH Clock Stretching Read Write I2CxTRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY DS30010038C-page 238  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 17.2 Setting Baud Rate when Operating 17.3 Slave Address Masking as a Bus Master The I2CxMSK register (Register17-4) designates To compute the Baud Rate Generator reload value, use address bit positions as “don’t care” for both 7-Bit and Equation17-1. 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave EQUATION 17-1: COMPUTING BAUD RATE module to respond, whether the corresponding address RELOAD VALUE(1) bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is set to ‘0010000000’, the slave module will detect both (( 1 ) FCY) addresses, ‘0000000000’ and ‘0010000000’. I2CxBRG = – PGDX  – 2 FSCL 2 To enable address masking, the Intelligent Peripheral Management Interface (IPMI) must be disabled by Note1: Based on FCY = FOSC/2; Doze mode clearing the STRICT bit (I2CxCONL<11>). and PLL are disabled. Note: As a result of changes in the I2C™ proto- col, the addresses in Table17-1 are reserved and will not be Acknowledged in Slave mode. This includes any address mask settings that include any of these addresses. TABLE 17-1: I2Cx RESERVED ADDRESSES(1) Slave Address R/W Bit Description 0000 000 0 General Call Address(2) 0000 000 1 Start Byte 0000 001 x Cbus Address 0000 01x x Reserved 0000 1xx x HS Mode Master Code 1111 0xx x 10-Bit Slave Upper Byte(3) 1111 1xx x Reserved Note 1: The address bits listed here will never cause an address match independent of address mask settings. 2: This address will be Acknowledged only if GCEN=1. 3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.  2013-2015 Microchip Technology Inc. DS30010038C-page 239

PIC24FJ128GA204 FAMILY REGISTER 17-1: I2CxCONL: I2Cx CONTROL REGISTER LOW R/W-0 U-0 R/W-0, HC R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL(1) STRICT A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit (writable from SW only) 1 = Enables the I2Cx module, and configures the SDAx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I2C™ pins are controlled by port functions bit 14 Unimplemented: Read as ‘0’ bit 13 I2CSIDL: I2Cx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (I2C Slave mode only)(1) Module resets and (I2CEN = 0) sets SCLREL = 1. If STREN = 0:(2) 1 = Releases clock 0 = Forces clock low (clock stretch) If STREN = 1: 1 = Releases clock 0 = Holds clock low (clock stretch); user may program this bit to ‘0’; clock stretch is at the next SCLx low bit 11 STRICT: I2Cx Strict Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced; for reserved addresses, refer to Table17-1. (In Slave Mode) – The device doesn’t respond to reserved address space and addresses falling in that category are NACKed. (In Master Mode) – The device is allowed to generate addresses with reserved address space. 0 = Reserved addressing would be Acknowledged. (In Slave Mode) – The device will respond to an address falling in the reserved address space. When there is a match with any of the reserved addresses, the device will generate an ACK. (In Master Mode) – Reserved. bit 10 A10M: 10-Bit Slave Address Flag bit 1 = I2CxADD is a 10-bit slave address 0 = I2CADD is a 7-bit slave address bit 9 DISSLW: Slew Rate Control Disable bit 1 = Slew rate control is disabled for Standard Speed mode (100 kHz, also disabled for 1 MHz mode) 0 = Slew rate control is enabled for High-Speed mode (400 kHz) bit 8 SMEN: SMBus Input Levels Enable bit 1 = Enables input logic so thresholds are compliant with the SMBus specification 0 = Disables SMBus-specific inputs Note 1: Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end of slave reception. 2: Automatically cleared to ‘0’ at the beginning of slave transmission. DS30010038C-page 240  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 17-1: I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED) bit 7 GCEN: General Call Enable bit (I2C Slave mode only) 1 = Enables interrupt when a general call address is received in I2CxRSR; module is enabled for reception 0 = General call address is disabled bit 6 STREN: SCLx Clock Stretch Enable bit In I2C Slave mode only; used in conjunction with the SCLREL bit. 1 = Enables clock stretching 0 = Disables clock stretching bit 5 ACKDT: Acknowledge Data bit In I2C Master mode during Master Receive mode. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. In I2C Slave mode when AHEN = 1 or DHEN = 1. The value that the slave will transmit when it initiates an Acknowledge sequence at the end of an address or data reception. 1 = A NACK is sent 0 = ACK is sent bit 4 ACKEN: Acknowledge Sequence Enable bit In I2C Master mode only; applicable during Master Receive mode. 1 = Initiates Acknowledge sequence on SDAx and SCLx pins, and transmits ACKDT data bit 0 = Acknowledge sequence is Idle bit 3 RCEN: Receive Enable bit (I2C Master mode only) 1 = Enables Receive mode for I2C; automatically cleared by hardware at the end of an 8-bit receive data byte 0 = Receive sequence is not in progress bit 2 PEN: Stop Condition Enable bit (I2C Master mode only) 1 = Initiates Stop condition on SDAx and SCLx pins 0 = Stop condition is Idle bit 1 RSEN: Restart Condition Enable bit (I2C Master mode only) 1 = Initiates Restart condition on the SDAx and SCLx pins 0 = Restart condition is Idle bit 0 SEN: Start Condition Enable bit (I2C Master mode only) 1 = Initiates Start condition on the SDAx and SCLx pins 0 = Start condition is Idle Note 1: Automatically cleared to ‘0’ at the beginning of slave transmission; automatically cleared to ‘0’ at the end of slave reception. 2: Automatically cleared to ‘0’ at the beginning of slave transmission.  2013-2015 Microchip Technology Inc. DS30010038C-page 241

PIC24FJ128GA204 FAMILY REGISTER 17-2: I2CxCONH: I2Cx CONTROL REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C™ Slave mode only). 1 = Enables interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled bit 5 SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only) 1 = Enables interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled bit 4 BOEN: Buffer Overwrite Enable bit (I2C Slave mode only) 1 = I2CxRCV is updated and an ACK is generated for a received address/data byte, ignoring the state of the I2COV bit only if the RBF bit = 0 0 = I2CxRCV is only updated when I2COV is clear bit 3 SDAHT: SDAx Hold Time Selection bit 1 = Minimum of 300 ns hold time on SDAx after the falling edge of SCLx 0 = Minimum of 100 ns hold time on SDAx after the falling edge of SCLx bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCLx, SDAx is sampled low when the module is outputting a high state, the BCL bit is set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences. 1 = Enables slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a matching received address byte; SCLREL bit (I2CxCONL<12>) will be cleared and the SCLx will be held low 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the SCLREL bit (I2CxCONL<12>) and SCLx is held low 0 = Data holding is disabled DS30010038C-page 242  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 17-3: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC R-0, HSC U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Hardware Settable bit bit 15 ACKSTAT: Acknowledge Status bit (updated in all Master and Slave modes) 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave bit 14 TRSTAT: Transmit Status bit (when operating as I2C™ master; applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress bit 13 ACKTIM: Acknowledge Time Status bit (valid in I2C Slave mode only) 1 = Indicates I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCLx clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCLx clock bit 12-11 Unimplemented: Read as ‘0’ bit 10 BCL: Bus Collision Detect bit (Master/Slave mode; cleared when I2C module is disabled, I2CEN = 0) 1 = A bus collision has been detected during a master or slave transmit operation 0 = No bus collision has been detected bit 9 GCSTAT: General Call Status bit (cleared after Stop detection) 1 = General call address was received 0 = General call address was not received bit 8 ADD10: 10-Bit Address Status bit (cleared after Stop detection) 1 = 10-bit address was matched 0 = 10-bit address was not matched bit 7 IWCOL: I2Cx Write Collision Detect bit 1 = An attempt to write to the I2CxTRN register failed because the I2C module is busy; must be cleared in software 0 = No collision bit 6 I2COV: I2Cx Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte; I2COV is a “don’tcare” in Transmit mode, must be cleared in software 0 = No overflow bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received or transmitted was an address bit 4 P: I2Cx Stop bit Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0. 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last  2013-2015 Microchip Technology Inc. DS30010038C-page 243

PIC24FJ128GA204 FAMILY REGISTER 17-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: I2Cx Start bit Updated when Start, Reset or Stop is detected; cleared when the I2C module is disabled, I2CEN = 0. 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read: Indicates the data transfer is output from the slave 0 = Write: Indicates the data transfer is input to the slave bit 1 RBF: Receive Buffer Full Status bit 1 = Receive is complete, I2CxRCV is full 0 = Receive is not complete, I2CxRCV is empty bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit is in progress, I2CxTRN is full (8 bits of data) 0 = Transmit is complete, I2CxTRN is empty REGISTER 17-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — MSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 MSK<9:0>: I2Cx Mask for Address Bit x Select bits 1 = Enables masking for bit x of the incoming message address; bit match is not required in this position 0 = Disables masking for bit x; bit match is required in this position DS30010038C-page 244  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 18.0 UNIVERSAL ASYNCHRONOUS • Baud Rates Range from 15 bps to 1 Mbps at 16 MIPS RECEIVER TRANSMITTER in 16x mode • 4-Deep, First-In-First-Out (FIFO) Transmit Data (UART) Buffer Note: This data sheet summarizes the features of • 4-Deep FIFO Receive Data Buffer this group of PIC24F devices. It is not • Parity, Framing and Buffer Overrun Error Detection intended to be a comprehensive reference • Support for 9-Bit mode with Address Detect source. For more information, refer to the (9th bit = 1) “dsPIC33/PIC24 Family Reference Man- • Separate Transmit and Receive Interrupts ual”, “Universal Asynchronous Receiver • Loopback mode for Diagnostic Support Transmitter (UART)” (DS70000582). The • Polarity Control for Transmit and Receive Lines information in this data sheet supersedes the information in the FRM. • Support for Sync and Break Characters • Supports Automatic Baud Rate Detection The Universal Asynchronous Receiver Transmitter • IrDA® Encoder and Decoder Logic (UART) module is one of the serial I/O modules available • Includes DMA Support in the PIC24F device family. The UART is a full-duplex, asynchronous system that can communicate with • 16x Baud Clock Output for IrDA Support peripheral devices, such as personal computers, • Smart Card ISO 7816 Support (UART1 and LIN/J2602, RS-232 and RS-485 interfaces. The module UART2 only): also supports a hardware flow control option with the - T = 0 protocol with automatic error handling UxCTS and UxRTS pins. The UART module includes - T = 1 protocol the ISO7816 compliant Smart Card support and the IrDA® encoder/decoder unit. - Dedicated Guard Time Counter (GTC) - Dedicated Waiting Time Counter (WTC) The PIC24FJ128GA204 family devices are equipped with four UART modules, referred to as UART1, A simplified block diagram of the UARTx module is UART2, UART3 and UART4. shown in Figure18-1. The UARTx module consists of these key important hardware elements: The primary features of the UARTx modules are: • Baud Rate Generator • Full-Duplex, 8 or 9-Bit Data Transmission through • Asynchronous Transmitter the UxTX and UxRX Pins • Asynchronous Receiver • Even, Odd or No Parity Options (for 8-bit data) • One or Two Stop bits Note: Throughout this section, references to register and bit names that may be asso- • Hardware Flow Control Option with the UxCTS ciated with a specific UART module are and UxRTS Pins referred to generically by the use of ‘x’ in • Fully Integrated Baud Rate Generator with 16-Bit place of the specific module number. Prescaler Thus, “UxSTA” might refer to the Status • Baud Rates Range from 61 bps to 4 Mbps at 16 MIPS register for either UART1, UART2, UART3 in 4x mode or UART4.  2013-2015 Microchip Technology Inc. DS30010038C-page 245

PIC24FJ128GA204 FAMILY FIGURE 18-1: UARTx SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator ISO 7816 Support IrDA® Hardware Flow Control UxRTS/BCLKx(1) (1) UxCTS UARTx Receiver UxRX(1,2) UARTx Transmitter UxTX(1,2) Note 1: The UARTx inputs and outputs must all be assigned to available RPn/RPIn pins before use. See Section11.4 “Peripheral Pin Select (PPS)” for more information. 2: The UxTX and UxRX pins need to be shorted to be used for the Smart Card interface; this should be taken care of by the user. DS30010038C-page 246  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 18.1 UARTx Baud Rate Generator (BRG) Equation18-2 shows the formula for computation of the baud rate when BRGH = 1. The UARTx module includes a dedicated, 16-bit Baud Rate Generator. The UxBRG register controls the EQUATION 18-2: UARTx BAUD RATE WITH period of a free-running, 16-bit timer. Equation18-1 BRGH = 1(1,2) shows the formula for computation of the baud rate when BRGH=0. FCY Baud Rate = 4 • (UxBRG + 1) EQUATION 18-1: UARTx BAUD RATE WITH BRGH = 0(1,2) UxBRG = FCY – 1 4 • Baud Rate FCY Baud Rate = 16 • (UxBRG + 1) Note1: FCY denotes the instruction cycle FCY clock frequency. UxBRG = – 1 16 • Baud Rate 2: Based on FCY = FOSC/2; Doze mode and PLL are disabled. Note1: FCY denotes the instruction cycle clock frequency (FOSC/2). The maximum baud rate (BRGH = 1) possible is FCY/4 2: Based on FCY = FOSC/2; Doze mode (for UxBRG = 0) and the minimum baud rate possible and PLL are disabled. is FCY/(4 * 65536). Writing a new value to the UxBRG register causes the Example18-1 shows the calculation of the baud rate BRG timer to be reset (cleared). This ensures the BRG error for the following conditions: does not wait for a timer overflow before generating the • FCY = 4 MHz new baud rate. • Desired Baud Rate = 9600 The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). EXAMPLE 18-1: BAUD RATE ERROR CALCULATION (BRGH = 0)(1) Desired Baud Rate = FCY/(16 (UxBRG + 1)) Solving for UxBRG Value: UxBRG = ((FCY/Desired Baud Rate)/16) – 1 UxBRG = ((4000000/9600)/16) – 1 UxBRG = 25 Calculated Baud Rate = 4000000/(16 (25 + 1)) = 9615 Error = (Calculated Baud Rate – Desired Baud Rate) Desired Baud Rate = (9615 – 9600)/9600 = 0.16% Note1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.  2013-2015 Microchip Technology Inc. DS30010038C-page 247

PIC24FJ128GA204 FAMILY 18.2 Transmitting in 8-Bit Data Mode 18.5 Receiving in 8-Bit or 9-Bit Data Mode 1. Set up the UARTx: a) Write appropriate values for data, parity and 1. Set up the UARTx (as described in Section18.2 Stop bits. “Transmitting in 8-Bit Data Mode”). b) Write appropriate baud rate value to the 2. Enable the UARTx. UxBRG register. 3. Set the URXEN bit (UxSTA<12>). c) Set up transmit and receive interrupt enable 4. A receive interrupt will be generated when one and priority bits. or more data characters have been received as 2. Enable the UARTx. per interrupt control bits, URXISEL<1:0>. 3. Set the UTXEN bit (causes a transmit interrupt, 5. Read the OERR bit to determine if an overrun two cycles after being set). error has occurred. The OERR bit must be reset 4. Write a data byte to the lower byte of the in software. UxTXREG word. The value will be immediately 6. Read UxRXREG. transferred to the Transmit Shift Register (TSR) The act of reading the UxRXREG character will move and the serial bit stream will start shifting out the next character to the top of the receive FIFO, with the next rising edge of the baud clock. including a new set of PERR and FERR values. 5. Alternatively, the data byte may be transferred while UTXEN = 0 and then, the user may set 18.6 Operation of UxCTS and UxRTS UTXEN. This will cause the serial bit stream to Control Pins begin immediately because the baud clock will start from a cleared state. UARTx Clear-to-Send (UxCTS) and Request-to-Send 6. A transmit interrupt will be generated as per (UxRTS) are the two hardware controlled pins that are interrupt control bits, UTXISEL<1:0>. associated with the UARTx modules. These two pins allow the UARTx to operate in Simplex and Flow 18.3 Transmitting in 9-Bit Data Mode Control mode. They are implemented to control the transmission and reception between the Data Terminal 1. Set up the UARTx (as described in Section18.2 Equipment (DTE). The UEN<1:0> bits in the UxMODE “Transmitting in 8-Bit Data Mode”). register configure these pins. 2. Enable the UARTx. 3. Set the UTXEN bit (causes a transmit interrupt). 18.7 Infrared Support 4. Write UxTXREG as a 16-bit value only. The UARTx module provides two types of infrared 5. A word write to UxTXREG triggers the transfer UART support: one is the IrDA clock output to support of the 9-bit data to the TSR. The serial bit stream an external IrDA encoder and decoder device (legacy will start shifting out with the first rising edge of module support), and the other is the full implementa- the baud clock. tion of the IrDA encoder and decoder. Note that 6. A transmit interrupt will be generated as per the because the IrDA modes require a 16x baud clock, they setting of control bits, UTXISELx. will only work when the BRGH bit (UxMODE<3>) is ‘0’. 18.4 Break and Sync Transmit 18.7.1 IrDA CLOCK OUTPUT FOR Sequence EXTERNAL IrDA SUPPORT To support external IrDA encoder and decoder devices, The following sequence will send a message frame the BCLKx pin (same as the UxRTS pin) can be header, made up of a Break, followed by an auto-baud configured to generate the 16x baud clock. With Sync byte. UEN<1:0> = 11, the BCLKx pin will output the 16x 1. Configure the UARTx for the desired mode. baud clock if the UARTx module is enabled. It can be 2. Set UTXEN and UTXBRK to set up the Break used to support the IrDA codec chip. character. 3. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). 4. Write ‘55h’ to UxTXREG; this loads the Sync character into the transmit FIFO. 5. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. DS30010038C-page 248  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 18.7.2 BUILT-IN IrDA ENCODER AND external power supply. The terminal is also responsible DECODER for clocking and resetting the Smart Card. The TX and RX line of the PIC24F device has to be shorted The UARTx has full implementation of the IrDA externally and then connected to the I/O line of the encoder and decoder as part of the UARTx module. Smart Card. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When There are two protocols which are widely used for enabled (IREN = 1), the receive pin (UxRX) acts as the Smart Card communication between terminal and input from the infrared receiver. The transmit pin Smart Card: (UxTX) acts as the output to the infrared transmitter. • T = 0 (asynchronous, half-duplex, byte-oriented protocol) 18.8 Smart Card ISO 7816 Support • T = 1 (asynchronous, half-duplex, block-oriented protocol) Figure18-2 shows a Smart Card subsystem using a PIC24F microcontroller with a UARTx module for The selection of T = 0 or T = 1 protocol is done using Smart Card data communication. VCC to power the the PTRCL bit in UxSCCON register. Smart Card can be supplied through a terminal or an FIGURE 18-2: SMART CARD SUBSYSTEM CONNECTION TERMINAL SMART CARD PIC24F TX I/O 2) (6 RX 1 8 7 A REFO CLK D R _I GPO RST T R ATTACHE(1) A GPI U VCC GND Note 1: Driven high upon card insertion. 2: Only UART1 and UART2 support Smart Card ISO 7816.  2013-2015 Microchip Technology Inc. DS30010038C-page 249

PIC24FJ128GA204 FAMILY 18.9 Registers • UxADMD: UARTx Address Mask Detect Register (Register18-4) The UART module consists of the following Special • UxBRG: UARTx Baud Rate Register Function Registers (SFRs): • UxSCCON: UARTx Smart Card Control Register • UxMODE: UARTx Mode Register (Register18-1) (Register18-5) • UxSTA: UARTx Status and Control Register • UxSCINT: UARTx Smart Card Interrupt Register (Register18-2) (Register18-6) • UxRXREG: UARTx Receive Register • UxGTC: UARTx Guard Time Counter Register • UxTXREG: UARTx Transmit Register • UxWTCL and UxWTCH: UARTx Waiting Time (Write-Only) (Register18-3) Counter Registers REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 UARTEN(1) — USIDL IREN(2) RTSMD — UEN1 UEN0 bit 15 bit 8 R/W-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> 0 = UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 USIDL: UARTx Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 IREN: IrDA® Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder are enabled 0 = IrDA encoder and decoder are disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN<1:0>: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by port latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by port latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by port latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx continues to sample the UxRX pin; interrupt is generated on the falling edge, bit is cleared in hardware on the following rising edge 0 = No wake-up is enabled Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: This feature is only available for the 16x BRG mode (BRGH=0). DS30010038C-page 250  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enables Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enables baud rate measurement on the next character – requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement is disabled or completed bit 4 URXINV: UARTx Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode (4 BRG clock cycles per bit) 0 = Standard Speed mode (16 BRG clock cycles per bit) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. 2: This feature is only available for the 16x BRG mode (BRGH=0).  2013-2015 Microchip Technology Inc. DS30010038C-page 251

PIC24FJ128GA204 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV(1) UTXISEL0 URXEN UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown HS = Hardware Settable bit HC = Hardware Clearable bit bit 15,13 UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: UARTx IrDA® Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ IREN = 1: 1 = UxTX Idle state is ‘1’ 0 = UxTX Idle state is ‘0’ bit 12 URXEN: UARTx Receive Enable bit 1 = Receive is enabled, UxRX pin is controlled by UARTx 0 = Receive is disabled, UxRX pin is controlled by the port bit 11 UTXBRK: UARTx Transmit Break bit 1 = Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission is disabled or completed bit 10 UTXEN: UARTx Transmit Enable bit(2) 1 = Transmit is enabled, UxTX pin is controlled by UARTx 0 = Transmit is disabled, any pending transmission is aborted and the buffer is reset; UxTX pin is controlled by the port bit 9 UTXBF: UARTx Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN=1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”. DS30010038C-page 252  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits 11 = Interrupt is set on an RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on an RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer; receive buffer has one or more characters bit 5 ADDEN: Address Character Detect bit (bit 8 of received data=1) 1 = Address Detect mode is enabled (if 9-bit mode is not selected, this does not take effect) 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (the character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (the character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (10 transition); will reset the receive buffer and the RSR to the empty state) bit 0 URXDA: UARTx Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: The value of this bit only affects the transmit properties of the module when the IrDA® encoder is enabled (IREN=1). 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. For more information, see Section11.4 “Peripheral Pin Select (PPS)”.  2013-2015 Microchip Technology Inc. DS30010038C-page 253

PIC24FJ128GA204 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER (NORMALLY WRITE-ONLY) W-x U-0 U-0 U-0 U-0 U-0 U-0 W-x LAST(1) — — — — — — UxTXREG8 bit 15 bit 8 W-x W-x W-x W-x W-x W-x W-x W-x UxTXREG7 UxTXREG6 UxTXREG5 UxTXREG4 UxTXREG3 UxTXREG2 UxTXREG1 UxTXREG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 LAST: Last Byte Indicator for Smart Card Support bits(1) bit 14-9 Unimplemented: Read as ‘0’ bit 8 UxTXREG8: Data of the Transmitted Character bit (in 9-bit mode) bit 7-0 UxTXREG<7:0>: Data of the Transmitted Character bits Note 1: This bit is only available for UART1 and UART2. REGISTER 18-4: UxADMD: UARTx ADDRESS MATCH DETECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADMMASK7 ADMMASK6 ADMMASK5 ADMMASK4 ADMMASK3 ADMMASK2 ADMMASK1 ADMMASK0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADMADDR7 ADMADDR6 ADMADDR5 ADMADDR4 ADMADDR3 ADMADDR2 ADMADDR1 ADMADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 ADMMASK<7:0>: UARTx ADMADDR<7:0> (UxADMD<7:0>) Masking bits For ADMMASK<x>: 1 = ADMADDR<x> is used to detect the address match 0 = ADMADDR<x> is not used to detect the address match bit 7-0 ADMADDR<7:0>: UARTx Address Detect Task Off-Load bits Used with the ADMMASK<7:0> bits (UxADMD<15:8>) to off-load the task of detecting the address character from the processor during Address Detect mode. DS30010038C-page 254  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 18-5: UxSCCON: UARTx SMART CARD CONTROL REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — TXRPT1(2) TXRPT0(2) CONV T0PD(2) PTRCL SCEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-4 TXRPT<1:0>: Transmit Repeat Selection bits(2) 11 = Retransmits the error byte four times 10 = Retransmits the error byte three times 01 = Retransmits the error byte twice 00 = Retransmits the error byte once bit 3 CONV: Logic Convention Selection bit 1 = Inverse logic convention 0 = Direct logic convention bit 2 T0PD: Pull-Down Duration for T=0 Error Handling bit(2) 1 = 2 ETU 0 = 1 ETU bit 1 PTRCL: Smart Card Protocol Selection bit 1 = T=1 0 = T=0 bit 0 SCEN: Smart Card Mode Enable bit 1 = Smart Card mode is enabled if UARTEN (UxMODE<15>)=1 0 = Smart Card mode is disabled Note 1: This register is only available for UART1 and UART2. 2: These bits are applicable to T = 0 only, see the PTRCL bit (UxSCCON<1>).  2013-2015 Microchip Technology Inc. DS30010038C-page 255

PIC24FJ128GA204 FAMILY REGISTER 18-6: UxSCINT: UARTx SMART CARD INTERRUPT REGISTER(1) U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — RXRPTIF(2) TXRPTIF(2) — — WTCIF GTCIF bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — PARIE(2) RXRPTIE(2) TXRPTIE(2) — — WTCIE GTCIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 RXRPTIF: Receive Repeat Interrupt Flag bit(2) 1 = Parity error has persisted after the same character has been received five times (four retransmits) 0 = Flag is cleared bit 12 TXRPTIF: Transmit Repeat Interrupt Flag bit(2) 1 = Line error has been detected after the last retransmit per TXRPT<1:0> (see Register18-5) 0 = Flag is cleared bit 11-10 Unimplemented: Read as ‘0’ bit 9 WTCIF: Waiting Time Counter Interrupt Flag bit 1 = Waiting Time Counter has reached 0 0 = Waiting Time Counter has not reached 0 bit 8 GTCIF: Guard Time Counter Interrupt Flag bit 1 = Guard Time Counter has reached 0 0 = Guard Time Counter has not reached 0 bit 7 Unimplemented: Read as ‘0’ bit 6 PARIE: Parity Interrupt Enable bit(2) 1 = An interrupt is invoked when a character is received with a parity error; see the PERR bit (UxSTA<3>) in Register18-2 for the interrupt flag 0 = Interrupt is disabled bit 5 RXRPTIE: Receive Repeat Interrupt Enable bit(2) 1 = An interrupt is invoked when a parity error has persisted after the same character has been received five times (four retransmits) 0 = Interrupt is disabled bit 4 TXRPTIE: Transmit Repeat Interrupt Enable bit(2) 1 = An interrupt is invoked when a line error is detected after the last retransmit per the TXRPT<1:0> bits has been completed (see Register18-5) 0 = Interrupt is disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 WTCIE: Waiting Time Counter Interrupt Enable bit 1 = Waiting Time Counter interrupt is enabled 0 = Waiting Time Counter interrupt is disabled bit 0 GTCIE: Guard Time Counter Interrupt Enable bit 1 = Guard Time Counter interrupt is enabled 0 = Guard Time Counter interrupt is disabled Note 1: This register is only available for UART1 and UART2. 2: This bit is applicable to T = 0 only, see the PTRCL bit (UxSCCON<1>). DS30010038C-page 256  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 19.0 DATA SIGNAL MODULATOR The modulated output signal is generated by perform- (DSM) ing a logical AND operation of both the carrier and modulator signals, and then it is provided to the Note: This data sheet summarizes the features of MDOUT pin. Using this method, the DSM can generate this group of PIC24F devices. It is not the following types of key modulation schemes: intended to be a comprehensive reference • Frequency Shift Keying (FSK) source. For more information, refer to • Phase-Shift Keying (PSK) the “dsPIC33/PIC24 Family Reference • On-Off Keying (OOK) Manual”, “Data Signal Modulator (DSM)” (DS39744). The information in this data Figure19-1 shows a simplified block diagram of the sheet supersedes the information in the Data Signal Modulator peripheral. FRM. The Data Signal Modulator (DSM) allows the user to mix a digital data stream (the “modulator signal”) with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module, either internally from the output of a peripheral, or externally through an input pin. FIGURE 19-1: SIMPLIFIED BLOCK DIAGRAM OF THE DATA SIGNAL MODULATOR CH<3:0> MDEN VSS MDCIN1 EN MDCIN2 Data Signal REFO Clock Modulator OC/PWM1 MDCARH OC/PWM2 OC/PWM3 OC/PWM4 CHPOL OC/PWM5 OC/PWM6 D SYNC MS<3:0> Q 1 MDBIT MDMIN SSP1 (SDOx) 0 SSP2 (SDOx) SSP3 (SDOx) CHSYNC UART1 (TX) UART2 (TX) MDSRC UART3 (TX) MDOUT UART4 (TX) OC/PWM1 MDOE OC/PWM2 MDOPOL OC/PWM3 OC/PWM4 OC/PWM5 OC/PWM6 D SYNC CL<3:0> Q 1 VSS MDCIN1 MDCIN2 0 REFO Clock OC/PWM1 MDCARL CLSYNC OC/PWM2 OC/PWM3 OC/PWM4 CLPOL OC/PWM5 OC/PWM6  2013-2015 Microchip Technology Inc. DS30010038C-page 257

PIC24FJ128GA204 FAMILY REGISTER 19-1: MDCON: DATA SIGNAL MODULATOR CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 MDEN — MDSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-1 R/W-0 U-0 U-0 U-0 R/W-0 — MDOE MDSLR MDOPOL — — — MDBIT(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 MDEN: DSM Module Enable bit 1 = Modulator module is enabled and mixing input signals 0 = Modulator module is disabled and has no output bit 14 Unimplemented: Read as ‘0’ bit 13 MDSIDL: DSM Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-7 Unimplemented: Read as ‘0’ bit 6 MDOE: DSM Module Pin Output Enable bit 1 = Modulator pin output is enabled 0 = Modulator pin output is disabled bit 5 MDSLR: MDOUT Pin Slew Rate Limiting bit 1 = MDOUT pin slew rate limiting is enabled 0 = MDOUT pin slew rate limiting is disabled bit 4 MDOPOL: DSM Output Polarity Select bit 1 = Modulator output signal is inverted 0 = Modulator output signal is not inverted bit 3-1 Unimplemented: Read as ‘0’ bit 0 MDBIT: Manual Modulation Input bit(1) 1 = Carrier is modulated 0 = Carrier is not modulated Note 1: The MDBIT must be selected as the modulation source (MDSRC<3:0> = 0000). DS30010038C-page 258  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 19-2: MDSRC: DATA SIGNAL MODULATOR SOURCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x SODIS(1) — — — MS3(2) MS2(2) MS1(2) MS0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 SODIS: DSM Source Output Disable bit(1) 1 = Output signal driving the peripheral output pin (selected by MS<3:0>) is disabled 0 = Output signal driving the peripheral output pin (selected by MS<3:0>) is enabled bit 6-4 Unimplemented: Read as ‘0’ bit 3-0 MS<3:0> DSM Source Selection bits(2) 1111 = Unimplemented 1110 = SPI3 module output (SDO3) 1101 = Output Compare/PWM Module 6 output 1100 = Output Compare/PWM Module 5 output 1011 = Output Compare/PWM Module 4 output 1010 = Output Compare/PWM Module 3 output 1001 = Output Compare/PWM Module 2 output 1000 = Output Compare/PWM Module 1 output 0111 = UART4 TX output 0110 = UART3 TX output 0101 = UART2 TX output 0100 = UART1 TX output 0011 = SPI2 module output (SDO2) 0010 = SPI1 module output (SDO1) 0001 = Input on MDMIN pin 0000 = Manual modulation using MDBIT (MDCON<0>) Note 1: This bit is only affected by a POR. 2: These bits are not affected by a POR.  2013-2015 Microchip Technology Inc. DS30010038C-page 259

PIC24FJ128GA204 FAMILY REGISTER 19-3: MDCAR: DATA SIGNAL MODULATOR CARRIER CONTROL REGISTER R/W-x R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x CHODIS CHPOL CHSYNC — CH3(1) CH2(1) CH1(1) CH0(1) bit 15 bit 8 R/W-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x R/W-x CLODIS CLPOL CLSYNC — CL3(1) CL2(1) CL1(1) CL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CHODIS: DSM High Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by CH<3:0>) is disabled 0 = Output signal driving the peripheral output pin is enabled bit 14 CHPOL: DSM High Carrier Polarity Select bit 1 = Selected high carrier signal is inverted 0 = Selected high carrier signal is not inverted bit 13 CHSYNC: DSM High Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the high carrier before allowing a switch to the low carrier 0 = Modulator output is not synchronized to the high time carrier signal(1) bit 12 Unimplemented: Read as ‘0’ bit 11-8 CH<3:0> DSM Data High Carrier Selection bits(1) 1111 • • = Reserved • 1010 1001 = Output Compare/PWM Module 6 output 1000 = Output Compare/PWM Module 5 output 0111 = Output Compare/PWM Module 4 output 0110 = Output Compare/PWM Module 3 output 0101 = Output Compare/PWM Module 2 output 0100 = Output Compare/PWM Module 1 output 0011 = Reference Clock Output (REFO) 0010 = Input on MDCIN2 pin 0001 = Input on MDCIN1 pin 0000 = VSS bit 7 CLODIS: Modulator Low Carrier Output Disable bit 1 = Output signal driving the peripheral output pin (selected by CL<3:0>) is disabled 0 = Output signal driving the peripheral output pin is enabled bit 6 CLPOL: Modulator Low Carrier Polarity Select bit 1 = Selected low carrier signal is inverted 0 = Selected low carrier signal is not inverted Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. DS30010038C-page 260  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 19-3: MDCAR: DATA SIGNAL MODULATOR CARRIER CONTROL REGISTER (CONTINUED) bit 5 CLSYNC: DSM Low Carrier Synchronization Enable bit 1 = Modulator waits for a falling edge on the low carrier before allowing a switch to the high carrier 0 = Modulator output is not synchronized to the low time carrier signal(1) bit 4 Unimplemented: Read as ‘0’ bit 3-0 CL<3:0>: DSM Data Low Carrier Selection bits(1) Bit settings are identical to those for CH<3:0>. Note 1: Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.  2013-2015 Microchip Technology Inc. DS30010038C-page 261

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 262  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 20.0 ENHANCED PARALLEL Key features of the EPMP module are: MASTER PORT (EPMP) • Extended Data Space (EDS) Interface allows Direct Access from the CPU Note: This data sheet summarizes the features of • Up to 10 Programmable Address Lines this group of PIC24F devices. It is not • Up to 2 Chip Select Lines intended to be a comprehensive reference • Up to 1 Acknowledgment Line source. For more information, refer to (one per chip select) the “dsPIC33/PIC24 Family Reference Manual”, “Enhanced Parallel Master • 4-Bit and 8-Bit Wide Data Bus Port (EPMP)” (DS39730). The information • Programmable Strobe Options (per chip select) in this data sheet supersedes the - Individual Read and Write Strobes or; information in the FRM. - Read/Write Strobe with Enable Strobe The Enhanced Parallel Master Port (EPMP) module • Programmable Address/Data Multiplexing provides a parallel, 4-bit (Master mode only) and 8-bit • Programmable Address Wait States (Master and Slave modes) data bus interface to com- • Programmable Data Wait States (per chip select) municate with off-chip modules, such as memories, • Programmable Polarity on Control Signals FIFOs, LCD controllers, and other microcontrollers. (per chip select) This module can serve as either the master or the slave • Legacy Parallel Slave Port (PSP) Support on the communication bus. • Enhanced Parallel Slave Port Support For EPMP Master modes, all external addresses are - Address Support mapped into the internal Extended Data Space (EDS). - 4-Byte Deep Auto-Incrementing Buffer This is done by allocating a region of the EDS for each chip select and then assigning each chip select to a particular external resource, such as a memory or 20.1 Memory Addressable in Different external controller. This region should not be assigned Modes to another device resource, such as RAM or SFRs. To The memory space addressable by the device perform a write or read on an external resource, the depends on the address/data multiplexing selection; it CPU simply performs a write or read within the address varies from 1K to 2 Mbytes. Refer to Table20-1 for range assigned for the EPMP. different memory-addressable modes.  2013-2015 Microchip Technology Inc. DS30010038C-page 263

PIC24FJ128GA204 FAMILY TABLE 20-1: MEMORY ADDRESSABLE IN DIFFERENT MODES Data Port Size PMA<9:8> PMA<7:0> PMD<7:4> PMD<3:0> Accessible memory Demultiplexed Address (ADRMUX<1:0> = 00) 8-Bit (PTSZ<1:0> = 00) Addr<9:8> Addr<7:0> Data 1K 4-Bit (PTSZ<1:0> = 01) Addr<9:8> Addr<7:0> — Data 1K 1 Address Phase (ADRMUX<1:0> = 01) 8-Bit (PTSZ<1:0> = 00) — PMALL Addr<7:0> Data 1K Addr<7:4> Addr<3:0> 4-Bit (PTSZ<1:0> = 01) Addr<9:8> PMALL 1K — Data (1) 2 Address Phases (ADRMUX<1:0> = 10) PMALL Addr<7:0> 8-Bit (PTSZ<1:0> = 00) — PMALH Addr<15:8> 64K — Data PMALL Addr<3:0> 4-Bit (PTSZ<1:0> = 01) Addr<9:8> PMALH Addr<7:4> 1K — Data 3 Address Phases (ADRMUX<1:0> = 11) PMALL Addr<7:0> PMALH Addr<15:8> 8-Bit (PTSZ<1:0> = 00) — 2 Mbytes PMALU Addr<22:16> — Data PMALL Addr<3:0> PMALH Addr<7:4> 4-Bit (PTSZ<1:0> = 01) Addr<13:12> 16K PMALU Addr<11:8> — Data DS30010038C-page 264  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 20-2: ENHANCED PARALLEL MASTER PORT PIN DESCRIPTIONS Pin Name Type Description (Alternate Function) O Address Bus bit 14 PMA<14> I/O Data Bus bit 14 (16-bit port with multiplexed addressing) (PMCS1) O Chip Select 1 (alternate location) PMA<9:3> O Address Bus bits<9:3> PMA<2> O Address Bus bit 2 (PMALU) O Address Latch Upper Strobe for Multiplexed Address PMA<1> I/O Address Bus bit 1 (PMALH) O Address Latch High Strobe for Multiplexed Address PMA<0> I/O Address Bus bit 0 (PMALL) O Address Latch Low Strobe for Multiplexed Address I/O Data Bus bits<7:0>, Data bits<15-8> PMD<7:0> O Address Bus bits<7:0> PMCS1 I/O Chip Select 1 PMCS2 I/O Chip Select 2 PMWR I/O Write Strobe PMRD I/O Read Strobe PMBE1 O Byte Indicator PMBE0 O Nibble or Byte Indicator PMACK1 I Acknowledgment Signal 1  2013-2015 Microchip Technology Inc. DS30010038C-page 265

PIC24FJ128GA204 FAMILY REGISTER 20-1: PMCON1: EPMP CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 PMPEN — PSIDL ADRMUX1 ADRMUX0 — MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP ALMODE — BUSKEEP IRQM1 IRQM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PMPEN: EPMP Enable bit 1 = EPMP is enabled 0 = EPMP is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 PSIDL: EPMP Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using 3 address phases 10 = Lower address bits are multiplexed with data bits using 2 address phases 01 = Lower address bits are multiplexed with data bits using 1 address phase 00 = Address and data appear on separate pins bit 10 Unimplemented: Read as ‘0’ bit 9-8 MODE<1:0>: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP: Pins used are PMRD, PMWR, PMCS, PMD<7:0> and PMA<1:0> 01 = Buffered PSP: Pins used are PMRD, PMWR, PMCS and PMD<7:0> 00 = Legacy Parallel Slave Port: Pins used are PMRD, PMWR, PMCS and PMD<7:0> bit 7-6 CSF<1:0>: Chip Select Function bits 11 = Reserved 10 = PMA<14> is used for Chip Select 1 01 = Reserved 00 = PMCS1 is used for Chip Select 1 bit 5 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) bit 4 ALMODE: Address Latch Strobe Mode bit 1 = Enables “smart” address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disables “smart” address strobes bit 3 Unimplemented: Read as ‘0’ bit 2 BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in a high-impedance state when not actively being driven bit 1-0 IRQM<1:0>: Interrupt Request Mode bits 11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt is generated at the end of a read/write cycle 00 = No interrupt is generated DS30010038C-page 266  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 20-2: PMCON2: EPMP CONTROL REGISTER 2 R-0, HSC U-0 R/C-0, HS R/C-0, HS U-0 U-0 U-0 U-0 PMPBUSY — ERROR TIMEOUT — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RADDR23(1) RADDR22(1) RADDR21(1) RADDR20(1) RADDR19(1) RADDR18(1) RADDR17(1) RADDR16(1) bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit bit 15 PMPBUSY: EPMP Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14 Unimplemented: Read as ‘0’ bit 13 ERROR: EPMP Error bit 1 = Transaction error (illegal transaction was requested) 0 = Transaction completed successfully bit 12 TIMEOUT: EPMP Time-out bit 1 = Transaction timed out 0 = Transaction completed successfully bit 11-8 Unimplemented: Read as ‘0’ bit 7-0 RADDR<23:16>: EPMP Reserved Address Space bits(1) Note 1: If RADDR<23:16> = 00000000, then the last EDS address for Chip Select 2 will be FFFFFFh.  2013-2015 Microchip Technology Inc. DS30010038C-page 267

PIC24FJ128GA204 FAMILY REGISTER 20-3: PMCON3: EPMP CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 PTWREN PTRDEN PTBE1EN PTBE0EN — AWAITM1 AWAITM0 AWAITE bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PTWREN: EPMP Write/Enable Strobe Port Enable bit 1 = PMWR port is enabled 0 = PMWR port is disabled bit 14 PTRDEN: EPMP Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled bit 13 PTBE1EN: EPMP High Nibble/Byte Enable Port Enable bit 1 = PMBE1 port is enabled 0 = PMBE1 port is disabled bit 12 PTBE0EN: EPMP Low Nibble/Byte Enable Port Enable bit 1 = PMBE0 port is enabled 0 = PMBE0 port is disabled bit 11 Unimplemented: Read as ‘0’ bit 10-9 AWAITM<1:0>: Address Latch Strobe Wait States bits 11 = Wait of 3½ TCY 10 = Wait of 2½ TCY 01 = Wait of 1½ TCY 00 = Wait of ½ TCY bit 8 AWAITE: Address Hold After Address Latch Strobe Wait States bits 1 = Wait of 1¼ TCY 0 = Wait of ¼ TCY bit 7-0 Unimplemented: Read as ‘0’ DS30010038C-page 268  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 20-4: PMCON4: EPMP CONTROL REGISTER 4 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — PTEN14 — — — — PTEN<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN<7:3> PTEN<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14 PTEN14: PMA14 Port Enable bit 1 = PMA14 functions as either Address Line 14 or Chip Select 1 0 = PMA14 functions as port I/O bit 13-10 Unimplemented: Read as ‘0’ bit 9-3 PTEN<9:3>: EPMP Address Port Enable bits 1 = PMA<9:3> function as EPMP address lines 0 = PMA<9:3> function as port I/Os bit 2-0 PTEN<2:0>: PMALU/PMALH/PMALL Strobe Enable bits 1 = PMA<2:0> function as either address lines or address latch strobes 0 = PMA<2:0> function as port I/Os  2013-2015 Microchip Technology Inc. DS30010038C-page 269

PIC24FJ128GA204 FAMILY REGISTER 20-5: PMCSxCF: EPMP CHIP SELECT x CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 CSDIS CSP CSPTEN BEP — WRSP RDSP SM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ACKP PTSZ1 PTSZ0 — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CSDIS: Chip Select x Disable bit 1 = Disables the Chip Select x functionality 0 = Enables the Chip Select x functionality bit 14 CSP: Chip Select x Polarity bit 1 = Active-high (PMCSx) 0 = Active-low (PMCSx) bit 13 CSPTEN: PMCSx Port Enable bit 1 = PMCSx port is enabled 0 = PMCSx port is disabled bit 12 BEP: Chip Select x Nibble/Byte Enable Polarity bit 1 = Nibble/byte enable is active-high (PMBE0, PMBE1) 0 = Nibble/byte enable is active-low (PMBE0, PMBE1) bit 11 Unimplemented: Read as ‘0’ bit 10 WRSP: Chip Select x Write Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master mode when SM = 1: 1 = Enable strobe is active-high 0 = Enable strobe is active-low bit 9 RDSP: Chip Select x Read Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Read strobe is active-high (PMRD) 0 = Read strobe is active-low (PMRD) For Master mode when SM = 1: 1 = Read/write strobe is active-high (PMRD/PMWR) 0 = Read/Write strobe is active-low (PMRD/PMWR) bit 8 SM: Chip Select x Strobe Mode bit 1 = Read/write and enable strobes (PMRD/PMWR) 0 = Read and write strobes (PMRD and PMWR) bit 7 ACKP: Chip Select x Acknowledge Polarity bit 1 = ACK is active-high (PMACK1) 0 = ACK is active-low (PMACK1) bit 6-5 PTSZ<1:0>: Chip Select x Port Size bits 11 = Reserved 10 = Reserved 01 = 4-bit port size (PMD<3:0>) 00 = 8-bit port size (PMD<7:0>) bit 4-0 Unimplemented: Read as ‘0’ DS30010038C-page 270  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 20-6: PMCSxBS: EPMP CHIP SELECT x BASE ADDRESS REGISTER(2) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) R/W(1) BASE<23:16> bit 15 bit 8 R/W(1) U-0 U-0 U-0 R/W(1) U-0 U-0 U-0 BASE15 — — — BASE11 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 BASE<23:15>: Chip Select x Base Address bits(1) bit 6-4 Unimplemented: Read as ‘0’ bit 3 BASE11: Chip Select x Base Address bit(1) bit 2-0 Unimplemented: Read as ‘0’ Note 1: The value at POR is 0080h for PMCS1BS and 0880h for PMCS2BS. 2: If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for Chip Select 1 will be FFFFFFh. In this case, Chip Select 2 should not be used. PMCS1BS has no such feature.  2013-2015 Microchip Technology Inc. DS30010038C-page 271

PIC24FJ128GA204 FAMILY REGISTER 20-7: PMCSxMD: EPMP CHIP SELECT x MODE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 ACKM1 ACKM0 AMWAIT2 AMWAIT1 AMWAIT0 — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DWAITB1 DWAITB0 DWAITM3 DWAITM2 DWAITM1 DWAITM0 DWAITE1 DWAITE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 ACKM<1:0>: Chip Select x Acknowledge Mode bits 11 = Reserved 10 = PMACKx is used to determine when a read/write operation is complete 01 = PMACKx is used to determine when a read/write operation is complete with time-out (If DWAITM<3:0> = 0000, the maximum time-out is 255 TCY or else it is DWAITM<3:0> cycles.) 00 = PMACKx is not used bit 13-11 AMWAIT<2:0>: Chip Select x Alternate Master Wait States bits 111 = Wait of 10 alternate master cycles • • • 001 = Wait of 4 alternate master cycles 000 = Wait of 3 alternate master cycles bit 10-8 Unimplemented: Read as ‘0’ bit 7-6 DWAITB<1:0>: Chip Select x Data Setup Before Read/Write Strobe Wait States bits 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY bit 5-2 DWAITM<3:0>: Chip Select x Data Read/Write Strobe Wait States bits For Write Operations: 1111 = Wait of 15½ TCY • • • 0001 = Wait of 1½ TCY 0000 = Wait of ½ TCY For Read Operations: 1111 = Wait of 15¾ TCY • • • 0001 = Wait of 1¾ TCY 0000 = Wait of ¾ TCY DS30010038C-page 272  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 20-7: PMCSxMD: EPMP CHIP SELECT x MODE REGISTER (CONTINUED) bit 1-0 DWAITE<1:0>: Chip Select x Data Hold After Read/Write Strobe Wait States bits For Write Operations: 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY For Read Operations: 11 = Wait of 3 TCY 10 = Wait of 2 TCY 01 = Wait of 1 TCY 00 = Wait of 0 TCY REGISTER 20-8: PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) R-0, HSC R/W-0, HS U-0 U-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC IBF IBOV — — IB3F(1) IB2F(1) IB1F(1) IB0F(1) bit 15 bit 8 R-1, HSC R/W-0, HS U-0 U-0 R-1, HSC R-1, HSC R-1, HSC R-1, HSC OBE OBUF — — OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable Input Buffer registers are full 0 = Some or all of the writable Input Buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full Input Buffer register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IB3F:IB0F: Input Buffer x Status Full bits(1) 1 = Input Buffer x contains unread data (reading the buffer will clear this bit) 0 = Input Buffer x does not contain unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable Output Buffer registers are empty 0 = Some or all of the readable Output Buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty Output Buffer register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OB3E:OB0E: Output Buffer x Status Empty bit 1 = Output Buffer x is empty (writing data to the buffer will clear this bit) 0 = Output Buffer x contains untransmitted data Note 1: Even though an individual bit represents the byte in the buffer, the bits corresponding to the word (Byte 0 and 1, or Byte 2 and 3) get cleared, even on byte reading.  2013-2015 Microchip Technology Inc. DS30010038C-page 273

PIC24FJ128GA204 FAMILY REGISTER 20-9: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 Unimplemented: Read as ‘0’ bit 0 PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers DS30010038C-page 274  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 21.0 REAL-TIME CLOCK AND • BCD format for smaller software overhead CALENDAR (RTCC) • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock crystal/ Note: This data sheet summarizes the features 32K INTRC frequency with periodic auto-adjust of this group of PIC24F devices. It is not • Optimized for long-term battery operation intended to be a comprehensive refer- • Fractional second synchronization ence source. For more information on the • Calibration to within ±2.64 seconds error per Real-Time Clock and Calendar, refer to month the “dsPIC33/PIC24 Family Reference Manual”, “RTCC with External Power • Calibrates up to 260 ppm of crystal error Control” (DS39745). • Ability to periodically wake-up external devices without CPU intervention (external power control) The RTCC provides the user with a Real-Time Clock • Power control output for external circuit control and Calendar (RTCC) function that can be calibrated. • Calibration takes effect every 15 seconds Key features of the RTCC module are: • Runs from any one of the following: • Operates in Deep Sleep mode - External Real-Time Clock (RTC) of 32.768 kHz • Selectable clock source - Internal 31.25 kHz LPRC clock • Provides hours, minutes and seconds using - 50 Hz or 60 Hz external input 24-hour format • Visibility of one half second period 21.1 RTCC Source Clock • Provides calendar – weekday, date, month and year The user can select between the SOSC crystal oscillator, LPRC internal oscillator or an external 50 Hz/ • Alarm-configurable for half a second, one second, 60Hz power line input as the clock reference for the 10 seconds, one minute, 10 minutes, one hour, RTCC module. This gives the user an option to trade off one day, one week, one month or one year system cost, accuracy and power consumption, based • Alarm repeat with decrementing counter on the overall system needs. • Alarm with indefinite repeat chime • Year 2000 to 2099 leap year correction FIGURE 21-1: RTCC BLOCK DIAGRAM Input from SOSC/LPRC Oscillator or External Source RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers ALCFGRPT 0.5 Sec YEAR MTHDY RTCC Timer RTCVAL WKDYHR Alarm MINSEC Event Comparator RTCPWC ALMTHDY ALWDHR Alarm Registers with Masks ALRMVAL ALMINSEC RTCCSWT Repeat Counter RTCC Interrupt RTCOUT<1:0> Power Control RTCOE 11 RTCC Interrupt and Power Control Logic Alarm Pulse 00 1s 01 RTCC Clock Source Pin 10  2013-2015 Microchip Technology Inc. DS30010038C-page 275

PIC24FJ128GA204 FAMILY 21.2 RTCC Module Registers TABLE 21-2: ALRMVAL REGISTER MAPPING The RTCC module registers are organized into three categories: ALRMPTR Alarm Value Register Window • RTCC Control Registers <1:0> ALRMVAL<15:8> ALRMVAL<7:0> • RTCC Value Registers 00 ALRMMIN ALRMSEC • Alarm Value Registers 01 ALRMWD ALRMHR 21.2.1 REGISTER MAPPING 10 ALRMMNTH ALRMDAY To limit the register interface, the RTCC Timer and 11 — — Alarm Time registers are accessed through corre- Considering that the 16-bit core does not distinguish sponding Register Pointers. The RTCC Value register between 8-bit and 16-bit read operations, the user must window (RTCVALH and RTCVALL) uses the be aware that when reading either the ALRMVALH or RTCPTR<1:0> bits (RCFGCAL<9:8>) to select the ALRMVALL bytes, the ALRMPTR<1:0> value will be desired Timer register pair (see Table21-1). decremented. The same applies to the RTCVALH or By writing the RTCVALH byte, the RTCC Pointer value, RTCVALL bytes with the RTCPTR<1:0> being the RTCPTR<1:0> bits decrement by one until they decremented. reach ‘00’. Once they reach ‘00’, the MINUTES and Note: This only applies to read operations and SECONDS value will be accessible through RTCVALH not write operations. and RTCVALL until the pointer value is manually changed. 21.2.2 WRITE LOCK TABLE 21-1: RTCVAL REGISTER MAPPING In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL<13>) must be RTCC Value Register Window RTCPTR<1:0> set (see Example21-1). RTCVAL<15:8> RTCVAL<7:0> Note: To avoid accidental writes to the timer, it is 00 MINUTES SECONDS recommended that the RTCWREN bit 01 WEEKDAY HOURS (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be 10 MONTH DAY set, there is only one instruction cycle time 11 — YEAR window allowed between the 55h/AA The Alarm Value register window (ALRMVALH and sequence and the setting of RTCWREN; ALRMVALL) uses the ALRMPTR<1:0> bits therefore, it is recommended that code (ALCFGRPT<9:8>) to select the desired Alarm register follow the procedure in Example21-1. pair (see Table21-2). 21.2.3 SELECTING RTCC CLOCK SOURCE By writing the ALRMVALH byte, the ALRMPTR<1:0> bits (the Alarm Pointer value) decrement by one until The clock source for the RTCC module can be selected they reach ‘00’. Once they reach ‘00’, the ALRMMIN using the RTCLK<1:0> bits in the RTCPWC register. and ALRMSEC value will be accessible through When the bits are set to ‘00’, the Secondary Oscillator ALRMVALH and ALRMVALL until the pointer value is (SOSC) is used as the reference clock and when the manually changed. bits are ‘01’, LPRC is used as the reference clock. When RTCLK<1:0> = 10 and 11, the external power line (50Hz and 60Hz) is used as the clock source. EXAMPLE 21-1: SETTING THE RTCWREN BIT asm volatile(“push w7”); asm volatile(“push w8”); asm volatile(“disi #5”); asm volatile(“mov #0x55, w7”); asm volatile(“mov w7, _NVMKEY”); asm volatile(“mov #0xAA, w8”); asm volatile(“mov w8, _NVMKEY”); asm volatile(“bset _RCFGCAL, #13”); //set the RTCWREN bit asm volatile(“pop w8”); asm volatile(“pop w7”); DS30010038C-page 276  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 21.3 Registers 21.3.1 RTCC CONTROL REGISTERS REGISTER 21-1: RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R/W-0 R/W-0 R/W-0 RTCEN(2) — RTCWREN RTCSYNC HALFSEC(3) RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled bit 9-8 RTCPTR<1:0>: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL<15:8>: 11 = Reserved 10 = MONTH 01 = WEEKDAY 00 = MINUTES RTCVAL<7:0>: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.  2013-2015 Microchip Technology Inc. DS30010038C-page 277

PIC24FJ128GA204 FAMILY REGISTER 21-1: RCFGCAL: RTCC CALIBRATION/CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 127 RTC clock pulses every 15 seconds • • • 00000001 = Minimum positive adjustment; adds 1 RTC clock pulse every 15 seconds 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 1 RTC clock pulse every 15 seconds • • • 10000000 = Maximum negative adjustment; subtracts 128 RTC clock pulses every 15 seconds Note 1: The RCFGCAL register is only affected by a POR. 2: A write to the RTCEN bit is only allowed when RTCWREN=1. 3: This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. DS30010038C-page 278  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 21-2: RTCPWC: RTCC POWER CONTROL REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWCEN PWCPOL PWCPRE PWSPRE RTCLK1(2) RTCLK0(2) RTCOUT1 RTCOUT0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PWCEN: Power Control Enable bit 1 = Power control is enabled 0 = Power control is disabled bit 14 PWCPOL: Power Control Polarity bit 1 = Power control output is active-high 0 = Power control output is active-low bit 13 PWCPRE: Power Control/Stability Prescaler bit 1 = PWC stability window clock is divide-by-2 of the source RTCC clock 0 = PWC stability window clock is divide-by-1 of the source RTCC clock bit 12 PWSPRE: Power Control Sample Prescaler bit 1 = PWC sample window clock is divide-by-2 of the source RTCC clock 0 = PWC sample window clock is divide-by-1 of the source RTCC clock bit 11-10 RTCLK<1:0>: RTCC Clock Source Select bits(2) 11 = External power line (60 Hz) 10 = External power line source (50 Hz) 01 = Internal LPRC Oscillator 00 = External Secondary Oscillator (SOSC) bit 9-8 RTCOUT<1:0>: RTCC Output Source Select bits 11 = Power control 10 = RTCC clock 01 = RTCC seconds clock 00 = RTCC alarm pulse bit 7-0 Unimplemented: Read as ‘0’ Note 1: The RTCPWC register is only affected by a POR. 2: When a new value is written to these register bits, the lower half of the MINSEC register should also be written to properly reset the clock prescalers in the RTCC.  2013-2015 Microchip Technology Inc. DS30010038C-page 279

PIC24FJ128GA204 FAMILY REGISTER 21-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h bit 13-10 AMASK<3:0>: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved – do not use 11xx = Reserved – do not use bit 9-8 ALRMPTR<1:0>: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = PWCSTAB ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = PWCSAMP bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times • • • 00000000 = Alarm will not repeat The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless CHIME=1. DS30010038C-page 280  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 21.3.2 RTCVAL REGISTER MAPPINGS REGISTER 21-4: YEAR: YEAR VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN2 YRTEN1 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7-4 YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. bit 3-0 YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 21-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2013-2015 Microchip Technology Inc. DS30010038C-page 281

PIC24FJ128GA204 FAMILY REGISTER 21-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 21-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS30010038C-page 282  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 21.3.3 ALRMVAL REGISTER MAPPINGS REGISTER 21-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x — — — MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. bit 11-8 MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. bit 3-0 DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1. REGISTER 21-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. bit 3-0 HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. Note 1: A write to this register is only allowed when RTCWREN=1.  2013-2015 Microchip Technology Inc. DS30010038C-page 283

PIC24FJ128GA204 FAMILY REGISTER 21-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. bit 11-8 MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. bit 7 Unimplemented: Read as ‘0’ bit 6-4 SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. bit 3-0 SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS30010038C-page 284  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 21-11: RTCCSWT: RTCC POWER CONTROL AND SAMPLE WINDOW TIMER REGISTER(1) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSTAB7 PWCSTAB6 PWCSTAB5 PWCSTAB4 PWCSTAB3 PWCSTAB2 PWCSTAB1 PWCSTAB0 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PWCSAMP7(2) PWCSAMP6(2) PWCSAMP5(2) PWCSAMP4(2) PWCSAMP3(2) PWCSAMP2(2) PWCSAMP1(2) PWCSAMP0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 PWCSTAB<7:0>: Power Control Stability Window Timer bits 11111111 = Stability window is 255 TPWCCLK clock periods 11111110 = Stability window is 254 TPWCCLK clock periods • • • 00000001 = Stability window is 1 TPWCCLK clock period 00000000 = No stability window; sample window starts when the alarm event triggers bit 7-0 PWCSAMP<7:0>: Power Control Sample Window Timer bits(2) 11111111 = Sample window is always enabled, even when PWCEN = 0 11111110 = Sample window is 254 TPWCCLK clock periods • • • 00000001 = Sample window is 1 TPWCCLK clock period 00000000 = No sample window Note 1: A write to this register is only allowed when RTCWREN=1. 2: The sample window always starts when the stability window timer expires, except when its initial value is 00h.  2013-2015 Microchip Technology Inc. DS30010038C-page 285

PIC24FJ128GA204 FAMILY 21.4 Calibration 21.5.1 CONFIGURING THE ALARM The real-time crystal input can be calibrated using the The alarm feature is enabled using the ALRMEN bit. periodic auto-adjust feature. When properly calibrated, This bit is cleared when an alarm is issued. Writes to the RTCC can provide an error of less than 3 seconds ALRMVAL should only take place when ALRMEN = 0. per month. This is accomplished by finding the number As shown in Figure21-2, the interval selection of the of error clock pulses and storing the value into the alarm is configured through the AMASK<3:0> bits lower half of the RCFGCAL register. The 8-bit signed (ALCFGRPT<13:10>). These bits determine which and value loaded into the lower half of RCFGCAL is how many digits of the alarm must match the clock multiplied by four and will either be added or subtracted value for the alarm to occur. from the RTCC timer, once every minute. Refer to the The alarm can also be configured to repeat based on a steps below for RTCC calibration: preconfigured interval. The amount of times this 1. Using another timer resource on the device, the occurs, once the alarm is enabled, is stored in the user must find the error of the 32.768 kHz ARPT<7:0> bits (ALCFGRPT<7:0>). When the value crystal. of the ARPTx bits equals 00h and the CHIME bit 2. Once the error is known, it must be converted to (ALCFGRPT<14>) is cleared, the repeat function is the number of error clock pulses per minute. disabled, and only a single alarm will occur. The alarm 3. a) If the oscillator is faster than ideal (negative can be repeated, up to 255 times, by loading result from Step 2), the RCFGCAL register value ARPT<7:0> with FFh. must be negative. This causes the specified After each alarm is issued, the value of the ARPTx bits number of clock pulses to be subtracted from is decremented by one. Once the value has reached the timer counter, once every minute. 00h, the alarm will be issued one last time, after which, b) If the oscillator is slower than ideal (positive the ALRMEN bit will be cleared automatically and the result from Step 2), the RCFGCAL register value alarm will turn off. must be positive. This causes the specified Indefinite repetition of the alarm can occur if the number of clock pulses to be subtracted from CHIME bit = 1. Instead of the alarm being disabled the timer counter, once every minute. when the value of the ARPTx bits reaches 00h, it rolls over to FFh and continues counting indefinitely while EQUATION 21-1: CHIME is set. (Ideal Frequency† – Measured Frequency) * 60 = Clocks per Minute 21.5.2 ALARM INTERRUPT † Ideal Frequency = 32,768 Hz At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that Writes to the lower half of the RCFGCAL register operates at half the frequency of the alarm. This output should only occur when the timer is turned off, or is completely synchronous to the RTCC clock and can immediately after the rising edge of the seconds pulse, be used as a trigger clock to other peripherals. except when SECONDS = 00, 15, 30 or 45. This is due to the auto-adjust of the RTCC at 15-second intervals. Note: Changing any of the registers, other than the RCFGCAL and ALCFGRPT registers, Note: It is up to the user to include, in the error and the CHIME bit while the alarm is value, the initial error of the crystal: drift enabled (ALRMEN = 1), can result in a due to temperature and drift due to crystal false alarm event leading to a false alarm aging. interrupt. To avoid a false alarm event, the timer and alarm values should only be 21.5 Alarm changed while the alarm is disabled (ALRMEN = 0). It is recommended that • Configurable from half second to one year the ALCFGRPT register and CHIME bit be • Enabled using the ALRMEN bit changed when RTCSYNC = 0. (ALCFGRPT<15>) • One-time alarm and repeat alarm options available DS30010038C-page 286  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 21-2: ALARM MASK SETTINGS Day of Alarm Mask Setting the (AMASK<3:0>) Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s 0100 - Every 10 minutes m s s 0101 - Every hour m m s s 0110 - Every day h h m m s s 0111 - Every week d h h m m s s 1000 - Every month d d h h m m s s 1001 - Every year(1) m m d d h h m m s s Note 1: Annually, except when configured for February 29. 21.6 Power Control external switch to turn on or off the power to one or more external devices. The active-low setting may also The RTCC includes a power control feature that allows be used in conjunction with an open-drain setting on the device to periodically wake-up an external device, the RTCC pin, in order to drive the ground pin(s) of the wait for the device to be stable before sampling wake-up external device directly (with the appropriate external events from that device and then shut down the external VDD pull-up device), without the need for external device. This can be done completely autonomously by switches. Finally, the CHIME bit should be set to enable the RTCC, without the need to wake from the current the PWC periodicity. lower power mode (Sleep, Deep Sleep, etc.). 21.7 RTCC VBAT Operation To use this feature: 1. Enable the RTCC (RTCEN = 1). The RTCC can operate in VBAT mode when there is a power loss on the VDD pin. The RTCC will continue to 2. Set the PWCEN bit (RTCPWC<15>). operate if the VBAT pin is powered on (it is usually 3. Configure the RTCC pin to drive the PWC control connected to the battery). signal (RTCOE = 1 and RTCOUT<1:0>=11). Note: It is recommended to connect the VBAT The polarity of the PWC control signal may be chosen pin to VDD if the VBAT mode is not used using the PWCPOL bit (RTCPWC<14>). An active-low (not connected to the battery). or active-high signal may be used with the appropriate  2013-2015 Microchip Technology Inc. DS30010038C-page 287

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 288  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 22.0 CRYPTOGRAPHIC ENGINE • Support for internal context saving • Session key encryption and loading Note: This data sheet summarizes the features • Half-duplex operation of the PIC24FJ128GA204 family of • DES and Triple DES (3DES) encryption and devices. It is not intended to be a compre- decryption (64-bit block size): hensive reference source. To complement the information in this data sheet, refer to - Supports 64-bit keys and 2-key or 3-key Triple DES the “dsPIC33/PIC24 Family Reference Manual”, “Cryptographic Engine” • AES encryption and decryption (128-bit block size): (DS70005133) which is available from the - Supports key sizes of 128, 192 or 256 bits Microchip website (www.microchip.com). • Supports ECB, CBC, CFB, OFB and CTR modes for both DES and AES standards The Cryptographic Engine provides a new set of data • Programmatically secure key storage: security options. Using its own free-standing state machines, the engine can independently perform NIS - 512-bit OTP array for key storage, not standard encryption and decryption of data inde- readable from other memory spaces pendently of the CPU. This eliminates the concerns of - 32-bit Configuration Page excessive CPU or program memory overhead that - Simple in-module programming interface encryption and decryption would otherwise require, - Supports Key Encryption Key (KEK) while enhancing the application’s security. • Support for True and Pseudorandom Number The primary features of the Cryptographic Engine are: Generation (PRNG) (NIST SP800-90 compliant) • Memory-mapped 128-bit and 256-bit memory A simplified block diagram of the Cryptographic Engine spaces for encryption/decryption data is shown in Figure22-1. • Multiple options for key storage, selection and management FIGURE 22-1: CRYPTOGRAPHIC ENGINE BLOCK DIAGRAM CRYCONL Cryptographic and CRYCONH OTP Control CRYSTAT CRYOTP CFGPAGE OTP Programming OTP Key Store and Configuration Key Management CRYKEY Mapped to 256 Bits SFR Space DES Engine CRYTXTA 128 Bits CRYTXTB AES 128 Bits Engine CRYTXTC 128 Bits  2013-2015 Microchip Technology Inc. DS30010038C-page 289

PIC24FJ128GA204 FAMILY 22.1 Data Register Spaces Once the encryption operation, and the appropriate and valid key configuration is selected, the operation is per- There are four register spaces used for cryptographic formed by setting the CRYGO bit. This bit is automatically data and key storage: cleared by hardware when the operation is complete. • CRYTXTA The CRYGO bit can also be manually cleared by soft- • CRYTXTB ware; this causes any operation in progress to terminate • CRYTXTC immediately. Clearing this bit in software also sets the • CRYKEY CRYABRT bit (CRYSTAT<5>). For most operations, CRYGO can only be set when an Although mapped into the SFR space, all of these Data OTP operation is not being performed and there are no Spaces are actually implemented as 128-bit or 256-bit other error conditions. CRYREAD, CRYWR, CRYABRT, wide arrays, rather than groups of 16-bit wide Data reg- isters. Reads and writes to and from these arrays are ROLLOVR, MODFAIL and KEYFAIL must all be ‘0’. automatically handled as if they were any other register Setting CRYWR and CRYGO simultaneously will not in the SFR space. initiate an OTP programming operation or any other operation. Setting CRYGO when the module is CRYTXTA through CRYTXTC are 128-bit wide spaces; disabled (CRYON = 0) also has no effect. they are used for writing data to and reading from the Cryptographic Engine. Additionally, they are also used 22.3 Enabling the Engine for storing intermediate results of the encryption/ decryption operation. None of these registers may be The Cryptographic Engine is enabled by setting the written to when the module is performing an operation CRYON bit. Clearing this bit disables both the DES and (CRYGO = 1). AES engines, as well as causing the following register CRYTXTA and CRYTXTB normally serve as inputs to bits to be held in Reset: the encryption/decryption process. • CRYGO (CRYCONL<8>) CRYTXTA usually contains the initial plaintext or cipher- • TXTABSY (CRYSTAT<6>) text to be encrypted or decrypted. Depending on the • CRYWR (CRYOTP<0>) mode of operation, CRYTXTB may contain the ciphertext All other register bits and registers may be read and output or intermediate cipher data. It may also function as written while CRYON = 0. a programmable length counter in certain operations. CRYTXTC is primarily used to store the final output of 22.4 Operation During Sleep and Idle an encryption/decryption operation. It is also used as Modes the input register for data to be programmed to the secure OTP array. 22.4.1 OPERATION DURING SLEEP MODES CRYKEY is a 256-bit wide space, used to store cryp- Whenever the device enters any Sleep or Deep Sleep tographic keys for the selected operation; it is writable mode, all operation engine state machines are reset. from both the SFR space and the secure OTP array. This feature helps to preserve the integrity, or any data Although mapped into the SFR space, it is a write-only being encrypted or decrypted, by discarding any memory area; any data placed here, regardless of its intermediate text that might be used to break the key. source, cannot be read back by any run-time operations. Any OTP programming operations under way when a This feature helps to ensure the security of any key data. Sleep mode is entered are also halted. Depending on what is being programmed, this may result in permanent 22.2 Modes of Operation loss of a memory location or potentially the use of the The Cryptographic Engine supports the following modes entire secure OTP array. Users are advised to perform of operation, determined by the OPMOD<3:0> bits: OTP programming only when entry into power-saving modes is disabled. • Block Encryption • Block Decryption Note: OTP programming errors, regardless of the • AES Decryption Key Expansion source, are not recoverable errors. Users • Random Number Generation should ensure that all foreseeable interrup- tions to the programming operation, • Session Key Generation including device interrupts and entry into • Session Key Encryption power-saving modes, are disabled. • Session Key Loading The OPMOD<3:0> bits may be changed while CRYON is set. They should only be changed when a cryptographic operation is not being done (CRYGO = 0).  2013-2015 Microchip Technology Inc. DS30010038C-page 290

PIC24FJ128GA204 FAMILY 22.4.2 OPERATION DURING IDLE MODE 22.7 Decrypting Data When the CRYSIDL bit (CRYCONL<13>) is ‘0’, the 1. If not already set, set the CRYON bit. engine will continue any ongoing operations without 2. Configure the CPHRSEL, CPHRMODx, interruption when the device enters Idle mode. KEYMODx and KEYSRCx bits as desired to When CRYSIDL is ‘1’, the module behaves as in Sleep select the proper mode and key length. modes. 3. Set OPMOD<3:0> to ‘0001’. 4. If a software key is being used, write the 22.5 Specific Cryptographic CRYKEY register. It is only necessary to write Operations the lowest n bits of CRYKEY for a key length of n, as all unused CRYKEY bits are ignored. This section provides the step-wise details for each 5. If an AES-ECB or AES-CBC mode decryption is operation type that is available with the Cryptographic Engine. being performed, you must first perform an AES decryption key expansion operation. 22.6 Encrypting Data 6. Read the KEYFAIL status bit. If this bit is ‘1’, an illegal configuration has been selected and the 1. If not already set, set the CRYON bit. encrypt operation will not be performed. 2. Configure the CPHRSEL, CPHRMODx, 7. Write the data to be decrypted into the appropriate KEYMODx and KEYSRCx bits as desired to text/data register. For a DES decrypt operation, it select the proper mode and key length. is only necessary to write the lowest 64 bits of 3. Set OPMOD<3:0> to ‘0000’. CRYTXTB. 4. If a software key is being used, write it to the 8. Set the CRYGO bit. CRYKEY register. It is only necessary to write 9. If this is the first decrypt operation after a Reset, the lowest n bits of CRYKEY for a key length of or if a key storage program operation was per- n, as all unused CRYKEY bits are ignored. formed after the last decrypt operation, or if the 5. Read the KEYFAIL bit. If this bit is ‘1’, an illegal KEYMODx or KEYSRCx fields are changed, the configuration has been selected and the encrypt engine will perform a new key expansion operation will NOT be performed. operation. This will result in extra clock cycles 6. Write the data to be encrypted to the appropriate for the decrypt operation, but will otherwise be transparent to the application (i.e., the CRYGO CRYTXT register. For a single DES encrypt operation, it is only necessary to write the lowest bit will be cleared only after the key expansion and the decrypt operation have completed). 64 bits. However, for data less than the block size (64 bits for DES, 128 bits for AES), it is the 10. In ECB and CBC modes, set the FREEIE bit responsibility of the software to properly pad the (CRYCONL<10>) to enable the optional upper bits within the block. CRYTXTA interrupt to indicate when the next plaintext block can be loaded. 7. Set the CRYGO bit. 11. Poll the CRYGO bit until it is cleared or wait for 8. In ECB and CBC modes, set the FREEIE bit (CRYCONL<10>) to enable the optional the CRYDNIF module interrupt (DONEIE must be set). If other Cryptographic Engine interrupts CRYTXTA interrupt to indicate when the next are enabled, it will be necessary to poll the plaintext block can be loaded. CRYGO bit to verify the interrupt source. 9. Poll the CRYGO bit until it is cleared or wait for 12. Read the decrypted block out of the appropriate the CRYDNIF module interrupt (DONEIE must text/data register. be set). If other Cryptographic Engine interrupts are enabled, it will be necessary to poll the 13. Repeat Steps 6 through 10 to encrypt further CRYGO bit to verify the interrupt source. blocks in the message with the same key. 10. Read the encrypted block from the appropriate CRYTXT register. 11. Repeat Steps 5 through 8 to encrypt further blocks in the message with the same key.  2013-2015 Microchip Technology Inc. DS30010038C-page 291

PIC24FJ128GA204 FAMILY 22.8 Encrypting a Session Key 22.9 Receiving a Session Key Note: ECB and CBC modes are restricted to Note: ECB and CBC modes are restricted to 128-bit session keys only. 128-bit session keys only. 1. If not already set, set the CRYON bit. 1. If not already set, set the CRYON bit. 2. If not already programmed, program the 2. If not already programmed, program the SKEYEN bit to ‘1’. SKEYEN bit to ‘1’. Note: Setting SKEYEN permanently makes Note: Setting SKEYEN permanently makes Key#1 available as a Key Encryption Key Key#1 available as a Key Encryption Key only. It cannot be used for other encryption only. It cannot be used for other encryp- or decryption operations after that. tion or decryption operations after that. It also permanently disables the ability of 3. Set OPMOD<3:0> to ‘1110’. software to decrypt the session key into 4. Configure the CPHRSEL, CPHRMOD<2:0> and the CRYTXTA register, thereby breaking KEYMOD<1:0> register bit fields as desired, set programmatic security (i.e., software can SKEYSEL to ‘0’. read the unencrypted key). 5. Read the KEYFAIL status bit. If this bit is ‘1’, an 3. Set OPMOD<3:0> to ‘1111’. illegal configuration has been selected and the encrypt operation will not be performed. 4. Configure the CPHRSEL, CPHRMOD<2:0> and KEYMOD<1:0> register bit fields as desired, set 6. Write the software generated session key into SKEYSEL to ‘0’. the CRYKEY register or generate a random key into the CRYKEY register. It is only necessary to 5. Read the KEYFAIL status bit. If this bit is ‘1’, an write the lowest n bits of CRYKEY for a key illegal configuration has been selected and the length of n, as all unused key bits are ignored. encrypt operation will NOT be performed. 7. Set the CRYGO bit. Poll the bit until it is cleared 6. Write the encrypted session key received into by hardware; alternatively, set the DONEIE bit the appropriate CRYTXT register. (CRYCONL<11>) to generate an interrupt when 7. Set the CRYGO bit. Poll the bit until it is cleared the encryption is done. by hardware; alternatively, set the DONEIE bit 8. Read the encrypted session key out of the (CRYCONL<11>) to generate an interrupt when appropriate CRYTXT register. the process is done. 9. For total key lengths of more than 128 bits, set 8. For total key lengths of more than 128 bits, set SKEYSEL to ‘1’ and repeat Steps 6 and 7. SKEYSEL to ‘1’ and repeat Steps 6 and 7. 10. Set KEYSRC<3:0> to ‘0000’ to use the session 9. Set KEYSRC<3:0> to ‘0000’ to use the newly key to encrypt data. generated session key to encrypt and decrypt data.  2013-2015 Microchip Technology Inc. DS30010038C-page 292

PIC24FJ128GA204 FAMILY 22.10 Generating a Pseudorandom To generate the pseudorandom number: Number (PRN) 1. Load NEW_KEY value from RAM into CRYKEY. 2. Load NEW_CTR value from RAM into CRYTXTB. For operations that require a Pseudorandom Number (PRN), the method outlined in NIST SP800-90 can be 3. Load CRYTXTA with 0h (128 bits). adapted for efficient use with the Cryptographic 4. Configure the engine for AES encryption, CTR Engine. This method uses the AES algorithm in CTR mode (OPMOD<3:0> = 0000, CPHRSEL = 1, mode to create PRNs with minimal CPU overhead. CPHMOD<2:0> = 100). PRNs generated in this manner can be used for cryp- 5. Perform an encrypt operation by setting CRYGO. tographic purposes or any other purpose that the host 6. Copy the generated PRN in CRYTXTC application may require. (PRNG_VALUE) to RAM. The random numbers used as initial seeds can be 7. Repeat the encrypt operation. taken from any source convenient to the user’s applica- 8. Store the value of CRYTXTC from this round as tion. If possible, a non-deterministic random number the new value of NEW_KEY. source should be used. 9. Repeat the encrypt operation. Note: PRN generation is not available when 10. Store the value of CRYTXTC from this round as software keys are disabled (SWKYDIS = 1). the new value of NEW_CTR. To perform the initial reseeding operation, and subse- Subsequent PRNs can be generated by repeating this quent reseedings after the reseeding interval has procedure until the reseeding interval has expired. At expired: that point, the reseeding operation is performed using 1. Store a random number (128 bits) in CRYTXTA. the stored values of NEW_KEY and NEW_CTR. 2. For the initial generation ONLY, use a key value 22.11 Generating a Random Number of 0h (128 bits) and a counter value of 0h. 3. Configure the engine for AES encryption, CTR 1. Enable the Cryptographic mode (CRYON mode (OPMOD<3:0> = 0000, CPHRSEL = 1, (CRYCONL<0>) = 1). CPHMOD<2:0> = 100). 2. Set the OPMOD<3:0> bits to ‘1010’. 4. Perform an encrypt operation by setting 3. Start the request by setting the CRYGO bit CRYGO. (CRYCONL<8>) to ‘1’. 5. Move the results in CRYTXTC to RAM. This is 4. Wait for the CRYGO bit to be cleared to ‘0’ by the new key value (NEW_KEY). the hardware. 6. Store another random number (128 bits) in 5. Read the random number from the CRYTXTA CRYTXTA. registers. 7. Configure the module for encryption as in Step3. 8. Perform an encrypt operation by setting 22.12 Testing the Key Source CRYGO. Configuration 9. Store this value in RAM. This is the new counter value (NEW_CTR). The validity of the key source configuration can always be tested by writing the appropriate register bits and 10. For subsequent reseeding operations, use then reading the KEYFAIL register bit. No operation NEW_KEY and NEW_CTR for the starting key and needs to be started to perform this check; the module counter values. does not even need to be enabled.  2013-2015 Microchip Technology Inc. DS30010038C-page 293

PIC24FJ128GA204 FAMILY 22.13 Programming CFGPAGE (Page 0) 22.14 Programming Keys Configuration Bits 1. If not already set, set the CRYON bit. 1. If not already set, set the CRYON bit. Set 2. Configure KEYPG<3:0> to the page you want to KEYPG<3:0> to ‘0000’. program. 2. Read the PGMFAIL status bit. If this bit is ‘1’, an 3. Read the PGMFAIL status bit. If this bit is ‘1’, an illegal configuration has been selected and the illegal configuration has been selected and the programming operation will not be performed. programming operation will not be performed. 3. Write the data to be programmed into the 4. Write the data to be programmed into the Configuration Page into CRYTXTC<31:0>. Any Configuration Page into CRYTXTC<63:0>. Any bits that are set (‘1’) will be permanently bits that are set (‘1’) will be permanently programmed, while any bits that are cleared (‘0’) programmed, while any bits that are cleared (‘0’) will not be programmed and may be will not be programmed and may be programmed at a later time. programmed at a later time. 4. Set the CRYWR bit. Poll the bit until it is cleared; 5. Set the CRYWR bit. Poll the bit until it is cleared; alternatively, set the OTPIE bit (CRYOTP<6>) to alternatively, set the OTPIE bit (CRYOTP<6>) to enable the optional OTP done interrupt. enable the optional OTP done interrupt. 5. Once all programming has completed, set the 6. Repeat Steps 2 through 5 for each OTP array CRYREAD bit to reload the values from the on- page to be programmed. chip storage. A read operation must be 7. Once all programming has completed, set the performed to complete programming. CRYREAD bit to reload the values from the on- Note: Do not clear the CRYON bit while the chip storage. A read operation must be CRYREAD bit is set; this will result in an performed to complete programming. incomplete read operation and unavailable Note: Do not clear the CRYON bit while the key data. To recover, set CRYON and CRYREAD bit is set; this will result in an CRYREAD, and allow the read operation to incomplete read operation and unavailable fully complete. key data. To recover, set CRYON and 6. Poll the CRYREAD bit until it is cleared; alterna- CRYREAD, and allow the read operation to tively, set the OTPIE bit (CRYOTP<6>) to fully complete. enable the optional OTP done interrupt. 8. Poll the CRYREAD bit until it is cleared; alterna- 7. For production programming, the TSTPGM bit tively, set the OTPIE bit (CRYOTP<6>) to can be set to indicate a successful programming enable the optional OTP done interrupt. operation. When TSTPGM is set, the PGMTST 9. For production programming, the TSTPGM bit bit (CRYOTP<7>) will also be set, allowing can be set to indicate a successful programming users to see the OTP array status with operation. When TSTPGM is set, the PGMTST performing a read operation on the array. bit (CRYOTP<7>) will also be set, allowing Note: If the device enters Sleep mode during OTP users to see the OTP array status with programming, the contents of the OTP performing a read operation on the array. array may become corrupted. This is not a Note: If the device enters Sleep mode during OTP recoverable error. Users must ensure that programming, the contents of the OTP array entry into power-saving modes is disabled may become corrupted. This is not a recov- before OTP programming is performed. erable error. Users must ensure that entry into power-saving modes is disabled before OTP programming is performed. 22.15 Verifying Programmed Keys To maintain key security, the secure OTP array has no provision to read back its data to any user-accessible memory space in any operating mode. Therefore, there is no way to directly verify programmed data. The only method for verifying that they have been programmed correctly is to perform an encryption operation with a known plaintext/ciphertext pair for each programmed key.  2013-2015 Microchip Technology Inc. DS30010038C-page 294

PIC24FJ128GA204 FAMILY REGISTER 22-1: CRYCONL: CRYPTOGRAPHIC CONTROL LOW REGISTER R/W-0 U-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) U-0 R/W-0, HC(1) CRYON — CRYSIDL(3) ROLLIE DONEIE FREEIE — CRYGO bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) OPMOD3(2) OPMOD2(2) OPMOD1(2) OPMOD0(2) CPHRSEL(2) CPHRMOD2(2) CPHRMOD1(2) CPHRMOD0(2) bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRYON: Cryptographic Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CRYSIDL: Cryptographic Stop in Idle Control bit(3) 1 = Stops module operation in Idle mode 0 = Continues module operation in Idle mode bit 12 ROLLIE: CRYTXTB Rollover Interrupt Enable bit(1) 1 = Generates an interrupt event when the counter portion of CRYTXTB rolls over to ‘0’ 0 = Does not generate an interrupt event when the counter portion of CRYTXTB rolls over to ‘0’ bit 11 DONEIE: Operation Done Interrupt Enable bit(1) 1 = Generates an interrupt event when the current cryptographic operation completes 0 = Does not generate an interrupt event when the current cryptographic operation completes; software must poll the CRYGO or CRYBSY bit to determine when current cryptographic operation is complete bit 10 FREEIE: Input Text Interrupt Enable bit(1) 1 = Generates an interrupt event when the input text (plaintext or ciphertext) is consumed during the current cryptographic operation 0 = Does not generate an interrupt event when the input text is consumed bit 9 Unimplemented: Read as ‘0’ bit 8 CRYGO: Cryptographic Engine Start bit(1) 1 = Starts the operation specified by OPMOD<3:0> (cleared automatically when operation is done) 0 = Stops the current operation (when cleared by software); also indicates the current operation has completed (when cleared by hardware) Note 1: These bits are reset on system Resets or whenever the CRYMD bit is set. 2: Writes to these bit fields are locked out whenever an operation is in progress (CRYGO bit is set). 3: If the device enters Idle mode when CRYSIDL = 1, the module will stop its current operation. Entering into Idle mode while an OTP write operation is in process can result in irreversible corruption of the OTP.  2013-2015 Microchip Technology Inc. DS30010038C-page 295

PIC24FJ128GA204 FAMILY REGISTER 22-1: CRYCONL: CRYPTOGRAPHIC CONTROL LOW REGISTER (CONTINUED) bit 7-4 OPMOD<3:0>: Operating Mode Selection bits(1,2) 1111 = Loads session key (decrypt session key in CRYTXTA/CRYTXTB using the Key Encryption Key and write to CRYKEY) 1110 = Encrypts session key (encrypt session key in CRYKEY using the Key Encryption Key and write to CRYTXTA/CRYTXTB) 1011 = Reserved 1010 = Generate a random number 1001 • • = Reserved • 0011 0010 = AES decryption key expansion 0001 = Decryption 0000 = Encryption bit 3 CPHRSEL: Cipher Engine Select bit(1,2) 1 = AES engine 0 = DES engine bit 2-0 CPHRMOD<2:0>: Cipher Mode bits(1,2) 11x = Reserved 101 = Reserved 100 = Counter (CTR) mode 011 = Output Feedback (OFB) mode 010 = Cipher Feedback (CFB) mode 001 = Cipher Block Chaining (CBC) mode 000 = Electronic Codebook (ECB) mode Note 1: These bits are reset on system Resets or whenever the CRYMD bit is set. 2: Writes to these bit fields are locked out whenever an operation is in progress (CRYGO bit is set). 3: If the device enters Idle mode when CRYSIDL = 1, the module will stop its current operation. Entering into Idle mode while an OTP write operation is in process can result in irreversible corruption of the OTP.  2013-2015 Microchip Technology Inc. DS30010038C-page 296

PIC24FJ128GA204 FAMILY REGISTER 22-2: CRYCONH: CRYPTOGRAPHIC CONTROL HIGH REGISTER U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) — CTRSIZE6(2,3) CTRSIZE5(2,3) CTRSIZE4(2,3) CTRSIZE3(2,3) CTRSIZE2(2,3) CTRSIZE1(2,3) CTRSIZE0(2,3) bit 15 bit 8 R/W-0(1) R/W-0(1) R/W-0(1) U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) SKEYSEL KEYMOD1(2) KEYMOD0(2) — KEYSRC3(2) KEYSRC2(2) KEYSRC1(2) KEYSRC0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-8 CTRSIZE<6:0>: Counter Size Select bits(1,2,3) Counter is defined as CRYTXTB<n:0>, where n = CTRSIZEx. The counter increments after each operation and generates a rollover event when the counter rolls over from (2n-1 – 1) to 0. 1111111 = 128 bits (CRYTXTB<127:0>) 1111110 = 127 bits (CRYTXTB<126:0>) • • • 0000010 = 3 bits (CRYTXTB<2:0>) 0000001 = 2 bits (CRYTXTB<1:0>) 0000000 = 1 bit (CRYTXTB<0>); rollover event occurs when CRYTXTB<0> toggles from ‘1’ to ‘0’ bit 7 SKEYSEL: Session Key Select bit(1) 1 = Key generation/encryption/loading performed with CRYKEY<255:128> 0 = Key generation/encryption/loading performed with CRYKEY<127:0> bit 6-5 KEYMOD<1:0>: AES/DES Encrypt/Decrypt Key Mode/Key Length Select bits(1,2) For DES Encrypt/Decrypt Operations (CPHRSEL = 0): 11 = 64-bit, 3-key 3DES 10 = Reserved 01 = 64-bit, standard 2-key 3DES 00 = 64-bit DES For AES Encrypt/Decrypt Operations (CPHRSEL = 1): 11 = Reserved 10 = 256-bit AES 01 = 192-bit AES 00 = 128-bit AES bit 4 Unimplemented: Read as ‘0’ bit 3-0 KEYSRC<3:0>: Cipher Key Source bits(1,2) Refer to Table22-1 and Table22-2 for KEYSRC<3:0> values. Note 1: These bits are reset on system Resets or whenever the CRYMD bit is set. 2: Writes to these bit fields are locked out whenever an operation is in progress (CRYGO bit is set). 3: Used only in CTR operations when CRYTXTB is being used as a counter; otherwise, these bits have no effect.  2013-2015 Microchip Technology Inc. DS30010038C-page 297

PIC24FJ128GA204 FAMILY REGISTER 22-3: CRYSTAT: CRYPTOGRAPHIC STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/HSC-x(1) R/HSC-0(1) R/C-0, HS(2) R/C-0, HS(2) U-0 R/HSC-0(1) R/HSC-x(1) R/HSC-x(1) CRYBSY(4) TXTABSY CRYABRT(5) ROLLOVR — MODFAIL(3) KEYFAIL(3,4) PGMFAIL(3,4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ HS = Hardware Settable bit C = Clearable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Reset State Conditional bit bit 15-8 Unimplemented: Read as ‘0’ bit 7 CRYBSY: Cryptographic OTP Array Busy Status bit(1,4) 1 = The cryptography module is performing a cryptographic operation or OTP operation 0 = The module is not currently performing any operation bit 6 TXTABSY: CRYTXTA Busy Status bit(1) 1 = The CRYTXTA register is busy and may not be written to 0 = The CRYTXTA is free and may be written to bit 5 CRYABRT: Cryptographic Operation Aborted Status bit(2,5) 1 = Last operation was aborted by clearing the CRYGO bit in software 0 = Last operation completed normally (CRYGO cleared in hardware) bit 4 ROLLOVR: Counter Rollover Status bit(2) 1 = The CRYTXTB counter rolled over on the last CTR mode operation; once set, this bit must be cleared by software before the CRYGO bit can be set again 0 = No rollover event has occurred bit 3 Unimplemented: Read as ‘0’ bit 2 MODFAIL: Mode Configuration Fail Flag bit(1,3) 1 = Currently selected operating and Cipher mode configuration is invalid; the CRYWR bit cannot be set until a valid mode is selected (automatically cleared by hardware with any valid configuration) 0 = Currently selected operating and Cipher mode configurations are valid bit 1 KEYFAIL: Key Configuration Fail Status bit(1,3,4) See Table22-1 and Table22-2 for invalid key configurations. 1 = Currently selected key and mode configurations are invalid; the CRYWR bit cannot be set until a valid mode is selected (automatically cleared by hardware with any valid configuration) 0 = Currently selected configurations are valid bit 0 PGMFAIL: Key Storage/Configuration Program Fail Flag bit(1,3,4) 1 = The page indicated by KEYPG<3:0> is reserved or locked; the CRYWR bit cannot be set and no programming operation can be started 0 = The page indicated by KEYPG<3:0> is available for programming Note 1: These bits are reset on system Resets or whenever the CRYMD bit is set. 2: These bits are reset on system Resets when the CRYMD bit is set or when CRYGO is cleared. 3: These bits are functional even when the module is disabled (CRYON = 0); this allows mode configurations to be validated for compatibility before enabling the module. 4: These bits are automatically set during all OTP read operations, including the initial read at POR. Once the read is completed, the bit assumes the proper state that reflects the current configuration. 5: If this bit is set, a cryptographic operation cannot be performed.  2013-2015 Microchip Technology Inc. DS30010038C-page 298

PIC24FJ128GA204 FAMILY REGISTER 22-4: CRYOTP: CRYPTOGRAPHIC OTP PAGE PROGRAM CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/HSC-x(1) R/W-0(1) R/S/HC-1 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) R/S/HC-0(2) PGMTST OTPIE CRYREAD(3,4) KEYPG3 KEYPG2 KEYPG1 KEYPG0 CRYWR(3,4) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 PGMTST: Key Storage/Configuration Program Test bit(1) This bit mirrors the state of the TSTPGM bit and is used to test the programming of the secure OTP array after programming. 1 = TSTPGM (CFGPAGE<30>) is programmed (‘1’) 0 = TSTPGM is not programmed (‘0’) bit 6 OTPIE: Key Storage/Configuration Program Interrupt Enable bit(1) 1 = Generates an interrupt when the current programming or read operation completes 0 = Does not generate an interrupt when the current programming or read operation completes; software must poll the CRYWR, CRYREAD or CRYBSY bit to determine when the current programming operation is complete bit 5 CRYREAD: Cryptographic Key Storage/Configuration Read bit(3,4) 1 = This bit is set to start a read operation; read operation is in progress while this bit is set and CRYGO = 1 0 = Read operation has completed bit 4-1 KEYPG<3:0>: Key Storage/Configuration Program Page Select bits(1) 1111 • • = Reserved • 1001 1000 = OTP Page 8 0111 = OTP Page 7 0110 = OTP Page 6 0101 = OTP Page 5 0100 = OTP Page 4 0011 = OTP Page 3 0010 = OTP Page 2 0001 = OTP Page 1 0000 = Configuration Page (CFGPAGE, OTP Page 0) bit 0 CRYWR: Cryptographic Key Storage/Configuration Program bit(2,3,4) 1 = Programs the Key Storage/Configuration bits with the value found in CRYTXTC<63:0> 0 = Program operation has completed Note 1: These bits are reset on systems Resets or whenever the CRYMD bit is set. 2: These bits are reset on systems Resets, when the CRYMD bit is set or when CRYGO is cleared. 3: Set this bit only when CRYON = 1 and CRYGO = 0. Do not set CRYREAD or CRYWR both, at any given time. 4: Do not clear CRYON or these bits while they are set; always allow the hardware operation to complete and clear the bit automatically.  2013-2015 Microchip Technology Inc. DS30010038C-page 299

PIC24FJ128GA204 FAMILY REGISTER 22-5: CFGPAGE: SECURE ARRAY CONFIGURATION BITS (OTP PAGE 0) REGISTER r-x R/PO-x U-x U-x R/PO-x R/PO-x R/PO-x R/PO-x — TSTPGM(1) — — KEY4TYPE1 KEY4TYPE0 KEY3TYPE1 KEY3TYPE0 bit 31 bit 24 R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x KEY2TYPE1 KEY2TYPE0 KEY1TYPE1 KEY1TYPE0 SKEYEN LKYSRC7 LKYSRC6 LKYSRC5 bit 23 bit 16 R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x LKYSRC4 LKYSRC3 LKYSRC2 LKYSRC1 LKYSRC0 SRCLCK WRLOCK8 WRLOCK7 bit 15 bit 8 R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x R/PO-x WRLOCK6 WRLOCK5 WRLOCK74 WRLOCK3 WRLOCK2 WRLOCK1 WRLOCK0 SWKYDIS bit 7 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 Reserved: Do not modify bit 30 TSTPGM: Customer Program Test bit(1) 1 = CFGPAGE has been programmed 0 = CFGPAGE has not been programmed bit 29-28 Unimplemented: Read as ‘0’ bit 27-26 KEY4TYPE<1:0>: Key Type for OTP Pages 7 and 8 bits 00 = Keys in these pages are for DES/2DES operations only 01 = Keys in these pages are for 3DES operations only 10 = Keys in these pages are for 128-bit AES operations only 11 = Keys in these pages are for 192-bit/256-bit AES operations only bit 25-24 KEY3TYPE<1:0>: Key Type for OTP Pages 5 and 6 bits 00 = Keys in these pages are for DES/2DES operations only 01 = Keys in these pages are for 3DES operations only 10 = Keys in these pages are for 128-bit AES operations only 11 = Keys in these pages are for 192-bit/256-bit AES operations only bit 23-22 KEY2TYPE<1:0>: Key Type for OTP Pages 3 and 4 bits 00 = Keys in these pages are for DES/2DES operations only 01 = Keys in these pages are for 3DES operations only 10 = Keys in these pages are for 128-bit AES operations only 11 = Keys in these pages are for 192-bit/256-bit AES operations only bit 21-20 KEY1TYPE<1:0>: Key Type for OTP Pages 1 and 2 bits 00 = Keys in these pages are for DES/2DES operations only 01 = Keys in these pages are for 3DES operations only 10 = Keys in these pages are for 128-bit AES operations only 11 = Keys in these pages are for 192-bit/256-bit AES operations only Note 1: This bit’s state is mirrored by the PGMTST bit (CRYOTP<7>).  2013-2015 Microchip Technology Inc. DS30010038C-page 300

PIC24FJ128GA204 FAMILY REGISTER 22-5: CFGPAGE: SECURE ARRAY CONFIGURATION BITS (OTP PAGE 0) REGISTER (CONTINUED) bit 19 SKEYEN: Session Key Enable bit 1 = Stored Key #1 may be used only as a Key Encryption Key 0 = Stored Key #1 may be used for any operation bit 18-11 LKYSRC<7:0>: Locked Key Source Configuration bits If SRCLCK = 1: 1xxxxxxx = Key Source is as if KEYSRC<3:0>=1111 01xxxxxx = Key Source is as if KEYSRC<3:0>=0111 001xxxxx = Key Source is as if KEYSRC<3:0>=0110 0001xxxx = Key Source is as if KEYSRC<3:0>=0101 00001xxx = Key Source is as if KEYSRC<3:0>=0100 000001xx = Key Source is as if KEYSRC<3:0>=0011 0000001x = Key Source is as if KEYSRC<3:0>=0010 00000001 = Key Source is as if KEYSRC<3:0>=0001 00000000 = Key Source is as if KEYSRC<3:0>=0000 If SRCLCK = 0: These bits are ignored. bit 10 SRCLCK: Key Source Lock bit 1 = The key source is determined by the KEYSRC<3:0> (CRYCONH<3:0>) bits (software key selection is disabled) 0 = The key source is determined by the KEYSRC<3:0> (CRYCONH<3:0>) bits (locked key selection is disabled) bit 9-1 WRLOCK<8:0>: Write Lock Page Enable bits For OTP Pages 0 (CFGPAGE) through 8: 1 = OTP Page is permanently locked and may not be programmed 0 = OTP Page is unlocked and may be programmed bit 0 SWKYDIS: Software Key Disable bit 1 = Software key (CRYKEY register) is disabled; when KEYSRC<3:0> = 0000, the KEYFAIL status bit will be set and no encryption/decryption/session key operations can be started until KEYSRC<3:0> bits are changed to a value other than ‘0000’ 0 = Software key (CRYKEY register) can be used as a key source when KEYSRC<3:0>=0000 Note 1: This bit’s state is mirrored by the PGMTST bit (CRYOTP<7>).  2013-2015 Microchip Technology Inc. DS30010038C-page 301

PIC24FJ128GA204 FAMILY TABLE 22-1: DES/3DES KEY SOURCE SELECTION Session Key Source (SESSKEY) Mode of OTP Array KEYMOD<1:0> KEYSRC<3:0> Operation Address 0 1 0000(1) CRYKEY<63:0> — 0001 DES Key #1 Key Config Error(2) <63:0> 0010 DES Key #2 <127:64> 0011 DES Key #3 <191:128> 0100 DES Key #4 <255:192> 64-Bit DES 00 0101 DES Key #5 <319:256> 0110 DES Key #6 <383:320> 0111 DES Key #7 <447:384> 1111 Reserved(2) — All Others Key Config Error(2) — 0000(1) CRYKEY<63:0> (1st/3rd) — CRYKEY<127:64> (2nd) 0001 DES Key #1 (1st/3rd) Key Config Error(2) <63:0> DES Key #2 (2nd) <127:64> 64-Bit, 2-Key 0010 DES Key #3 (1st/3rd) <191:128> 3DES DES Key #4 (2nd) <255:192> 01 (Standard 2-Key 0011 DES Key #5 (1st/3rd) <319:256> E-D-E/D-E-D) DES Key #6 (2nd) <383:320> 0100 DES Key #7 (1st/3rd) <447:384> DES Key #8 (2nd) <511:448> 1111 Reserved(2) — All Others Key Config Error(2) — (Reserved) 10 xxxx Key Config Error(2) — 0000(1) CRYKEY<63:0> (1st Iteration) — CRYKEY<127:64> (2nd Iteration) CRYKEY<191:128> (3rd Iteration) 0001 DES Key #1 (1st) Key Config Error(2) <63:0> DES Key #2 (2nd) <127:64> 64-Bit, 3-Key DES Key #3 (3rd) <191:128> 11 3DES 0010 DES Key #4 (1st) <255:192> DES Key #5 (2nd) <319:256> DES Key #6 (3rd) <383:320> 1111 Reserved(2) — All Others Key Config Error(2) — Note 1: This configuration is considered a Key Configuration Error (KEYFAIL bit is set) if SWKYDIS is also set. 2: The KEYFAIL bit (CRYSTAT<1>) is set when these configurations are selected and remains set until a valid configuration is selected.  2013-2015 Microchip Technology Inc. DS30010038C-page 302

PIC24FJ128GA204 FAMILY TABLE 22-2: AES KEY MODE/SOURCE SELECTION Key Source Mode of KEYMOD<1:0> KEYSRC<3:0> OTP Address Operation SKEYEN=0 SKEYEN=1 0000(1) CRYKEY<127:0> — 0001 AES Key #1 Key Config Error(2) <127:0> 0010 AES Key #2 <255:128> 128-Bit AES 00 0011 AES Key #3 <383:256> 0100 AES Key #4 <511:384> 1111 Reserved(2) — All Others Key Config Error(2) — 0000(1) CRYKEY<191:0> — 0001 AES Key #1 Key Config Error(2) <191:0> 192-Bit AES 01 0010 AES Key #2 <383:192> 1111 Reserved(2) — All Others Key Config Error(2) — 0000(1) CRYKEY<255:0> — 0001 AES Key #1 Key Config Error(2) <255:0> 256-Bit AES 10 0010 AES Key #2 <511:256> 1111 Reserved(2) — All Others Key Config Error(2) — (Reserved) 11 xxxx Key Config Error(2) — Note 1: This configuration is considered a Key Configuration Error (KEYFAIL bit is set) if SWKYDIS is also set. 2: The KEYFAIL bit (CRYSTAT<1>) is set when these configurations are selected and remains set until a valid configuration is selected.  2013-2015 Microchip Technology Inc. DS30010038C-page 303

PIC24FJ128GA204 FAMILY NOTES:  2013-2015 Microchip Technology Inc. DS30010038C-page 304

PIC24FJ128GA204 FAMILY 23.0 32-BIT PROGRAMMABLE The 32-bit programmable CRC generator provides a CYCLIC REDUNDANCY CHECK hardware implemented method of quickly generating checksums for various networking and security (CRC) GENERATOR applications. It offers the following features: Note: This data sheet summarizes the features • User-programmable CRC polynomial equation, of this group of PIC24F devices. It is not up to 32 bits intended to be a comprehensive reference • Programmable shift direction (little or big-endian) source. For more information, refer to • Independent data and polynomial lengths the “dsPIC33/PIC24 Family Reference • Configurable interrupt output Manual”, “32-Bit Programmable Cyclic • Data FIFO Redundancy Check (CRC)” (DS30009729). The information in this Figure23-1 displays a simplified block diagram of the data sheet supersedes the information in CRC generator. A simple version of the CRC shift the FRM. engine is displayed in Figure23-2. FIGURE 23-1: CRC MODULE BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO FIFO Empty (4x32, 8x16 or 16x8) Event CRCISEL CRC CRCWDATH CRCWDATL 1 Interrupt LENDIAN 0 Shift Buffer 1 CRC Shift Engine 0 Shift Complete Event Shifter Clock 2 * FCY FIGURE 23-2: CRC SHIFT ENGINE DETAIL CRC Shift Engine CRCWDATH CRCWDATL Read/Write Bus X0 X1 Xn(1) Shift Buffer Data BBiitt 00 Bit 1 Bit n(1) Note 1: n = PLEN<4:1> + 1.  2013-2015 Microchip Technology Inc. DS30010038C-page 305

PIC24FJ128GA204 FAMILY 23.1 User Interface 23.1.2 DATA INTERFACE The module incorporates a FIFO that works with a 23.1.1 POLYNOMIAL INTERFACE variable data width. Input data width can be configured The CRC module can be programmed for CRC to any value between 1 and 32 bits using the polynomials of up to the 32nd order, using up to 32 bits. DWIDTH<4:0> bits (CRCCON2<12:8>). When the data width is greater than 15, the FIFO is 4 words deep. Polynomial length, which reflects the highest exponent When the DWIDTHx bits are between 15 and 8, the in the equation, is selected by the PLEN<4:0> bits FIFO is 8 words deep. When the DWIDTHx bits are (CRCCON2<4:0>). less than 8, the FIFO is 16 words deep. The CRCXORL and CRCXORH registers control which The data for which the CRC is to be calculated must exponent terms are included in the equation. Setting a first be written into the FIFO. Even if the data width is particular bit includes that exponent term in the equa- less than 8, the smallest data element that can be tion. Functionally, this includes an XOR operation on written into the FIFO is 1 byte. For example, if the the corresponding bit in the CRC engine. Clearing the DWIDTHx bits are 5, then the size of the data is bit disables the XOR. DWIDTH<4:0> + 1 or 6. The data is written as a whole For example, consider two CRC polynomials, one is a byte; the two unused upper bits are ignored by the 16-bit and the other is a 32-bit equation. module. Once data is written into the MSb of the CRCDAT reg- EQUATION 23-1: 16-BIT, 32-BIT CRC isters (that is, the MSb as defined by the data width), POLYNOMIALS the value of the VWORD<4:0> bits (CRCCON1<12:8>) increments by one. For example, if the DWIDTHx bits X16 + X12 + X5 + 1 are 24, the VWORDx bits will increment when bit 7 of and CRCDATH is written. Therefore, CRCDATL must always be written to before CRCDATH. X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 The CRC engine starts shifting data when the CRCGO bit is set and the value of the VWORDx bits is greater than zero. To program these polynomials into the CRC generator, Each word is copied out of the FIFO into a buffer register, set the register bits, as shown in Table23-1. which decrements the VWORDx bits. The data is then Note that the appropriate positions are set to ‘1’ to indi- shifted out of the buffer. The CRC engine continues shift- cate that they are used in the equation (for example, ing at a rate of two bits per instruction cycle, until the X26 and X23). The ‘0’ bit required by the equation is VWORDx bits reach zero. This means that for a given always XORed; thus, X0 is a don’t care. For a poly- data width, it takes half that number of instructions for nomial of length 32, it is assumed that the 32nd bit will each word to complete the calculation. For example, it be used. Therefore, the X<31:1> bits do not have the takes 16 cycles to calculate the CRC for a single word of 32nd bit. 32-bit data. When the VWORDx bits reach the maximum value for the configured value of the DWIDTHx bits (4, 8 or 16), the CRCFUL bit becomes set. When the VWORDx bits reach zero, the CRCMPT bit becomes set. The FIFO is emptied and the VWORD<4:0> bits are set to ‘00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORDx bits is done. TABLE 23-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS Bit Values CRC Control Bits 16-Bit Polynomial 32-Bit Polynomial PLEN<4:0> 01111 11111 X<31:16> 0000 0000 0000 0001 0000 0100 1100 0001 X<15:0> 0001 0000 0010 000x 0001 1101 1011 011x DS30010038C-page 306  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 23.1.3 DATA SHIFT DIRECTION 4. Clear old results by writing 00h to CRCWDATL and CRCWDATH. The CRCWDAT registers can The LENDIAN bit (CRCCON1<3>) is used to control also be left unchanged to resume a previously the shift direction. By default, the CRC will shift data halted calculation. through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting 5. Set the CRCGO bit to start calculation. allows better integration with various communication 6. Write the remaining data into the FIFO as space schemes and removes the overhead of reversing the becomes available. bit order in software. Note that this only changes the 7. When the calculation completes, CRCGO is direction the data is shifted into the engine. The result automatically cleared. An interrupt will be of the CRC calculation will still be a normal CRC result, generated if CRCISEL = 1. not a reverse CRC result. 8. Read CRCWDATL and CRCWDATH for the result of the calculation. 23.1.4 INTERRUPT OPERATION There are eight registers used to control programmable The module generates an interrupt that is configurable CRC operation: by the user for either of two conditions. • CRCCON1 If CRCISEL is ‘0’, an interrupt is generated when the • CRCCON2 VWORD<4:0> bits make a transition from a value of ‘1’ to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated • CRCXORL after the CRC operation finishes and the module sets • CRCXORH the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ • CRCDATL will not generate an interrupt. Note that when an • CRCDATH interrupt occurs, the CRC calculation would not yet be • CRCWDATL complete. The module will still need (PLEN + 1)/2 clock • CRCWDATH cycles, after the interrupt is generated, until the CRC calculation is finished. The CRCCON1 and CRCCON2 registers (Register23-1 and Register23-2) control the operation of the module 23.1.5 TYPICAL OPERATION and configure the various settings. To use the module for a typical CRC calculation: The CRCXOR registers (Register23-3 and 1. Set the CRCEN bit to enable the module. Register23-4) select the polynomial terms to be used in the CRC equation. The CRCDAT and CRCWDAT 2. Configure the module for desired operation: registers are each register pairs that serve as buffers a) Program the desired polynomial using the for the double-word input data and CRC processed CRCXORL and CRCXORH registers, and the output, respectively. PLEN<4:0> bits. b) Configure the data width and shift direction using the DWIDTH<4:0> and LENDIAN bits. c) Select the desired Interrupt mode using the CRCISEL bit. 3. Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is set or no data is left.  2013-2015 Microchip Technology Inc. DS30010038C-page 307

PIC24FJ128GA204 FAMILY REGISTER 23-1: CRCCON1: CRC CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC CRCEN — CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0, HSC R-1, HSC R/W-0 R/W-0, HC R/W-0 U-0 U-0 U-0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — bit 7 bit 0 Legend: HC = Hardware Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH registers are reset; other SFRs are NOT reset bit 14 Unimplemented: Read as ‘0’ bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 VWORD<4:0>: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<4:0>  7 or 16 when PLEN<4:0> 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: CRC FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready bit 4 CRCGO: Start CRC bit 1 = Starts CRC serial shifter 0 = CRC serial shifter is turned off bit 3 LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the FIFO, starting with the LSb (little-endian) 0 = Data word is shifted into the FIFO, starting with the MSb (big-endian) bit 2-0 Unimplemented: Read as ‘0’ DS30010038C-page 308  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 23-2: CRCCON2: CRC CONTROL REGISTER 2 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 DWIDTH<4:0>: Data Word Width Configuration bits Configures the width of the data word (Data Word Width – 1). bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 PLEN<4:0>: Polynomial Length Configuration bits Configures the length of the polynomial (Polynomial Length – 1).  2013-2015 Microchip Technology Inc. DS30010038C-page 309

PIC24FJ128GA204 FAMILY REGISTER 23-3: CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 X<15:1>: XOR of Polynomial Term xn Enable bits bit 0 Unimplemented: Read as ‘0’ REGISTER 23-4: CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<31:24> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X<23:16> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-0 X<31:16>: XOR of Polynomial Term xn Enable bits DS30010038C-page 310  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 24.0 12-BIT A/D CONVERTER WITH 24.1 Basic Operation THRESHOLD DETECT To perform a standard A/D conversion: Note: This data sheet summarizes the features 1. Configure the module: of this group of PIC24F devices. It is not a) Configure port pins as analog inputs by intended to be a comprehensive refer- setting the appropriate bits in the ANSx ence source. For more information on registers (see Section11.2 “Configuring the 12-Bit A/D Converter, refer to the Analog Port Pins (ANSx)” for more “dsPIC33/PIC24 Family Reference information). Manual”, “12-Bit A/D Converter with b) Select the voltage reference source to Threshold Detect” (DS39739). match the expected range on analog inputs (AD1CON2<15:13>). The 12-bit A/D Converter has the following key c) Select the positive and negative multiplexer features: inputs for each channel (AD1CHS<15:0>). • Successive Approximation Register (SAR) d) Select the analog conversion clock to match Conversion the desired data rate with the processor • Conversion Speeds of up to 200ksps clock (AD1CON3<7:0>). • Up to 20 Analog Input Channels (internal and e) Select the appropriate sample/conversion external) sequence (AD1CON1<7:4> and • Selectable 10-Bit or 12-Bit (default) Conversion AD1CON3<12:8>). Resolution f) For Channel A scanning operations, select • Multiple Internal Reference Input Channels the positive channels to be included • External Voltage Reference Input Pins (AD1CSSH and AD1CSSL registers). • Unipolar Differential Sample-and-Hold (S/H) g) Select how conversion results are Amplifier presented in the buffer (AD1CON1<9:8> • Automated Threshold Scan and Compare and AD1CON5 register). Operation to Pre-Evaluate Conversion Results h) Select the interrupt rate (AD1CON2<5:2>). • Selectable Conversion Trigger Source i) Turn on A/D module (AD1CON1<15>). • Fixed Length (one word per channel), 2. Configure the A/D interrupt (if required): Configurable Conversion Result Buffer a) Clear the AD1IF bit (IFS0<13>). • Four Options for Results Alignment b) Enable the AD1IE interrupt (IEC0<13>). • Configurable Interrupt Generation c) Select the A/D interrupt priority (IPC3<6:4>). • Enhanced DMA Operations with Indirect Address 3. If the module is configured for manual sampling, Generation set the SAMP bit (AD1CON1<1>) to begin • Operation During CPU Sleep and Idle modes sampling. The 12-bit A/D Converter module is an enhanced version of the 10-bit module offered in earlier PIC24 devices. It is a Successive Approximation Register (SAR) Converter, enhanced with 12-bit resolution, a wide range of automatic sampling options, tighter inte- gration with other analog modules and a configurable results buffer. It also includes a unique Threshold Detect feature that allows the module itself to make simple decisions based on the conversion results, and enhanced opera- tion with the DMA Controller through Peripheral Indirect Addressing (PIA). A simplified block diagram for the module is shown in Figure24-1.  2013-2015 Microchip Technology Inc. DS30010038C-page 311

PIC24FJ128GA204 FAMILY FIGURE 24-1: 12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC24FJ128GA204 FAMILY) Internal Data Bus AVDD VR+ AVSS ect el 16 VREF+ V SR VR- VREF- Comparator VINH VR- VR+ VINL S/H DAC AN0 AN1 12-Bit SAR Conversion Logic AN2 VINH Data Formatting A X U Extended DMA Data (3) M AN9 VINL ADC1BUF0: ADC1BUFF(2) AN10(1) AN11(1) AD1CON1 AD1CON2 AN12(1) AD1CON3 AD1CON4 VBG VINH AD1CON5 B X AD1CHS VBG/2 MU AD1CHITL AD1CHITH VBAT/2 VINL AD1CSSL AVDD AD1CSSH AD1DMBUF AVSS CTMU Sample Control Control Logic Conversion Control 16 Input MUX Control DMA Data Bus Note 1: AN10 through AN12 are implemented on 44-pin devices only. 2: A/D result buffers are numbered in hexadecimal; ADC1BUF0 through ADC1BUFF represent Buffers 0 through 15. 3: AN8 is not implemented on PIC24FJ128GA204 devices. DS30010038C-page 312  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 24.2 Extended DMA Operations The IA is created by combining the base address within a channel buffer with three to five bits (depending on In addition to the standard features available on all 12-bit the buffer size) to identify the channel. The base A/D Converters, PIC24FJ128GA204 family devices address ranges from zero to seven bits wide, depend- implement a limited extension of DMA functionality. This ing on the buffer size. The address is right-padded with extension adds features that work with the device’s DMA a ‘0’ in order to maintain address alignment in the Data Controller to expand the A/D module’s data storage Space. The concatenated channel and base address abilities beyond the module’s built-in buffer. bits are then left-padded with zeros, as necessary, to The Extended DMA functionality is controlled by the complete the 11-bit IA. DMAEN bit (AD1CON1<11>); setting this bit enables The IA is configured to auto-increment during write the functionality. The DMABM bit (AD1CON1<12>) operations by using the SMPIx bits (AD1CON2<6:2>). configures how the DMA feature operates. As with PIA operations for any DMA-enabled module, 24.2.1 EXTENDED BUFFER MODE the base destination address in the DMADSTn register must be masked properly to accommodate the IA. Extended Buffer mode (DMABM = 1) is useful for Table24-1 shows how complete addresses are storing the results of channels. It can also be used to formed. Note that the address masking varies for each store the conversion results on any A/D channel in any buffer size option. Because of masking requirements, implemented address in data RAM. some address ranges may not be available for certain In Extended Buffer mode, all data from the A/D Buffer buffer sizes. Users should verify that the DMA base register, and channels above 26, is mapped into data address is compatible with the buffer size selected. RAM. Conversion data is written to a destination Figure24-2 shows how the parts of the address define specified by the DMA Controller, specifically by the the buffer locations in data memory. In this case, the DMADSTn register. This allows users to read the con- module “allocates” 256 bytes of data RAM (1000h to version results of channels above 26, which do not 1100h) for 32 buffers of four words each. However, this have their own memory-mapped A/D buffer locations, is not a hard allocation and nothing prevents these from data memory. locations from being used for other purposes. For When using Extended Buffer mode, always set the example, in the current case, if Analog Channels 1, 3 BUFREGEN bit to disable FIFO operation. In addition, and 8 are being sampled and converted, conversion disable the Split Buffer mode by clearing the BUFM bit. data will only be written to the channel buffers, starting at 1008h, 1018h and 1040h. The holes in the PIA buffer 24.2.2 PIA MODE space can be used for any other purpose. It is the When DMABM = 0, the A/D module is configured to func- user’s responsibility to keep track of buffer locations tion with the DMA Controller for Peripheral Indirect and prevent data overwrites. Addressing (PIA) mode operations. In this mode, the A/D module generates an 11-bit Indirect Address (IA). This is 24.3 A/D Operation with VBAT ORed with the destination address in the DMA Controller One of the A/D channels is connected to the VBAT pin to define where the A/D conversion data will be stored. to monitor the VBAT voltage. This allows monitoring the In PIA mode, the buffer space is created as a series of VBAT pin voltage (battery voltage) with no external con- contiguous smaller buffers, one per analog channel. nection. The voltage measured, using the A/D VBAT The size of the channel buffer determines how many monitor, is VBAT/2. The voltage can be calculated by analog channels can be accommodated. The size of reading A/D = ((VBAT/2)/VDD) * 1024 for 10-bit A/D and the buffer is selected by the DMABL<2:0> bits ((VBAT/2)/VDD) * 4096 for 12 bit A/D. (AD1CON4<2:0>). The size options range from a When using the VBAT A/D monitor: single word per buffer to 128 words. Each channel is allocated a buffer of this size, regardless of whether or • Connect the A/D channel to ground to discharge not the channel will actually have conversion data. the sample capacitor. • Because of the high-impedance of VBAT, select higher sampling time to get an accurate reading. Since the VBAT pin is connected to the A/D during sampling, to prolong the VBAT battery life, the recommendation is to only select the VBAT channel when needed.  2013-2015 Microchip Technology Inc. DS30010038C-page 313

PIC24FJ128GA204 FAMILY 24.4 Registers • AD1CHITL (Register24-8) • AD1CSSH and AD1CSSL (Register24-9 and The 12-bit A/D Converter is controlled through a total of Register24-10) 11 registers: • AD1CTMENL (Register24-11) • AD1CON1 through AD1CON5 (Register24-1 • AD1DMBUF (not shown) – The 16-bit conversion through Register24-5) buffer for Extended Buffer mode • AD1CHS (Register24-6) TABLE 24-1: INDIRECT ADDRESS GENERATION IN PIA MODE Available Buffer Size per Generated Offset Allowable DMADSTn DMABL<2:0> Input Channel (words) Address (lower 11 bits) Addresses Channels 000 1 000 00cc ccc0 32 xxxx xxxx xx00 0000 001 2 000 0ccc ccn0 32 xxxx xxxx x000 0000 010 4 000 cccc cnn0 32 xxxx xxxx 0000 0000 011 8 00c cccc nnn0 32 xxxx xxx0 0000 0000 100 16 0cc cccn nnn0 32 xxxx xx00 0000 0000 101 32 ccc ccnn nnn0 32 xxxx x000 0000 0000 110 64 ccc cnnn nnn0 16 xxxx x000 0000 0000 111 128 ccc nnnn nnn0 8 xxxx x000 0000 0000 Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits), x = User-definable range of DMADSTn for base address, 0 = Masked bits of DMADSTn for IA. DS30010038C-page 314  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 24-2: EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE (4-WORD BUFFERS PER CHANNEL) A/D Module DMABL<2:0> = 010 (16-Word Buffer Size) Data RAM (PIA Mode) BBA Channel Ch 0 Buffer (4 Words) 1000h ccccc (0-31) 000 cccc cnn0 (IA) Ch 1 Buffer (4 Words) 1008h Ch 2 Buffer (4 Words) 1010h Ch 3 Buffer (4 Words) 1018h nn (0-3) Destination (Buffer Base Address) Range Ch 7 Buffer (4 Words) 1038h 1000h (DMA Base Address) Ch 8 Buffer (4 Words) 1040h Ch 29 Buffer (4 Words) 10F0h Ch 29 Buffer (4 Words) 10F8h DMADSTn Ch 31 Buffer (4 Words) 1100h DMA Channel Buffer Address Channel Address Address Mask DMA Base Address Ch 0, Word 0 1000h 0001 0000 0000 0000 Ch 0, Word 1 1002h 0001 0000 0000 0010 Ch 0, Word 2 1004h 0001 0000 0000 0100 Ch 0, Word 3 1006h 0001 0000 0000 0110 Ch 1, Word 0 1008h 0001 0000 0000 1000 Ch 1, Word 1 100Ah 0001 0000 0000 1010 Ch 1, Word 2 100Ch 0001 0000 0000 1100 Ch 1, Word 3 100Eh 0001 0000 0000 1110  2013-2015 Microchip Technology Inc. DS30010038C-page 315

PIC24FJ128GA204 FAMILY REGISTER 24-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL DMABM(1) DMAEN MODE12 FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC SSRC3 SSRC2 SSRC1 SSRC0 — ASAM SAMP DONE bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: A/D Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 DMABM: Extended DMA Buffer Mode Select bit(1) 1 = Extended Buffer mode: Buffer address is defined by the DMADSTn register 0 = PIA mode: Buffer addresses are defined by the DMA Controller and AD1CON4<2:0> bit 11 DMAEN: Extended DMA/Buffer Enable bit 1 = Extended DMA and buffer features are enabled 0 = Extended features are disabled bit 10 MODE12: 12-Bit Operation Mode bit 1 = 12-bit A/D operation 0 = 10-bit A/D operation bit 9-8 FORM<1:0>: Data Output Format bits (see formats following) 11 = Fractional result, signed, left justified 10 = Absolute fractional result, unsigned, left justified 01 = Decimal result, signed, right justified 00 = Absolute decimal result, unsigned, right justified bit 7-4 SSRC<3:0>: Sample Clock Source Select bits 1xxx = Unimplemented, do not use 0111 = Internal counter ends sampling and starts conversion (auto-convert); do not use in Auto-Scan mode 0110 = Unimplemented 0101 = TMR1 0100 = CTMU 0011 = TMR5 0010 = TMR3 0001 = INT0 0000 = The SAMP bit must be cleared by software to start conversion bit 3 Unimplemented: Read as ‘0’ bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion; SAMP bit is auto-set 0 = Sampling begins when SAMP bit is manually set Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN=1). DS30010038C-page 316  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 24-1: AD1CON1: A/D CONTROL REGISTER 1 (CONTINUED) bit 1 SAMP: A/D Sample Enable bit 1 = A/D Sample-and-Hold amplifiers are sampling 0 = A/D Sample-and-Hold amplifiers are holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion cycle has completed 0 = A/D conversion cycle has not started or is in progress Note 1: This bit is only available when Extended DMA/Buffer features are available (DMAEN=1).  2013-2015 Microchip Technology Inc. DS30010038C-page 317

PIC24FJ128GA204 FAMILY REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PVCFG1 PVCFG0 NVCFG0 OFFCAL BUFREGEN CSCNA — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS(1) SMPI4 SMPI3 SMPI2 SMPI1 SMPI0 BUFM(1) ALTS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 PVCFG<1:0>: A/D Converter Positive Voltage Reference Configuration bits 1x = Unimplemented, do not use 01 = External VREF+ 00 = AVDD bit 13 NVCFG0: A/D Converter Negative Voltage Reference Configuration bit 1 = External VREF- 0 = AVSS bit 12 OFFCAL: Offset Calibration Mode Select bit 1 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to AVSS 0 = Inverting and non-inverting inputs of channel Sample-and-Hold are connected to normal inputs bit 11 BUFREGEN: A/D Buffer Register Enable bit 1 = Conversion result is loaded into the buffer location determined by the converted channel 0 = A/D result buffer is treated as a FIFO bit 10 CSCNA: Scan Input Selections for CH0+ During Sample A bit 1 = Scans inputs 0 = Does not scan inputs bit 9-8 Unimplemented: Read as ‘0’ bit 7 BUFS: Buffer Fill Status bit(1) 1 = A/D is currently filling ADC1BUF8-ADC1BUFF, user should access data in ADC1BUF0-ADC1BUF7 0 = A/D is currently filling ADC1BUF0-ADC1BUF7, user should access data in ADC1BUF8-ADC1BUFF Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN=0). In addition, BUFS is only used when BUFM=1. DS30010038C-page 318  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED) bit 6-2 SMPI<4:0>: Interrupt Sample/DMA Increment Rate Select bits When DMAEN = 1: 11111 = Increments the DMA address after completion of the 32nd sample/conversion operation 11110 = Increments the DMA address after completion of the 31st sample/conversion operation • • • 00001 = Increments the DMA address after completion of the 2nd sample/conversion operation 00000 = Increments the DMA address after completion of each sample/conversion operation When DMAEN = 0: 11111 = Interrupts at the completion of the conversion for each 32nd sample 11110 = Interrupts at the completion of the conversion for each 31st sample • • • 00001 = Interrupts at the completion of the conversion for every other sample 00000 = Interrupts at the completion of the conversion for each sample bit 1 BUFM: Buffer Fill Mode Select bit(1) 1 = Starts buffer filling at ADC1BUF0 on first interrupt and ADC1BUF8 on next interrupt 0 = Always starts filling buffer at ADC1BUF0 bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses channel input selects for Sample A on first sample and Sample B on next sample 0 = Always uses channel input selects for Sample A Note 1: These bits are only applicable when the buffer is used in FIFO mode (BUFREGEN=0). In addition, BUFS is only used when BUFM=1.  2013-2015 Microchip Technology Inc. DS30010038C-page 319

PIC24FJ128GA204 FAMILY REGISTER 24-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC EXTSAM PUMPEN SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADRC: A/D Conversion Clock Source bit 1 = RC clock 0 = Clock derived from system clock bit 14 EXTSAM: Extended Sampling Time bit 1 = A/D is still sampling after SAMP=0 0 = A/D is finished sampling bit 13 PUMPEN: Charge Pump Enable bit 1 = Charge pump for switches is enabled 0 = Charge pump for switches is disabled bit 12-8 SAMC<4:0>: Auto-Sample Time Select bits 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD bit 7-0 ADCS<7:0>: A/D Conversion Clock Select bits 11111111 = 256 • TCY = TAD • • • 00000001 = 2•TCY=TAD 00000000 = TCY=TAD DS30010038C-page 320  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 24-4: AD1CON4: A/D CONTROL REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — DMABL<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 DMABL<2:0>: DMA Buffer Size Select bits(1) 111 = Allocates 128 words of buffer to each analog input 110 = Allocates 64 words of buffer to each analog input 101 = Allocates 32 words of buffer to each analog input 100 = Allocates 16 words of buffer to each analog input 011 = Allocates 8 words of buffer to each analog input 010 = Allocates 4 words of buffer to each analog input 001 = Allocates 2 words of buffer to each analog input 000 = Allocates 1 word of buffer to each analog input Note 1: The DMABL<2:0> bits are only used when AD1CON1<11> = 1 and AD1CON1<12> = 0; otherwise, their value is ignored.  2013-2015 Microchip Technology Inc. DS30010038C-page 321

PIC24FJ128GA204 FAMILY REGISTER 24-5: AD1CON5: A/D CONTROL REGISTER 5 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 ASEN LPEN CTMREQ BGREQ — — ASINT1 ASINT0 bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — WM1 WM0 CM1 CM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ASEN: Auto-Scan Enable bit 1 = Auto-scan is enabled 0 = Auto-scan is disabled bit 14 LPEN: Low-Power Enable bit 1 = Low power is enabled after scan 0 = Full power is enabled after scan bit 13 CTMREQ: CTMU Request bit 1 = CTMU is enabled when the A/D is enabled and active 0 = CTMU is not enabled by the A/D bit 12 BGREQ: Band Gap Request bit 1 = Band gap is enabled when the A/D is enabled and active 0 = Band gap is not enabled by the A/D bit 11-10 Unimplemented: Read as ‘0’ bit 9-8 ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits 11 = Interrupt after Threshold Detect sequence has completed and valid compare has occurred 10 = Interrupt after valid compare has occurred 01 = Interrupt after Threshold Detect sequence has completed 00 = No interrupt bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 WM<1:0>: Write Mode bits 11 = Reserved 10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid match occurs, as defined by the CMx and ASINTx bits) 01 = Convert and save (conversion results are saved to locations as determined by the register bits when a match occurs, as defined by the CMx bits) 00 = Legacy operation (conversion data is saved to a location determined by the buffer register bits) bit 1-0 CM<1:0>: Compare Mode bits 11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined by the corresponding buffer pair) 10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the corresponding buffer pair) 01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding buffer register) 00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer register) DS30010038C-page 322  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 24-6: AD1CHS: A/D SAMPLE SELECT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB2 CH0NB1 CH0NB0 CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA2 CH0NA1 CH0NA0 CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 CH0NB<2:0>: Sample B Channel 0 Negative Input Select bits 1xx = Unimplemented 011 = Unimplemented 010 = AN1 001 = Unimplemented 000 = VREF-/AVSS bit 12-8 CH0SB<4:0>: Sample B Channel 0 Positive Input Select bits 11111 = VBAT/2(1) 11110 = AVDD(1) 11101 = AVSS(1) 11100 = Band Gap Voltage (VBG) reference(1) 11011 = VBG/2(1) 01110 = CTMU 01101 = CTMU temperature sensor input (does not require AD1CTMENL<12> to be set) 01100 = AN12(2) 01011 = AN11(2) 01010 = AN10(2) 01001 = AN9 01000 = AN8 00111 = AN7 00110 = AN6 00101 = AN5 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 7-5 CH0NA<2:0>: Sample A Channel 0 Negative Input Select bits Same definitions as for CHONB<2:0>. bit 4-0 CH0SA<4:0>: Sample A Channel 0 Positive Input Select bits Same definitions as for CHOSB<4:0>. Note 1: These input channels do not have corresponding memory-mapped result buffers. 2: These channels are unimplemented in 28-pin devices.  2013-2015 Microchip Technology Inc. DS30010038C-page 323

PIC24FJ128GA204 FAMILY REGISTER 24-7: ANCFG: A/D BAND GAP REFERENCE CONFIGURATION U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — VBG2EN VBGEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-2 Unimplemented: Read as ‘0’ bit 1 VBG2EN: A/D Input VBG/2 Enable bit 1 = Band Gap Voltage, divided by two reference (VBG/2), is enabled 0 = Band Gap Voltage, divided by two reference (VBG/2), is disabled bit 0 VBGEN: A/D Input VBG Enable bit 1 = Band Gap Voltage (VBG) reference is enabled 0 = Band Gap Voltage (VBG) reference is disabled DS30010038C-page 324  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 24-8: AD1CHITL: A/D SCAN COMPARE HIT REGISTER (LOW WORD) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CHH<12:9>(1) CHH8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-9 CHH<12:9>: A/D Compare Hit bits(1) If CM<1:0>=11: 1 = A/D Result Buffer n has been written with data or a match has occurred 0 = A/D Result Buffer n has not been written with data For All Other Values of CM<1:0>: 1 = A match has occurred on A/D Result Channel n 0 = No match has occurred on A/D Result Channel n bit 8-0 CHH<8:0>: A/D Compare Hit bits If CM<1:0>=11: 1 = A/D Result Buffer n has been written with data or a match has occurred 0 = A/D Result Buffer n has not been written with data For All Other Values of CM<1:0>: 1 = A match has occurred on A/D Result Channel n 0 = No match has occurred on A/D Result Channel n Note 1: The CHH<12:10> bits are unimplemented in 28-pin devices, read as ‘0’.  2013-2015 Microchip Technology Inc. DS30010038C-page 325

PIC24FJ128GA204 FAMILY REGISTER 24-9: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH WORD) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CSS<31:27> — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 CSS<31:27>: A/D Input Scan Selection bits 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan bit 10-0 Unimplemented: Read as ‘0’ REGISTER 24-10: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW WORD) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CSS<14:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSS<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-0 CSS<14:0>: A/D Input Scan Selection bits(1) 1 = Includes corresponding channel for input scan 0 = Skips channel for input scan Note 1: The CSS<12:10> bits are unimplemented in 28-pin devices, read as ‘0’. DS30010038C-page 326  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 24-11: AD1CTMENL: CTMU ENABLE REGISTER (LOW WORD) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CTMEN<12:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMEN<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12-0 CTMEN<12:0>: CTMU Enable During Conversion bits(1) 1 = CTMU is enabled and connected to the selected channel during conversion 0 = CTMU is not connected to this channel Note 1: The CTMEN<12:10> bits are unimplemented in 28-pin devices, read as ‘0’.  2013-2015 Microchip Technology Inc. DS30010038C-page 327

PIC24FJ128GA204 FAMILY FIGURE 24-3: 10-BIT A/D CONVERTER ANALOG INPUT MODEL RIC  250 Sampling Switch Rs ANx RSS RSS  3 k CHOLD VA CPIN ILEAKAGE = 4.4 pF 500 nA VSS Legend: CPIN = Input Capacitance(1) VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to Various Junctions RIC = Interconnect Resistance RSS = Sampling Switch Resistance CHOLD = Sample/Hold Capacitance (from DAC) Note 1: The CPIN value depends on the device package and is not tested. The effect of CPIN is negligible if Rs  5 k. EQUATION 24-1: A/D CONVERSION CLOCK PERIOD TAD = TCY (ADCS + 1) TAD ADCS = – 1 TCY Note: Based on TCY = 2/FOSC; Doze mode and PLL are disabled. DS30010038C-page 328  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 24-4: 12-BIT A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 1111 1111 1111 (4095) 1111 1111 1110 (4094) 0010 0000 0011 (2051) 0010 0000 0010 (2050) 0010 0000 0001 (2049) 0010 0000 0000 (2048) 0001 1111 1111 (2047) 0001 1111 1110 (2046) 0001 1111 1101 (2045) 0000 0000 0001 (1) 0000 0000 0000 (0) Voltage Level 0 VR-V– VR+ R-V+R- 4096 2048 * (V– V)R+ R-4096 4095 * (V– V)R+ R-4096VR+ (V – V)INHINL + + VR- VR-  2013-2015 Microchip Technology Inc. DS30010038C-page 329

PIC24FJ128GA204 FAMILY FIGURE 24-5: 10-BIT A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) Voltage Level 0 VR-V– VR+ R-V+R- 1024 512 * (V– V)R+ R-1024 1023 * (V– V)R+ R-1024 VR+ (V – V)INHINL V+R- +R- V DS30010038C-page 330  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 25.0 TRIPLE COMPARATOR voltage reference input from one of the internal band MODULE gap references or the comparator voltage reference generator (VBG, VBG/2 and CVREF). Note: This data sheet summarizes the features of The comparator outputs may be directly connected to this group of PIC24F devices. It is not the CxOUT pins. When the respective COE bit equals intended to be a comprehensive reference ‘1’, the I/O pad logic makes the unsynchronized output source. For more information, refer to of the comparator available on the pin. the “dsPIC33/PIC24 Family Reference A simplified block diagram of the module in shown in Manual”, “Scalable Comparator Module” Figure25-1. Diagrams of the possible individual (DS39734). The information in this data comparator configurations are shown in Figure25-2. sheet supersedes the information in the FRM. Each comparator has its own control register, CMxCON (Register25-1), for enabling and configuring The triple comparator module provides three dual input its operation. The output and event status of all three comparators. The inputs to the comparator can be comparators is provided in the CMSTAT register configured to use any one of five external analog inputs (Register25-2). (CxINA, CxINB, CxINC, CxIND and VREF+) and a FIGURE 25-1: TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL<1:0> CCH<1:0> Trigger/Interrupt CEVT Input Logic CPOL COE Select VIN- Logic C1 00 VIN+ CxINB C1OUT CxINC 01 COUT Pin 10 CxIND 00 11 EVPOL<1:0> VBG Trigger/Interrupt CEVT 01 VBG/2 Logic CPOL COE 11 VIN- CVREF+ C2 VIN+ C2OUT Pin CVREFM<1:0>(1) COUT EVPOL<1:0> 0 CxINA + 1 1 Trigger/Interrupt CEVT CVREF+ Logic CPOL COE 0 CVREF VIN- C3 CVREFP(1) VIN+ C3OUT Pin COUT CREF Note 1: Refer to the CVRCON register (Register26-1) for bit details.  2013-2015 Microchip Technology Inc. DS30010038C-page 331

PIC24FJ128GA204 FAMILY FIGURE 25-2: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 0 Comparator Off CEN=0, CREF=x, CCH<1:0>=xx COE VIN- Cx VIN+ Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare Comparator CxINC > CxINA Compare CEN=1, CCH<1:0>=00, CVREFM<1:0> = xx CEN=1, CCH<1:0> =01, CVREFM<1:0> = xx COE COE VIN- VIN- CxINB CxINC Cx Cx VIN+ VIN+ CxINA CxINA CxOUT CxOUT Pin Pin Comparator CxIND > CxINA Compare Comparator VBG > CxINA Compare CEN=1, CCH<1:0> =10, CVREFM<1:0> = xx CEN=1, CCH<1:0> =11, CVREFM<1:0> = 00 COE COE CxIND VIN- VBG VIN- Cx Cx VIN+ VIN+ CxINA CxOUT CxINA CxOUT Pin Pin Comparator VBG > CxINA Compare Comparator CxIND > CxINA Compare CEN=1, CCH<1:0> =11, CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11, CVREFM<1:0> = 11 COE COE VBG/2 VIN- VREF+ VIN- CxINA VIN+ Cx CxOUT CxINA VIN+ Cx CxOUT Pin Pin DS30010038C-page 332  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 25-3: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN=1, CCH<1:0> =00, CVREFM<1 :0> = xx CEN=1, CCH<1:0> =01, CVREFM<1:0> = xx COE COE VIN- VIN- CxINB CxINC Cx Cx VIN+ VIN+ CVREF CxOUT CVREF CxOUT Pin Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0> =10, CVREFM<1:0> = xx CEN=1, CCH<1:0> =11, CVREFM<1:0> = 00 COE COE CxIND VIN- VBG VIN- Cx Cx VIN+ VIN+ CVREF CxOUT CVREF CxOUT Pin Pin Comparator VBG > CVREF Compare Comparator CxIND > CVREF Compare CEN=1, CCH<1:0> =11, CVREFM<1:0> = 01 CEN=1, CCH<1:0> =11, CVREFM<1:0> = 11 COE VBG/2 VIN- COE VREF+ VIN- Cx Cx VIN+ CVREF VIN+ CxOUT CVREF CxOUT Pin Pin FIGURE 25-4: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1 Comparator CxINB > CVREF Compare Comparator CxINC > CVREF Compare CEN=1, CCH<1:0> =00, CVREFM<1:0> = xx CEN=1, CCH<1:0>=01, CVREFM<1:0> = xx COE COE VIN- VIN- CxINB CxINC Cx Cx VIN+ VIN+ VREF+ CxOUT VREF+ CxOUT Pin Pin Comparator CxIND > CVREF Compare Comparator VBG > CVREF Compare CEN=1, CCH<1:0>=10, CVREFM<1:0> = xx CEN=1, CCH<1:0>=11, CVREFM<1:0> = 00 COE COE VIN- VIN- CxIND VBG Cx Cx VIN+ VIN+ VREF+ CxOUT VREF+ CxOUT Pin Pin Comparator VBG > CVREF Compare CEN=1, CCH<1:0>=11, CVREFM<1:0> = 01 COE VIN- VBG/2 Cx VIN+ VREF+ CxOUT Pin  2013-2015 Microchip Technology Inc. DS30010038C-page 333

PIC24FJ128GA204 FAMILY R EGISTER 25-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0, HS R-0, HSC CON COE CPOL — — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1(1) EVPOL0(1) — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as ‘0’ bit 9 CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL<1:0> has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN- 0 = VIN+ < VIN- When CPOL = 1: 1 = VIN+ < VIN- 0 = VIN+ > VIN- bit 7-6 EVPOL<1:0>: Trigger/Event/Interrupt Polarity Select bits(1) 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on the high-to-low transition of the comparator output 01 = Trigger/event/interrupt is generated on the low-to-high transition of the comparator output 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ Note 1: If the EVPOL<1:0> bits are set to a value other than ‘00’, the first interrupt generated will occur on any transition of COUT. Subsequent interrupts will occur based on the EVPOLx bits setting. DS30010038C-page 334  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 25-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM<1:0> bits in the CVRCON register 10 = Inverting input of the comparator connects to the CxIND pin 01 = Inverting input of the comparator connects to the CxINC pin 00 = Inverting input of the comparator connects to the CxINB pin Note 1: If the EVPOL<1:0> bits are set to a value other than ‘00’, the first interrupt generated will occur on any transition of COUT. Subsequent interrupts will occur based on the EVPOLx bits setting. REGISTER 25-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC CMIDL — — — — C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC — — — — — C3OUT C2OUT C1OUT bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinues operation of all comparators when device enters Idle mode 0 = Continues operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as ‘0’ bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON<9>). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). bit 7-3 Unimplemented: Read as ‘0’ bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON<8>). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>).  2013-2015 Microchip Technology Inc. DS30010038C-page 335

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 336  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 26.0 COMPARATOR VOLTAGE 26.1 Configuring the Comparator REFERENCE Voltage Reference The comparator voltage reference module is controlled Note: This data sheet summarizes the features of through the CVRCON register (Register26-1). The this group of PIC24F devices. It is not comparator voltage reference provides a range of output intended to be a comprehensive reference voltages with 32 distinct levels. The comparator refer- source. For more information, refer to the “dsPIC33/PIC24 Family Reference ence supply voltage can come from either VDD and VSS Manual”, “Comparator Voltage Reference or the external CVREF+ and CVREF- pins. The voltage source is selected by the CVRSS bit (CVRCON<5>). Module” (DS39709). The information in this data sheet supersedes the information in The settling time of the comparator voltage reference the FRM. must be considered when changing the CVREF output. FIGURE 26-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVREF+ AVDD CVRSS = 0 CVR<4:0> R CVREN R R R X U M 32 Steps 1 CVREF o- 2-t CVROE R 3 R CVREF R Pin CVRSS = 1 CVREF- CVRSS = 0 AVSS  2013-2015 Microchip Technology Inc. DS30010038C-page 337

PIC24FJ128GA204 FAMILY REGISTER 26-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CVREFP CVREFM1 CVREFM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRSS CVR4 CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CVREFP: Comparator Voltage Reference Select bit (valid only when CREF is ‘1’) 1 = VREF+ is used as a reference voltage to the comparators 0 = The CVR (4-bit DAC) within this module provides the reference voltage to the comparators bit 9-8 CVREFM<1:0>: Comparator Voltage Band Gap Reference Source Select bits (valid only when CCH<1:0> = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Band gap voltage, divided by two, is provided as an input to the comparators 10 = Reserved 11 = VREF+ pin is provided as an input to the comparators bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin bit 5 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF- 0 = Comparator reference source, CVRSRC = AVDD – AVSS bit 4-0 CVR<4:0>: Comparator VREF Value Selection bits CVREF = (CVR<4:0>/32) • (CVRSRC) DS30010038C-page 338  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 27.0 CHARGE TIME 27.1 Measuring Capacitance MEASUREMENT UNIT (CTMU) The CTMU module measures capacitance by generating an output pulse, with a width equal to the Note: This data sheet summarizes the features of time between edge events, on two separate input this group of PIC24F devices. It is not channels. The pulse edge events to both input intended to be a comprehensive reference channels can be selected from four sources: two source. For more information on the internal peripheral modules (OC1 and Timer1) and up Charge Time Measurement Unit, refer to to 13 external pins (CTED1 through CTED13). This the “dsPIC33/PIC24 Family Reference pulse is used with the module’s precision current Manual”, “Charge Time Measurement source to calculate capacitance according to the Unit (CTMU) with Threshold Detect” relationship: (DS39743). The Charge Time Measurement Unit (CTMU) is a EQUATION 27-1: flexible analog module that provides charge dV measurement, accurate differential time measurement I = C • dT between pulse sources and asynchronous pulse generation. Its key features include: For capacitance measurements, the A/D Converter • Thirteen external edge input trigger sources samples an external Capacitor (CAPP) on one of its • Polarity control for each edge source input channels after the CTMU output’s pulse. A • Control of edge sequence Precision Resistor (RPR) provides current source calibration on a second A/D channel. After the pulse • Control of response to edge levels or edge ends, the converter determines the voltage on the transitions capacitor. The actual calculation of capacitance is • Time measurement resolution of onenanosecond performed in software by the application. • Accurate current source suitable for capacitive Figure27-1 illustrates the external connections used measurement for capacitance measurements and how the CTMU and Together with other on-chip analog modules, the CTMU A/D modules are related in this application. This can be used to precisely measure time, measure example also shows the edge events coming from capacitance, measure relative changes in capacitance Timer1, but other configurations using external edge or generate output pulses that are independent of the sources are possible. A detailed discussion on system clock. The CTMU module is ideal for interfacing measuring capacitance and time with the CTMU with capacitive-based touch sensors. module is provided in the “dsPIC33/PIC24 Family Ref- The CTMU is controlled through three registers: erence Manual”, “Charge Time Measurement Unit CTMUCON1, CTMUCON2 and CTMUICON. (CTMU) with Threshold Detect” (DS39743). CTMUCON1 enables the module and controls the mode of operation of the CTMU, as well as controlling edge sequencing. CTMUCON2 controls edge source selection and edge source polarity selection. The CTMUICON register selects the current range of current source and trims the current.  2013-2015 Microchip Technology Inc. DS30010038C-page 339

PIC24FJ128GA204 FAMILY FIGURE 27-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP RPR DS30010038C-page 340  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 27.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON1<12>), the Time measurements on the pulse width can be similarly internal current source is connected to the B input of performed using the A/D module’s Internal Capacitor Comparator 2. A Capacitor (CDELAY) is connected to (CAD) and a precision resistor for current calibration. the Comparator 2 pin, C2INB, and the Comparator Figure27-2 displays the external connections used for Voltage Reference, CVREF, is connected to C2INA. time measurements, and how the CTMU and A/D CVREF is then configured for a specific trip point. The modules are related in this application. This example module begins to charge CDELAY when an edge event also shows both edge events coming from the external is detected. When CDELAY charges above the CVREF CTEDx pins, but other configurations using internal trip point, a pulse is output on CTPLS. The length of the edge sources are possible. pulse delay is determined by the value of CDELAY and the CVREF trip point. 27.3 Pulse Generation and Delay Figure27-3 illustrates the external connections for The CTMU module can also generate an output pulse pulse generation, as well as the relationship of the with edges that are not synchronous with the device’s different analog modules required. While CTED1 is system clock. More specifically, it can generate a pulse shown as the input pulse source, other options are with a programmable delay from an edge event input to available. A detailed discussion on pulse generation the module. with the CTMU module is provided in the “dsPIC33/ PIC24 Family Reference Manual”. FIGURE 27-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDx EDG1 Current Source CTEDx EDG2 Output Pulse A/D Converter ANx CAD RPR FIGURE 27-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTMU CTEDx EDG1 CTPLS Current Source Comparator C2INB – C2 CDELAY CVREF  2013-2015 Microchip Technology Inc. DS30010038C-page 341

PIC24FJ128GA204 FAMILY REGISTER 27-1: CTMUCON1: CTMU CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: CTMU Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: CTMU Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7-0 Unimplemented: Read as ‘0’ DS30010038C-page 342  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 27-2: CTMUCON2: CTMU CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 EDG1MOD: Edge 1 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 14 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response bit 13-10 EDG1SEL<3:0>: Edge 1 Source Select bits 1111 = Edge 1 source is Comparator 3 output 1110 = Edge 1 source is Comparator 2 output 1101 = Edge 1 source is Comparator 1 output 1100 = Edge 1 source is IC3 1011 = Edge 1 source is IC2 1010 = Edge 1 source is IC1 1001 = Edge 1 source is CTED8 1000 = Edge 1 source is CTED7(1) 0111 = Edge 1 source is CTED6 0110 = Edge 1 source is CTED5 0101 = Edge 1 source is CTED4 0100 = Edge 1 source is CTED3 0011 = Edge 1 source is CTED1 0010 = Edge 1 source is CTED2 0001 = Edge 1 source is OC1 0000 = Edge 1 source is Timer1 bit 9 EDG2STAT: Edge 2 Status bit Indicates the status of Edge 2 and can be written to control current source. 1 = Edge 2 has occurred 0 = Edge 2 has not occurred bit 8 EDG1STAT: Edge 1 Status bit Indicates the status of Edge 1 and can be written to control current source. 1 = Edge 1 has occurred 0 = Edge 1 has not occurred bit 7 EDG2MOD: Edge 2 Edge-Sensitive Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 6 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response Note 1: Edge source, CTED7, is not available in 28-pin packages.  2013-2015 Microchip Technology Inc. DS30010038C-page 343

PIC24FJ128GA204 FAMILY REGISTER 27-2: CTMUCON2: CTMU CONTROL REGISTER 2 (CONTINUED) bit 5-2 EDG2SEL<3:0>: Edge 2 Source Select bits 1111 = Edge 2 source is Comparator 3 output 1110 = Edge 2 source is Comparator 2 output 1101 = Edge 2 source is Comparator 1 output 1100 = Unimplemented; do not use 1011 = Edge 2 source is IC3 1010 = Edge 2 source is IC2 1001 = Edge 2 source is IC1 1000 = Edge 2 source is CTED13 0111 = Edge 2 source is CTED12 0110 = Edge 2 source is CTED11 0101 = Edge 2 source is CTED10 0100 = Edge 2 source is CTED9 0011 = Edge 2 source is CTED1 0010 = Edge 2 source is CTED2 0001 = Edge 2 source is OC1 0000 = Edge 2 source is Timer1 bit 1-0 Unimplemented: Read as ‘0’ Note 1: Edge source, CTED7, is not available in 28-pin packages. DS30010038C-page 344  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 27-3: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 • • • 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG<1:0> 111111 = Minimum negative change from nominal current • • • 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG<1:0>: Current Source Range Select bits 11 = 100 × Base Current 10 = 10 × Base Current 01 = Base current level (0.55 A nominal) 00 = 1000 x Base Current bit 7-0 Unimplemented: Read as ‘0’  2013-2015 Microchip Technology Inc. DS30010038C-page 345

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 346  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 28.0 HIGH/LOW-VOLTAGE DETECT The High/Low-Voltage Detect (HLVD) module is a (HLVD) programmable circuit that allows the user to specify both the device voltage trip point and the direction of Note: This data sheet summarizes the features of change. this group of PIC24F devices. It is not An interrupt flag is set if the device experiences an intended to be a comprehensive reference excursion past the trip point in the direction of change. source. For more information on the If the interrupt is enabled, the program execution will High/Low-Voltage Detect, refer to the branch to the interrupt vector address and the software “dsPIC33/PIC24 Family Reference can then respond to the interrupt. Manual”, “High-Level Integration with The HLVD Control register (see Register28-1) Programmable High/Low-Voltage Detect completely controls the operation of the HLVD module. (HLVD)” (DS39725). This allows the circuitry to be “turned off” by the user FIGURE 28-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM Externally Generated Trip Point VDD VDD HLVDIN HLVDL<3:0> HLVDEN VDIR X U Set M HLVDIF 1 o- 6-t 1 Internal Voltage Reference 1.20V Typical HLVDEN  2013-2015 Microchip Technology Inc. DS30010038C-page 347

PIC24FJ128GA204 FAMILY REGISTER 28-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — LSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD is enabled 0 = HLVD is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 LSIDL: High/Low-Voltage Detect Stop in Idle Mode bit 1 = Discontinues module operation when device enters Idle mode 0 = Continues module operation in Idle mode bit 12-8 Unimplemented: Read as ‘0’ bit 7 VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL<3:0>) 0 = Event occurs when voltage equals or falls below trip point (HLVDL<3:0>) bit 6 BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Internal reference voltage is stable; the High-Voltage Detect logic generates the interrupt flag at the specified voltage range 0 = Internal reference voltage is unstable; the High-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the HLVD interrupt should not be enabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 HLVDL<3:0>: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip Point 1(1) 1101 = Trip Point 2(1) 1100 = Trip Point 3(1) • • • 0100 = Trip Point 11(1) 00xx = Unused Note 1: For the actual trip point, see Section32.0 “Electrical Characteristics”. DS30010038C-page 348  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 29.0 SPECIAL FEATURES 29.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ128GA204 Note: This data sheet summarizes the features FAMILY DEVICES of this group of PIC24F devices. It is not In PIC24FJ128GA204 family devices, the Configuration intended to be a comprehensive refer- bytes are implemented as volatile memory. This means ence source. For more information, refer that configuration data must be programmed each time to the following sections of the “dsPIC33/ the device is powered up. Configuration data is stored PIC24 Family Reference Manual”. The in the four words at the top of the on-chip program information in this data sheet supersedes memory space, known as the Flash Configuration the information in the FRMs. Words. Their specific locations are shown in Table29-1. • “Watchdog Timer (WDT)” These are packed representations of the actual device (DS39697) Configuration bits, whose actual locations are distributed • “High-Level Device Integration” among several locations in configuration space. The (DS39719) configuration data is automatically loaded from the Flash • “Programming and Diagnostics” Configuration Words to the proper Configuration (DS39716) registers during device Resets. PIC24FJ128GA204 family devices include several Note: Configuration data is reloaded on all types features intended to maximize application flexibility and of device Resets. reliability, and minimize cost through elimination of When creating applications for these devices, users external components. These are: should always specifically allocate the location of the • Flexible Configuration Flash Configuration Word for configuration data. This is • Watchdog Timer (WDT) to make certain that program code is not stored in this • Code Protection address when the code is compiled. • JTAG Boundary Scan Interface The upper byte of all Flash Configuration Words in • In-Circuit Serial Programming™ (ICSP™) program memory should always be ‘0000 0000’. This • In-Circuit Emulation (ICE) makes them appear to be NOP instructions in the remote event that their locations are ever executed by 29.1 Configuration Bits accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘0’s to these The Configuration bits can be programmed (read as ‘0’), locations has no effect on device operation. or left unprogrammed (read as ‘1’), to select various Note: Performing a page erase operation on the device configurations. These bits are mapped starting at last page of program memory clears the program memory location, F80000h. A detailed explana- Flash Configuration Words, enabling code tion of the various bit functions is provided in protection as a result. Therefore, users Register29-1 through Register29-6. should avoid performing page erase Note that address, F80000h, is beyond the user program operations on the last page of program memory space. In fact, it belongs to the configuration memory. memory space (800000h-FFFFFFh), which can only be accessed using Table Reads and Table Writes. TABLE 29-1: FLASH CONFIGURATION WORD LOCATIONS FOR THE PIC24FJ128GA204 FAMILY Configuration Word Addresses Device 1 2 3 4 PIC24FJ64GA2XX ABFEh ABFCh ABFAh ABF8h PIC24FJ128GA2XX 157FEh 157FCh 157FAh 157F8h  2013-2015 Microchip Technology Inc. DS30010038C-page 349

PIC24FJ128GA204 FAMILY REGISTER 29-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 — JTAGEN GCP GWRP DEBUG LPCFG ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN1 FWDTEN0 WINDIS FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 Reserved: The value is unknown; program as ‘0’ bit 14 JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are not allowed bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 LPCFG: Low-Voltage/Retention Regulator Configuration bit 1 = Low-voltage/retention regulator is always disabled 0 = Low-power, low-voltage/retention regulator is enabled and controlled in firmware by the RETEN bit bit 9-8 ICS<1:0>: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7-6 FWDTEN<1:0>: Watchdog Timer Configuration bits 11 = WDT is always enabled; the SWDTEN bit has no effect 10 = WDT is enabled and controlled in firmware by the SWDTEN bit 01 = WDT is enabled only in Run mode and disabled in Sleep modes; SWDTEN bit is disabled 00 = WDT is disabled; the SWDTEN bit is disabled bit 5 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled (FWDTEN<1:0> must not be ‘00’) bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 DS30010038C-page 350  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 29-1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) bit 3-0 WDTPS<3:0>: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1  2013-2015 Microchip Technology Inc. DS30010038C-page 351

PIC24FJ128GA204 FAMILY REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 r-0 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 R/PO-1 IESO — WDTCMX ALTCMPI — FNOSC2 FNOSC1 FNOSC0 bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 FCKSM1 FCKSM0 OSCIOFCN WDTCLK1 WDTCLK0 — POSCMD1 POSCMD0 bit 7 bit 0 Legend: r = Reserved bit PO = Program Once bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled bit 14 Reserved: Read as ‘0’ bit 13 WDTCMX: WDT Clock Multiplex Control bit 1 = WDT clock source is determined by the WDTCLK<1:0> Configuration bits 0 = WDT always uses LPRC as its clock source bit 12 ALTCMPI: Alternate Comparator Input bit 1 = C1INC is on RB13, C2INC is on RB9 and C3INC is on RA0 0 = C1INC, C2INC and C3INC are on RB9 bit 11 Reserved: Configure as ‘1‘ bit 10-8 FNOSC<2:0>: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 7-6 FCKSM<1:0>: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 5 OSCIOFCN: OSCO Pin Configuration bit If POSCMD<1:0> = 11 or 00: 1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RA3 functions as port I/O (RA3) If POSCMD<1:0> = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RA3. Note 1: The 31 kHz FRC source is used when a Windowed WDT mode is selected and the LPRC is not being used as the system clock. The LPRC is used when the device is in Sleep mode and in all other cases. DS30010038C-page 352  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 29-2: CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 4-3 WDTCLK<1:0>: WDT Clock Source Select bits When WDTCMX = 1: 11 = LPRC 10 = Either the 31kHz FRC source or LPRC, depending on device configuration(1) 01 = SOSC input 00 = System clock when active, LPRC while in Sleep mode When WDTCMX = 0: LPRC is always the WDT clock source. bit 2 Reserved: Configure as ‘1’ bit 1-0 POSCMD<1:0>: Primary Oscillator Configuration bits 11 = Primary Oscillator mode is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected Note 1: The 31 kHz FRC source is used when a Windowed WDT mode is selected and the LPRC is not being used as the system clock. The LPRC is used when the device is in Sleep mode and in all other cases.  2013-2015 Microchip Technology Inc. DS30010038C-page 353

PIC24FJ128GA204 FAMILY REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 WPEND WPCFG WPDIS BOREN PLLSS(4) WDTWIN1 WDTWIN0 SOSCSEL bit 15 bit 8 r-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 — WPFP6(3) WPFP5 WPFP4 WPFP3 WPFP2 WPFP1 WPFP0 bit 7 bit 0 Legend: PO = Program Once bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 WPEND: Segment Write Protection End Page Select bit 1 = Protected program memory segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by WPFP<6:0> 0 = Protected program memory segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by WPFP<6:0> bit 14 WPCFG: Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(1) 0 = Last page and Flash Configuration Words are write-protected provided WPDIS = 0 bit 13 WPDIS: Segment Write Protection Disable bit 1 = Segmented program memory write protection is disabled 0 = Segmented program memory write protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits bit 12 BOREN: Brown-out Reset Enable bit 1 = BOR is enabled (all modes except Deep Sleep) 0 = BOR is disabled bit 11 PLLSS: PLL Secondary Selection Configuration bit(4) 1 = PLL is fed by the Primary Oscillator 0 = PLL is fed by the on-chip Fast RC (FRC) Oscillator bit 10-9 WDTWIN<1:0>: Watchdog Timer Window Width Select bits 11 = 25% 10 = 37.5% 01 = 50% 00 = 75% bit 8 SOSCSEL: SOSC Selection bit 1 = SOSC circuit is selected 0 = Digital (SCLKI) mode(2) Note 1: Regardless of WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Word page, the Configuration Word page is protected. 2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table11-1). 3: For the 64K devices (PIC24FJ64GA2XX), maintain WPFP6 as ‘0’. 4: This Configuration bit only takes effect when PLL is not being used. DS30010038C-page 354  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 29-3: CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) bit 7 Reserved: Always maintain as ‘1’ bit 6-0 WPFP<6:0>: Write-Protected Code Segment Boundary Page bits(3) Designates the 512 instruction words page boundary of the protected Code Segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. Note 1: Regardless of WPCFG status, if WPEND = 1 or if the WPFP<6:0> bits correspond to the Configuration Word page, the Configuration Word page is protected. 2: Ensure that the SCLKI pin is made a digital input while using this configuration (see Table11-1). 3: For the 64K devices (PIC24FJ64GA2XX), maintain WPFP6 as ‘0’. 4: This Configuration bit only takes effect when PLL is not being used.  2013-2015 Microchip Technology Inc. DS30010038C-page 355

PIC24FJ128GA204 FAMILY REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 IOL1WAY I2C1SEL PLLDIV3 PLLDIV2 PLLDIV1 PLLDIV0 — DSSWEN bit 15 bit 8 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 DSWDTEN DSBOREN DSWDTOSC DSWDTPS4 DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: PO = Program Once bit r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 Unimplemented: Read as ‘1’ bit 15 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>) can be set once, provided the unlock sequence has been completed; once set, the Peripheral Pin Select registers cannot be written to a second time 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed bit 14 I2C1SEL: Alternate I2C1 Location Select bit 1 = I2C1 uses the SCL1 and SDA1 pins 0 = I2C1 uses the ASCL1 and ASDA1 pins bit 13-10 PLLDIV<3:0>: PLL Prescaler Select bits 1111 = PLL is disabled 1110 = 8x PLL is selected 1101 = 6x PLL is selected 1100 = 4x PLL is selected 1011 • • = Reserved, do not use • 0000 bit 9 Reserved: Always maintain as ‘1’ bit 8 DSSWEN: Deep Sleep Software Control Select bit 1 = Deep Sleep operation is enabled and controlled by the DSEN bit 0 = Deep Sleep operation is disabled bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = Deep Sleep WDT is enabled 0 = Deep Sleep WDT is disabled bit 6 DSBOREN: Deep Sleep Brown-out Reset Enable bit 1 = BOR is enabled in Deep Sleep mode 0 = BOR is disabled in Deep Sleep mode (remains active in other Sleep modes) bit 5 DSWDTOSC: Deep Sleep Watchdog Timer Clock Select bit 1 = Clock source is LPRC 0 = Clock source is SOSC DS30010038C-page 356  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY REGISTER 29-4: CW4: FLASH CONFIGURATION WORD 4 (CONTINUED) bit 4-0 DSWDTPS<4:0>: Deep Sleep Watchdog Timer Postscaler Select bits 11111 = 1:68,719,476,736 (25.7 days) 11110 = 1:34,359,738,368(12.8 days) 11101 = 1:17,179,869,184 (6.4 days) 11100 = 1:8,589,934592 (77.0 hours) 11011 = 1:4,294,967,296 (38.5 hours) 11010 = 1:2,147,483,648 (19.2 hours) 11001 = 1:1,073,741,824 (9.6 hours) 11000 = 1:536,870,912 (4.8 hours) 10111 = 1:268,435,456 (2.4 hours) 10110 = 1:134,217,728 (72.2 minutes) 10101 = 1:67,108,864 (36.1 minutes) 10100 = 1:33,554,432 (18.0 minutes) 10011 = 1:16,777,216 (9.0 minutes) 10010 = 1:8,388,608 (4.5 minutes) 10001 = 1:4,194,304 (135.3s) 10000 = 1:2,097,152 (67.7s) 01111 = 1:1,048,576 (33.825s) 01110 = 1:524,288 (16.912s) 01101 = 1:262,114 (8.456s) 01100 = 1:131,072 (4.228s) 01011 = 1:65,536 (2.114s) 01010 = 1:32,768 (1.057s) 01001 = 1:16,384 (528.5 ms) 01000 = 1:8,192 (264.3 ms) 00111 = 1:4,096 (132.1 ms) 00110 = 1:2,048 (66.1 ms) 00101 = 1:1,024 (33 ms) 00100 = 1:512 (16.5 ms) 00011 = 1:256 (8.3 ms) 00010 = 1:128 (4.1 ms) 00001 = 1:64 (2.1 ms) 00000 = 1:32 (1 ms)  2013-2015 Microchip Technology Inc. DS30010038C-page 357

PIC24FJ128GA204 FAMILY REGISTER 29-5: DEVID: DEVICE ID REGISTER U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-16 Unimplemented: Read as ‘1’ bit 15-8 FAMID<7:0>: Device Family Identifier bits 0100 1100 = PIC24FJ128GA204 family bit 7-0 DEV<7:0>: Individual Device Identifier bits 0101 0000 = PIC24FJ64GA202 0101 0010 = PIC24FJ128GA202 0101 0001 = PIC24FJ64GA204 0101 0011 = PIC24FJ128GA204 REGISTER 29-6: DEVREV: DEVICE REVISION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R R R R — — — — REV<3:0> bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit bit 23-4 Unimplemented: Read as ‘0’ bit 3-0 REV<3:0>: Device Revision Identifier bits DS30010038C-page 358  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 29.2 On-Chip Voltage Regulator 29.2.1 ON-CHIP REGULATOR AND POR All PIC24FJ128GA204 family devices power their core The voltage regulator requires a small amount of time digital logic at a nominal 1.8V. This may create an issue to transition from a disabled or standby state into for designs that are required to operate at a higher normal operating mode. During this time, designated typical voltage, such as 3.3V. To simplify system as TVREG, code execution is disabled. TVREG is applied design, all devices in the PIC24FJ128GA204 family every time the device resumes operation after any incorporate an on-chip regulator that allows the device power-down, including Sleep mode. TVREG is deter- mined by the status of the VREGS bit (RCON<8>). to run its core logic from VDD. Refer to Section32.0 “Electrical Characteristics” for This regulator is always enabled. It provides a constant more information on TVREG. voltage (1.8V nominal) to the digital core logic, from a VDD of about 2.1V, all the way up to the device’s Note: For more information, see Section32.0 VDDMAX. It does not have the capability to boost VDD “Electrical Characteristics”. The infor- levels. In order to prevent “brown-out” conditions when mation in this data sheet supersedes the the voltage drops too low for the regulator, the Brown- information in the “dsPIC33/PIC24 Family out Reset occurs. Then, the regulator output follows Reference Manual”. VDD with a typical voltage drop of 300mV. 29.2.2 VOLTAGE REGULATOR STANDBY A low-ESR capacitor (such as ceramic) must be MODE connected to the VCAP pin (Figure29-1). This helps to maintain the stability of the regulator. The recommended The on-chip regulator always consumes a small incre- value for the Filter Capacitor (CEFC) is provided in mental amount of current over IDD/IPD, including when Section32.1 “DC Characteristics”. the device is in Sleep mode, even though the core digital logic does not require power. To provide addi- FIGURE 29-1: CONNECTIONS FOR THE tional savings in applications where power resources ON-CHIP REGULATOR are critical, the regulator can be made to enter Standby mode on its own, whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit 3.3V(1) (RCON<8>). Clearing the VREGS bit enables the PIC24FXXXGA2XX Standby mode. When waking up from Standby mode, the regulator needs to wait for TVREG to expire before VDD wake-up. VCAP 29.2.3 LOW-VOLTAGE/RETENTION CEFC REGULATOR (10F typ) VSS When a power-saving mode, such as Sleep is used, PIC24FJ128GA204 family devices may use a separate low-power, low-voltage/retention regulator to power Note: This is a typical operating voltage. Refer to Section32.0 “Electrical Characteristics” for critical circuits. This regulator, which operates at 1.2V the full operating ranges of VDD. nominal, maintains power to data RAM and the RTCC while all other core digital logic is powered down. It operates only in Sleep and VBAT modes. The low-voltage/retention regulator is described in more detail in Section10.1.3 “Low-Voltage/Retention Regulator”.  2013-2015 Microchip Technology Inc. DS30010038C-page 359

PIC24FJ128GA204 FAMILY 29.3 Watchdog Timer (WDT) The WDT Flag bit, WDTO (RCON<4>), is not auto- matically cleared following a WDT time-out. To detect For PIC24FJ128GA204 family devices, the WDT is subsequent WDT events, the flag must be cleared in driven by the LPRC Oscillator. When the WDT is software. enabled, the clock source is also enabled. Note: The CLRWDT and PWRSAV instructions The nominal WDT clock source from LPRC is 31 kHz. clear the prescaler and postscaler counts This feeds a prescaler that can be configured for either when executed. 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. 29.3.1 WINDOWED OPERATION With a 31 kHz input, the prescaler yields a nominal WDT Time-out (TWDT) period of 1 ms in 5-bit mode or The Watchdog Timer has an optional Fixed Window 4ms in 7-bit mode. mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the window A variable postscaler divides down the WDT prescaler width, 25%, 37.5%, 50% or 75% of the programmed output and allows for a wide range of time-out periods. WDT period controlled by WDTWIN<1:0> Configura- The postscaler is controlled by the WDTPS<3:0> Con- tion bits (CW3<10:9>). A CLRWDT instruction executed figuration bits (CW1<3:0>), which allows the selection before that window causes a WDT Reset, similar to a of a total of 16 settings, from 1:1 to 1:32,768. Using the WDT time-out. prescaler and postscaler time-out periods, ranges from 1ms to 131 seconds can be achieved. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1<5>) to ‘0’. The WDT, prescaler and postscaler are reset: • On any device Reset 29.3.2 CONTROL REGISTER • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit The WDT is enabled or disabled by the FWDTEN<1:0> after changing the NOSCx bits) or by hardware Configuration bits. When the Configuration bits, (i.e., Fail-Safe Clock Monitor) FWDTEN<1:0> = 11, the WDT is always enabled. • When a PWRSAV instruction is executed The WDT can be optionally controlled in software when (i.e., Sleep or Idle mode is entered) the Configuration bits, FWDTEN<1:0> = 10. When • When the device exits Sleep or Idle mode to FWDTEN<1:0> = 00, the Watchdog Timer is always resume normal operation disabled. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN • By a CLRWDT instruction during normal execution control bit is cleared on any device Reset. The software If the WDT is enabled, it will continue to run during WDT option allows the user to enable the WDT for Sleep or Idle modes. When the WDT time-out occurs, critical Code Segments and disable the WDT during the device will wake the device and code execution will non-critical segments for maximum power savings. continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE (RCON<3:2>) bits will need to be cleared in software after the device wakes up. FIGURE 29-2: WDT BLOCK DIAGRAM SWDTEN LPRC Control FWDTEN<1:0> Wake from Sleep FWPSA WDTPS<3:0> Prescaler WDT Postscaler WDT Overflow LPRC Input (5-bit/7-bit) Counter 1:1 to 1:32.768 Reset 31 kHz 1 ms/4 ms All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS30010038C-page 360  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 29.4 Program Verification and Code Segment (CS) protection provides an added level Code Protection of protection to a designated area of program memory by disabling the NVM safety interlock whenever a write PIC24FJ128GA204 family devices provide two compli- or erase address falls within a specified range. It does mentary methods to protect application code from not override General Segment protection controlled by overwrites and erasures. These also help to protect the the GCP bit or GWRP bit. For example, if the GCP and device from inadvertent configuration changes during GWRP bits are enabled, enabling segmented code run time. protection for the bottom half of program memory does not undo General Segment protection for the top half. 29.4.1 GENERAL SEGMENT PROTECTION The size and type of protection for the segmented code For all devices in the PIC24FJ128GA204 family, the range are configured by the WPFPx, WPEND, WPCFG on-chip program memory space is treated as a single and WPDIS bits in Configuration Word 3. Code Seg- block, known as the General Segment (GS). Code pro- ment protection is enabled by programming the WPDIS tection for this block is controlled by one Configuration bit (= 0). The WPFPx bits specify the size of the seg- bit, GCP. This bit inhibits external reads and writes to ment to be protected by specifying the 512-word code the program memory space. It has no direct effect in page that is the start or end of the protected segment. normal execution mode. The specified region is inclusive, therefore, this page Write protection is controlled by the GWRP bit in the will also be protected. Configuration Word. When GWRP is programmed to The WPEND bit determines if the protected segment ‘0’, internal write and erase operations to program uses the top or bottom of the program space as a memory are blocked. boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary 29.4.2 CODE SEGMENT PROTECTION of the protected segment. Leaving WPEND unpro- In addition to global General Segment protection, a grammed (= 1) protects the specified page through the separate subrange of the program memory space can last page of implemented program memory, including be individually protected against writes and erases. the Configuration Word locations. This area can be used for many purposes where a A separate bit, WPCFG, is used to protect the last page separate block of write and erase-protected code is of program space, including the Flash Configuration needed, such as bootloader applications. Unlike Words. Programming WPCFG (= 0) protects the last common boot block implementations, the specially page, in addition to the pages selected by the WPEND protected segment in the PIC24FJ128GA204 family and WPFP<6:0> bits setting. This is useful in circum- devices can be located by the user anywhere in the stances where write protection is needed for both the program space and configured in a wide range of sizes. Code Segment in the bottom of the memory and the Flash Configuration Words. The various options for segment code protection are shown in Table29-2. TABLE 29-2: CODE SEGMENT PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Erase/Write Protection of Code Segment WPDIS WPEND WPCFG 1 x x No additional protection is enabled; all program memory protection is configured by GCP and GWRP. 0 1 x Addresses from the first address of the code page are defined by WPFP<6:0> through the end of implemented program memory (inclusive); erase/write-protected, including Flash Configuration Words. 0 0 1 Address, 000000h, through the last address of the code page, are defined by WPFP<6:0> (inclusive); erase/write-protected. 0 0 0 Address, 000000h, through the last address of code page, are defined by WPFP<6:0> (inclusive); erase/write-protected and the last page, including Flash Configuration Words, are erase/write-protected.  2013-2015 Microchip Technology Inc. DS30010038C-page 361

PIC24FJ128GA204 FAMILY 29.4.3 CONFIGURATION REGISTER 29.6 In-Circuit Serial Programming PROTECTION PIC24FJ128GA204 family microcontrollers can be The Configuration registers are protected against serially programmed while in the end application circuit. inadvertent or unwanted changes or reads in two ways. This is simply done with two lines for clock (PGECx) The primary protection method is the same as that of and data (PGEDx), and three other lines for power the RP registers – shadow registers contain a compli- (VDD), ground (VSS) and MCLR. This allows customers mentary value which is constantly compared with the to manufacture boards with unprogrammed devices actual value. and then program the microcontroller just before To safeguard against unpredictable events, Configura- shipping the product. This also allows the most recent tion bit changes resulting from individual cell-level firmware or a custom firmware to be programmed. disruptions (such as ESD events) will cause a parity error and trigger a device Reset. 29.7 In-Circuit Debugger The data for the Configuration registers is derived from When MPLAB® ICD 3 is selected as a debugger, the in- the Flash Configuration Words in program memory. circuit debugging functionality is enabled. This function When the GCP bit is set, the source data for device allows simple debugging functions when used with configuration is also protected as a consequence. Even MPLAB IDE. Debugging functionality is controlled if General Segment protection is not enabled, the through the PGECx (Emulation/Debug Clock) and device configuration can be protected by using the PGEDx (Emulation/Debug Data) pins. appropriate Code Segment protection setting. To use the in-circuit debugger function of the device, the design must implement ICSP connections to 29.5 JTAG Interface MCLR, VDD, VSS and the PGECx/PGEDx pin pair, des- PIC24FJ128GA204 family devices implement a JTAG ignated by the ICSx Configuration bits. In addition, interface, which supports boundary scan device testing when the feature is enabled, some of the resources are and programming. not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. DS30010038C-page 362  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 30.0 DEVELOPMENT SUPPORT 30.1 MPLAB X Integrated Development Environment Software The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user of software and hardware development tools: interface for Microchip and third-party software, and • Integrated Development Environment hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, - MPLAB® X IDE Software MPLAB X IDE is an entirely new IDE with a host of free • Compilers/Assemblers/Linkers software components and plug-ins for high- - MPLAB XC Compiler performance application development and debugging. - MPASMTM Assembler Moving between tools and upgrading from software - MPLINKTM Object Linker/ simulators to hardware debugging and programming MPLIBTM Object Librarian tools is simple with the seamless user interface. - MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs, Various Device Families a configurable watch window and a feature-rich editor • Simulators that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new - MPLAB X SIM Software Simulator users. With the ability to support multiple tools on • Emulators multiple projects with simultaneous debugging, MPLAB - MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced • In-Circuit Debuggers/Programmers users. - MPLAB ICD 3 Feature-Rich Editor: - PICkit™ 3 • Color syntax highlighting • Device Programmers • Smart code completion makes suggestions and - MPLAB PM3 Device Programmer provides hints as you type • Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined Evaluation Kits and Starter Kits rules • Third-party development tools • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • Multiple projects • Multiple tools • Multiple configurations • Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker  2013-2015 Microchip Technology Inc. DS30010038C-page 363

PIC24FJ128GA204 FAMILY 30.2 MPLAB XC Compilers 30.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16 and 32-bit MCU The MPLINK Object Linker combines relocatable and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using ease of use. MPLAB XC Compilers run on Windows, directives from a linker script. Linux or MAC OS X. The MPLIB Object Librarian manages the creation and For easy source level debugging, the compilers provide modification of library files of precompiled code. When debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only IDE. the modules that contain that routine will be linked in The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be devices and commands, with no time or memory used efficiently in many different applications. restrictions, and offer sufficient code optimization for The object linker/library features include: most applications. • Efficient linking of single libraries instead of many MPLAB XC Compilers include an assembler, linker and smaller files utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping files that can then be archived or linked with other related modules together relocatable object files and archives to create an exe- • Flexible creation of libraries with easy module cutable file. MPLAB XC Compiler uses the assembler listing, replacement, deletion and extraction to produce its object file. Notable features of the assembler include: 30.5 MPLAB Assembler, Linker and • Support for the entire device instruction set Librarian for Various Device • Support for fixed-point and floating-point data Families • Command-line interface • Rich directive set MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, • Flexible macro language PIC32 and dsPIC DSC devices. MPLAB XC Compiler • MPLAB X IDE compatibility uses the assembler to produce its object file. The assembler generates relocatable object files that can 30.3 MPASM Assembler then be archived or linked with other relocatable object files and archives to create an executable file. Notable The MPASM Assembler is a full-featured, universal features of the assembler include: macro assembler for PIC10/12/16/18 MCUs. • Support for the entire device instruction set The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data files, MAP files to detail memory usage and symbol • Command-line interface reference, absolute LST files that contain source lines • Rich directive set and generated machine code, and COFF files for • Flexible macro language debugging. • MPLAB X IDE compatibility The MPASM Assembler features include: • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS30010038C-page 364  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 30.6 MPLAB X SIM Software Simulator 30.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful, logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB buffer and logic analyzer display extend the power of IDE. the simulator to record and track program execution, The MPLAB ICD 3 In-Circuit Debugger probe is actions on I/O, most peripherals and internal registers. connected to the design engineer’s PC using a high- The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target symbolic debugging using the MPLAB XCCompilers, with a connector compatible with the MPLAB ICD 2 or and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers. debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software 30.9 PICkit 3 In-Circuit Debugger/ development tool. Programmer 30.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program- Emulator System ming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full- Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the programs all 8, 16 and 32-bit MCU, and DSC devices target via a Microchip debug (RJ-11) connector (com- with the easy-to-use, powerful graphical user interface of patible with MPLAB ICD 3 and MPLAB REAL ICE). The the MPLAB X IDE. connector uses two device I/O pins and the Reset line The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™). connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) 30.10 MPLAB PM3 Device Programmer or with the new high-speed, noise tolerant, Low- The MPLAB PM3 Device Programmer is a universal, Voltage Differential Signal (LVDS) interconnection CE compliant device programmer with programmable (CAT5). voltage verification at VDDMIN and VDDMAX for The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod- significant advantages over competitive emulators ular, detachable socket assembly to support various including full-speed emulation, run-time variable package types. The ICSP cable assembly is included watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program three meters) interconnection cables. PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications.  2013-2015 Microchip Technology Inc. DS30010038C-page 365

PIC24FJ128GA204 FAMILY 30.11 Demonstration/Development 30.12 Third-Party Development Tools Boards, Evaluation Kits and Microchip also offers a great collection of tools from Starter Kits third-party vendors. These tools are carefully selected to offer good value and unique functionality. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers DSCs allows quick application development on fully from companies, such as SoftLog and CCS functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel areas for adding custom circuitry and provide applica- and Trace Systems tion firmware and source code for examination and • Protocol Analyzers from companies, such as modification. Saleae and Total Phase The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies, EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstra- tion software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS30010038C-page 366  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 31.0 INSTRUCTION SET SUMMARY The literal instructions that involve data movement may use some of the following operands: Note: This chapter is a brief summary of the • A literal value to be loaded into a W register or file PIC24F Instruction Set Architecture (ISA) register (specified by the value of ‘k’) and is not intended to be a comprehensive • The W register or file register where the literal reference source. value is to be loaded (specified by ‘Wb’ or ‘f’) The PIC24F instruction set adds many enhancements However, literal instructions that involve arithmetic or to the previous PIC® MCU instruction sets, while main- logical operations use some of the following operands: taining an easy migration from previous PIC MCU • The first source operand, which is a register, ‘Wb’, instruction sets. Most instructions are a single program without any address modifier memory word. Only three instructions require two program memory locations. • The second source operand, which is a literal value Each single-word instruction is a 24-bit word divided • The destination of the result (only if not the same into an 8-bit opcode, which specifies the instruction as the first source operand), which is typically a type and one or more operands, which further specify register, ‘Wd’, with or without an address modifier the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic The control instructions may use some of the following categories: operands: • Word or byte-oriented operations • A program memory address • Bit-oriented operations • The mode of the Table Read and Table Write • Literal operations instructions • Control operations All instructions are a single word, except for certain double-word instructions, which were made double- Table31-1 shows the general symbols used in word instructions so that all the required information is describing the instructions. The PIC24F instruction set available in these 48 bits. In the second word, the summary in Table31-2 lists all the instructions, along 8MSbs are ‘0’s. If this second word is executed as an with the status flags affected by each instruction. instruction (by itself), it will execute as a NOP. Most word or byte-oriented W register instructions Most single-word instructions are executed in a single (including barrel shift instructions) have three instruction cycle, unless a conditional test is true or the operands: Program Counter is changed as a result of the instruc- • The first source operand, which is typically a tion. In these cases, the execution takes two instruction register, ‘Wb’, without any address modifier cycles, with the additional instruction cycle(s) executed • The second source operand, which is typically a as a NOP. Notable exceptions are the BRA (unconditional/ register, ‘Ws’, with or without an address modifier computed branch), indirect CALL/GOTO, all Table Reads • The destination of the result, which is typically a and Table Writes, and RETURN/RETFIE instructions, register, ‘Wd’, with or without an address modifier which are single-word instructions but take two or three cycles. However, word or byte-oriented file register instructions have two operands: Certain instructions that involve skipping over the sub- sequent instruction require either two or three cycles if • The file register specified by the value, ‘f’ the skip is performed, depending on whether the • The destination, which could either be the file instruction being skipped is a single-word or two-word register, ‘f’, or the W0 register, which is denoted instruction. Moreover, double-word moves require two as ‘WREG’ cycles. The double-word instructions execute in two Most bit-oriented instructions (including simple rotate/ instruction cycles. shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2013-2015 Microchip Technology Inc. DS30010038C-page 367

PIC24FJ128GA204 FAMILY TABLE 31-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” <text] Means “the location addressed by text” { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit Bit Selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register {Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd]} Wdo Destination W register  {Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb]} Wm,Wn Dividend, Divisor Working register pair (direct addressing) Wn One of 16 Working registers {W0..W15} Wnd One of 16 destination Working registers {W0..W15} Wns One of 16 source Working registers {W0..W15} WREG W0 (Working register used in file register instructions) Ws Source W register {Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws]} Wso Source W register {Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb]} DS30010038C-page 368  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected ADD ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND AND f f = f.AND. WREG 1 1 N, Z AND f,WREG WREG = f.AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3)  2013-2015 Microchip Technology Inc. DS30010038C-page 369

PIC24FJ128GA204 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected BTSS BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 Z BTSTS BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None CLRWDT CLRWDT Clear Watchdog Timer 1 1 WDTO, Sleep COM COM f f = f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb – Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow 1 1 C, DC, N, OV, Z (Wb – Ws – C) CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if  1 1 None (2 or 3) DAW DAW.B Wn Wn = Decimal Adjust Wn 1 1 C DEC DEC f f = f –1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f –1 1 1 C, DC, N, OV, Z DEC Ws,Wd Wd = Ws – 1 1 1 C, DC, N, OV, Z DEC2 DEC2 f f = f – 2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f – 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws – 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DS30010038C-page 370  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected GOTO GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC INC f f = f + 1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z INC2 INC2 f f = f + 2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 C, DC, N, OV, Z IOR IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG NEG f f = f + 1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP NOP No Operation 1 1 None NOPR No Operation 1 1 None POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None POP.S Pop Shadow Registers 1 1 All PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None PUSH.S Push Shadow Registers 1 1 None  2013-2015 Microchip Technology Inc. DS30010038C-page 371

PIC24FJ128GA204 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW #lit10,Wn Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 C, N, Z RLNC RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 N, Z RRC RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB SUB f f = f – WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f – WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn – lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb – Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb – lit5 1 1 C, DC, N, OV, Z SUBB SUBB f f = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB f,WREG WREG = f – WREG – (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn – lit10 – (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb – Ws – (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb – lit5 – (C) 1 1 C, DC, N, OV, Z SUBR SUBR f f = WREG – f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG – f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws – Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 – Wb 1 1 C, DC, N, OV, Z SUBBR SUBBR f f = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG – f – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws – Wb – (C) 1 1 C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 – Wb – (C) 1 1 C, DC, N, OV, Z SWAP SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None DS30010038C-page 372  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 31-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly # of # of Status Flags Assembly Syntax Description Mnemonic Words Cycles Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 None TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N  2013-2015 Microchip Technology Inc. DS30010038C-page 373

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 374  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 32.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ128GA204 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ128GA204 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature.............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any general purpose digital or analog pin (not 5.5V tolerant) with respect to VSS.......-0.3V to (VDD + 0.3V) Voltage on any general purpose digital or analog pin (5.5V tolerant, including MCLR) with respect to VSS: When VDD = 0V:..........................................................................................................................-0.3V to +4.0V When VDD  2.0V:.......................................................................................................................-0.3V to +6.0V Voltage on AVDD with respect to VSS ...................................................(VDD – 0.3V) to (lesser of: 4.0V or (VDD + 0.3V)) Voltage on AVSS with respect to VSS ........................................................................................................-0.3V to +0.3V Voltage on VBAT with respect to VSS......................................................................................................... -0.3V to +4.0V Maximum current out of VSS pin...........................................................................................................................300 mA Maximum current into VDD pin (Note1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin....................................................................................................25 mA Maximum current sunk by all ports.......................................................................................................................200 mA Maximum current sourced by all ports (Note1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table32-1). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2013-2015 Microchip Technology Inc. DS30010038C-page 375

PIC24FJ128GA204 FAMILY 32.1 DC Characteristics FIGURE 32-1: PIC24FJ128GA204 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.6V 3.6V PIC24FJXXXGA2XX )D D V ( e g (Note 1) (Note 1) a t ol V 32 MHz Frequency Note: Lower operating boundary is 2.0V or VBOR (when BOR is enabled), whichever is lower. For best analog performance, operation above 2.2V is suggested, but not required. TABLE 32-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit PIC24FJ128GA204: Operating Junction Temperature Range TJ -40 — +125 °C Operating Ambient Temperature Range TA -40 — +85 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) PD PINT + PI/O W I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TABLE 32-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 7.50 mm 28-Pin SOIC JA 49 — °C/W (Note1) Package Thermal Resistance, 6x6x0.9 mm 28-Pin QFN-S JA 33.7 — °C/W (Note1) Package Thermal Resistance, 8x8 mm 44-Pin QFN JA 28 — °C/W (Note1) Package Thermal Resistance, 10x10x1 mm 44-Pin TQFP JA 39.3 — °C/W (Note1) Package Thermal Resistance, 5.30 mm 28-Pin SSOP JA — — °C/W (Note1) Package Thermal Resistance, 300 mil 28-Pin SPDIP JA — — °C/W (Note1) Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations. DS30010038C-page 376  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. Operating Voltage DC10 VDD Supply Voltage 2.0 — 3.6 V BOR disabled VBOR — 3.6 V BOR enabled DC12 VDR RAM Data Retention Greater of: — — V VBOR used only if BOR is Voltage(1) VPORREL or enabled (BOREN = 1) VBOR DC16 VPOR VDD Start Voltage VSS — — V (Note2) to Ensure Internal Power-on Reset Signal DC16A VPORREL VDD Power-on Reset 1.80 1.88 1.95 V (Note3) Release Voltage DC17A SRVDD Recommended 0.05 — — V/ms 0-3.3V in 66 ms, VDD Rise Rate 0-2.5V in 50ms to Ensure Internal (Note2) Power-on Reset Signal DC17B VBOR Brown-out Reset 2.0 2.1 2.2 V (Note3) Voltage on VDD Transition, High-to-Low Note 1: This is the limit to which VDD may be lowered and the RAM contents will always be retained. 2: If the VPOR or SRVDD parameters are not met, or the application experiences slow power-down VDD ramp rates, it is recommended to enable and use BOR. 3: On a rising VDD power-up sequence, application firmware execution begins at the higher of the VPORREL or VBOR level (when BOREN = 1).  2013-2015 Microchip Technology Inc. DS30010038C-page 377

PIC24FJ128GA204 FAMILY TABLE 32-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Operating Current (IDD)(2) DC19 0.20 0.28 mA -40°C to +125°C 2.0V 0.5 MIPS, DC20A 0.21 0.28 mA -40°C to +125°C 3.3V FOSC = 1 MHz DC20 0.38 0.52 mA -40°C to +125°C 2.0V 1 MIPS, 0.39 0.52 mA -40°C to +125°C 3.3V FOSC = 2 MHz DC23 1.5 2.0 mA -40°C to +125°C 2.0V 4 MIPS, 1.5 2.0 mA -40°C to +125°C 3.3V FOSC = 8 MHz DC24 5.6 7.6 mA -40°C to +125°C 2.0V 16 MIPS, 5.7 7.6 mA -40°C to +125°C 3.3V FOSC = 32 MHz DC31 23 78 A -40°C to +85°C 2.0V — 98 A +125°C 2.0V LPRC (15.5 KIPS), 25 80 A -40°C to +85°C 3.3V FOSC = 31 kHz — 100 A +125°C 3.3V Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Typical parameters are for design guidance only and are not tested. 2: The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail-to-rail. All I/O pins are configured as outputs and driven to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, program memory and data memory are operational. No peripheral modules are operating; however, every peripheral is being clocked (PMDx bits are all zeroed). DS30010038C-page 378  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Idle Current (IIDLE)(2) DC40 116 150 A -40°C to +85°C 2.0V — 170 A +125°C 2.0V 1 MIPS, 123 160 A -40°C to +85°C 3.3V FOSC = 2 MHz — 180 A +125°C 3.3V DC43 0.39 0.5 mA -40°C to +85°C 2.0V — 0.52 mA +125°C 2.0V 4 MIPS, 0.41 0.54 mA -40°C to +85°C 3.3V FOSC = 8 MHz — 0.56 mA +125°C 3.3V DC47 1.5 1.9 mA -40°C to +85°C 2.0V — 2 mA +125°C 2.0V 16 MIPS, 1.6 2.0 mA -40°C to +85°C 3.3V FOSC = 32 MHz — 2.1 mA +125°C 3.3V DC50 0.54 0.61 mA -40°C to +85°C 2.0V 4 MIPS (FRC), 0.54 0.64 mA -40°C to +85°C 3.3V FOSC = 8 MHz DC51 17 78 A -40°C to +85°C 2.0V — 128 A +125°C 2.0V LPRC (15.5 KIPS), 18 80 A -40°C to +85°C 3.3V FOSC = 31 kHz — 130 A +125°C 3.3V Note 1: Data in the “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base IIDLE current is measured with the core off, the clock on and all modules turned off. Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.  2013-2015 Microchip Technology Inc. DS30010038C-page 379

PIC24FJ128GA204 FAMILY TABLE 32-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Power-Down Current (IPD)(5,6) DC60 2.9 17 A -40°C 4.3 17 A +25°C 8.3 27.5 A +60°C 2.0V 20 27.5 A +85°C — 79 A +125°C Sleep(2) 2.9 18 A -40°C 4.3 18 A +25°C 8.4 28 A +60°C 3.3V 20.5 28 A +85°C — 80 A +125°C DC61 0.07 — A -40°C 0.38 — A +25°C 2.0V 2.6 — A +60°C 9.0 — A +125°C Low-Voltage Sleep(3) 0.09 — A -40°C 0.42 — A +25°C 3.3V 2.75 — A +60°C 9.0 — A +125°C DC70 0.1 700 nA -40°C 18 700 nA +25°C 230 1700 nA +60°C 2.0V 1.8 3.0 A +85°C — 24 A +125°C Deep Sleep 5 900 nA -40°C 75 900 nA +25°C 540 3450 nA +60°C 3.3V 1.5 6.0 A +85°C — 48 A +125°C DC74 0.4 2.0 A -40°C to +125°C 0V RTCC with VBAT mode (LPRC/SOSC)(4) Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: The retention low-voltage regulator is disabled; RETEN (RCON<12>) = 0, LPCFG (CW1<10>) = 1. 3: The retention low-voltage regulator is enabled; RETEN (RCON<12>) = 1, LPCFG (CW1<10>) = 0. 4: The VBAT pin is connected to the battery and RTCC is running with VDD = 0. 5: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off. 6: These currents are measured on the device containing the most memory in this family. DS30010038C-page 380  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-7: DC CHARACTERISTICS: CURRENT (BOR, WDT, DSBOR, DSWDT)(4) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Parameter Operating Typical(1) Max Units VDD Conditions No. Temperature Incremental Current Brown-out Reset (BOR)(2) DC25 3.1 5.0 A -40°C to +125°C 2.0V BOR(2) 4.3 6.0 A -40°C to +125°C 3.3V Incremental Current Watchdog Timer (WDT)(2) DC71 0.8 1.5 A -40°C to +125°C 2.0V WDT(2) 0.8 1.5 A -40°C to +125°C 3.3V Incremental Current High/Low-Voltage Detect (HLVD)(2) DC75 4.2 15 A -40°C to +125°C 2.0V HLVD(2) 4.2 15 A -40°C to +125°C 3.3V Incremental Current Real-Time Clock and Calendar (RTCC)(2) DC77 0.3 1.0 A -40°C to +125°C 2.0V RTCC (with SOSC)(2) 0.35 1.0 A -40°C to +125°C 3.3V DC77A 0.3 1.0 A -40°C to +125°C 2.0V RTCC (with LPRC)(2) 0.35 1.0 A -40°C to +125°C 3.3V Incremental Current Deep Sleep BOR (DSBOR)(2) DC81 0.11 0.40 A -40°C to +125°C 2.0V Deep Sleep BOR(2) 0.12 0.40 A -40°C to +125°C 3.3V Incremental Current Deep Sleep Watchdog Timer Reset (DSWDT)(2) DC80 0.24 0.40 A -40°C to +125°C 2.0V Deep Sleep WDT(2) 0.24 0.40 A -40°C to +125°C 3.3V VBAT A/D Monitor(3) DC91 1.5 — A -40°C to +125°C 3.3V VBAT = 2V 4 — A -40°C to +125°C 3.3V VBAT = 3.3V Note 1: Data in the Typical column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Incremental current while the module is enabled and running. 3: The A/D channel is connected to the VBAT pin internally; this is the current during A/D VBAT operation. 4: The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.  2013-2015 Microchip Technology Inc. DS30010038C-page 381

PIC24FJ128GA204 FAMILY TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbo Characteristic Min Typ(1) Max Units Conditions No. l VIL Input Low Voltage(3) DI10 I/O Pins with ST Buffer VSS — 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS — 0.15 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.2 VDD V DI18 I/O Pins with I2C™ Buffer VSS — 0.3 VDD V DI19 I/O Pins with SMBus Buffer VSS — 0.8 V SMBus enabled VIH Input High Voltage(3) DI20 I/O Pins with ST Buffer: with Analog Functions 0.8VDD — VDD V Digital Only 0.8VDD — 5.5 V DI21 I/O Pins with TTL Buffer: with Analog Functions 0.25 VDD + 0.8 — VDD V Digital Only 0.25 VDD + 0.8 — 5.5 V DI25 MCLR 0.8 VDD — VDD V DI26 OSCI (XT mode) 0.7 VDD — VDD V DI27 OSCI (HS mode) 0.7 VDD — VDD V DI28 I/O Pins with I2C Buffer: with Analog Functions 0.7 VDD — VDD V Digital Only 0.7 VDD — 5.5 V DI29 I/O Pins with SMBus Buffer: with Analog Functions 2.1 — VDD V 2.5V  VPIN  VDD Digital Only 2.1 — 5.5 V DI30 ICNPU CNxx Pull-up Current 150 340 550 A VDD = 3.3V, VPIN = VSS DI30A ICNPD CNxx Pull-Down Current 150 310 550 A VDD = 3.3V, VPIN = VDD IIL Input Leakage Current(2) DI50 I/O Ports — — ±1 A VSS  VPIN  VDD, pin at high-impedance DI51 Analog Input Pins — — ±1 A VSS  VPIN  VDD, pin at high-impedance DI55 MCLR — — ±1 A VSS VPIN VDD DI56 OSCI/CLKI — — ±1 A VSS VPIN VDD, EC, XT and HS modes Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Negative current is defined as current sourced by the pin. 3: Refer to Table1-3 for I/O pin buffer types. DS30010038C-page 382  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbo Characteristic Min Typ(1) Max Units Conditions No. l VOL Output Low Voltage DO10 I/O Ports — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2V DO16 OSCO/CLKO — — 0.4 V IOL = 6.6 mA, VDD = 3.6V — — 0.4 V IOL = 5.0 mA, VDD = 2V VOH Output High Voltage DO20 I/O Ports 3.0 — — V IOH = -3.0 mA, VDD = 3.6V 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.65 — — V IOH = -1.0 mA, VDD = 2V 1.4 — — V IOH = -3.0 mA, VDD = 2V DO26 OSCO/CLKO 2.4 — — V IOH = -6.0 mA, VDD = 3.6V 1.4 — — V IOH = -1.0 mA, VDD = 2V Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 32-10: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. Program Flash Memory D130 EP Cell Endurance 20000 — — E/W -40C to +125C D131 VPR VDD for Read VMIN — 3.6 V VMIN = Minimum Operating Voltage D132B VDD for Self-Timed Write VMIN — 3.6 V VMIN = Minimum Operating Voltage D133A TIW Self-Timed Word Write — 20 — s Cycle Time Self-Timed Row Write — 1.5 — ms Cycle Time D133B TIE Self-Timed Page Erase 20 — 40 ms Time D134 TRETD Characteristic Retention 20 — — Year If no other specifications are violated D135 IDDP Supply Current during — 5 — mA Programming D136 VOTP OTP Programming 3.1 — 3.6 V D137 TOTP OTP Memory Write/Bit — 500 — s Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated.  2013-2015 Microchip Technology Inc. DS30010038C-page 383

PIC24FJ128GA204 FAMILY TABLE 32-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristics Min Typ Max Units Comments No. DVR TVREG Voltage Regulator Start-up Time — 10 — s VREGS = 1 with any POR or BOR DVR10 VBG Internal Band Gap Reference — 1.2 — V DVR11 TBG Band Gap Reference — 1 — ms Start-up Time DVR20 VRGOUT Regulator Output Voltage — 1.8 — V VDD > 1.9V DVR21 CEFC External Filter Capacitor Value 4.7 10 — F Series resistance < 3 recommended; < 5 required DVR30 VLVR Low-Voltage Regulator — 1.2 — V RETEN = 1, LPCFG = 0 Output Voltage TABLE 32-12: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. DC18 VHLVD HLVD Voltage on VDD HLVDL<3:0> = 0100(1) 3.45 3.59 3.74 V Transition HLVDL<3:0> = 0101 3.33 3.45 3.58 V HLVDL<3:0> = 0110 3.0 3.125 3.25 V HLVDL<3:0> = 0111 2.8 2.92 3.04 V HLVDL<3:0> = 1000 2.7 2.81 2.93 V HLVDL<3:0> = 1001 2.50 2.6 2.70 V HLVDL<3:0> = 1010 2.4 2.52 2.64 V HLVDL<3:0> = 1011 2.30 2.4 2.50 V HLVDL<3:0> = 1100 2.20 2.29 2.39 V HLVDL<3:0> = 1101 2.1 2.19 2.28 V HLVDL<3:0> = 1110 2.0 2.08 2.17 V DC101 VTHL HLVD Voltage on HLVDL<3:0> = 1111 — 1.2 — V HLVDIN Pin Transition Note 1: Trip points for values of HLVD<3:0> from ‘0000’ to ‘0011’ are not implemented. DS30010038C-page 384  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-13: COMPARATOR DC SPECIFICATIONS Operating Conditions: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. D300 VIOFF Input Offset Voltage — 20 ±40 mV (Note1) D301 VICM Input Common-Mode Voltage 0 — VDD V (Note1) D302 CMRR Common-Mode Rejection 55 — — dB (Note1) Ratio D306 IQCMP AVDD Quiescent Current per — 27 — µs Comparator enabled Comparator D307 TRESP Response Time — 300 — ns (Note2) D308 TMC2OV Comparator Mode Change to — — 10 µs Valid Output Note 1: Parameters are characterized but not tested. 2: Measured with one input at VDD/2 and the other transitioning from VSS to VDD, 40 mV step, 15 mV overdrive. TABLE 32-14: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Comments No. VR310 TSET Settling Time — — 10 µs (Note1) VRD311 CVRAA Absolute Accuracy -100 — 100 mV VRD312 CVRUR Unit Resistor Value (R) — 4.5 — k Note 1: Measures the interval while CVR<4:0> transitions from ‘11111’ to ‘00000’.  2013-2015 Microchip Technology Inc. DS30010038C-page 385

PIC24FJ128GA204 FAMILY TABLE 32-15: VBAT OPERATING VOLTAGE SPECIFICATIONS Param Symbol Characteristic Min Typ Max Units Comments No. DVB01 VBT Operating Voltage 1.6 — 3.6 V Battery connected to the VBAT pin DVB10 VBTADC VBAT A/D Monitoring 1.6 — 3.6 V A/D monitoring the VBAT pin using Voltage Specification(1) the internal A/D channel Note 1: Measuring the A/D value using the A/D is represented by the equation: Measured Voltage = ((VBAT/2)/VDD) * 4096) for 12-bit A/D TABLE 32-16: CTMU CURRENT SOURCE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) DC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Sym Characteristic Min Typ(1) Max(3) Units Comments Conditions No. DCT10 IOUT1 CTMU Current 208 550 797 nA CTMUICON<9:8> = 00 Source, Base Range DCT11 IOUT2 CTMU Current 3.32 5.5 7.67 A CTMUICON<9:8> = 01 Source, 10x Range 2.5V < VDD < VDDMAX DCT12 IOUT3 CTMU Current 32.22 55 77.78 A CTMUICON<9:8> = 10 Source, 100x Range DCT13 IOUT4 CTMU Current 322 550 777 A CTMUICON<9:8>=11(2) Source, 1000x Range DCT21 V Temperature Diode — -3 — mV/°C Voltage Change per Degree Celsius Note 1: Nominal value at the center point of the current trim range (CTMUICON<15:10> = 000000). 2: Do not use this current range with a temperature sensing diode. 3: Maximum values are tested at +85°C. DS30010038C-page 386  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 32.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ128GA204 family AC characteristics and timing parameters. TABLE 32-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial AC CHARACTERISTICS -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section32.1 “DC Characteristics”. FIGURE 32-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSCO Load Condition 2 – for OSCO VDD/2 Pin CL RL VSS Pin CL RL = 464 CL = 50 pF for all pins except OSCO VSS 15 pF for OSCO output TABLE 32-18: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO50 COSCO OSCO/CLKO Pin — — 15 pF In XT and HS modes when external clock is used to drive OSCI DO56 CIO All I/O Pins and OSCO — — 50 pF EC mode DO58 CB SCLx, SDAx — — 400 pF In I2C™ mode Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2013-2015 Microchip Technology Inc. DS30010038C-page 387

PIC24FJ128GA204 FAMILY FIGURE 32-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS30 OS31 OS31 OS25 CLKO OS40 OS41 TABLE 32-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS10 FOSC External CLKI Frequency DC — 32 MHz EC (External clocks allowed 4 — 48 MHz ECPLL (Note2) only in EC mode) Oscillator Frequency 3.5 — 10 MHz XT 4 — 8 MHz XTPLL 10 — 32 MHz HS 12 — 32 MHz HSPLL 31 — 33 kHz SOSC OS20 TOSC TOSC = 1/FOSC — — — — See Parameter OS10 for FOSC value OS25 TCY Instruction Cycle Time(3) 62.5 — DC ns OS30 TosL, External Clock in (OSCI) 0.45 x TOSC — — ns EC TosH High or Low Time OS31 TosR, External Clock in (OSCI) — — 20 ns EC TosF Rise or Fall Time OS40 TckR CLKO Rise Time(4) — 6 10 ns OS41 TckF CLKO Fall Time(4) — 6 10 ns Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Represents input to the system clock prescaler. PLL dividers and postscalers must still be configured so that the system clock frequency does not exceed the maximum frequency shown in Figure32-1. 3: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max” cycle time limit is “DC” (no clock) for all devices. 4: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS30010038C-page 388  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-20: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. OS50 FPLLI USB PLL Input 2 4 4 MHz ECPLL mode Frequency Range 2 4 4 MHz HSPLL mode 2 4 4 MHz XTPLL mode OS52 TLOCK USB PLL Start-up Time — — 128 s (Lock Time) OS53 DCLK CLKO Stability (Jitter) -0.25 — 0.25 % OS54 F4xPLL 4x PLL Input Frequency 2 — 8 MHz 4x PLL Range OS55 F6xPLL 6x PLL Input Frequency 2 — 5 MHz 6x PLL Range OS56 F8xPLL 8x PLL Input Frequency 2 — 4 MHz 8x PLL Range OS57 TxPLLLOCK PLL Start-up Time — — 24 s (Lock Time) OS58 DxPLLCLK PLL CLKO Stability -2 — 2 % (Jitter) Note 1: These parameters are characterized but not tested in manufacturing. TABLE 32-21: INTERNAL RC ACCURACY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Characteristic Min Typ Max Units Conditions No. F20 FRC Accuracy @ 8MHz -1 ±0.15 1 % 2.0V  VDD 3.6V, 0°C  TA +85°C (Note1) 1.5 — 1.5 % 2.0V  VDD 3.6V, -40°C  TA 0°C -0.20 ±0.05 -0.20 % 2.0V  VDD 3.6V, -40°C  TA +85°C, self-tune is enabled and locked (Note2) — 3 5 % 2.0V  VDD 3.6V, TA = +125°C F21 LPRC @ 31 kHz -20 — 20 % VCAP Output Voltage = 1.8V F22 OSCTUN Step-Size — 0.05 — %/bit F23 FRC Self-Tune Lock Time — <5 8 ms (Note3) Note 1: To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. 2: Accuracy is measured with respect to the reference source. 3: Time from reference clock stable and in range to FRC tuned within range specified by F20 (with self-tune).  2013-2015 Microchip Technology Inc. DS30010038C-page 389

PIC24FJ128GA204 FAMILY FIGURE 32-4: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Start Stop Condition Condition Note: Refer to Figure32-2 for load conditions. TABLE 32-22: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM30 TSU:STA Start Condition 100 kHz mode TCY (BRG + 1) — s Only relevant for Setup Time Repeated Start 400 kHz mode TCY (BRG + 1) — s condition 1 MHz mode(2) TCY (BRG + 1) — s IM31 THD:STA Start Condition 100 kHz mode TCY (BRG + 1) — s After this period, the Hold Time first clock pulse is 400 kHz mode TCY (BRG + 1) — s generated 1 MHz mode(2) TCY (BRG + 1) — s IM33 TSU:STO Stop Condition 100 kHz mode TCY (BRG + 1) — s Setup Time 400 kHz mode TCY (BRG + 1) — s 1 MHz mode(2) TCY (BRG + 1) — s IM34 THD:STO Stop Condition 100 kHz mode TCY (BRG + 1) — ns Hold Time 400 kHz mode TCY (BRG + 1) — ns 1 MHz mode(2) TCY (BRG + 1) — ns Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section17.2 “Setting Baud Rate when Operating as a Bus Master” for details. 2: Maximum Pin Capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS30010038C-page 390  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 32-5: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM11 IM21 SCLx IM10 IM25 IM26 IM20 SDAx In IM45 IM40 SDAx Out Note: Refer to Figure32-2 for load conditions. TABLE 32-23: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min(1) Max Units Conditions No. IM10 TLO:SCL Clock Low 100 kHz mode TCY (BRG + 1) — s Time 400 kHz mode TCY (BRG + 1) — s 1 MHz mode(2) TCY (BRG + 1) — s IM11 THI:SCL Clock High 100 kHz mode TCY (BRG + 1) — s Time 400 kHz mode TCY (BRG + 1) — s 1 MHz mode(2) TCY (BRG + 1) — s IM20 TF:SCL SDAx and 100 kHz mode — 300 ns CB is specified to be from SCLx 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF Fall Time 1 MHz mode(2) — 100 ns IM21 TR:SCL SDAx and 100 kHz mode — 1000 ns CB is specified to be from SCLx 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF Rise Time 1 MHz mode(2) — 300 ns IM25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns IM26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(2) 0.2 — ns IM40 TAA:SCL Output 100 kHz mode — 3500 ns Valid from 400 kHz mode — 1000 ns Clock 1 MHz mode(2) — 400 ns IM45 TBF:SDA Bus Free 100 kHz mode 4.7 — s Time the bus must be free Time 400 kHz mode 1.3 — s before a new transmission can start 1 MHz mode(2) 0.5 — s IM50 CB Bus Capacitive Loading — 400 pF Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section17.2 “Setting Baud Rate when Operating as a Bus Master” for details. 2: Maximum Pin Capacitance = 10 pF for all I2C pins (for 1 MHz mode only).  2013-2015 Microchip Technology Inc. DS30010038C-page 391

PIC24FJ128GA204 FAMILY FIGURE 32-6: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS34 IS30 IS33 SDAx Start Stop Condition Condition TABLE 32-24: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS30 TSU:STA Start Condition 100 kHz mode 4.7 — s Only relevant for Repeated Setup Time 400 kHz mode 0.6 — s Start condition 1 MHz mode(1) 0.25 — s IS31 THD:STA Start Condition 100 kHz mode 4.0 — s After this period, the first clock Hold Time 400 kHz mode 0.6 — s pulse is generated 1 MHz mode(1) 0.25 — s IS33 TSU:STO Stop Condition 100 kHz mode 4.7 — s Setup Time 400 kHz mode 0.6 — s 1 MHz mode(1) 0.6 — s IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns Hold Time 400 kHz mode 600 — ns 1 MHz mode(1) 250 — ns Note 1: Maximum Pin Capacitance = 10 pF for all I2C pins (for 1 MHz mode only). DS30010038C-page 392  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 32-7: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out TABLE 32-25: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Max Units Conditions No. IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1 MHz mode(1) 0.5 — s IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 100 ns IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF 1 MHz mode(1) — 300 ns IS25 TSU:DAT Data Input 100 kHz mode 250 — ns Setup Time 400 kHz mode 100 — ns 1 MHz mode(1) 100 — ns IS26 THD:DAT Data Input 100 kHz mode 0 — ns Hold Time 400 kHz mode 0 0.9 s 1 MHz mode(1) 0 0.3 s IS40 TAA:SCL Output Valid 100 kHz mode 0 3500 ns From Clock 400 kHz mode 0 1000 ns 1 MHz mode(1) 0 350 ns IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s Time the bus must be free before a 400 kHz mode 1.3 — s new transmission can start 1 MHz mode(1) 0.5 — s IS50 CB Bus Capacitive Loading — 400 pF Note 1: Maximum Pin Capacitance = 10 pF for all I2C pins (for 1 MHz mode only).  2013-2015 Microchip Technology Inc. DS30010038C-page 393

PIC24FJ128GA204 FAMILY TABLE 32-26: RC OSCILLATOR START-UP TIME Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. FR0 TFRC FRC Oscillator Start-up — 15 — s Time FR1 TLPRC Low-Power RC Oscillator — 50 — s Start-up Time FIGURE 32-8: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin Old Value New Value (Output) DO31 DO32 Note: Refer to Figure32-2 for load conditions. TABLE 32-27: CLKO AND I/O TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ(1) Max Units Conditions No. DO31 TIOR Port Output Rise Time — 10 25 ns DO32 TIOF Port Output Fall Time — 10 25 ns DI35 TINP INTx Pin High or Low 20 — — ns Time (input) DI40 TRBP CNxx High or Low Time 2 — — TCY (input) Note 1: Data in the “Typ” column is at 3.3V, +25°C unless otherwise stated. DS30010038C-page 394  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-28: RESET AND BROWN-OUT RESET REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. SY10 TMCL MCLR Pulse Width (Low) 2 — — s SY12 TPOR Power-on Reset Delay — 2 — s SY13 TIOZ I/O High-Impedance from Lesser of: — (3TCY + 2) s MCLR Low or Watchdog (3TCY + 2) Timer Reset or 700 SY25 TBOR Brown-out Reset Pulse 1 — — s VDD VBOR Width SY45 TRST Internal State Reset Time — 50 — s SY70 TDSWU Deep Sleep Wake-up — 200 — s VCAP is fully discharged Time before wake-up SY71 TPM Program Memory — 20 — s Sleep wake-up with Wake-up Time VREGS = 0 — 1 — s Sleep wake-up with VREGS = 1 SY72 TLVR Low-Voltage Regulator — 90 — s Sleep wake-up with Wake-up Time VREGS = 0 — 70 — s Sleep wake-up with VREGS = 1  2013-2015 Microchip Technology Inc. DS30010038C-page 395

PIC24FJ128GA204 FAMILY FIGURE 32-9: TIMER1, 2, 3, 4 AND 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx11 Tx15 Tx20 OS60 TMRx Note: Refer to Figure32-2 for load conditions. TABLE 32-29: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TA10 TTXH T1CK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet No Prescaler Parameter TA15 Synchronous, 10 — — ns with Prescaler Asynchronous 10 — — ns TA11 TTXL T1CK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet No Prescaler Parameter TA15 Synchronous, 10 — — ns with Prescaler Asynchronous 10 — — ns TA15 TTXP T1CK Input Period Synchronous, TCY + 40 — — ns No Prescaler Synchronous, Greater of: — — — N = Prescale Value with Prescaler 20 ns or (1, 8, 64, 256) (TCY + 40)/N Asynchronous 20 — — ns OS60 FT1 SOSC1/T1CK Oscillator Input Frequency DC — 50 kHz Range (oscillator enabled by setting bit, TCS (T1CON<1>)) TA20 TCKEXTMRL Delay from External T1CK Clock Edge 0.5 TCY — 1.5 TCY — to Timer Increment Note 1: Timer1 is a Type A. DS30010038C-page 396  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY T ABLE 32-30: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TB10 TTXH TxCK High Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler Parameter TB15 Synchronous, 10 — — ns with prescaler TB11 TTXL TxCK Low Time Synchronous, 0.5 TCY + 20 — — ns Must also meet no prescaler Parameter TB15 Synchronous, 10 — — ns with prescaler TB15 TTXP TxCK Input Synchronous, TCY + 40 — — ns N = Prescale Value Period no prescaler (1, 8, 64, 256) Synchronous, Greater of: with prescaler 20 ns or (TCY + 40)/N TB20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — Edge to Timer Increment TABLE 32-31: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min Typ Max Units Conditions No. TC10 TTXH TxCK High Time Synchronous 0.5 TCY + 20 — — ns Must also meet Parameter TC15 TC11 TTXL TxCK Low Time Synchronous 0.5 TCY + 20 — — ns Must also meet Parameter TC15 TC15 TTXP TxCK Input Synchronous, TCY + 40 — — ns N = Prescale Value Period no prescaler (1, 8, 64, 256) Synchronous, Greater of: with prescaler 20 ns or (TCY + 40)/N TC20 TCKEXTMRL Delay from External TxCK Clock 0.5 TCY — 1.5 TCY — Edge to Timer Increment  2013-2015 Microchip Technology Inc. DS30010038C-page 397

PIC24FJ128GA204 FAMILY FIGURE 32-10: INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure32-2 for load conditions. TABLE 32-32: INPUT CAPTURE x TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Max Units Conditions No. IC10 TccL ICx Input Low Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC11 TccH ICx Input High Time No Prescaler 0.5 TCY + 20 — ns With Prescaler 10 — ns IC15 TccP ICx Input Period (TCY + 40)/N — ns N = Prescale Value (1, 4, 16) Note 1: These parameters are characterized but not tested in manufacturing. FIGURE 32-11: OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure32-2 for load conditions. TABLE 32-33: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC10 TccF OCx Output Fall Time — — — ns See Parameter DO32 OC11 TccR OCx Output Rise Time — — — ns See Parameter DO31 Note 1: These parameters are characterized but not tested in manufacturing. DS30010038C-page 398  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 32-12: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx TABLE 32-34: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ Max Units Conditions No. OC15 TFD Fault Input to PWM I/O — — 50 ns Change OC20 TFLT Fault Input Pulse Width 50 — — ns Note 1: These parameters are characterized but not tested in manufacturing.  2013-2015 Microchip Technology Inc. DS30010038C-page 399

PIC24FJ128GA204 FAMILY FIGURE 32-13: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SP10 SP21 SP20 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP31 SP30 SDIx MSb In Bit 14 - - - -1 LSb In SP40 SP41 Note: Refer to Figure32-2 for load conditions. TABLE 32-35: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKx Output Low Time TCY/2 — — ns (Note3) SP11 TscH SCKx Output High Time TCY/2 — — ns (Note3) SP20 TscF SCKx Output Fall Time — — — ns See Parameter DO32 (Note4) SP21 TscR SCKx Output Rise Time — — — ns See Parameter DO31 (Note4) SP30 TdoF SDOx Data Output Fall Time — — — ns See Parameter DO32 (Note4) SP31 TdoR SDOx Data Output Rise Time — — — ns See Parameter DO31 (Note4) SP35 TscH2doV, SDOx Data Output Valid After — 6 20 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 23 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS30010038C-page 400  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 32-14: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP21 SP20 SP11 SP10 SCKx (CKP = 1) SP35 SP20 SP21 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP40 SDIx MSb In Bit 14 - - - -1 LSb In SP41 Note: Refer to Figure32-2 for load conditions. TABLE 32-36: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP10 TscL SCKx Output Low Time(3) TCY/2 — — ns SP11 TscH SCKx Output High Time(3) TCY/2 — — ns SP20 TscF SCKx Output Fall Time(4) — — — ns See Parameter DO32 SP21 TscR SCKx Output Rise Time(4) — — — ns See Parameter DO31 SP30 TdoF SDOx Data Output Fall — — — ns See Parameter DO32 Time(4) SP31 TdoR SDOx Data Output Rise — — — ns See Parameter DO31 Time(4) SP35 TscH2doV, SDOx Data Output Valid After — 6 20 ns TscL2doV SCKx Edge SP36 TdoV2sc, SDOx Data Output Setup to 30 — — ns TdoV2scL First SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data 23 — — ns TdiV2scL Input to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 30 — — ns TscL2diL to SCKx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins.  2013-2015 Microchip Technology Inc. DS30010038C-page 401

PIC24FJ128GA204 FAMILY FIGURE 32-15: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SSx SP50 SP52 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP72 SP73 SP35 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-2 for load conditions. TABLE 32-37: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(3) — 10 25 ns SP73 TscR SCKx Input Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output Fall Time(3) — — — ns See Parameter DO32 SP31 TdoR SDOx Data Output Rise Time(3) — — — ns See Parameter DO31 SP35 TscH2doV, SDOx Data Output Valid After — — 30 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx Input 120 — — ns TssL2scL SP51 TssH2doZ SSx  to SDOx Output 10 — 50 ns High-Impedance(3) SP52 TscH2ssH, SSx After SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: Assumes 50 pF load on all SPIx pins. DS30010038C-page 402  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY FIGURE 32-16: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 SSx SP50 SP52 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SCKx (CKP = 1) SP35 SP72 SP73 SP52 SDOx MSb Bit 14 - - - - - -1 LSb SP30, SP31 SP51 SDIx MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure32-2 for load conditions.  2013-2015 Microchip Technology Inc. DS30010038C-page 403

PIC24FJ128GA204 FAMILY TABLE 32-38: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic(1) Min Typ(2) Max Units Conditions No. SP70 TscL SCKx Input Low Time 30 — — ns SP71 TscH SCKx Input High Time 30 — — ns SP72 TscF SCKx Input Fall Time(3) — 10 25 ns SP73 TscR SCKx Input Rise Time(3) — 10 25 ns SP30 TdoF SDOx Data Output — — — ns See Parameter DO32 Fall Time(3) SP31 TdoR SDOx Data Output — — — ns See Parameter DO31 Rise Time(3) SP35 TscH2doV, SDOx Data Output Valid After — — 30 ns TscL2doV SCKx Edge SP40 TdiV2scH, Setup Time of SDIx Data Input 20 — — ns TdiV2scL to SCKx Edge SP41 TscH2diL, Hold Time of SDIx Data Input 20 — — ns TscL2diL to SCKx Edge SP50 TssL2scH, SSx  to SCKx  or SCKx  120 — — ns TssL2scL Input SP51 TssH2doZ SSx  to SDOX Output 10 — 50 ns High-Impedance(4) SP52 TscH2ssH SSx  After SCKx Edge 1.5 TCY + 40 — — ns TscL2ssH SP60 TssL2doV SDOx Data Output Valid After — — 50 ns SSx Edge Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. 3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPIx pins. DS30010038C-page 404  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY TABLE 32-39: A/D MODULE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Device Supply AD01 AVDD Module VDD Supply Greater of: — Lesser of: V VDD – 0.3 VDD + 0.3 or 2.2 or 3.6 AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.3 V Reference Inputs AD05 VREFH Reference Voltage High AVSS + 1.7 — AVDD V AD06 VREFL Reference Voltage Low AVSS — AVDD – 1.7 V AD07 VREF Absolute Reference AVSS – 0.3 — AVDD + 0.3 V Voltage Analog Inputs AD10 VINH-VINL Full-Scale Input Span VREFL — VREFH V (Note2) AD11 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V AD12 VINL Absolute VINL Input AVSS – 0.3 — AVDD/3 V Voltage AD13 Leakage Current — ±1.0 ±610 nA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5k AD17 RIN Recommended — — 2.5K  10-bit Impedance of Analog Voltage Source A/D Accuracy AD20B Nr Resolution — 12 — bits AD21B INL Integral Nonlinearity — ±1 <±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22B DNL Differential Nonlinearity — — <±1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23B GERR Gain Error — ±1 ±3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24B EOFF Offset Error — ±1 ±2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25B Monotonicity(1) — — — — Guaranteed Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. 2: Measurements are taken with the external VREF+ and VREF- used as the A/D voltage reference.  2013-2015 Microchip Technology Inc. DS30010038C-page 405

PIC24FJ128GA204 FAMILY TABLE 32-40: A/D CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param Symbol Characteristic Min. Typ Max. Units Conditions No. Clock Parameters AD50 TAD A/D Clock Period 75 — — ns TCY = 75 ns, AD1CON3 in default state AD51 tRC A/D Internal RC Oscillator — 250 — ns Period Conversion Rate AD55 tCONV Conversion Time — 14 — TAD AD56 FCNV Throughput Rate — — 200 ksps AVDD > 2.7V AD57 tSAMP Sample Time — 1 — TAD Clock Parameters AD61 tPSS Sample Start Delay from 2 — 3 TAD Setting Sample bit (SAMP) Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. DS30010038C-page 406  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 33.0 PACKAGING INFORMATION 33.1 Package Marking Information 28-Lead QFN-S Example XXXXXXXX 24FJ128 XXXXXXXX GA202 YYWWNNN 1510017 28-Lead SOIC (.300”) Example XXXXXXXXXXXXXXXXXXXX PIC24FJ128GA202 XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX 1510017 YYWWNNN 28-Lead SPDIP Example XXXXXXXXXXXXXXXXX PIC24FJ128GA202 XXXXXXXXXXXXXXXXX YYWWNNN 1510017 28-Lead SSOP Example XXXXXXXXXXXX PIC24FJ128 XXXXXXXXXXXX GA202 YYWWNNN 1510017 Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2013-2015 Microchip Technology Inc. DS30010038C-page 407

PIC24FJ128GA204 FAMILY 44-Lead QFN Example XXXXXXXXXX PIC24FJ128 XXXXXXXXXX GA204 XXXXXXXXXX YYWWNNN 1510017 44-Lead TQFP Example XXXXXXXXXX PIC24FJ128 XXXXXXXXXX GA204 XXXXXXXXXX YYWWNNN 1510017 DS30010038C-page 408  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 33.2 Package Details The following sections give the technical details of the packages.  2013-2015 Microchip Technology Inc. DS30010038C-page 409

PIC24FJ128GA204 FAMILY DS30010038C-page 410  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)(cid:16)(cid:17)(cid:7)(cid:8)(cid:9)(cid:18)(cid:11)(cid:7)(cid:13)(cid:19)(cid:9)(cid:20)(cid:21)(cid:9)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:7)(cid:15)(cid:22)(cid:7)(cid:23)(cid:6)(cid:9)(cid:24)(cid:25)(cid:25)(cid:26)(cid:9)(cid:27)(cid:9)(cid:28)(cid:29)(cid:28)(cid:29)(cid:30)(cid:31) (cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$(cid:16)(cid:18)(cid:20)(cid:4)%& ’(cid:14)(cid:13)((cid:9)(cid:30)(cid:31))(cid:30)(cid:9)!!(cid:9)*(cid:21)+(cid:13)(cid:7)(cid:15)(cid:13)(cid:9)(cid:5)(cid:6)+(cid:23)(cid:13)( (cid:20)(cid:21)(cid:13)(cid:6), (cid:31)(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)!(cid:10)" (cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)%(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)  2013-2015 Microchip Technology Inc. DS30010038C-page 411

PIC24FJ128GA204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30010038C-page 412  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS30010038C-page 413

PIC24FJ128GA204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30010038C-page 414  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)%(-(cid:14)+(cid:22)(cid:9)%!(cid:7)(cid:11)(cid:11)(cid:9).(cid:17)(cid:13)(cid:11)(cid:14)+(cid:6)(cid:9)(cid:24)%%(cid:26)(cid:9)(cid:27)(cid:9)/(cid:31)0(cid:30)(cid:9)!!(cid:9)"(cid:21)(cid:8)#(cid:9)$%%.(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), (cid:31)(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)!(cid:10)" (cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)%(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) D N E E1 1 2 b NOTE1 e c A A2 φ A1 L1 L 5(cid:15)(cid:7) " (cid:6)(cid:19)66(cid:19)(cid:6)0(cid:13)0(cid:26)(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)6(cid:7)!(cid:7) " (cid:6)(cid:19)7 78(cid:6) (cid:6)(cid:25)9 7#!/(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" 7 (cid:3): ((cid:7) (cid:8)(cid:11) (cid:14) (cid:4)(cid:20),2(cid:2)3(cid:22)4 8-(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2);(cid:14)(cid:7)(cid:17)(cid:11) (cid:25) < < (cid:3)(cid:20)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:25)(cid:3) (cid:29)(cid:20),2 (cid:29)(cid:20)(cid:5)2 (cid:29)(cid:20):2 (cid:22) (cid:28)(cid:15)%(cid:10)))(cid:2) (cid:25)(cid:29) (cid:4)(cid:20)(cid:4)2 < < 8-(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)=(cid:7)% (cid:11) 0 (cid:5)(cid:20)(cid:23)(cid:4) (cid:5)(cid:20):(cid:4) :(cid:20)(cid:3)(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)% (cid:11) 0(cid:29) 2(cid:20)(cid:4)(cid:4) 2(cid:20)(cid:30)(cid:4) 2(cid:20),(cid:4) 8-(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)6(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:24)(cid:20)(cid:24)(cid:4) (cid:29)(cid:4)(cid:20)(cid:3)(cid:4) (cid:29)(cid:4)(cid:20)2(cid:4) (cid:31)(cid:10)(cid:10) (cid:2)6(cid:14)(cid:15)(cid:17) (cid:11) 6 (cid:4)(cid:20)22 (cid:4)(cid:20)(cid:5)2 (cid:4)(cid:20)(cid:24)2 (cid:31)(cid:10)(cid:10) (cid:12)(cid:9)(cid:7)(cid:15) 6(cid:29) (cid:29)(cid:20)(cid:3)2(cid:2)(cid:26)0(cid:31) 6(cid:14)(cid:28)%(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:8) (cid:4)(cid:20)(cid:4)(cid:24) < (cid:4)(cid:20)(cid:3)2 (cid:31)(cid:10)(cid:10) (cid:2)(cid:25)(cid:15)(cid:17)(cid:16)(cid:14) (cid:3) (cid:4)> (cid:23)> :> 6(cid:14)(cid:28)%(cid:2)=(cid:7)% (cid:11) / (cid:4)(cid:20)(cid:3)(cid:3) < (cid:4)(cid:20)(cid:30): (cid:20)(cid:21)(cid:13)(cid:6)(cid:12), (cid:29)(cid:20) ((cid:7)(cid:15)(cid:2)(cid:29)(cid:2)-(cid:7)"#(cid:28)(cid:16)(cid:2)(cid:7)(cid:15)%(cid:14).(cid:2))(cid:14)(cid:28) #(cid:9)(cid:14)(cid:2)!(cid:28)(cid:18)(cid:2)-(cid:28)(cid:9)(cid:18)’(cid:2)/# (cid:2)!#" (cid:2)/(cid:14)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)%(cid:2)&(cid:7) (cid:11)(cid:7)(cid:15)(cid:2) (cid:11)(cid:14)(cid:2)(cid:11)(cid:28) (cid:8)(cid:11)(cid:14)%(cid:2)(cid:28)(cid:9)(cid:14)(cid:28)(cid:20) (cid:3)(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)"(cid:2)(cid:21)(cid:2)(cid:28)(cid:15)%(cid:2)0(cid:29)(cid:2)%(cid:10)(cid:2)(cid:15)(cid:10) (cid:2)(cid:7)(cid:15)(cid:8)(cid:16)#%(cid:14)(cid:2)!(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:20)(cid:2)(cid:6)(cid:10)(cid:16)%(cid:2))(cid:16)(cid:28)"(cid:11)(cid:2)(cid:10)(cid:9)(cid:2)(cid:12)(cid:9)(cid:10) (cid:9)#"(cid:7)(cid:10)(cid:15)"(cid:2)"(cid:11)(cid:28)(cid:16)(cid:16)(cid:2)(cid:15)(cid:10) (cid:2)(cid:14).(cid:8)(cid:14)(cid:14)%(cid:2)(cid:4)(cid:20)(cid:3)(cid:4)(cid:2)!!(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)"(cid:7)%(cid:14)(cid:20) (cid:30)(cid:20) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:7)(cid:15)(cid:17)(cid:2)(cid:28)(cid:15)%(cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:12)(cid:14)(cid:9)(cid:2)(cid:25)(cid:22)(cid:6)0(cid:2)1(cid:29)(cid:23)(cid:20)2(cid:6)(cid:20) 3(cid:22)4* 3(cid:28)"(cid:7)(cid:8)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:20)(cid:2)(cid:13)(cid:11)(cid:14)(cid:10)(cid:9)(cid:14) (cid:7)(cid:8)(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)(cid:14).(cid:28)(cid:8) (cid:2)-(cid:28)(cid:16)#(cid:14)(cid:2)"(cid:11)(cid:10)&(cid:15)(cid:2)&(cid:7) (cid:11)(cid:10)# (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)"(cid:20) (cid:26)0(cid:31)* (cid:26)(cid:14))(cid:14)(cid:9)(cid:14)(cid:15)(cid:8)(cid:14)(cid:2)(cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)’(cid:2)#"#(cid:28)(cid:16)(cid:16)(cid:18)(cid:2)&(cid:7) (cid:11)(cid:10)# (cid:2) (cid:10)(cid:16)(cid:14)(cid:9)(cid:28)(cid:15)(cid:8)(cid:14)’(cid:2))(cid:10)(cid:9)(cid:2)(cid:7)(cid:15))(cid:10)(cid:9)!(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:12)#(cid:9)(cid:12)(cid:10)"(cid:14)"(cid:2)(cid:10)(cid:15)(cid:16)(cid:18)(cid:20) (cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:8)(cid:11)(cid:15)(cid:10)(cid:16)(cid:10)(cid:17)(cid:18)(cid:21)(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)4(cid:4)(cid:23)(cid:27)(cid:4)(cid:5)(cid:30)3  2013-2015 Microchip Technology Inc. DS30010038C-page 415

PIC24FJ128GA204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS30010038C-page 416  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY (cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:7)(cid:8)(cid:9)%(cid:22)(cid:14)++#(cid:9)(cid:10)(cid:11)(cid:7)(cid:12)(cid:13)(cid:14)(cid:15)(cid:9)1(cid:17)(cid:7)(cid:11)(cid:9)2+(cid:4)(cid:5)(cid:14)+(cid:6)(cid:9)(cid:24)%(cid:10)(cid:26)(cid:9)(cid:27)(cid:9)0(cid:30)(cid:30)(cid:9)!(cid:14)(cid:11)(cid:9)"(cid:21)(cid:8)#(cid:9)$%(cid:10)12(cid:10)& (cid:20)(cid:21)(cid:13)(cid:6), (cid:31)(cid:10)(cid:9)(cid:2) (cid:11)(cid:14)(cid:2)!(cid:10)" (cid:2)(cid:8)#(cid:9)(cid:9)(cid:14)(cid:15) (cid:2)(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)%(cid:9)(cid:28)&(cid:7)(cid:15)(cid:17)"’(cid:2)(cid:12)(cid:16)(cid:14)(cid:28)"(cid:14)(cid:2)"(cid:14)(cid:14)(cid:2) (cid:11)(cid:14)(cid:2)(cid:6)(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17)(cid:2)(cid:22)(cid:12)(cid:14)(cid:8)(cid:7))(cid:7)(cid:8)(cid:28) (cid:7)(cid:10)(cid:15)(cid:2)(cid:16)(cid:10)(cid:8)(cid:28) (cid:14)%(cid:2)(cid:28) (cid:2) (cid:11) (cid:12)*++&&&(cid:20)!(cid:7)(cid:8)(cid:9)(cid:10)(cid:8)(cid:11)(cid:7)(cid:12)(cid:20)(cid:8)(cid:10)!+(cid:12)(cid:28)(cid:8)$(cid:28)(cid:17)(cid:7)(cid:15)(cid:17) N NOTE1 E1 1 2 3 D E A A2 L c A1 b1 b e eB 5(cid:15)(cid:7) " (cid:19)74;0(cid:22) (cid:21)(cid:7)!(cid:14)(cid:15)"(cid:7)(cid:10)(cid:15)(cid:2)6(cid:7)!(cid:7) " (cid:6)(cid:19)7 78(cid:6) (cid:6)(cid:25)9 7#!/(cid:14)(cid:9)(cid:2)(cid:10))(cid:2)((cid:7)(cid:15)" 7 (cid:3): ((cid:7) (cid:8)(cid:11) (cid:14) (cid:20)(cid:29)(cid:4)(cid:4)(cid:2)3(cid:22)4 (cid:13)(cid:10)(cid:12)(cid:2) (cid:10)(cid:2)(cid:22)(cid:14)(cid:28) (cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) (cid:25) < < (cid:20)(cid:3)(cid:4)(cid:4) (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:25)(cid:3) (cid:20)(cid:29)(cid:3)(cid:4) (cid:20)(cid:29)(cid:30)2 (cid:20)(cid:29)2(cid:4) 3(cid:28)"(cid:14)(cid:2) (cid:10)(cid:2)(cid:22)(cid:14)(cid:28) (cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) (cid:25)(cid:29) (cid:20)(cid:4)(cid:29)2 < < (cid:22)(cid:11)(cid:10)#(cid:16)%(cid:14)(cid:9)(cid:2) (cid:10)(cid:2)(cid:22)(cid:11)(cid:10)#(cid:16)%(cid:14)(cid:9)(cid:2)=(cid:7)% (cid:11) 0 (cid:20)(cid:3)(cid:24)(cid:4) (cid:20)(cid:30)(cid:29)(cid:4) (cid:20)(cid:30)(cid:30)2 (cid:6)(cid:10)(cid:16)%(cid:14)%(cid:2)((cid:28)(cid:8)$(cid:28)(cid:17)(cid:14)(cid:2)=(cid:7)% (cid:11) 0(cid:29) (cid:20)(cid:3)(cid:23)(cid:4) (cid:20)(cid:3):2 (cid:20)(cid:3)(cid:24)2 8-(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)6(cid:14)(cid:15)(cid:17) (cid:11) (cid:21) (cid:29)(cid:20)(cid:30)(cid:23)2 (cid:29)(cid:20)(cid:30),2 (cid:29)(cid:20)(cid:23)(cid:4)(cid:4) (cid:13)(cid:7)(cid:12)(cid:2) (cid:10)(cid:2)(cid:22)(cid:14)(cid:28) (cid:7)(cid:15)(cid:17)(cid:2)((cid:16)(cid:28)(cid:15)(cid:14) 6 (cid:20)(cid:29)(cid:29)(cid:4) (cid:20)(cid:29)(cid:30)(cid:4) (cid:20)(cid:29)2(cid:4) 6(cid:14)(cid:28)%(cid:2)(cid:13)(cid:11)(cid:7)(cid:8)$(cid:15)(cid:14)"" (cid:8) (cid:20)(cid:4)(cid:4): (cid:20)(cid:4)(cid:29)(cid:4) (cid:20)(cid:4)(cid:29)2 5(cid:12)(cid:12)(cid:14)(cid:9)(cid:2)6(cid:14)(cid:28)%(cid:2)=(cid:7)% (cid:11) /(cid:29) (cid:20)(cid:4)(cid:23)(cid:4) (cid:20)(cid:4)2(cid:4) (cid:20)(cid:4)(cid:5)(cid:4) 6(cid:10)&(cid:14)(cid:9)(cid:2)6(cid:14)(cid:28)%(cid:2)=(cid:7)% (cid:11) / (cid:20)(cid:4)(cid:29)(cid:23) (cid:20)(cid:4)(cid:29): (cid:20)(cid:4)(cid:3)(cid:3) 8-(cid:14)(cid:9)(cid:28)(cid:16)(cid:16)(cid:2)(cid:26)(cid:10)&(cid:2)(cid:22)(cid:12)(cid:28)(cid:8)(cid:7)(cid:15)(cid:17)(cid:2)(cid:2)? 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DS30010038C-page 417

PIC24FJ128GA204 FAMILY DS30010038C-page 418  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY  2013-2015 Microchip Technology Inc. DS30010038C-page 419

PIC24FJ128GA204 FAMILY DS30010038C-page 420  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D1 B NOTE 2 (DATUM A) (DATUM B) E1 E A A NOTE 1 2X N 0.20 H A B 2X 1 2 3 0.20 H A B TOP VIEW 4X 11 TIPS 0.20 C A B A A2 C SEATING PLANE 0.10 C A1 SIDE VIEW 1 2 3 N NOTE 1 44 X b 0.20 C A B e BOTTOM VIEW Microchip Technology Drawing C04-076C Sheet 1 of 2  2013-2015 Microchip Technology Inc. DS30010038C-page 421

PIC24FJ128GA204 FAMILY 44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging H c θ L (L1) SECTION A-A Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Leads N 44 Lead Pitch e 0.80 BSC Overall Height A - - 1.20 Standoff A1 0.05 - 0.15 Molded Package Thickness A2 0.95 1.00 1.05 Overall Width E 12.00 BSC Molded Package Width E1 10.00 BSC Overall Length D 12.00 BSC Molded Package Length D1 10.00 BSC Lead Width b 0.30 0.37 0.45 Lead Thickness c 0.09 - 0.20 Lead Length L 0.45 0.60 0.75 Footprint L1 1.00 REF Foot Angle θ 0° 3.5° 7° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Exact shape of each corner is optional. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076C Sheet 2 of 2 DS30010038C-page 422  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013-2015 Microchip Technology Inc. DS30010038C-page 423

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 424  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY APPENDIX A: REVISION HISTORY Revision C (March 2015) This revision incorporates the following updates: Revision A (July 2013) • Registers: Original data sheet for the PIC24FJ128GA204 family of - Register25-1 devices. • Tables: - Table32-4, Table32-5, Table32-6 and Revision B (May 2014) Table32-21 This revision incorporates the following updates: • Package Marking examples in Section33.0 “Packaging Information” were updated • Sections: - Added Section16.5 “Audio Mode” and Section16.6 “Registers” Section16.1 “Standard Master Mode”, Section16.2 “Standard Slave Mode”, Section16.3 “Enhanced Master Mode” and Section16.4 “Enhanced Slave Mode” - Added Section18.9 “Registers” - Updated Section17.3 “Slave Address Masking”, - Updated Section29.3.1 “Windowed Operation” • Registers: - Updated Register8-45, Register11-2, Register11-29, Register16-6, Register16-7, Register17-1, Register17-2, Register18-2, Register18-4, Register18-6, Register22-5 - Updated note in Section18.0 “Universal Asynchronous Receiver Transmitter (UART)” - Updated Sections: Section18.5 “Receiving in 8-Bit or 9-Bit Data Mode” • Tables: - Included Table32-22, Table32-23, Table32-24 and Table32-25 - Updated Tables:Table4-4, Table4-6, Table4-9, Table4-10, Table4-11, Table4-12, Table4-13, Table4-28, Table32-3, Table32-4, Table32-5, Table32-6, Table32-7, Table32-8, Table32-10, Table32-12, Table32-13, Table32-14, Table32-15, Table32-16 and Table32-20 • Figures: - Included Figure32-5, Figure32-6, Figure32-7 and Figure32-8 • Examples: - Updated Example21-1 • Packaging diagrams in Section33.0 “Packaging Information” were updated • Changes to text and formatting were incorporated throughout the document  2013-2015 Microchip Technology Inc. DS30010038C-page 425

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 426  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY INDEX A CTMU Typical Connections and Internal Configuration for Pulse Delay Generation........341 A/D CTMU Typical Connections and Internal Control Registers......................................................314 Configuration for Time Measurement...............341 Extended DMA Operations.......................................313 Data Access from Program Space Address Operation..................................................................311 Generation..........................................................63 Transfer Functions Data Signal Modulator..............................................257 10-Bit................................................................330 Direct Memory Access (DMA)....................................67 12-Bit................................................................329 EDS Address Generation for Read............................59 AC Characteristics EDS Address Generation for Write.............................60 A/D Conversion Timing.............................................406 Extended Data Space (EDS)......................................58 A/D Module Specifications........................................405 High/Low-Voltage Detect (HLVD).............................347 and Timing Parameters.............................................387 I2Cx Module.............................................................238 Capacitive Loading on Output Pins...........................387 Individual Comparator Configurations, CLKO and I/O Timing Requirements........................394 CREF = 0..........................................................332 External Clock Timing Requirements........................388 I2C Bus Data (Master Mode).............................390, 391 Individual Comparator Configurations, I2C Bus Data (Slave Mode).......................................393 CREF = 1, CVREFP = 0...................................333 I2C Bus Start/Stop Bit (Slave Mode).........................392 Individual Comparator Configurations, CREF = 1, CVREFP = 1...................................333 Input Capture x Timing Requirements......................398 Input Capture x Module............................................205 Internal RC Accuracy................................................389 MCLR Pin Connections..............................................22 Load Conditions and Requirements for On-Chip Regulator Connections...............................359 Specifications....................................................387 Output Compare x (16-Bit Mode).............................212 Output Compare x Requirements.............................398 Output Compare x (Double-Buffered, PLL Clock Timing Specifications...............................389 16-Bit PWM Mode)...........................................214 RC Oscillator Start-up Time......................................394 PIC24F CPU Core......................................................28 Reset and Brown-out Reset Requirements..............395 PIC24FJ128GA204 Family (General).........................13 Simple OCx/PWM Mode Requirements....................399 PSV Operation Access (Lower Word)........................66 SPIx Master Mode (CKE = 0) Requirements............400 PSV Operation Access (Upper Word)........................66 SPIx Master Mode (CKE = 1) Requirements............401 Recommended Minimum Connections.......................21 SPIx Slave Mode (CKE = 0) Requirements..............402 Reset System.............................................................81 SPIx Slave Mode (CKE = 1) Requirements..............404 RTCC Module...........................................................275 Timer1 External Clock Requirements.......................396 Shared I/O Port Structure.........................................167 Timer2 and Timer4 External Clock Smart Card Subsystem Connection.........................249 Requirements...................................................397 SPIx Master, Frame Master Connection..................235 Timer3 and Timer5 External Clock SPIx Master, Frame Slave Connection....................236 Requirements...................................................397 SPIx Master/Slave Connection Alternate Interrupt Vector Table (AIVT)..............................87 (Enhanced Buffer Modes).................................235 Assembler SPIx Master/Slave Connection MPASM Assembler...................................................364 (Standard Mode)...............................................234 B SPIx Module (Enhanced Mode)................................223 Block Diagrams SPIx Module (Standard Mode).................................222 10-Bit A/D Converter Analog Input Model.................328 SPIx Slave, Frame Master Connection....................236 12-Bit A/D Converter.................................................312 SPIx Slave, Frame Slave Connection......................236 16-Bit Asynchronous Timer3/5..................................201 System Clock............................................................141 16-Bit Synchronous Timer2/4...................................201 Timer2/3 and Timer4/5 (32-Bit)................................200 16-Bit Timer1 Module................................................195 Triple Comparator Module........................................331 Accessing Program Space Using UARTx (Simplified)...................................................246 Table Instructions...............................................64 Watchdog Timer (WDT)............................................360 Addressing for Table Registers...................................75 C Buffer Address Generation in PIA Mode...................315 C Compilers CALL Stack Frame......................................................61 MPLAB XC Compilers..............................................364 Comparator Voltage Reference Module...................337 Charge Time Measurement Unit. See CTMU. CPU Programmer’s Model..........................................29 CRC Module.............................................................305 CRC Shift Engine Detail............................................305 Cryptographic Engine...............................................289 CTMU Connections and Internal Configuration for Capacitance Measurement..........................340  2013-2015 Microchip Technology Inc. DS30010038C-page 427

PIC24FJ128GA204 FAMILY Code Examples D Basic Clock Switching Sequence..............................148 Data Memory Configuring UART1 Input/Output Functions.............176 Address Space...........................................................35 EDS Read from Program Memory in Assembly..........65 Extended Data Space (EDS)......................................58 EDS Read in Assembly...............................................59 Memory Map...............................................................35 EDS Write in Assembly...............................................60 Near Data Space........................................................36 Erasing a Program Memory Block (Assembly)...........78 SFR Space.................................................................36 Erasing a Program Memory Block (C Language).......79 Software Stack...........................................................61 Initiating a Programming Sequence............................79 Space Organization, Alignment..................................36 Loading the Write Buffers...........................................79 Data Signal Modulator (DSM)...........................................257 Port Read/Write in Assembly....................................171 Data Signal Modulator. See DSM. Port Read/Write in C.................................................171 DC Characteristics PWRSAV Instruction Syntax.....................................156 Comparator Specifications........................................385 Repeat Sequence.....................................................158 Comparator Voltage Reference Specifications.........385 Setting the RTCWREN Bit........................................276 CTMU Current Source Specifications.......................386 Single-Word Flash Programming................................80  Current (BOR, WDT, DSBOR, DSWDT)...............381 Single-Word Flash Programming (C Language).........80 High/Low-Voltage Detect..........................................384 Code Protection................................................................361 I/O Pin Input Specifications.......................................382 Code Segment Protection.........................................361 I/O Pin Output Specifications....................................383 Configuration Options.......................................361 Idle Current (IIDLE)....................................................379 Configuration Register Protection.............................362 Internal Voltage Regulator Specifications.................384 General Segment Protection.....................................361 Operating Current (IDD)............................................378 Comparator Voltage Reference........................................337 Power-Down Current (IPD)........................................380 Configuring................................................................337 Program Memory......................................................383 Configuration Bits..............................................................349 Temperature and Voltage Specifications..................377 Core Features.......................................................................9 Thermal Operating Conditions..................................376 CPU Thermal Packaging...................................................376 Arithmetic Logic Unit (ALU).........................................32 VBAT Operating Voltage Specifications.....................386 Control Registers........................................................30 Demo/Development Boards, Evaluation Core Registers............................................................28 and Starter Kits.........................................................366 Programmer’s Model...................................................27 Development Support.......................................................363 CRC Third-Party Tools......................................................366 Polynomials...............................................................306 Device Features Setup Examples for 16 and 32-Bit Polynomials........306 28-Pin Devices............................................................12 User Interface...........................................................306 44-Pin Devices............................................................11 Cryptographic Engine..................................................10, 289 Direct Memory Access Controller. See DMA. Data Register Spaces...............................................290 DMA....................................................................................67 Decrypting Data........................................................291 Channel Trigger Sources............................................74 Enabling....................................................................290 Control Registers........................................................70 Encrypting Data........................................................291 Peripheral Module Disable (PMD)..............................70 Operation Modes......................................................290 Summary of Operations..............................................68 Idle....................................................................291 Types of Data Transfers.............................................69 Sleep.................................................................290 Typical Setup..............................................................70 Programming DMA Controller...................................................................10 CFGPAGE Configuration Bits...........................294 DSM Keys..................................................................294 Verifying Keys...................................................294 E Pseudorandom Number Generation (PRN)..............293 Electrical Characteristics Random Number Generation....................................293 Absolute Maximum Ratings......................................375 Session Keys V/F Graph (Industrial)...............................................376 Encrypting.........................................................292 Enhanced Parallel Master Port (EPMP)...........................263 Receiving..........................................................292 Enhanced Parallel Master Port. See EPMP. Testing Key Source Configuration............................293 EPMP CTMU Key Features............................................................263 Measuring Capacitance............................................339 Memory Addressable in Different Modes..................263 Measuring Time........................................................341 Pin Descriptions........................................................265 Pulse Generation and Delay.....................................341 Customer Change Notification Service.............................433 Customer Notification Service...........................................433 Customer Support.............................................................433 Cyclic Redundancy Check. See CRC. DS30010038C-page 428  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY Equations Input Capture with Dedicated Timers...............................205 16-Bit, 32-Bit CRC Polynomials................................306 Instruction Set A/D Conversion Clock Period...................................328 Overview...................................................................369 Baud Rate Reload Calculation..................................239 Summary..................................................................367 Calculating the PWM Period.....................................214 Symbols Used in Opcode Descriptions....................368 Calculation for Maximum PWM Resolution...............215 Interfacing Program and Data Spaces................................62 Fractional Divisor for ROTRIMx Bits.........................149 Inter-Integrated Circuit. See I2C. Relationship Between Device and Internet Address...............................................................433 SPIx Clock Speed.............................................236 Interrupt Vector Table (IVT)................................................87 UARTx Baud Rate with BRGH = 0...........................247 Interrupts UARTx Baud Rate with BRGH = 1...........................247 Control and Status Registers......................................91 Errata....................................................................................7 Implemented Vectors..................................................89 Extended Data Space (EDS)............................................263 Reset Sequence.........................................................87 Setup and Service Procedures.................................140 F Trap Vectors...............................................................88 Flash Configuration Word Locations.................................349 Vector Table...............................................................88 Flash Configuration Words.................................................34 J Flash Program Memory......................................................75 and Table Instructions.................................................75 JTAG Interface.................................................................362 Control Registers........................................................76 K Enhanced ICSP Operation..........................................76 JTAG Operation..........................................................76 Key Features....................................................................349 Programming Algorithm..............................................78 L Programming Operations............................................76 RTSP Operation..........................................................76 Low-Voltage/Retention Regulator.....................................157 Single-Word Programming..........................................80 M G Memory Organization.........................................................33 Getting Started with 16-Bit MCUs.......................................21 Microchip Internet Web Site..............................................433 Basic Connection Requirements.................................21 MPLAB Assembler, Linker, Librarian................................364 Configuration of Analog/Digital Pins During ICSP......26 MPLAB ICD 3 In-Circuit Debugger...................................365 External Oscillator Pins...............................................25 MPLAB PM3 Device Programmer....................................365 ICSP Pins....................................................................24 MPLAB REAL ICE In-Circuit Emulator System................365 Master Clear (MCLR) Pin............................................22 MPLAB X Integrated Development Power Supply Pins......................................................22 Environment Software..............................................363 Unused I/Os................................................................26 MPLAB X SIM Software Simulator...................................365 Voltage Regulator Pins...............................................23 MPLIB Object Librarian.....................................................364 MPLINK Object Linker......................................................364 H N High/Low-Voltage Detect (HLVD).....................................347 High/Low-Voltage Detect. See HLVD. Near Data Space................................................................36 I O I/O Ports On-Chip Voltage Regulator...............................................359 Analog Port Pins Configuration (ANSx)....................168 POR..........................................................................359 Configuring Analog/Digital Function of I/O Pin..........168 Standby Mode..........................................................359 Input Change Notification (ICN)................................171 Oscillator Input Voltage Levels for Port/Pin Tolerated Clock Switching Operation.......................................147 Description Input...............................................168 Sequence.........................................................147 Open-Drain Configuration.........................................168 Configuration Bit Values for Clock Selection............142 Parallel (PIO)............................................................167 Control Registers......................................................143 Peripheral Pin Select................................................172 FRC Self-Tuning.......................................................148 Pull-ups and Pull-Downs...........................................171 Initial Configuration on POR.....................................142 Selectable Input Sources..........................................173 Initial CPU Clocking Scheme....................................142 Selectable Output Sources.......................................174 On-Chip PLL.............................................................153 Write/Read Timing....................................................168 Reference Clock Output...........................................149 I2C Output Compare Communicating as Master in 32-Bit Cascaded Mode.............................................211 Single Master Environment...............................237 Operations................................................................212 Reserved Addresses.................................................239 Synchronous and Trigger Modes.............................211 Setting Baud Rate as Bus Master.............................239 Output Compare with Dedicated Timers...........................211 Slave Address Masking............................................239 Input Capture 32-Bit Cascaded Mode.............................................206 Operations................................................................206 Synchronous and Trigger Modes..............................205  2013-2015 Microchip Technology Inc. DS30010038C-page 429

PIC24FJ128GA204 FAMILY P Peripheral Pin Select..................................................54 PORTA.......................................................................48 Packaging.........................................................................407 PORTB.......................................................................48 Details.......................................................................409 PORTC.......................................................................48 Marking.....................................................................407 Real-Time Clock and Calendar (RTCC).....................53 Peripheral Pin Select (PPS)..............................................172 SPI1............................................................................46 Available Peripherals and Pins.................................172 SPI2............................................................................46 Configuration Control................................................175 SPI3............................................................................47 Considerations for Use.............................................176 System Control (Clock and Reset).............................55 Control Registers......................................................177 Timers.........................................................................41 Input Mapping...........................................................173 UART..........................................................................45 Mapping Exceptions..................................................175 Registers Output Mapping........................................................174 AD1CHITL (A/D Scan Compare Hit, Low Word)......325 Peripheral Priority.....................................................172 AD1CHS (A/D Sample Select)..................................323 PICkit 3 In-Circuit Debugger/Programmer........................365 AD1CON1 (A/D Control 1)........................................316 Pinout Descriptions.............................................................14 AD1CON2 (A/D Control 2)........................................318 Power-Saving Features.....................................................155 AD1CON3 (A/D Control 3)........................................320 Clock Frequency, Clock Switching............................165 AD1CON4 (A/D Control 4)........................................321 Doze Mode................................................................165 AD1CON5 (A/D Control 5)........................................322 Instruction-Based Modes..........................................156 AD1CSSH (A/D Input Scan Select, High Word).......326 Deep Sleep.......................................................158 AD1CSSL (A/D Input Scan Select, Low Word).........326 Idle....................................................................157 AD1CTMENL (CTMU Enable, Low Word)................327 Sleep.................................................................157 ALCFGRPT (Alarm Configuration)...........................280 Overview of Modes...................................................155 ALMINSEC (Alarm Minutes and VBAT Mode................................................................160 Seconds Value)................................................284 Product Identification System............................................435 ALMTHDY (Alarm Month and Day Value)................283 Program Memory ALWDHR (Alarm Weekday and Hours Value)..........283 Access Using Table Instructions.................................64 ANCFG (A/D Band Gap Address Construction..................................................62 Reference Configuration).................................324 Address Space............................................................33 ANSA (PORTA Analog Function Selection).............169 Flash Configuration Words.........................................34 ANSB (PORTB Analog Function Selection).............169 Hard Memory Vectors.................................................34 ANSC (PORTC Analog Function Selection).............170 Memory Maps.............................................................33 CFGPAGE (Secure Array Configuration Bits)..........300 Organization................................................................34 CLKDIV (Clock Divider)............................................145 Reading from Program Memory Using EDS...............65 CMSTAT (Comparator Status).................................335 Program Verification..........................................................361 CMxCON (Comparator x Control, Programmable Cyclic Redundancy Check (CRC) Comparators 1-3).............................................334 Generator..................................................................305 CORCON (CPU Core Control).............................31, 93 Pulse-Width Modulation (PWM) Mode..............................213 CRCCON1 (CRC Control 1).....................................308 Pulse-Width Modulation. See PWM. CRCCON2 (CRC Control 2).....................................309 PWM CRCXORH (CRC XOR Polynomial, High Byte).......310 Duty Cycle and Period..............................................214 CRCXORL (CRC XOR Polynomial, Low Byte).........310 R CRYCONH (Cryptographic Control High).................297 Real-Time Clock and Calendar (RTCC)............................275 CRYCONL (Cryptographic Control Low)..................295 Real-Time Clock and Calendar. See RTCC. CRYOTP (Cryptographic OTP Page Register Maps Program Control)..............................................299 A/D Converter.............................................................49 CRYSTAT (Cryptographic Status)............................298 Analog Configuration..................................................50 CTMUCON1 (CTMU Control 1)................................342 Comparator.................................................................53 CTMUCON2 (CTMU Control 2)................................343 CPU Core....................................................................37 CTMUICON (CTMU Current Control).......................345 CRC............................................................................54 CVRCON (Comparator Voltage Cryptographic Engine.................................................56 Reference Control)...........................................338 CTMU..........................................................................50 CW1 (Flash Configuration Word 1)...........................350 Data Signal Modulator (DSM).....................................53 CW2 (Flash Configuration Word 2)...........................352 Deep Sleep.................................................................56 CW3 (Flash Configuration Word 3)...........................354 DMA............................................................................51 CW4 (Flash Configuration Word 4)...........................356 Enhanced Parallel Master/Slave Port.........................52 DEVID (Device ID)....................................................358 I2C...............................................................................44 DEVREV (Device Revision)......................................358 ICN..............................................................................38 DMACHn (DMA Channel n Control)...........................72 Input Capture..............................................................42 DMACON (DMA Engine Control)................................71 Interrupt Controller......................................................39 DMAINTn (DMA Channel n Interrupt).........................73 NVM............................................................................56 DSCON (Deep Sleep Control)..................................162 Output Compare.........................................................43 DSWAKE (Deep Sleep Wake-up Source)................163 Pad Configuration (PADCFG1)...................................48 HLVDCON (High/Low-Voltage Detect Control)........348 Peripheral Module Disable (PMD)..............................57 I2CxCONH (I2Cx Control High)................................242 DS30010038C-page 430  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY I2CxCONL (I2Cx Control Low)..................................240 PMCSxMD (EPMP Chip Select x Mode)..................272 I2CxMSK (I2Cx Slave Mode Address Mask)............244 PMSTAT (EPMP Status, Slave Mode).....................273 I2CxSTAT (I2Cx Status)...........................................243 RCFGCAL (RTCC Calibration ICxCON1 (Input Capture x Control 1).......................207 and Configuration)............................................277 ICxCON2 (Input Capture x Control 2).......................208 RCON (Reset Control)................................................82 IEC0 (Interrupt Enable Control 0).............................106 RCON2 (Reset and System Control 2)...............84, 164 IEC1 (Interrupt Enable Control 1).............................108 REFOCONH (Reference Oscillator IEC2 (Interrupt Enable Control 2).............................110 Control High)....................................................151 IEC3 (Interrupt Enable Control 3).............................112 REFOCONL (Reference Oscillator IEC4 (Interrupt Enable Control 4).............................114 Control Low).....................................................150 IEC5 (Interrupt Enable Control 5).............................115 REFOTRIML (Reference Oscillator Trim).................152 IEC6 (Interrupt Enable Control 6).............................116 RPINR0 (PPS Input 0)..............................................177 IEC7 (Interrupt Enable Control 7).............................116 RPINR1 (PPS Input 1)..............................................177 IFS0 (Interrupt Flag Status 0).....................................96 RPINR11 (PPS Input 11)..........................................180 IFS1 (Interrupt Flag Status 1).....................................98 RPINR17 (PPS Input 17)..........................................180 IFS2 (Interrupt Flag Status 2)...................................100 RPINR18 (PPS Input 18)..........................................181 IFS3 (Interrupt Flag Status 3)...................................102 RPINR19 (PPS Input 19)..........................................181 IFS4 (Interrupt Flag Status 4)...................................103 RPINR2 (PPS Input 2)..............................................178 IFS5 (Interrupt Flag Status 5)...................................104 RPINR20 (PPS Input 20)..........................................182 IFS6 (Interrupt Flag Status 6)...................................105 RPINR21 (PPS Input 21)..........................................182 IFS7 (Interrupt Flag Status 7)...................................105 RPINR22 (PPS Input 22)..........................................183 INTCON1 (Interrupt Control 1)....................................94 RPINR23 (PPS Input 23)..........................................183 INTCON2 (Interrupt Control 2)....................................95 RPINR27 (PPS Input 27)..........................................184 INTTREG (Interrupt Controller Test).........................139 RPINR28 (PPS Input 28)..........................................184 IPC0 (Interrupt Priority Control 0).............................117 RPINR29 (PPS Input 29)..........................................185 IPC1 (Interrupt Priority Control 1).............................118 RPINR30 (PPS Input 30)..........................................185 IPC10 (Interrupt Priority Control 10).........................127 RPINR31 (PPS Input 31)..........................................186 IPC11 (Interrupt Priority Control 11).........................128 RPINR7 (PPS Input 7)..............................................178 IPC12 (Interrupt Priority Control 12).........................129 RPINR8 (PPS Input 8)..............................................179 IPC13 (Interrupt Priority Control 13).........................130 RPINR9 (PPS Input 9)..............................................179 IPC14 (Interrupt Priority Control 14).........................131 RPOR0 (PPS Output 0)............................................187 IPC15 (Interrupt Priority Control 15).........................132 RPOR1 (PPS Output 1)............................................187 IPC16 (Interrupt Priority Control 16).........................133 RPOR10 (PPS Output 10)........................................192 IPC18 (Interrupt Priority Control 18).........................134 RPOR11 (PPS Output 11)........................................192 IPC19 (Interrupt Priority Control 19).........................134 RPOR12 (PPS Output 12)........................................193 IPC2 (Interrupt Priority Control 2).............................119 RPOR2 (PPS Output 2)............................................188 IPC20 (Interrupt Priority Control 20).........................135 RPOR3 (PPS Output 3)............................................188 IPC21 (Interrupt Priority Control 21).........................136 RPOR4 (PPS Output 4)............................................189 IPC22 (Interrupt Priority Control 22).........................137 RPOR5 (PPS Output 5)............................................189 IPC26 (Interrupt Priority Control 26).........................138 RPOR6 (PPS Output 6)............................................190 IPC29 (Interrupt Priority Control 29).........................138 RPOR7 (PPS Output 7)............................................190 IPC3 (Interrupt Priority Control 3).............................120 RPOR8 (PPS Output 8)............................................191 IPC4 (Interrupt Priority Control 4).............................121 RPOR9 (PPS Output 9)............................................191 IPC5 (Interrupt Priority Control 5).............................122 RTCCSWT (RTCC Power Control and IPC6 (Interrupt Priority Control 6).............................123 Sample Window Timer)....................................285 IPC7 (Interrupt Priority Control 7).............................124 RTCPWC (RTCC Power Control).............................279 IPC8 (Interrupt Priority Control 8).............................125 SPIxCON1H (SPIx Control 1 High)..........................226 IPC9 (Interrupt Priority Control 9).............................126 SPIxCON1L (SPIx Control 1 Low)............................224 MDCAR (DSM Carrier Control).................................260 SPIxCON2L (SPIx Control 2 Low)............................228 MDCON (DSM Control)............................................258 SPIxIMSKH (SPIx Interrupt Mask High)...................233 MDSRC (DSM Source Control)................................259 SPIxIMSKL (SPIx Interrupt Mask Low).....................232 MINSEC (RTCC Minutes and Seconds Value).........282 SPIxSTATH (SPIx Status High)................................231 MTHDY (RTCC Month and Day Value)....................281 SPIxSTATL (SPIx Status Low).................................229 NVMCON (Flash Memory Control).............................77 SR (ALU STATUS)...............................................30, 92 OCxCON1 (Output Compare x Control 1)................216 T1CON (Timer1 Control)..........................................196 OCxCON2 (Output Compare x Control 2)................218 TxCON (Timer2/4 Control).......................................202 OSCCON (Oscillator Control)...................................143 TyCON (Timer3/5 Control).......................................204 OSCTUN (FRC Oscillator Tune)...............................146 UxADMD (UARTx Address Match Detect)...............254 PADCFG1 (Pad Configuration Control)....................274 UxMODE (UARTx Mode).........................................250 PMCON1 (EPMP Control 1).....................................266 UxSCCON (UARTx Smart Card Control).................255 PMCON2 (EPMP Control 2).....................................267 UxSCINT (UARTx Smart Card Interrupt)..................256 PMCON3 (EPMP Control 3).....................................268 UxSTA (UARTx Status and Control)........................252 PMCON4 (EPMP Control 4).....................................269 UxTXREG (UARTx Transmit)...................................254 PMCSxBS (EPMP Chip Select x Base Address)......271 WKDYHR (RTCC Weekday and Hours Value)........282 PMCSxCF (EPMP Chip Select x Configuration).......270 YEAR (RTCC Year Value)........................................281  2013-2015 Microchip Technology Inc. DS30010038C-page 431

PIC24FJ128GA204 FAMILY Resets T BOR (Brown-out Reset)..............................................81 Timer1...............................................................................195 Brown-out Reset (BOR)..............................................85 Timer2/3 and Timer4/5.....................................................199 Clock Source Selection...............................................85 Timing Diagrams CM (Configuration Mismatch Reset)...........................81 CLKO and I/O Characteristics..................................394 Delay Times................................................................86 External Clock...........................................................388 Device Times..............................................................85 I2C Bus Data (Master Mode)....................................391 IOPUWR (Illegal Opcode Reset)................................81 I2C Bus Data (Slave Mode)......................................393 MCLR (Master Clear Pin Reset).................................81 I2C Bus Start/Stop Bits (Master Mode).....................390 POR (Power-on Reset)...............................................81 I2C Bus Start/Stop Bits (Slave Mode).......................392 RCON Flags, Operation..............................................84 Input Capture x (ICx)................................................398 SFR States..................................................................85 OCx/PWM Characteristics........................................399 SWR (RESET Instruction)...........................................81 Output Compare x (OCx)..........................................398 TRAPR (Trap Conflict Reset)......................................81 SPIx Master Mode (CKE = 0)...................................400 UWR (Uninitialized W Register Reset)........................81 SPIx Master Mode (CKE = 1)...................................401 WDT (Watchdog Timer Reset)....................................81 SPIx Slave Mode (CKE = 0).....................................402 Revision History................................................................425 SPIx Slave Mode (CKE = 1).....................................403 RTCC Timer1, 2, 3, 4, 5 External Clock..............................396 Alarm Configuration..................................................286 Triple Comparator Module................................................331 Alarm Mask Settings (figure).....................................287 Calibration.................................................................286 U Clock Source Selection.............................................276 UART Control Registers......................................................277 Baud Rate Error Calculation.....................................247 Module Registers......................................................276 Baud Rate Generator (BRG)....................................247 Power Control...........................................................287 Control Registers......................................................250 Register Mapping......................................................276 Infrared Support........................................................248 Source Clock.............................................................275 Operation of UxCTS and UxRTS Pins......................248 VBAT Operation.........................................................287 Receiving Write Lock.................................................................276 8-Bit or 9-Bit Data Mode...................................248 S Smart Card ISO 7816 Support..................................249 Transmitting Selective Peripheral Module Control.................................165 8-Bit Data Mode................................................248 Serial Peripheral Interface (SPI).......................................221 9-Bit Data Mode................................................248 Serial Peripheral Interface. See SPI. Break and Sync Sequence...............................248 SFR Space..........................................................................36 Universal Asynchronous Receiver Transmitter. See UART. Software Stack....................................................................61 Special Features.................................................................10 W SPI Watchdog Timer (WDT)....................................................360 Audio Mode...............................................................224 Control Register........................................................360 Control Registers......................................................224 Windowed Operation................................................360 Enhanced Master Mode............................................223 WWW Address.................................................................433 Enhanced Slave Mode..............................................223 WWW, On-Line Support.......................................................7 Standard Master Mode.............................................222 Standard Slave Mode...............................................222 DS30010038C-page 432  2013-2015 Microchip Technology Inc.

PIC24FJ FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at Users of Microchip products can receive assistance www.microchip.com. This web site is used as a means through several channels: to make files and information easily available to • Distributor or Representative customers. Accessible by using your favorite Internet • Local Sales Office browser, the web site contains the following • Field Application Engineer (FAE) information: • Technical Support • Product Support – Data sheets and errata, application notes and sample programs, design Customers should contact their distributor, resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for documents, latest software releases and archived support. Local sales offices are also available to help software customers. A listing of sales offices and locations is included in the back of this document. • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, Technical support is available through the web site online discussion groups, Microchip consultant at: http://microchip.com/support program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2013-2015 Microchip Technology Inc. DS30010038C-page 433

PIC24FJ FAMILY NOTES: DS30010038C-page 434  2013-2015 Microchip Technology Inc.

PIC24FJ128GA204 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 128 GA2 04 T - I / PT - XXX Examples: a) PIC24FJ128GA202-I/MM: Microchip Trademark PIC24F device with 128-Kbyte program memory, 8-Kbyte data memory, 28-pin, Architecture Industrial temp., QFN-S package. Flash Memory Family b) PIC24FJ128GA204-I/PT: PIC24F device with 128-Kbyte program Program Memory Size (Kbyte) memory, 8-Kbyte data memory, 44-pin, Product Group Industrial temp., TQFP package. Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family FJ = Flash program memory Product Group GA2= General purpose microcontrollers Pin Count 02 = 28-pin 04 = 44-pin Temperature Range I = -40C to +85C (Industrial) E = -40C to +125C (Extended) Package MM = 28-lead (6x6x0.9 mm) QFN-S (Quad Flat) ML = 44-lead (8x8 mm) QFN (Quad Flat) PT = 44-lead (10x10x1 mm) TQFP (Thin Quad Flatpack) SO = 28-lead (7.50 mm wide) SOIC (Small Outline) SP = 28-lead (300 mil) SPDIP (Skinny Plastic Dual In-Line) SS = 28-lead (5.30 mm) SSOP (Plastic Shrink Small Outline) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2013-2015 Microchip Technology Inc. DS30010038C-page 435

PIC24FJ128GA204 FAMILY NOTES: DS30010038C-page 436  2013-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, ensure that your application meets with your specifications. LANCheck, MediaLB, MOST, MOST logo, MPLAB, MICROCHIP MAKES NO REPRESENTATIONS OR OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, WARRANTIES OF ANY KIND WHETHER EXPRESS OR SST, SST Logo, SuperFlash and UNI/O are registered IMPLIED, WRITTEN OR ORAL, STATUTORY OR trademarks of Microchip Technology Incorporated in the OTHERWISE, RELATED TO THE INFORMATION, U.S.A. and other countries. INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR The Embedded Control Solutions Company and mTouch are FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated arising from this information and its use. Use of Microchip in the U.S.A. devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, the buyer’s risk, and the buyer agrees to defend, indemnify and CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit hold harmless Microchip from any and all damages, claims, Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, suits, or expenses resulting from such use. No licenses are KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, conveyed, implicitly or otherwise, under any Microchip MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code intellectual property rights. Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-205-3 QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures == ISO/TS 16949 == are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2013-2015 Microchip Technology Inc. DS30010038C-page 437

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: PIC24FJ128GA202-I/SP PIC24FJ128GA204-I/PT PIC24FJ128GA202-I/SO PIC24FJ128GA202-I/MM PIC24FJ128GA202-I/SS PIC24FJ128GA204-I/ML PIC24FJ64GA202-E/SS PIC24FJ128GA202-E/SO PIC24FJ64GA204-E/PT PIC24FJ64GA202-E/MM PIC24FJ64GA202-E/SP PIC24FJ128GA202-E/SP PIC24FJ64GA202-E/SO PIC24FJ128GA202-E/MM PIC24FJ128GA202-E/SS PIC24FJ128GA204-E/ML PIC24FJ128GA204-E/PT PIC24FJ64GA204-E/ML PIC24FJ128GA202T-I/SO PIC24FJ128GA202T-I/MM PIC24FJ128GA202T-I/SS PIC24FJ64GA204-I/PT PIC24FJ64GA204T-I/PT PIC24FJ128GA204T-I/ML PIC24FJ128GA204T-I/PT PIC24FJ64GA202T-I/SS PIC24FJ64GA202-I/SP PIC24FJ64GA204-I/ML PIC24FJ64GA202-I/SO PIC24FJ64GA202-I/MM PIC24FJ64GA202T-I/SO PIC24FJ64GA202T-I/MM PIC24FJ64GA202-I/SS PIC24FJ64GA204T-I/ML