Product Sample & Technical Tools & Support & Folder Buy Documents Software Community OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 OP07x Precision Operational Amplifiers 1 Features 3 Description • LowNoise These devices offer low offset and long-term stability 1 by means of a low-noise, chopperless, • NoExternalComponentsRequired bipolar-input-transistor amplifier circuit. For most • ReplaceChopperAmplifiersataLowerCost applications, external components are not required • WideInput-VoltageRange:0to ±14V(Typ) for offset nulling and frequency compensation. The true differential input, with a wide input-voltage range • WideSupply-VoltageRange: ±3Vto±18V and outstanding common-mode rejection, provides maximum flexibility and performance in high-noise 2 Applications environments and in noninverting applications. Low • WirelessBaseStationControlCircuits bias currents and extremely high input impedances aremaintainedovertheentiretemperaturerange. • OpticalNetworkControlCircuits • Instrumentation DeviceInformation(1) • SensorsandControls PARTNUMBER PACKAGE(PIN) BODYSIZE • PrecisionFilters SO(8) 6.20mm×5.30mm OP07x SOIC(8) 4.90mm×3.91mm PDIP(8) 9.81mm×6.35mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. 4 Simplified Schematic 1 OFFSET N1 3 IN+ + 6 OUT 2 IN− − 8 OFFSET N2 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 9.2 FunctionalBlockDiagram.........................................7 2 Applications........................................................... 1 9.3 FeatureDescription...................................................7 3 Description............................................................. 1 9.4 DeviceFunctionalModes..........................................7 4 SimplifiedSchematic............................................. 1 10 ApplicationandImplementation.......................... 8 10.1 GeneralApplication.................................................8 5 RevisionHistory..................................................... 2 10.2 TypicalApplication .................................................8 6 PinFunctions......................................................... 3 11 PowerSupplyRecommendations..................... 10 7 Specifications......................................................... 4 12 Layout................................................................... 11 7.1 AbsoluteMaximumRatings......................................4 12.1 LayoutGuidelines.................................................11 7.2 HandlingRatings.......................................................4 12.2 LayoutExample....................................................11 7.3 RecommendedOperatingConditions.......................4 13 DeviceandDocumentationSupport................. 12 7.4 ThermalInformation..................................................4 7.5 ElectricalCharacteristics...........................................5 13.1 RelatedLinks........................................................12 7.6 OperatingCharacteristics..........................................6 13.2 Trademarks...........................................................12 13.3 ElectrostaticDischargeCaution............................12 8 TypicalCharacteristics.......................................... 6 13.4 Glossary................................................................12 9 DetailedDescription.............................................. 7 14 Mechanical,Packaging,andOrderable 9.1 Overview...................................................................7 Information........................................................... 12 5 Revision History ChangesfromRevisionF(January2014)toRevisionG Page • AddedApplications,DeviceInformationtable,PinFunctionstable,HandlingRatingstable,ThermalInformation table,TypicalCharacteristics,FeatureDescriptionsection,DeviceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation Supportsection,andMechanical,Packaging,andOrderableInformationsection................................................................ 1 ChangesfromRevisionE(May2004)toRevisionF Page • DeletedOrderingInformationtable........................................................................................................................................ 1 2 SubmitDocumentationFeedback Copyright©1983–2014,TexasInstrumentsIncorporated ProductFolderLinks:OP07C OP07D

OP07C,OP07D www.ti.com SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 6 Pin Functions DORPPACKAGE (TOPVIEW) OFFSETN1 1 8 OFFSETN2 IN− 2 7 VCC+ IN+ 3 6 OUT VCC− 4 5 NC NC−Nointernalconnection PinFunctions PIN TYPE DESCRIPTION NAME NO. IN+ 3 I Noninvertinginput IN– 2 I Invertinginput NC 5 — Donotconnect OFFSETN1 1 I Externalinputoffsetvoltageadjustment OFFSETN2 8 I Externalinputoffsetvoltageadjustment OUT 6 O Output V + 7 — Positivesupply CC V – 4 — Negativesupply CC Copyright©1983–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:OP07C OP07D

OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V (2) 0 22 CC+ Supplyvoltage V V (2) –22 0 CC– Differentialinputvoltage(3) ±30 V V Inputvoltagerange(eitherinput)(4) ±22 V I Durationofoutputshortcircuit(5) Unlimited T Operatingvirtual-junctiontemperature 150 °C J Leadtemperature1.6mm(1/16in)fromcasefor10s 260 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allvoltagevalues,unlessotherwisenoted,arewithrespecttothemidpointbetweenV andV . CC+ CC− (3) DifferentialvoltagesareatIN+withrespecttoIN−. (4) Themagnitudeoftheinputvoltagemustneverexceedthemagnitudeofthesupplyvoltageor15V,whicheverisless. (5) Theoutputmaybeshortedtogroundortoeitherpowersupply. 7.2 Handling Ratings PARAMETER DEFINITION MIN MAX UNIT T Storagetemperaturerange –65 150 °C STG Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all Electrostatic pins(1) 0 1000 V V (ESD) Discharge Chargeddevicemodel(CDM),perJEDECspecificationJESD22- C101,allpins(2) 0 1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 7.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V 3 18 CC+ Supplyvoltage V –3 –18 V CC– V Common-modeinputvoltage V =±15V –13 13 IC CC± T Operatingfree-airtemperature 0 70 °C A 7.4 Thermal Information THERMALMETRIC(1) D P UNIT R Junction-to-ambientthermalresistance 97 85 °C/W θJA (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport(SPRA953). 4 SubmitDocumentationFeedback Copyright©1983–2014,TexasInstrumentsIncorporated ProductFolderLinks:OP07C OP07D

OP07C,OP07D www.ti.com SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 7.5 Electrical Characteristics atspecifiedfree-airtemperature,V =±15V(unlessotherwisenoted)(1) CC± OP07C OP07D PARAMETER TESTCONDITIONS TA(2) UNIT MIN TYP MAX MIN TYP MAX 25°C 60 150 VIO Inputoffsetvoltage VO=0V RS=50Ω µV 0°Cto70°C 85 250 Temperaturecoefficient αVIO ofinputoffsetvoltage VO=0V RS=50Ω 0°Cto70°C 0.5 2.5 µV/°C Long-termdriftofinput See 0.4 µV/mo offsetvoltage Offsetadjustmentrange RS=20kΩ, SeeFigure2 25°C ±4 mV 25°C 0.8 6 IIO Inputoffsetcurrent nA 0°Cto70°C 1.6 8 Temperaturecoefficient αIIO ofinputoffsetcurrent 0°Cto70°C 12 50 pA/°C 25°C ±1.8 ±12 IIB Inputbiascurrent nA 0°Cto70°C ±2.2 ±14 Temperaturecoefficient αIIB ofinputbiascurrent 0°Cto70°C 18 50 pA/°C Common-modeinput 25°C ±13 ±14 ±13 ±14 VICR voltagerange 0°Cto70°C ±13 ±13.5 ±13 ±13.5 V RL≥10kΩ ±12 ±13 ±12 ±13 RL≥2kΩ 25°C ±11.5 ±12.8 ±11.5 ±12.8 VOM Peakoutputvoltage V RL≥1kΩ ±12 ±12 RL≥2kΩ 0°Cto70°C ±11 ±12.6 ±11 ±12.6 VCC=15V,VO=1.4Vto11.4V, 25°C 100 400 400 Large-signaldifferential RL≥500kΩ AVD voltageamplification 25°C 120 400 120 400 V/mV VO=±10,RL=2kΩ 0°Cto70°C 100 400 100 400 B1 Unity-gainbandwidth 25°C 0.4 0.6 0.4 0.6 MHz ri Inputresistance 25°C 8 33 7 31 MΩ Common-mode 25°C 100 120 94 110 CMRR rejectionratio VIC=±13V,RS=50Ω 0°Cto70°C 97 120 94 106 dB Supply-voltagesensitivity 25°C 7 32 7 32 kSVS (ΔVIO/ΔVCC) VCC+=±3Vto±18V,RS=50Ω 0°Cto70°C 10 51 10 51 µV/V VO=0,Noload 80 150 80 150 PD Powerdissipation 25°C mW VCC+=±3V,VO=0,Noload 4 8 4 8 (1) Becauselong-termdriftcannotbemeasuredontheindividualdevicespriortoshipment,thisspecificationisnotintendedtobea warranty.Itisanengineeringestimateoftheaveragedtrendlineofdriftversustimeoverextendedperiodsafterthefirst30daysof operation. (2) Allcharacteristicsaremeasuredwithzerocommon-modeinputvoltage,unlessotherwisespecified. Copyright©1983–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:OP07C OP07D

OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 www.ti.com 7.6 Operating Characteristics atspecifiedfree-airtemperature,V =5V(unlessotherwisenoted) CC OP07C OP07D PARAMETER TESTCONDITIONS(1) UNIT TYP TYP f=10Hz 10.5 10.5 Vn Inputoffsetvoltage f=100Hz 10.2 10.3 nV/√Hz f=1kHz 9.8 9.8 VN(PP) Peak-to-peakequivalentinputnoisevoltage f=0.1Hzto10Hz 0.38 0.38 µV f=10Hz 0.35 0.35 In Equivalentinputnoisecurrent f=100Hz 0.15 0.15 nV/√Hz f=1kHz 0.13 0.13 IN(PP) Peak-to-peakequivalentinputnoisecurrent f=0.1Hzto10Hz 15 15 pA SR Slewrate RL≥2kΩ 0.3 0.3 V/µs (1) Allcharacteristicsaremeasuredunderopen-loopconditions,withzerocommon-modeinputvoltage,unlessotherwisenoted. 8 Typical Characteristics 200 Low Mean 150 High 100 V) µ O ( VI 50 0 -50 -50 0 50 100 150 T (°C) D001 Figure1.Input-OffsetVoltagevs.Temperature 6 SubmitDocumentationFeedback Copyright©1983–2014,TexasInstrumentsIncorporated ProductFolderLinks:OP07C OP07D

OP07C,OP07D www.ti.com SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 9 Detailed Description 9.1 Overview These devices offer low offset and long-term stability by means of a low-noise, chopperless, bipolar-input- transistor amplifier circuit. For most applications, external components are not required for offset nulling and frequency compensation. The true differential input, with a wide input-voltage range and outstanding common- mode rejection, provides maximum flexibility and performance in high-noise environments and in noninverting applications. Low bias currents and extremely high input impedances are maintained over the entire temperature range. Thesedevicesarecharacterizedforoperationfrom0°Cto70°C. 9.2 Functional Block Diagram VCC+ IN– OUT IN+ OFFSETN1 OFFSETN2 VCC– ComponentCount Transistors 22 Resistors 11 Diode 1 Capacitor 1 9.3 Feature Description 9.3.1 Offset-VoltageNullCapability The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current- gain betas (β), collector or emitter resistors, et cetera. The input offset pins allow the designer to adjust for these mismatches by external circuitry. See the Application and Implementation section for more details on design techniques. 9.3.2 SlewRate The slew rate is the rate at which an operational amplifier can change its output when there is a change on the input.TheOP07hasa0.3-V/μsslewrate. 9.4 Device Functional Modes The OP07 is powered on when the supply is connected. It can be operated as a single supply operational amplifierordualsupplyamplifierdependingontheapplication. Copyright©1983–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:OP07C OP07D

OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 www.ti.com 10 Application and Implementation 10.1 General Application The input offset voltage of operational amplifiers (op amps) arises from unavoidable mismatches in the differential input stage of the op-amp circuit caused by mismatched transistor pairs, collector currents, current- gain betas (β), collector or emitter resistors, etc. The input offset pins allow the designer to adjust for these mismatchesbyexternalcircuitry.Theseinputmismatchescanbeadjustedbyputtingresistorsorapotentiometer betweentheinputsasshowninFigure2.Apotentiometercanbeusedtofinetunethecircuitduringtestingorfor applications which require precision offset control. More information about designing using the input-offset pins, seeNullingInputOffsetVoltageofOperationalAmplifiers (SLOA045). 20 kΩ VCC+ OFFSETN1 OFFSET 1 N2 8 3 IN+ + 7 6 OUT IN− 2 − 4 VCC– Figure2. InputOffset-VoltageNullCircuit 10.2 Typical Application The voltage follower configuration of the operational amplifier is used for applications where a weak signal is used to drive a relatively high current load. This circuit is also called a buffer amplifier or unity gain amplifier. The inputs of an operational amplifier have a very high resistance which puts a negligible current load on the voltage source. The output resistance of the operational amplifier is almost negligible, so it can provide as much current asnecessarytotheoutputload. 10 k(cid:13) 12 V V OUT + V IN Figure3. VoltageFollowerSchematic 8 SubmitDocumentationFeedback Copyright©1983–2014,TexasInstrumentsIncorporated ProductFolderLinks:OP07C OP07D

OP07C,OP07D www.ti.com SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 Typical Application (continued) 10.2.1 DesignRequirements • Outputrangeof2Vto11V • Inputrangeof2Vto11V 10.2.2 DetailedDesignProcedure 10.2.2.1 OutputVoltageSwing The output voltage of an operational amplifier is limited by its internal circuitry to some level below the supply rails. For this amplifier, the output voltage swing is within ±12 V, which accommodates the input and output voltagerequirements. 10.2.2.2 SupplyandInputVoltage For correct operation of the amplifier, neither input must be higher than the recommended positive supply rail voltage or lower than the recommended negative supply rail voltage. The chosen amplifier must be able to operate at the supply voltage that accommodates the inputs. Because the input for this application goes up to 11 V, the supply voltage must be 12 V. Using a negative voltage on the lower rail, rather than ground, allows the amplifiertomaintainlinearityforinputsbelow2V. 10.2.3 ApplicationCurvesforOutputCharacteristics 12 0.4 10 0.3 0.2 8 OUT (V) 6 O (mA) 00..01 V II 4 ±0.1 2 ±0.2 0 ±0.3 0 2 4 6 8 10 12 0 2 4 6 8 10 12 VIN (V) VIN (V) C001 C002 Figure4.OutputVoltagevsInputVoltage Figure5.CurrentDrawnbytheInputoftheVoltage Follower(I )vstheInputVoltage IO 3.0 2.5 2.0 A) m C (1.5 C I 1.0 0.5 0.0 0 2 4 6 8 10 12 VIN (V) C003 Figure6.CurrentDrawnfromSupply(I )vstheInputVoltage CC Copyright©1983–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:OP07C OP07D

OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 www.ti.com 11 Power Supply Recommendations TheOP07isspecifiedforoperationfrom ±3to ±18V;manyspecificationsapplyfrom0°Cto70°C. CAUTION Supply voltages larger than ±22 V can permanently damage the device (see the AbsoluteMaximumRatings). Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout Guidelines. 10 SubmitDocumentationFeedback Copyright©1983–2014,TexasInstrumentsIncorporated ProductFolderLinks:OP07C OP07D

OP07C,OP07D www.ti.com SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 12 Layout 12.1 Layout Guidelines Forbestoperationalperformanceofthedevice,usegoodPCBlayoutpractices,including: • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low-impedance powersourceslocaltotheanalogcircuitry. – Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single supplyapplications. • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methodsofnoisesuppression.OnmultilayerPCBs,oneormorelayersareusuallydevotedtogroundplanes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, refer to CircuitBoardLayoutTechniques,(SLOA089). • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicularly, as opposedtoinparallel,withthenoisytrace. • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting inputminimizesparasiticcapacitance,asshowninLayoutExample. • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitivepartofthecircuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakagecurrentsfromnearbytracesthatareatdifferentpotentials. 12.2 Layout Example RIN VIN + VOUT RG RF Figure7. OperationalAmplifierSchematicforNoninvertingConfiguration Place components close to device and to each other to reduce parasitic errors Run the input traces as far away from the supply lines RF as possible OFFSET N1 OFFSET N2 VS+ Use low-ESR, ceramic RG bypass capacitor GND IN1í VCC+ VIN IN1+ OUT RIN VCCí NC GND Only needed for dual-supply operation GND VS- (or GND for single supply) VOUT Ground (GND) plane on another layer Figure8. OperationalAmplifierBoardLayoutforNoninvertingConfiguration Copyright©1983–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:OP07C OP07D

OP07C,OP07D SLOS099G–OCTOBER1983–REVISEDNOVEMBER2014 www.ti.com 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table1.RelatedLinks Technical Support& Parts ProductFolder Sample&Buy Tools&Software Documents Community OP07C Clickhere Clickhere Clickhere Clickhere Clickhere OP07D Clickhere Clickhere Clickhere Clickhere Clickhere 13.2 Trademarks Alltrademarksarethepropertyoftheirrespectiveowners. 13.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 13.4 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronymsanddefinitions. 14 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowserbasedversionsofthisdatasheet,refertothelefthandnavigation. 12 SubmitDocumentationFeedback Copyright©1983–2014,TexasInstrumentsIncorporated ProductFolderLinks:OP07C OP07D

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) OP-07DPSR ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D & no Sb/Br) OP-07DPSRG4 ACTIVE SO PS 8 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP-07D & no Sb/Br) OP07-W ACTIVE WAFERSALE YS 0 3603 TBD Call TI Call TI OP07CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C & no Sb/Br) OP07CDE4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C & no Sb/Br) OP07CDG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C & no Sb/Br) OP07CDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU | SN Level-1-260C-UNLIM 0 to 70 OP07C & no Sb/Br) OP07CDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C & no Sb/Br) OP07CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07C & no Sb/Br) OP07CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 OP07CP & no Sb/Br) OP07CPE4 ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 OP07CP & no Sb/Br) OP07DD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D & no Sb/Br) OP07DDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D & no Sb/Br) OP07DDRE4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 OP07D & no Sb/Br) OP07DP ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 OP07DP (RoHS) OP07DPE4 ACTIVE PDIP P 8 50 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 OP07DP (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) OP07CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OP07CDRG4 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 OP07DDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) OP07CDR SOIC D 8 2500 340.5 338.1 20.6 OP07CDRG4 SOIC D 8 2500 340.5 338.1 20.6 OP07DDR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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