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M September 1983 M Revised May 2005 7 4 H C 3 MM74HC373 7 3 3-STATE Octal D-Type Latch 3 - S T A General Description Features T E The MM74HC373 high speed octal D-type latches utilize (cid:1) Typical propagation delay: 18 ns O advanced silicon-gate CMOS technology. They possess (cid:1) Wide operating voltage range: 2 to 6 volts c tshtaen dhaigrhd CnoMisOeS i minmteugnraittye da ncidrc uloitws, paosw weerl l caosn tshuem apbtiiolitny toof (cid:1) Low input current: 1 PA maximum ta drive 15 LS-TTL loads. Due to the large output drive capa- (cid:1) Low quiescent current: 80 PA maximum (74 Series) l D bility and the 3-STATE feature, these devices are ideally (cid:1) Output drive capability: 15 LS-TTL loads - T suited for interfacing with bus lines in a bus organized sys- y tem. p e When the LATCH ENABLE input is HIGH, the Q outputs L will follow the D inputs. When the LATCH ENABLE goes a LOW, data at the D inputs will be retained at the outputs t c until LATCH ENABLE returns HIGH again. When a high h logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function, and pin-out com- patible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. Ordering Code: Order Number Package Number Package Description MM74HC373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HC373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Output Latch Data 373 Control Enable Output L H H H L H L L L L X Q0 H X X Z H HIGH Level L LOW Level Q0 Level of output before steady-state input conditions were established. Z High Impedance Top View © 2005 Fairchild Semiconductor Corporation DS005335 www.fairchildsemi.com

3 7 Absolute Maximum Ratings Recommended Operating 3 (Note 1) C (Note 2) Conditions H 74 Supply Voltage (VCC) (cid:16)0.5 to (cid:14)7.0V Min Max Units M DC Input Voltage (VIN) (cid:16)1.5 to VCC (cid:14)1.5V Supply Voltage (VCC) 2 6 V M DC Output Voltage (VOUT) (cid:16)0.5 to VCC (cid:14)0.5V DC Input or Output Voltage Clamp Diode Current (IIK, IOK) r20 mA (VIN,VOUT) 0 VCC V DC Output Current, per pin (IOUT) r35 mA Operating Temperature Range (TA) (cid:16)40 (cid:14)85 qC DC VCC or GND Current, per pin (ICC) r70 mA Input Rise or Fall Times Storage Temperature Range (TSTG) (cid:16)65qC to (cid:14)150qC (tr, tf) VCC 2.0V 1000 ns Power Dissipation (PD) VCC 4.5V 500 ns (Note 3) 600 mW VCC 6.0V 400 ns S.O. Package only 500 mW Note 1: Absolute Maximum Ratings are those values beyond which dam- Lead Temperature (TL) age to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. (Soldering 10 seconds) 260qC Note 3: Power Dissipation temperature derating — plastic “N” package: (cid:16) 12 mW/qC from 65qC to 85qC. DC Electrical Characteristics Symbol Parameter Conditions VCC TA 25qC TA (cid:16)40 to 85qC TA (cid:16)55 to 125qC Units Typ Guaranteed Limits VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V VOH Minimum HIGH Level VIN VIH or VIL Output Voltage |IOUT| d 20 PA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V VIN VIH or VIL |IOUT| d 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| d 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V VOL Maximum LOW Level VIN VIH or VIL Output Voltage |IOUT| d 20 PA 2.0V 0 0.1 0.1 0.1 V 4.5V 0 0.1 0.1 0.1 V 6.0V 0 0.1 0.1 0.1 V VIN VIH or VIL |IOUT| d 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V |IOUT| d 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V IIN Maximum Input VIN VCC or GND 6.0V r0.1 r1.0 r1.0 PA Current IOZ Maximum 3-STATE VIN VIH or VIL, OC VIH 6.0V r0.5 r5 r10 PA Output Leakage VOUT VCC or GND Current ICC Maximum Quiescent VIN VCC or GND 6.0V 8.0 80 160 PA Supply Current IOUT 0 PA Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur- rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. www.fairchildsemi.com 2

M AC Electrical Characteristics M 7 VCC 5V, TA 25qC, tr tf 6 ns 4 Guaranteed H Symbol Parameter Conditions Typ Units C Limit 3 tPHL, tPLH Maximum Propagation Delay, Data to Q CL 45 pF 18 25 ns 7 3 tPHL, tPLH Maximum Propagation Delay, LE to Q CL 45 pF 21 30 ns tPZH, tPZL Maximum Output Enable Time RL 1 k: 20 28 ns CL 45 pF tPHZ, tPLZ Maximum Output Disable Time RL 1 k: 18 25 ns CL 5 pF tS Minimum Set Up Time 5 ns tH Minimum Hold Time 10 ns tW Minimum Pulse Width 9 16 ns AC Electrical Characteristics VCC 2.0(cid:16)6.0V, CL 50 pF, tr tf 6 ns (unless otherwise specified) Symbol Parameter Conditions VCC TA 25qC TA (cid:16)40 to 85qC TA (cid:16)55 to 125qC Units Typ Guaranteed Limits tPHL, tPLH Maximum Propagation CL 50 pF 2.0V 50 150 188 225 ns Delay, Data to Q CL 150 pF 2.0V 80 200 250 300 ns CL 50 pF 4.5V 22 30 37 45 ns CL 150 pF 4.5V 30 40 50 60 ns CL 50 pF 6.0V 19 26 31 39 ns CL 150 pF 6.0V 26 35 44 53 ns tPHL, tPLH Maximum Propagation CL 50 pF 2.0V 63 175 220 263 ns Delay, LE to Q CL 150 pF 2.0V 110 225 280 338 ns CL 50 pF 4.5V 25 35 44 52 ns CL 150 pF 4.5V 35 45 56 68 ns CL 50 pF 6.0V 21 30 37 45 ns CL 150 pF 6.0V 28 39 49 59 ns tPZH, tPZL Maximum Output RL 1 k: Enable Time CL 50 pF 2.0V 50 150 188 225 ns CL 150 pF 2.0V 80 200 250 300 ns CL 50 pF 4.5V 21 30 37 45 ns CL 150 pF 4.5V 30 40 50 60 ns CL 50 pF 6.0V 19 26 31 39 ns CL 150 pF 6.0V 26 35 44 53 ns tPHZ, tPLZ Maximum Output Disable RL 1 k: 2.0V 50 150 188 225 ns Disable Time CL 50 pF 4.5V 21 30 37 45 ns 6.0V 19 26 31 39 ns tS Minimum Set Up Time 2.0V 50 60 75 ns 4.5V 9 13 15 ns 6.0V 9 11 13 ns tH Minimum Hold Time 2.0V 5 5 5 ns 4.5V 5 5 5 ns 6.0V 5 5 5 ns tW Minimum Pulse Width 2.0V 30 80 100 120 ns 4.5V 10 16 20 24 ns 6.0V 9 14 18 20 ns tTHL, tTLH Maximum Output Rise CL 50 pF 2.0V 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V 6 10 13 15 ns CPD Power Dissipation (per latch) Capacitance (Note 5) OC VCC 30 pF OC GND 50 pF CIN Maximum Input Capacitance 5 10 10 10 pF 3 www.fairchildsemi.com

3 7 AC Electrical Characteristics 3 (Continued) C H 74 Symbol Parameter Conditions VCC TA 25qC TA (cid:16)40 to 85qC TA (cid:16)55 to 125qC Units M Typ Guaranteed Limits M COUT Maximum Output 15 20 20 20 pF Capacitance Note 5: CPD determines the no load dynamic power consumption, PD CPD VCC2 f (cid:14) ICC VCC, and the no load dynamic current consumption, IS CPDVCCf (cid:14) ICC. www.fairchildsemi.com 4

M Physical Dimensions inches (millimeters) unless otherwise noted M 7 4 H C 3 7 3 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com

3 7 Physical Dimensions 3 inches (millimeters) unless otherwise noted (Continued) C H 4 7 M M 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6

M Physical Dimensions inches (millimeters) unless otherwise noted (Continued) M 7 4 H C 3 7 3 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com

h c Physical Dimensions inches (millimeters) unless otherwise noted (Continued) t a L e p y T - D l a t c O E T A T S - 3 3 7 3 C H 4 7 M M 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the device or system whose failure to perform can be rea- body, or (b) support or sustain life, and (c) whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the www.fairchildsemi.com user. www.fairchildsemi.com 8

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: MM74HC373N MM74HC373SJX MM74HC373MTC MM74HC373MTCX MM74HC373SJ MM74HC373WM MM74HC373WMX