MCP4706/4716/4726 8-/10-/12-Bit Voltage Output Digital-to-Analog Converter 2 with EEPROM and I C Interface Features Package Types • Output Voltage Resolutions MCP4706 / 16 / 26 - 12-bit: MCP4726 - 10-bit: MCP4716 VOUT 1 6 VREF VREF 1 6 VOUT - 8-bit: MCP4706 EP • Rail-to-Rail Output VSS 2 5 SCL SCL 2 7 5 VSS • Fast Settling Time of 6µs (typical) VDD 3 4 SDA SDA 3 4 VDD • DAC Voltage Reference Options 2x2DFN-6* SOT-23-6 - V DD - VREF Pin * Includes Exposed Thermal Pad (EP); see Table3-1. • Output Gain Options - Unity (1x) Description - 2x, only when V pin is used as voltage REF source The MCP4706/4716/4726 are single channel 8-bit, 10-bit, and 12-bit buffered voltage output Digital-to- • Nonvolatile Memory (EEPROM) Analog Converters (DAC) with nonvolatile memory and - Auto Recall of Saved DAC register setting an I2C Serial Interface. This family will also be referred - Auto Recall of Saved Device Configuration to as MCP47X6. (Voltage Reference, Gain, Power Down) The V pin or the device V can be selected as the REF DD • Power-Down Modes DAC’s reference voltage. When V is selected, V is DD DD - Disconnects output buffer connected internally to the DAC reference circuit. - Selection of V pull-down resistors When the V pin is used, the user can select the OUT REF (640kΩ, 125kΩ, or 1kΩ) output buffer’s gain to 1 or 2. When the gain is 2, the • Low Power Consumption VREF pin voltage should be limited to a maximum of V /2. - Normal Operation: 210µA typ. DD - Power Down Operation: 60nA typ. The DAC Register value and configuration bits can be (PD1:PD0 = “11”) programmed to nonvolatile memory (EEPROM). The nonvolatile memory holds the DAC Register and • Single-Supply Operation: 2.7V to 5.5V configuration bit values when the device is powered off. • I2C™ Interface: A device reset (such as a Power On Reset) latches - Eight Available Addresses these stored values into the volatile memory. - Standard (100kbps), Fast (400kbps), and Power-down modes enable system current reduction High-Speed (3.4Mbps) Modes when the DAC output voltage is not required. The V OUT • Small 6-lead SOT-23 and DFN (2x2) Packages pin can be configured to present a low, medium, or high • Extended Temperature Range: -40°C to +125°C resistance load. These devices have a two-wire I2C™ compatible serial Applications interface for standard (100kHz), fast (400kHz), or high speed (3.4MHz) mode. • Set Point or Offset Trimming • Sensor Calibration These devices are available in small 6-pin SOT-23 and DFN 2x2mm packages. • Low Power Portable Instrumentation • PC Peripherals • Data AcquisitionSystems • Motor Control © 2011 Microchip Technology Inc. DS22272A-page 1

MCP4706/4716/4726 Block Diagram V REF V :V REF1 REF0 VDD ce on Gain (1x or 2x) encti VRL (G = 0 or 1) VDD eferSele R V V SS PD1:PD0 Op OUT Buffer Amp ogic RDegAiCster der SDA e L Lad PD1:PD0 SCL C Interfac EEPROM Resistor VW 1kΩ 25kΩ 40kΩ 2 Control 1 6 I Logic DS22272A-page 2 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is CHARACTERISTICS a stress rating only and functional operation of the device at those or any other conditions above those indicated in the Absolute Maximum Ratings † operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods Voltage on VDD with respect to VSS................ -0.6V to +6.5V may affect device reliability. Voltage on all pins with respect to V SS -0.3V to V + 0.3V ................................................................................ DD Input clamp current, I (V < 0, V > V , V) IK I I DD I ....................................................................................±20mA Output clamp current, I (V < 0 or V > V ) OK O O DD ....................................................................................±20mA Maximum input current source/sunk by SDA, SCL pins ........................................................................................2mA Maximum output current sunk by SDA Output pin ......................................................................................25mA Maximum current out of V pin...................................50mA SS Maximum current into V pin......................................50mA DD Maximum current sourced by the V pin..................40mA OUT Maximum current sunk by the V pin........................40mA OUT Maximum current sunk by the V pin.........................40µA REF Package power dissipation (T = +50°C, T = +150°C) A J SOT-23-6.......................................................452mW DFN-6..........................................................1098mW Storage temperature.....................................-65°C to +150°C Ambient temperature with power applied ......................................................................-55°C to +125°C ESD protection on all pins ....................................≥ 6kV (HBM) ....................................................................................≥ 400V (MM) Maximum Junction Temperature (T ) .........................+150°C J © 2011 Microchip Technology Inc. DS22272A-page 3

MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5kΩ from VOUT to GND, CL = 100pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions Power Requirements Input Voltage V 2.7 — 5.5 V DD Input Current IDD — 210 400 µA VREF1:VREF0 = ‘00’, SCL = SDA = V , V is unloaded, SS OUT volatile DAC Register = 0x000 — 210 400 µA VREF1:VREF0 = ‘11’, VREF = VDD, SCL = SDA = V , V is unloaded, SS OUT volatile DAC Register = 0x000 Power-Down Current IDDP — 0.09 2 µA PD1:PD0 = ‘01’ (Note6), V not connected OUT Power-On Reset V — 2.2 — V RAM retention voltage, (V ) < V POR RAM POR Threshold Power-Up Ramp Rate V 1 — — V/S (Note1, Note4) RAMP Note 1: This parameter is ensured by design and is not 100% tested. 2: This gain error does not include offset error. See Section 2 for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V DD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current. 7: V = 5.5V. DD DS22272A-page 4 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5kΩ from VOUT to GND, CL = 100pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions DC Accuracy Offset Error V ±0.02 0.75 % of FSR Code = 0x000h OS VREF1:VREF0 = ‘00’, G = ‘0’ Offset Error Tempera- V /°C — ±1 — ppm/°C -40°C to +25°C OS ture — ±2 — ppm/°C +25°C to +85°C Coefficient Zero Scale Error E — 0.13 2.0 LSb MCP4706, Code = 0x00h ZS — 0.52 7.7 LSb MCP4716, Code = 0x000h — 2.05 30.8 LSb MCP4726, Code = 0x000h Full Scale Error E — 0.3 5.2 LSb MCP4706, Code = 0xFFh FS — 1.1 20.5 LSb MCP4716, Code = 0x3FFh — 4.1 82.0 LSb MCP4726, Code = 0xFFFh Gain Error g -2 -0.10 2 % of FSR MCP4706, Code = 0xFFh E (Note2) VREF1:VREF0 = ‘00’, G = ‘0’ -2 -0.10 2 % of FSR MCP4716, Code = 0x3FFh VREF1:VREF0 = ‘00’, G = ‘0’ -2 -0.10 2 % of FSR MCP4726, Code = 0xFFFh VREF1:VREF0 = ‘00’, G = ‘0’ Gain Error Drift ΔG/°C — -3 — ppm/°C Resolution n 8 bits MCP4706 10 bits MCP4716 12 bits MCP4726 INL Error INL -0.907 ±0.125 +0.907 LSb MCP4706 (codes: 6 to 250) (Note7) -3.625 ±0.5 +3.625 LSb MCP4716 (codes: 25 to 1000) -14.5 ±2 +14.5 LSb MCP4726 (codes: 100 to 4000) DNL Error DNL -0.05 ±0.0125 +0.05 LSb MCP4706 (codes: 6 to 250) (Note7) -0.188 ±0.05 +0.188 LSb MCP4716 (codes: 25 to 1000) -0.75 ±0.2 +0.75 LSb MCP4726 (codes: 100 to 4000) Note 1: This parameter is ensured by design and is not 100% tested. 2: This gain error does not include offset error. See Section 2 for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V DD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current. 7: V = 5.5V. DD © 2011 Microchip Technology Inc. DS22272A-page 5

MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5kΩ from VOUT to GND, CL = 100pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions Output Amplifier Minimum Output Volt- V — 0.01 — V Output Amplifier’s minimum drive OUT(MIN) age Maximum Output V — V – — V Output Amplifier’s maximum drive OUT(MAX) DD Voltage 0.04 Phase Margin PM — 66 — Degree CL = 400pF, RL = ∞ (°) Slew Rate SR — 0.55 — V/µs Short Circuit Current I 7 15 24 mA SC Settling Time t — 6 — µs Note3 SETTLING Power Down Output TPDD — 1 — µs PD1:PD0 = “00” -> ‘11’, ‘10’, or ‘01’ Disable Time Delay started from falling edge SCL at end of ACK bit. V = V - 10mV. V not OUT OUT OUT connected. Power Down Output TPDE — 10.5 — µs PD1:PD0 = ‘11’, ‘10’, or ‘01’ -> “00” Enable Time Delay started from falling edge SCL at end of ACK bit. Volatile DAC Register = FFh, V =10mV. V not connected. OUT OUT External Reference (V ) (Note1) REF Input Range V 0.04 — V - V Buffered Mode REF DD 0.04 0 — V V Unbuffered Mode DD Input Impedance R — 210 — kΩ Unbuffered Mode VREF Input Capacitance C_REF — 29 — pF Unbuffered Mode -3dB Bandwidth — 86.5 — kHz V = 2.048V ± 0.1V, REF VREF1:VREF0=‘10’, G = ‘0’ — 67.7 — kHz V = 2.048V ± 0.1V, REF VREF1:VREF0=‘10’, G = ‘1’ Total Harmonic Distor- THD — -73 — dB V = 2.048V ± 0.1V, REF tion VREF1:VREF0=‘10’, G = ‘0’, Frequency = 1kHz Dynamic Performance (Note1) Major Code Transition — 45 — nV-s 1 LSb change around major carry Glitch (800h to 7FFh) Digital Feedthrough — <10 — nV-s Note 1: This parameter is ensured by design and is not 100% tested. 2: This gain error does not include offset error. See Section 2 for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V DD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current. 7: V = 5.5V. DD DS22272A-page 6 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, VDD = 2.7V to 5.5V, VSS = 0V, RL = 5kΩ from VOUT to GND, CL = 100pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions Digital Interface Output Low Voltage V — — 0.4 V I = 3mA OL OL Input High Voltage V 0.7V — — V IH DD (SDA and SCL Pins) Input Low Voltage V — — 0.3V V IL DD (SDA and SCL Pins) Input Leakage I — — ±1 µA SCL = SDA = V or LI SS SCL = SDA = V DD Pin Capacitance C — — 3 pF (Note5) PIN EEPROM EEPROM Write Time T — 25 50 ms WRITE Data Retention — 200 — Years At +25°C, (Note1) Endurance 1 — — Million At +25°C, (Note1) Cycles Note 1: This parameter is ensured by design and is not 100% tested. 2: This gain error does not include offset error. See Section 2 for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V DD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = ‘10’, and ‘11’ configurations should have the same current. 7: V = 5.5V. DD © 2011 Microchip Technology Inc. DS22272A-page 7

MCP4706/4716/4726 1.1 I2C Mode Timing Waveforms and Requirements V (V ) V POR BOR DD tPORD tBORD SCL VIH VIH SDA VOUT VOUT pulled down by internal 500kΩ (typical) resistor I2C Interface is operational FIGURE 1-1: Power-On and Brown-Out Reset Waveforms. ACK Stop Start ACK SDA SCL t t PDE PDD V OUT FIGURE 1-2: I2C Power-Down Command Timing. TABLE 1-1: RESET TIMING Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ T ≤ +125°C (extended) A Timing Characteristics All parameters apply across the specified operating ranges unless noted. V = +2.7V to 5.5V, 5kΩ, 10kΩ, 50kΩ, 100kΩ devices. DD Typical specifications represent values for V = 5.5V, T = +25°C. DD A Parameters Sym Min Typ Max Units Conditions Power Up Reset t — 60 — µs Monitor ACK bit response to ensure device PORD Delay responds to command. Brown Out Reset t — 1 — µs V transitions from V → > V BORD DD DD(MIN) POR Delay V driven to V disabled OUT OUT Power Down Disable T — 2.5 — µs V = 5V PDD DD Time Delay PD1:PD0 → ‘00’ (from ‘01’, ‘10’, or ‘11’), from falling edge SCL at end of ACK bit. — 5 — µs V = 3V DD PD1:PD0 → ‘00’ (from ‘01’, ‘10’, or ‘11’), from falling edge SCL at end of ACK bit. Power Down Enable TPDE — 10.5 — µs PD1:PD0 → ‘01’, ‘10’, or ‘11’ (from ‘00’), Time Delay from falling edge SCL at end of ACK bit. DS22272A-page 8 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 V IH SCL 91 93 90 92 111 SDA V IL START STOP Condition Condition FIGURE 1-3: I2C Bus Start/Stop Bits Timing Waveforms. TABLE 1-2: I2C BUS START/STOP BITS REQUIREMENTS I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical characteristics Param. Symbol Characteristic Min Max Units Conditions No. F SCL pin Frequency Standard Mode 0 100 kHz C = 400pF, 2.7V - 5.5V SCL b Fast Mode 0 400 kHz C = 400pF, 2.7V - 5.5V b High-Speed 1.7 0 1.7 MHz C = 400pF, 4.5V - 5.5V b High-Speed 3.4 0 3.4 MHz C = 100pF, 4.5V - 5.5V b D102 C Bus capacitive 100kHz mode — 400 pF b loading 400kHz mode — 400 pF 1.7MHz mode — 400 pF 3.4MHz mode — 100 pF 90 TSU:STA START condition 100kHz mode 4700 — ns Only relevant for repeated Setup time 400kHz mode 600 — ns START condition 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 91 THD:STA START condition 100kHz mode 4000 — ns After this period the first Hold time 400kHz mode 600 — ns clock pulse is generated 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 92 TSU:STO STOP condition 100kHz mode 4000 — ns Setup time 400kHz mode 600 — ns 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 93 THD:STO STOP condition 100kHz mode 4000 — ns Hold time 400kHz mode 600 — ns 1.7MHz mode 160 — ns 3.4MHz mode 160 — ns 94 T HVC to SCL Setup time 25 — uS High Voltage Commands HVCSU 95 T SCL to HVC Hold time 25 — uS High Voltage Commands HVCHD © 2011 Microchip Technology Inc. DS22272A-page 9

MCP4706/4716/4726 103 100 102 101 SCL 90 106 91 107 92 SDA In 109 109 110 SDA Out FIGURE 1-4: I2C Bus Data Timing. T ABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage V range is described in Electrical characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 100 THIGH Clock high time 100kHz mode 4000 — ns 2.7V-5.5V 400kHz mode 600 — ns 2.7V-5.5V 1.7MHz mode 120 ns 4.5V-5.5V 3.4MHz mode 60 — ns 4.5V-5.5V 101 TLOW Clock low time 100kHz mode 4700 — ns 2.7V-5.5V 400kHz mode 1300 — ns 2.7V-5.5V 1.7MHz mode 320 ns 4.5V-5.5V 3.4MHz mode 160 — ns 4.5V-5.5V Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t ≥250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V and V of IH IL the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use C in pF for the calculations. b 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (T ) or Clock Low time (T ) can be SU:DAT LOW affected. Data Input: This parameter must be longer than t . SP Data Output: This parameter is characterized, and tested indirectly by testing T parameter. AA 7: Ensured by the T 3.4MHz specification test. AA 2 8: The specification is not part of the I C specification. T = T + T (or T ). AA HD:DAT FSDA RSDA DS22272A-page 10 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage V range is described in Electrical characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 102A(5) TRSCL SCL rise time 100kHz mode — 1000 ns Cb is specified to be from 10 to 400pF (100pF 400kHz mode 20 + 0.1Cb 300 ns maximum for 3.4MHz 1.7MHz mode 20 80 ns mode) 1.7MHz mode 20 160 ns After a Repeated Start condition or an Acknowledge bit 3.4MHz mode 10 40 ns 3.4MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit 102B(5) TRSDA SDA rise time 100kHz mode — 1000 ns Cb is specified to be from 10 to 400pF (100pF max 400kHz mode 20 + 0.1Cb 300 ns for 3.4MHz mode) 1.7MHz mode 20 160 ns 3.4MHz mode 10 80 ns 103A(5) TFSCL SCL fall time 100kHz mode — 300 ns Cb is specified to be from 10 to 400pF (100pF max 400kHz mode 20 + 0.1Cb 300 ns for 3.4MHz mode) 1.7MHz mode 20 80 ns 3.4MHz mode 10 40 ns 103B(5) TFSDA SDA fall time 100kHz mode — 300 ns Cb is specified to be from 400kHz mode 20 + 0.1Cb(4) 300 ns 10 to 400pF (100pF max for 3.4MHz mode) 1.7MHz mode 20 160 ns 3.4MHz mode 10 80 ns Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t ≥250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V and V of IH IL the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use C in pF for the calculations. b 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (T ) or Clock Low time (T ) can be SU:DAT LOW affected. Data Input: This parameter must be longer than t . SP Data Output: This parameter is characterized, and tested indirectly by testing T parameter. AA 7: Ensured by the T 3.4MHz specification test. AA 2 8: The specification is not part of the I C specification. T = T + T (or T ). AA HD:DAT FSDA RSDA © 2011 Microchip Technology Inc. DS22272A-page 11

MCP4706/4716/4726 TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage V range is described in Electrical characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 106 T Data input hold 100kHz mode 0 — ns 2.7V-5.5V, Note6 HD:DAT time 400kHz mode 0 — ns 2.7V-5.5V, Note6 1.7MHz mode 0 — ns 4.5V-5.5V, Note6 3.4MHz mode 0 — ns 4.5V-5.5V, Note6 107 T Data input setup 100kHz mode 250 — ns Note2 SU:DAT time 400kHz mode 100 — ns 1.7MHz mode 10 — ns 3.4MHz mode 10 — ns 109 T Output valid 100kHz mode — 3750 ns Note1, Note8 AA from clock 400kHz mode — 1200 ns 1.7MHz mode — 150 ns Cb = 100pF, Note1, Note7, Note8 — 310 ns Cb = 400pF, Note1, Note5, Note8 3.4MHz mode — 150 ns Cb = 100pF, Note1, Note8 110 TBUF Bus free time 100kHz mode 4700 — ns Time the bus must be free before a new transmission 400kHz mode 1300 — ns can start 1.7MHz mode N.A. — ns 3.4MHz mode N.A. — ns Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t ≥250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V and V of IH IL the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use C in pF for the calculations. b 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (T ) or Clock Low time (T ) can be SU:DAT LOW affected. Data Input: This parameter must be longer than t . SP Data Output: This parameter is characterized, and tested indirectly by testing T parameter. AA 7: Ensured by the T 3.4MHz specification test. AA 2 8: The specification is not part of the I C specification. T = T + T (or T ). AA HD:DAT FSDA RSDA DS22272A-page 12 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 TABLE 1-3: I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C ≤ TA ≤ +125°C (Extended) Operating Voltage V range is described in Electrical characteristics DD Param. Sym Characteristic Min Max Units Conditions No. 111 T Input filter spike 100kHz mode — 50 ns NXP Spec states N.A. SP suppression 400kHz mode — 50 ns (SDA and SCL) 1.7MHz mode — 10 ns Spike suppression 3.4MHz mode — 10 ns Spike suppression — — — ns Standard Mode, (Not Applicable) 50 (typ) — — ns Fast Mode 10 (typ) — — ns High Speed Mode 1.7 10 (typ) — — ns High Speed Mode 3.4 Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400kHz) I2C-bus device can be used in a standard-mode (100kHz) I2C-bus system, but the requirement t ≥250ns must then be met. This will automatically be the case if the device does not SU;DAT stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. T max.+t =1000+250=1250ns (according to the standard-mode I2C bus specification) before R SU;DAT the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V and V of IH IL the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use C in pF for the calculations. b 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I2C bus line. If this parameter is too long, the Data Input Setup (T ) or Clock Low time (T ) can be SU:DAT LOW affected. Data Input: This parameter must be longer than t . SP Data Output: This parameter is characterized, and tested indirectly by testing T parameter. AA 7: Ensured by the T 3.4MHz specification test. AA 2 8: The specification is not part of the I C specification. T = T + T (or T ). AA HD:DAT FSDA RSDA © 2011 Microchip Technology Inc. DS22272A-page 13

MCP4706/4716/4726 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V =+2.7V to +5.5V, V =GND. DD SS Parameters Symbol Min Typical Max Units Conditions Temperature Ranges Specified Temperature Range T -40 — +125 °C A Operating Temperature Range T -40 — +125 °C Note1 A Storage Temperature Range T -65 — +150 °C A Thermal Package Resistances Thermal Resistance, 6L-SOT-23 θ — 190 — °C/W JA Thermal Resistance, 6L-DFN (2 x 2) θ — 91 — °C/W JA Note 1: The MCP47X6 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause T to exceed the Maximum Junction Temperature of +150°C. J DS22272A-page 14 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5kΩ, CL = 100pF. 12 12 -40C -40C +25C +25C 8 +85C 8 +85C +125C +125C 4 4 b) b) S S L L or ( 0 or ( 0 Err Err L L N -4 N -4 I I -8 -8 -12 -12 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-1: INL vs. Code (code = 100 to FIGURE 2-4: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). 4000) and Temperature (MCP4726). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 3 3 -40C -40C +25C +25C 2 +85C 2 +85C +125C +125C 1 1 b) b) S S L L or ( 0 or ( 0 Err Err L L N-1 N-1 I I -2 -2 -3 -3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-2: INL vs. Code (code = 25 to FIGURE 2-5: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). 1000) and Temperature (MCP4716). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 1.0 1.0 -40C -40C +25C +25C +85C +85C +125C +125C 0.5 0.5 b) b) S S L L or ( 0.0 or ( 0.0 Err Err L L N N I I -0.5 -0.5 -1.0 -1.0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-3: INL vs. Code (code = 6 to FIGURE 2-6: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). 250) and Temperature (MCP4706). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 © 2011 Microchip Technology Inc. DS22272A-page 15

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 0.4 0.4 0.3 0.3 0.2 0.2 b) 0.1 b) 0.1 S S L L or ( 0.0 or ( 0.0 Err Err L -0.1 L -0.1 N N D D -0.2 -0.2 -40C -40C -0.3 ++2855CC -0.3 ++2855CC +125C +125C -0.4 -0.4 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-7: DNL vs. Code (code = 100 FIGURE 2-10: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). to 4000) and Temperature (MCP4726). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 0.3 0.3 0.2 0.2 0.1 0.1 b) b) S S L L or ( 0.0 or ( 0.0 Err Err L L N-0.1 N-0.1 D D -0.2 -+4205CC -0.2 -+4205CC +85C +85C +125C +125C -0.3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-8: DNL vs. Code (code = 25 to FIGURE 2-11: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). 1000) and Temperature (MCP4716). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 0.20 0.20 0.15 0.15 0.10 0.10 b) 0.05 b) 0.05 S S L L or ( 0.00 or ( 0.00 Err Err L -0.05 L -0.05 N N D D -0.10 -0.10 -40C -40C -0.15 ++2855CC -0.15 ++2855CC +125C +125C -0.20 -0.20 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-9: DNL vs. Code (code = 6 to FIGURE 2-12: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). 250) and Temperature (MCP4706). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 DS22272A-page 16 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 2.0 -18.0 2.7V 5.0V 5.5V -20.0 Zero Scale Error (LSb)011...505 Full Scale Error (LSb)----22228642....0000 -30.0 25..70VV 5.5V 0.0 -32.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-13: Zero Scale Error (ZSE) vs. FIGURE 2-16: Full Scale Error (FSE) vs. Temperature (MCP4726). Temperature (MCP4726). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 0.5 -4.0 2.7V 5.0V 5.5V 0.4 Zero Scale Error (LSb)00..23 Full Scale Error (LSb)---765...000 0.1 2.7V 5.0V 5.5V 0.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-14: Zero Scale Error (ZSE) vs. FIGURE 2-17: Full Scale Error (FSE) vs. Temperature (MCP4716). Temperature (MCP4716). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 0.20 0.0 2.7V 5.0V 5.5V Zero Scale Error (LSb)000...011505 Full Scale Error (LSb)---110...505 2.7V 5.0V 5.5V 0.00 -2.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-15: Zero Scale Error (ZSE) vs. FIGURE 2-18: Full Scale Error (FSE) vs. Temperature (MCP4706). Temperature (MCP4706). V = 5V, V :V = ‘00’. V = 2.7V, V :V = ‘00’. DD REF1 REF0 DD REF1 REF0 © 2011 Microchip Technology Inc. DS22272A-page 17

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 12 12 -40C -40C +25C +25C 8 +85C 8 +85C +125C +125C 4 4 b) b) S S L L or ( 0 or ( 0 Err Err L L N -4 N -4 I I -8 -8 -12 -12 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-19: INL vs. Code (code = 100 to FIGURE 2-22: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). 4000) and Temperature (MCP4726). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 3 3 -40C -40C +25C +25C 2 +85C 2 +85C +125C +125C 1 1 b) b) S S L L or ( 0 or ( 0 Err Err L L N-1 N-1 I I -2 -2 -3 -3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-20: INL vs. Code (code = 25 to FIGURE 2-23: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). 1000) and Temperature (MCP4716). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 1.0 1.0 -40C -40C +25C +25C +85C +85C +125C +125C 0.5 0.5 b) b) S S L L or ( 0.0 or ( 0.0 Err Err L L N N I I -0.5 -0.5 -1.0 -1.0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-21: INL vs. Code (code = 6 to FIGURE 2-24: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). 250) and Temperature (MCP4706). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD DS22272A-page 18 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 0.4 0.4 0.3 0.3 0.2 0.2 b) 0.1 b) 0.1 S S L L or ( 0.0 or ( 0.0 Err Err L -0.1 L -0.1 N N D D -0.2 -0.2 -40C -40C -0.3 ++2855CC -0.3 ++2855CC +125C +125C -0.4 -0.4 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-25: DNL vs. Code (code = 100 FIGURE 2-28: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). to 4000) and Temperature (MCP4726). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.3 0.3 0.2 0.2 0.1 0.1 b) b) S S L L or ( 0.0 or ( 0.0 Err Err L L N-0.1 N-0.1 D D -0.2 -+4205CC -0.2 -+4205CC +85C +85C +125C +125C -0.3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-26: DNL vs. Code (code = 25 to FIGURE 2-29: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). 1000) and Temperature (MCP4716). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.20 0.20 0.15 0.15 0.10 0.10 b) 0.05 b) 0.05 S S L L or ( 0.00 or ( 0.00 Err Err L -0.05 L -0.05 N N D D -0.10 -0.10 -40C -40C -0.15 ++2855CC -0.15 ++2855CC +125C +125C -0.20 -0.20 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-27: DNL vs. Code (code = 6 to FIGURE 2-30: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). 250) and Temperature (MCP4706). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD © 2011 Microchip Technology Inc. DS22272A-page 19

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 2.0 -18.0 2.7V 5.0V 5.5V -20.0 Zero Scale Error (LSb)011...505 Full Scale Error (LSb)----22228642....0000 -30.0 25..70VV 5.5V 0.0 -32.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-31: Zero Scale Error (ZSE) vs. FIGURE 2-34: Full Scale Error (FSE) vs. Temperature (MCP4726). Temperature (MCP4726). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.5 -4.0 2.7V 5.0V 5.5V 0.4 Zero Scale Error (LSb)00..23 Full Scale Error (LSb)---765...000 0.1 2.7V 5.0V 5.5V 0.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-32: Zero Scale Error (ZSE) vs. FIGURE 2-35: Full Scale Error (FSE) vs. Temperature (MCP4716). Temperature (MCP4716). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.20 0.0 2.7V 5.0V 5.5V Zero Scale Error (LSb)000...011505 Full Scale Error (LSb)---110...505 2.7V 5.0V 5.5V 0.00 -2.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-33: Zero Scale Error (ZSE) vs. FIGURE 2-36: Full Scale Error (FSE) vs. Temperature (MCP4706). Temperature (MCP4706). V = 5V, V :V = ‘10’, G = ‘0’, V = 2.7V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD DS22272A-page 20 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 12 12 -40C -40C +25C +25C 8 +85C 8 +85C +125C +125C 4 4 b) b) S S L L or ( 0 or ( 0 Err Err L L N -4 N -4 I I -8 -8 -12 -12 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-37: INL vs. Code (code = 100 to FIGURE 2-40: INL vs. Code (code = 100 to 4000) and Temperature (MCP4726). 4000) and Temperature (MCP4726). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 3 3 -40C -40C +25C +25C 2 +85C 2 +85C +125C +125C 1 1 b) b) S S L L or ( 0 or ( 0 Err Err L L N-1 N-1 I I -2 -2 -3 -3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-38: INL vs. Code (code = 25 to FIGURE 2-41: INL vs. Code (code = 25 to 1000) and Temperature (MCP4716). 1000) and Temperature (MCP4716). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 1.0 1.0 -40C -40C +25C +25C +85C +85C +125C +125C 0.5 0.5 b) b) S S L L or ( 0.0 or ( 0.0 Err Err L L N N I I -0.5 -0.5 -1.0 -1.0 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-39: INL vs. Code (code = 6 to FIGURE 2-42: INL vs. Code (code = 6 to 250) and Temperature (MCP4706). 250) and Temperature (MCP4706). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD © 2011 Microchip Technology Inc. DS22272A-page 21

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 0.4 0.4 0.3 0.3 0.2 0.2 b) 0.1 b) 0.1 S S L L or ( 0.0 or ( 0.0 Err Err L -0.1 L -0.1 N N D D -0.2 -0.2 -40C -40C -0.3 ++2855CC -0.3 ++2855CC +125C +125C -0.4 -0.4 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-43: DNL vs. Code (code = 100 FIGURE 2-46: DNL vs. Code (code = 100 to 4000) and Temperature (MCP4726). to 4000) and Temperature (MCP4726). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.3 0.3 0.2 0.2 0.1 0.1 b) b) S S L L or ( 0.0 or ( 0.0 Err Err L L N-0.1 N-0.1 D D -0.2 -+4205CC -0.2 -+4205CC +85C +85C +125C +125C -0.3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-44: DNL vs. Code (code = 25 to FIGURE 2-47: DNL vs. Code (code = 25 to 1000) and Temperature (MCP4716). 1000) and Temperature (MCP4716). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.20 0.20 0.15 0.15 0.10 0.10 b) 0.05 b) 0.05 S S L L or ( 0.00 or ( 0.00 Err Err L -0.05 L -0.05 N N D D -0.10 -0.10 -40C -40C -0.15 ++2855CC -0.15 ++2855CC +125C +125C -0.20 -0.20 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-45: DNL vs. Code (code = 6 to FIGURE 2-48: DNL vs. Code (code = 6 to 250) and Temperature (MCP4706). 250) and Temperature (MCP4706). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD DS22272A-page 22 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 2.0 -18.0 2.7V 5.0V 5.5V -20.0 Zero Scale Error (LSb)011...505 Full Scale Error (LSb)----22228642....0000 -30.0 25..70VV 5.5V 0.0 -32.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-49: Zero Scale Error (ZSE) vs. FIGURE 2-52: Full Scale Error (FSE) vs. Temperature (MCP4726). Temperature (MCP4726). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.5 -4.0 2.7V 5.0V 5.5V 0.4 Zero Scale Error (LSb)00..23 Full Scale Error (LSb)---765...000 0.1 2.7V 5.0V 5.5V 0.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-50: Zero Scale Error (ZSE) vs. FIGURE 2-53: Full Scale Error (FSE) vs. Temperature (MCP4716). Temperature (MCP4716). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD 0.20 0.0 2.7V 5.0V 5.5V Zero Scale Error (LSb)000...011505 Full Scale Error (LSb)---110...505 2.7V 5.0V 5.5V 0.00 -2.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-51: Zero Scale Error (ZSE) vs. FIGURE 2-54: Full Scale Error (FSE) vs. Temperature (MCP4706). Temperature (MCP4706). V = 5V, V :V = ‘11’, G = ‘0’, V = 2.7V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = V . V = V . REF DD REF DD © 2011 Microchip Technology Inc. DS22272A-page 23

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 16 0.5 2.7V 5.0V 0.4 5.5V 12 0.3 0.2 8 Sb) Sb) 0.1 L L or ( 4 or ( 0.0 L Err L Err-0.1 N 0 N I D-0.2 -0.3 -4 2.7V -0.4 5.0V 5.5V -8 -0.5 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-55: INL vs. Code (code = 100 to FIGURE 2-58: DNL vs. Code (code = 100 4000) and V (2.7V, 5V, 5.5V) (MCP4726). to 4000) and V (2.7V, 5V, 5.5V) (MCP4726). DD DD V :V = ‘10’, G = ‘1’, V = V /2, V :V = ‘10’, G = ‘1’, V = V /2, REF1 REF0 REF DD REF1 REF0 REF DD Temp = +25°C. Temp = +25°C. 3 0.4 2.7V 5.0V 2 5.5V 0.3 0.2 1 b) b) LS LS 0.1 or ( 0 or ( Err Err 0.0 L L N-1 N I D-0.1 -2 -0.2 2.7V 5.0V 5.5V -3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-56: INL vs. Code (code = 25 to FIGURE 2-59: DNL vs. Code (code = 25 to 1000) and V (2.7V, 5V, 5.5V) (MCP4716). 1000) and V (2.7V, 5V, 5.5V) (MCP4716). DD DD V :V = ‘10’, G = ‘1’, V = V /2, V :V = ‘10’, G = ‘1’, V = V /2, REF1 REF0 REF DD REF1 REF0 REF DD Temp = +25°C. Temp = +25°C. 1.0 0.30 2.7V 5.0V 0.25 5.5V 0.20 0.5 0.15 0.10 b) b) S S 0.05 L L or ( 0.0 or ( 0.00 Err Err-0.05 L L N N-0.10 I D -0.5 -0.15 -0.20 2.7V -0.25 55..05VV -1.0 -0.30 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-57: INL vs. Code (code = 6 to FIGURE 2-60: DNL vs. Code (code = 6 to 250) and V (2.7V, 5V, 5.5V) (MCP4706). 250) and V (2.7V, 5V, 5.5V) (MCP4706). DD DD V :V = ‘10’, G = ‘1’, V = V /2, V :V = ‘10’, G = ‘1’, V = V /2, REF1 REF0 REF DD REF1 REF0 REF DD Temp = +25°C. Temp = +25°C. DS22272A-page 24 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 16 0.5 2.7V 5.0V 0.4 5.5V 12 0.3 0.2 8 Sb) Sb) 0.1 L L or ( 4 or ( 0.0 L Err L Err-0.1 N 0 N I D-0.2 -0.3 -4 2.7V -0.4 5.0V 5.5V -8 -0.5 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-61: INL vs. Code (code = 100 to FIGURE 2-64: DNL vs. Code (code = 100 4000) and V (2.7V, 5V, 5.5V) (MCP4726). to 4000) and V (2.7V, 5V, 5.5V) (MCP4726). DD DD V :V = ‘11’, G = ‘1’, V = V /2, V :V = ‘11’, G = ‘1’, V = V /2, REF1 REF0 REF DD REF1 REF0 REF DD Temp = +25°C. Temp = +25°C. 3 0.4 2.7V 5.0V 2 5.5V 0.3 0.2 1 b) b) LS LS 0.1 or ( 0 or ( Err Err 0.0 L L N-1 N I D-0.1 -2 -0.2 2.7V 5.0V 5.5V -3 -0.3 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-62: INL vs. Code (code = 25 to FIGURE 2-65: DNL vs. Code (code = 25 to 1000) and V (2.7V, 5V, 5.5V) (MCP4716). 1000) and V (2.7V, 5V, 5.5V) (MCP4716). DD DD V :V = ‘11’, G = ‘1’, V = V /2, V :V = ‘11’, G = ‘1’, V = V /2, REF1 REF0 REF DD REF1 REF0 REF DD Temp = +25°C. Temp = +25°C. 1.0 0.30 2.7V 5.0V 0.25 5.5V 0.20 0.5 0.15 0.10 b) b) LS LS0.05 or ( 0.0 or (0.00 Err Err-0.05 L L N N-0.10 I D -0.5 -0.15 -0.20 2.7V -0.25 55..05VV -1.0 -0.30 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-63: INL vs. Code (code = 6 to FIGURE 2-66: DNL vs. Code (code = 6 to 250) and V (2.7V, 5V, 5.5V) (MCP4706). 250) and V (2.7V, 5V, 5.5V) (MCP4706). DD DD V :V = ‘11’, G = ‘1’, V = V /2, V :V = ‘11’, G = ‘1’, V = V /2, REF1 REF0 REF DD REF1 REF0 REF DD Temp = +25°C. Temp = +25°C. © 2011 Microchip Technology Inc. DS22272A-page 25

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 16 1.0 1V 1V 2V 3V 2V 4V 5V 12 3V 4V 5V 0.5 8 b) b) S S L L or ( 4 or ( 0.0 Err Err L L N 0 N I D -0.5 -4 -8 -1.0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-67: INL vs. Code (code = 100 to FIGURE 2-70: DNL vs. Code (code = 100 4000) and V (MCP4726). to 4000) and V (MCP4726). REF REF V = 5V, V :V = ‘10’, G = ‘0’, V = 5V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. REF REF 4 0.5 1V 1V 2V 3V 2V 0.4 4V 5V 3 34VV 0.3 5V 0.2 2 Sb) Sb) 0.1 NL Error (L 01 NL Error (L-00..10 I D-0.2 -0.3 -1 -0.4 -2 -0.5 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-68: INL vs. Code (code = 25 to FIGURE 2-71: DNL vs. Code (code = 25 to 1000) and V (MCP4716). 1000) and V (MCP4716). REF REF V = 5V, V :V = ‘10’, G = ‘0’, V = 5V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. REF REF 1.0 0.5 1V 2V 3V 0.4 4V 5V 0.3 0.5 0.2 Sb) Sb) 0.1 NL Error (L 0.0 NL Error (L-00..10 I D-0.2 -0.5 1V -0.3 2V 3V -0.4 4V -1.0 5V -0.5 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-69: INL vs. Code (code = 6 to FIGURE 2-72: DNL vs. Code (code = 6 to 250) and V (MCP4706). 250) and V (MCP4706). REF REF V = 5V, V :V = ‘10’, G = ‘0’, V = 5V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. REF REF DS22272A-page 26 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 16 1.0 1V 1V 2V 3V 2V 4V 5V 12 3V 4V 5V 0.5 8 b) b) S S L L or ( 4 or ( 0.0 Err Err L L N 0 N I D -0.5 -4 -8 -1.0 0 1024 2048 3072 4096 0 1024 2048 3072 4096 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-73: INL vs. Code (code = 100 to FIGURE 2-76: DNL vs. Code (code = 100 4000) and V (MCP4726). to 4000) and V (MCP4726). REF REF V = 5V, V :V = ‘11’, G = ‘0’, V = 5V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. REF REF 4 0.5 1V 1V 2V 3V 2V 0.4 4V 5V 3 34VV 0.3 5V 0.2 2 Sb) Sb) 0.1 NL Error (L 01 NL Error (L-00..10 I D-0.2 -0.3 -1 -0.4 -2 -0.5 0 128 256 384 512 640 768 896 1024 0 128 256 384 512 640 768 896 1024 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-74: INL vs. Code (code = 25 to FIGURE 2-77: DNL vs. Code (code = 25 to 1000) and V (MCP4716). 1000) and V (MCP4716). REF REF V = 5V, V :V = ‘11’, G = ‘0’, V = 5V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. REF REF 1.0 0.5 1V 2V 3V 0.4 4V 5V 0.3 0.5 0.2 Sb) Sb) 0.1 NL Error (L 0.0 NL Error (L-00..10 I D-0.2 -0.5 1V -0.3 2V 3V -0.4 4V -1.0 5V -0.5 0 32 64 96 128 160 192 224 256 0 32 64 96 128 160 192 224 256 Volatile DAC Register Code Volatile DAC Register Code FIGURE 2-75: INL vs. Code (code = 6 to FIGURE 2-78: DNL vs. Code (code = 6 to 250) and V (MCP4706). 250) and V (MCP4706). REF REF V = 5V, V :V = ‘11’, G = ‘0’, V = 5V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 DD REF1 REF0 V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. V = 1V, 2V, 3V, 4V, and 5V, Temp = +25°C. REF REF © 2011 Microchip Technology Inc. DS22272A-page 27

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L -20.0 -20.0 2.7V 2.7V 5.0V 5.0V -22.0 5.5V -22.0 5.5V b)-24.0 b)-24.0 S S L L or (-26.0 or (-26.0 Err Err ut -28.0 ut -28.0 p p Out-30.0 Out-30.0 -32.0 -32.0 -34.0 -34.0 -36.0 -36.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-79: Output Error vs. FIGURE 2-82: Output Error vs. Temperature (MCP4726). V = 2.7V and 5V, Temperature (MCP4726). V = 2.7V and 5V, DD DD V :V = ‘00’, Code = 4000. V :V = ‘10’, G = ‘0’, V = V , REF1 REF0 REF1 REF0 REF DD Code = 4000. -4.0 -4.0 2.7V 2.7V 5.0V 5.0V 5.5V 5.5V Output Error (LSb)--65..00 Output Error (LSb)--65..00 -7.0 -7.0 -8.0 -8.0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-80: Output Error vs. FIGURE 2-83: Output Error vs. Temperature (MCP4716). V = 2.7V and 5V, Temperature (MCP4716). V = 2.7V and 5V, DD DD V :V = ‘00’, Code = 1000. V :V = ‘10’, G = ‘0’, V = V , REF1 REF0 REF1 REF0 REF DD Code = 1000. -0.4 -0.4 255...705VVV 255...705VVV Output Error (LSb)---100...086 Output Error (LSb)---100...086 -1.2 -1.2 -1.4 -1.4 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-81: Output Error vs. FIGURE 2-84: Output Error vs. Temperature (MCP4706). VDD = 2.7V and 5V, Temperature (MCP4706). VDD = 2.7V and 5V, VREF1:VREF0 = ‘00’, Code = 250. VREF1:VREF0 = ‘10’, G = ‘0’, VREF = VDD, Code = 250. DS22272A-page 28 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L -20.0 2.7V 5.0V -22.0 5.5V b)-24.0 S L or (-26.0 Err ut -28.0 p Out-30.0 -32.0 -34.0 -36.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-85: Output Error vs. Temperature (MCP4726). V = 2.7V and 5V, DD V :V = ‘11’, G = ‘0’, V = V , REF1 REF0 REF DD Code = 4000. -4.0 2.7V 5.0V 5.5V b)-5.0 S L or ( Err ut -6.0 p ut O -7.0 -8.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-86: Output Error vs. Temperature (MCP4716). V = 2.7V and 5V, DD V :V = ‘11’, G = ‘0’, V = V , REF1 REF0 REF DD Code = 1000. -0.4 2.7V 5.0V 5.5V -0.6 b) S L or (-0.8 Err ut p ut-1.0 O -1.2 -1.4 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-87: Output Error vs. Temperature (MCP4706). V = 2.7V and 5V, DD V :V = ‘11’, G = ‘0’, V = V , REF1 REF0 REF DD Code = 250. © 2011 Microchip Technology Inc. DS22272A-page 29

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 250 500 2.7V 2.7V 225 3.3V 3.3V 4.5V 400 4.5V 5.0V 5.0V 5.5V 5.5V 200 A) A)300 u n I (DD115705 I (PowerDown200 100 125 100 0 -40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) FIGURE 2-88: I vs. Temperature. FIGURE 2-91: Powerdown Current vs. DD V = 2.7V and 5V, V :V = ‘00’. Temperature. DD REF1 REF0 V = 2.7V, 3.3V, 4.5V, 5.0V and 5.5V, DD PD1:PD0 = ‘11’. 250 2.7V 225 3.3V 4.5V 5.0V 5.5V 200 A) u I (DD175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-89: I vs. Temperature. DD V = 2.7V and 5V, V :V = ‘10’, G = ‘0’, DD REF1 REF0 V = V . REF DD 250 2.7V 225 3.3V 4.5V 5.0V 5.5V 200 A) u I (DD175 150 125 100 -40 -20 0 20 40 60 80 100 120 Temperature (°C) FIGURE 2-90: I vs. Temperature. DD V = 2.7V and 5V, V :V = ‘11’, G = ‘0’, DD REF1 REF0 V = V . REF DD DS22272A-page 30 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS RL L L 70 6 2.7V Code = FFFh 55..05VV 5 65 4 % V)DD60 (V)UT 3 V (IH VO 2 55 1 0 50 -40 -20 0 20 40 60 80 100 120 0 1000 2000 3000 4000 5000 Load Resistance (R ) ((cid:2)) Temperature (°C) L FIGURE 2-92: V Threshold of SDA/SCL FIGURE 2-94: V vs. Resistive Load. IH OUT Inputs vs. Temperature and V . V = 5.0V. DD DD 50 6 2.7V Code = FFFh Code = 000h 5.0V 5 5.5V 45 4 % V)DD40 (V)UT 3 V (IL VO 2 35 1 0 30 -40 -20 0 20 40 60 80 100 120 0 3 6 9 12 15 I (mA) Temperature (°C) SOURCE/SINK FIGURE 2-93: V Threshold of SDA/SCL FIGURE 2-95: V vs. Source / Sink IL OUT Inputs vs. Temperature and V . Current. V = 5.0V. DD DD © 2011 Microchip Technology Inc. DS22272A-page 31

MCP4706/4716/4726 Note: Unless otherwise indicated, T = +25°C, V = 5V, V = 0V, V = Internal, Gain = x1, R = 5kΩ, C = 100pF. A DD SS REF L L FIGURE 2-96: Full-Scale Settling Time FIGURE 2-98: Half-Scale Settling Time (000h to FFFh) (MCP4726). (400h to C00h) (MCP4726). FIGURE 2-97: Full-Scale Settling Time FIGURE 2-99: Half-Scale Settling Time (FFFh to 000h) (MCP4726). (C00h to 400h) (MCP4726). FIGURE 2-100: Exiting Power Down Mode (MCP4726, Volatile DAC Register = FFFh). DS22272A-page 32 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 3.0 PIN DESCRIPTIONS An overview of the pin functions are described in Section3.1 through Section3.7. The descriptions of the pins are listed in Table3-1. TABLE 3-1: MCP47X6 PINOUT DESCRIPTION Pin SOT-23 DFN Standard Function Buffer Symbol I/O Type 6L 6L 1 6 V A Analog Buffered analog voltage output pin OUT 2 5 V — P Ground reference pin for all circuitries on the device SS 3 4 V — P Supply Voltage Pin DD 4 3 SDA I/O ST I2C Serial Data Pin 5 2 SCL I ST I2C Serial Clock Pin 6 1 V A Analog Voltage Reference Input Pin REF — 7 EP — — Exposed Pad Note1 Legend: A = Analog pins I = Digital input (high Z) O = Digital output I/O = Input / Output P = Power Note 1: The DFN package has a contact on the bottom of the package. This contact is conductively connected to the die substrate, and therefore should be unconnected or connected to the same ground as the device’s V pin. SS © 2011 Microchip Technology Inc. DS22272A-page 33

MCP4706/4716/4726 3.1 Analog Output Voltage Pin (VOUT) 3.4 Serial Data Pin (SDA) V is the DAC analog output pin. The DAC output SDA is the serial data pin of the I2C interface. The SDA OUT has an output amplifier. V can swing from pin is used to write or read the DAC registers and OUT approximately 0V to approximately V . The full-scale configuration bits. The SDA pin is an open-drain DD range of the DAC output is from V to G * V , where N-channel driver. Therefore, it needs a pull-up resistor SS RL G is the gain selection option (1x or 2x). from the V line to the SDA pin. Except for start and DD stop conditions, the data on the SDA pin must be stable In normal mode, the DC impedance of the output pin is during the high period of the clock. The high or low about 1Ω. In Power-Down mode, the output pin is state of the SDA pin can only change when the clock internally connected to a known pull-down resistor of signal on the SCL pin is low. Refer to Section5.0 “I2C 1kΩ, 125kΩ, or 640kΩ. The Power-Down selection Serial Interface” for more details of I2C Serial bits settings are shown Table4-2. Interface communication. 3.2 Positive Power Supply Input (V ) DD 3.5 Serial Clock Pin (SCL) V is the positive supply voltage input pin. The input DD SCL is the serial clock pin of the I2C interface. The supply voltage is relative to V . SS MCP47X6 devices act only as a slave and the SCL pin The power supply at the VDD pin should be as clean as accepts only external serial clocks. The input data from possible for a good DAC performance. It is the Master device is shifted into the SDA pin on the recommended to use an appropriate bypass capacitor rising edges of the SCL clock and output from the of about 0.1µF (ceramic) to ground. An additional device occurs at the falling edges of the SCL clock. The 10µF capacitor (tantalum) in parallel is also SCL pin is an open-drain N-channel driver. Therefore, recommended to further attenuate high-frequency it needs a pull-up resistor from the V line to the SCL DD noise present in application boards. pin. Refer to Section5.0 “I2C Serial Interface” for more details of I2C Serial Interface communication. 3.3 Ground (V ) SS 3.6 Voltage Reference Pin (V ) The V pin is the device ground reference. REF SS The user must connect the V pin to a ground plane This pin is used for the external voltage reference input. SS through a low-impedance connection. If an analog The user can select VDD voltage or the VREF pin ground path is available in the application PCB (printed voltage as the reference resistor ladder’s voltage circuit board), it is highly recommended that the V pin reference. SS be tied to the analog ground path or isolated within an When the V pin signal is selected, there is an option REF analog ground plane of the circuit board. for this voltage to be buffered or unbuffered. This is offered in cases where the reference voltage does not have the current capability not to drop its voltage when connected to the internal resistor ladder circuit. When the V is selected as reference voltage, this pin DD is disconnected from the internal circuit. See Section4.2 “DAC’s (Resistor Ladder) Reference Voltage” and Table4-4 for more details on the configuration bits. 3.7 Exposed Pad (EP) This pad is conductively connected to the device's substrate. This pad should be tied to the same potential as the V pin (or left unconnected). This pad could be SS used to assist as a heat sink for the device when connected to a PCB heat sink. DS22272A-page 34 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 4.0 GENERAL DESCRIPTION 4.1 Power-On-Reset / Brown Out Reset (POR/BOR) The MCP4706, MCP4716, and MCP4726 devices are single channel voltage output 8-bit, 10-bit, and 12-bit The internal Power-On-Reset (POR) / Brown-Out DAC devices with nonvolatile memory (EEPROM) and Reset (BOR) circuit monitors the power supply voltage an I2C serial interface. This family will be referred to as (V ) during operation. This circuit ensures correct DD MCP47X6. device start-up at system power-up and power-down The devices use a resistor ladder architecture. The events. VRAM is the RAM retention voltage and is resistor ladder DAC is driven from a software always lower than the POR trip point voltage. selectable voltage reference source. The source can POR occurs as the voltage is rising (typically from 0V), be either the device’s internal VDD or the external VREF while BOR occurs as the voltage is falling (typically pin voltage. from V or higher). DD(MIN) The DAC output is buffered with a low power and When the rising V voltage crosses the V trip DD POR precision output amplifier (op amp). This output point, the following occurs: amplifier provides a rail-to-rail output with low offset • Nonvolatile DAC Register value latched into voltage and low noise. The gain of the output buffer is volatile DAC Register software configurable. • Nonvolatile configuration bit values latched into This device also has user programmable nonvolatile volatile configuration bits memory (EEPROM), which allows the user to save the • POR status bit is set (“1”) desired POR/BOR value of the DAC register and • The reset delay timer starts; when timer times out device configuration bits. (t ), the I2C interface is operational. The devices use a two-wire I2C serial communication PORD The analog output (V ) state will be determined by interface and operate with a single supply voltage from OUT the state of the volatile configuration bits and the DAC 2.7V to 5.5V. Register. This is called a POR reset (event). When the falling V voltage crosses the V trip DD POR point, the following occurs: • Device is forced into a power down state (PD1:PD0 = ‘11’). Analog circuitry is turned off. • Volatile DAC Register is forced to 000h • Volatile configuration bits V , V and G are REF1 REF0 forced to ‘0’ Figure4-1 illustrates the conditions for power-up and power-down events under typical conditions. Volatile memory POR starts Reset Delay Timer. Volatile memory retains data value When timer times out, I2C interface becomes corrupted can operate (if V >= V ) DD DD(MIN) V ) DD(MIN V V POR BOR T V PORD RAM (60µs max.) Normal Operation Device in Device in Below Device Device in unknown POR state minimum in powerunknown state EEPROM data latched into volatile operating down state configuration bits and DAC register. voltage state POR reset forced active POR status bit is set (“1”) BOR reset, volatile DAC Register = 000h volatile VREF1:VREF0 = 00 volatile G = 0 volatile PD1:PD0 = 11 FIGURE 4-1: Power-On-Reset Operation. © 2011 Microchip Technology Inc. DS22272A-page 35

MCP4706/4716/4726 4.2 DAC’s (Resistor Ladder) 4.3 Resistor Ladder Reference Voltage The resistor ladder is a digital potentiometer with the B The device can be configured to use one of three Terminal internally grounded and the A terminal voltage sources for the resistor ladder’s reference connected to the selected reference voltage (see voltage (V ) (see Figure4-2). These are: Figure4-3). The volatile DAC register controls the RL wiper position. The wiper voltage (V ) is proportional to 1. V pin voltage W DD the DAC register value divided by the number of 2. VREF pin voltage internally buffered resistor elements (RS) in the ladder (256, 1024, or 3. VREF pin voltage unbuffered 4096) related to the VRL voltage. The selection of the voltage is specified with the volatile V :V configuration bits (see Table4-4). There Note: The maximum wiper position is 2n - 1, REF1 REF0 are nonvolatile and volatile V :V configuration while the number of resistors in the REF1 REF0 bits. On a POR/BOR event, the state of the nonvolatile resistor ladder is 2n. This means that V :V configuration bits are latched into the when the DAC register is at full scale, REF1 REF0 volatile VREF1:VREF0 configuration bits. there is one resistor element (RS) between the wiper and the V voltage. When the user selects the V as reference, the V RL DD REF pin voltage is not connected to the resistor ladder. The resistor ladder (RRL) has a typical impedance of approximately 210kΩ. This resistor ladder resistance If the V pin is selected, then one needs to select REF (R ) may vary from device to device up to ±20%. between the buffered or unbuffered mode. RL Since this is a voltage divider configuration, the actual In unbuffered mode, the VREF pin voltage may be from RRL resistance does not effect the output given a fixed VSS to VDD. voltage at VRL. Note: In unbuffered mode, the voltage source If the unbuffered VREF pin is used as the VRL voltage should have a low output impedance. If source, this voltage source should have a low output the voltage source has a high output impedance. impedance, then the voltage on the When the DAC is powered down, the resistor ladder is VREF’s pin would be lower than expected. disconnected from the selected reference voltage. The resistor ladder has a typical impedance of 210kΩ and a typical capacitance of 29pF. PD1:PD0 VRL DAC Register In buffered mode, the V pin voltage may be from REF 0.01V to V -0.04V. The input buffer (amplifier) DD R n S(2 ) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the 2n - 1 input range and frequency response. R n S(2 - 1) Note: Any variation or noises on the reference 2n - 2 source can directly affect the DAC output. R n The reference voltage needs to be as R S(2 - 2) RL clean as possible for accurate DAC performance. VW VREF1:VREF0 1 V REF R VDD ce on S(1) ReferenSelecti VRL 0 Buffer DAC Register Value V = * V W # Resistors in Resistor Ladder RL FIGURE 4-2: Resistor Ladder Reference Where: Voltage Selection Block Diagram. # Resistors in Resistor Ladder = 256 (MCP4706) 1024 (MCP4716) 4096 (MCP4726) FIGURE 4-3: Resistor Ladder. DS22272A-page 36 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 4.4 Output Buffer / V Operation 4.4.2 OUTPUT VOLTAGE OUT The DAC output is buffered with a low power and The volatile DAC Register’s value controls the analog precision output amplifier (op amp). Figure4-4 shows VOUT voltage, along with the device’s five configuration a block diagram. bits. The volatile DAC Register’s value is unsigned binary. This amplifier provides a rail-to-rail output with low offset voltage and low noise. The user can select the The formula for the output voltage is given in Equation4-1. Table4-1 shows examples of volatile output gain of the output amplifier. Gain options are: DAC Register values and the corresponding theoretical a) Gain of 1, with either V or V pin used as DD REF V voltage for the MCP47X6 devices. OUT reference voltage b) Gain of 2, only when VREF pin is used as Note: When Gain = 2 (VRL = VREF), reference voltage. The VREF pin voltage should if VREF > VDD / 2, the VOUT voltage will be be limited to VDD/2. limited to VDD. So if VREF = VDD, then the The amplifier’s output can drive the resistive and high VOUT voltage will not change for volatile capacitive loads without oscillation. The amplifier DAC Register values mid-scale and provides a maximum load current which is enough for greater, since the op amp at full scale most programmable voltage reference applications. output. Refer to Section1.0 “Electrical Characteristics” for the specifications of the output amplifier. EQUATION 4-1: CALCULATING OUTPUT VOLTAGE (V ) OUT Note: The load resistance must keep higher V * DAC Register Value than 5kΩ for the stable and expected VOUT = R L * Gain # Resistors in Resistor Ladder analog output (to meet electrical specifications). # Resistors in Resistor Ladder = 4096 (MCP4726) 1024 (MCP4716) In any of the three Power-Down modes, the op amp is 256 (MCP4706) powered down and it’s output becomes a high impedance to the V pin. OUT The DAC register value will be latched on the falling edge of the acknowledge pulse of the write command’s last byte. Then the V voltage will start driving to the Gain (1x or 2x) OUT new value. (G = 0 or 1) The following events update the analog voltage output (V ): OUT Op • Power-On-Reset or General Call Reset VW Amp VOUT command: Output is updated with EEPROM data. • Falling edge of the acknowledge pulse of the last write command byte. FIGURE 4-4: Output Buffer Block Diagram. 4.4.2.1 Resolution / Step Voltage 4.4.1 PROGRAMMABLE GAIN The Step voltage is dependent on the device resolution and the output voltage range. One LSb is defined as The amplifier’s gain is controlled by the Gain (G) the ideal voltage difference between two successive configuration bit (See Table4-4) and the V reference RL codes. The step voltage can easily be calculated by selection. When the V reference selection is the RL using Equation4-1 where the DAC Register Value is device’s V voltage, the G bit is ignored and a gain of DD equal to 1. 1 is used. The volatile G bit value can be modified by: • POR event 4.4.3 DRIVING RESISTIVE AND CAPACITIVE LOADS • BOR event • I2C write commands The V pin can drive up to 100pF of capacitive load OUT • I2C General Call Reset command in parallel with a 5kΩ resistive load (to meet electrical specifications). Figure2-57 shows the V vs. OUT Resistive Load. V drops slowly as the load resistance decreases OUT after about 3.5kΩ. It is recommended to use a load with R greater than 5kΩ. L © 2011 Microchip Technology Inc. DS22272A-page 37

MCP4706/4716/4726 TABLE 4-1: DAC INPUT CODE VS. ANALOG OUTPUT (V ) (V = 5.0V) OUT DD LSb Gain V (4) Volatile DAC OUT Device V (1) Selection Register Value RL Equation uV (2) Equation V 5.0V 5.0V/4096 1,220.7 1x V * (4095/4096) * 1 4.998779 RL 1111 1111 1111 1x VRL * (4095/4096) * 1 2.499390 2.5V 2.5V/4096 610.4 2x(3) V * (4095/4096) * 2) 4.998779 RL 5.0V 5.0V/4096 1,220.7 1x V * (2047/4096) * 1) 2.498779 RL 0111 1111 1111 1x VRL * (2047/4096) * 1) 1.249390 2.5V 2.5V/4096 610.4 MCP4726 2x(3) VRL * (2047/4096) * 2) 2.498779 (12-bit) 5.0V 5.0V/4096 1,220.7 1x V * (1023/4096) * 1) 1.248779 RL 0011 1111 1111 1x VRL * (1023/4096) * 1) 0.624390 2.5V 2.5V/4096 610.4 2x(3) V * (1023/4096) * 2) 1.248779 RL 5.0V 5.0V/4096 1,220.7 1x V * (0/4096) * 1) 0 RL 0000 0000 0000 1x VRL * (0/4096) * 1) 0 2.5V 2.5V/4096 610.4 2x(3) V * (0/4096) * 2) 0 RL 5.0V 5.0V/1024 4,882.8 1x V * (1023/1024) * 1 4.995117 RL 11 1111 1111 1x VRL * (1023/1024) * 1 2.497559 2.5V 2.5V/1024 2,441.4 2x(3) V * (1023/1024) * 2 4.995117 RL 5.0V 5.0V/1024 4,882.8 1x V * (511/1024) * 1 2.495117 RL 01 1111 1111 1x VRL * (511/1024) * 1 1.247559 2.5V 2.5V/1024 2,441.4 MCP4716 2x(3) VRL * (511/1024) * 2 2.495117 (10-bit) 5.0V 5.0V/1024 4,882.8 1x V * (255/1024) * 1 1.245117 RL 00 1111 1111 1x VRL * (255/1024) * 1 0.622559 2.5V 2.5V/1024 2,441.4 2x(3) V * (255/1024) * 2 1.245117 RL 5.0V 5.0V/1024 4,882.8 1x V * (0/1024) * 1 0 RL 00 0000 0000 1x VRL * (0/1024) * 1 0 2.5V 2.5V/1024 2,441.4 2x(3) V * (0/1024) * 1 0 RL 5.0V 5.0V/256 19,531.3 1x V * (255/256) * 1 4.980469 RL 1111 1111 1x VRL * (255/256) * 1 2.490234 2.5V 2.5V/256 9,765.6 2x(3) V * (255/256) * 2 4.980469 RL 5.0V 5.0V/256 19,531.3 1x V * (127/256) * 1 2.480469 RL 0111 1111 1x VRL * (127/256) * 1 1.240234 2.5V 2.5V/256 9,765.6 MCP4706 2x(3) VRL * (127/256) * 2 2.480469 (8-bit) 5.0V 5.0V/256 19,531.3 1x V * (63/256) * 1 1.230469 RL 0011 1111 1x VRL * (63/256) * 1 0.615234 2.5V 2.5V/256 9,765.6 2x(3) V * (63/256) * 2 1.230469 RL 5.0V 5.0V/256 19,531.3 1x V * (0/256) * 1 0 RL 0000 0000 1x VRL * (0/256) * 1 0 2.5V 2.5V/256 9,765.6 2x(3) V * (0/256) * 2 0 RL Note 1: V is the resistor ladder’s reference voltage. It is independent of V :V selection. RL REF1 REF0 2: Gain selection of 2x requires voltage reference source to come from V pin and REF requires V pin voltage ≤ V / 2. REF DD 3: Requires G = ‘1’, VREF1:VREF0 = ‘10’ or ‘11’, and VRL ≤ VDD / 2. 4: These theoretical calculations do not take into account the offset and gain errors. DS22272A-page 38 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 4.5 Power-Down Operation To allow the application to conserve power when the Gain (1x or 2x) (Gx = 0 or 1) DAC operation is not required, three power down modes are available. The Power-Down configuration bits (PD1:PD0) control the power down operation V OUT (Figure4-5). All power down modes do the following: Op Amp V • Turning off most of its internal circuits (op amp, W resistor ladder, ...) • Op amp output becomes high impedance to the PD1:PD0 V pin OUT • Disconnects resistor ladder from reference Ω Ω Ω k k voltage (VRL) 1k 25 40 • Retains the value of the volatile DAC register and 1 6 configuration bits, and the nonvolatile (EEPROM) DAC register and configuration bits Depending on the selected power down mode, the FIGURE 4-5: Op Amp to VOUT Pin Block following will occur: Diagram. • V pin is switched to one of three resistive pull OUT 4.5.1 EXITING POWER-DOWN downs (See Table4-2) When the device exits the power down mode the - 640kΩ (typical) following occurs: - 125kΩ (typical) • Disabled circuits (op amp, resistor ladder, ...) are - 1kΩ (typical) turned on There is a delay (T ) between the PD1:PD0 bits PDE • Resistor ladder is connected to selected changing from ‘00’ to either ‘01’, ‘10’, or ‘11’ and the op reference voltage (V ) amp no longer driving the V output and the pull RL OUT • Selected pull down resistor is disconnected down resistors are sinking current. • The V output will be driven to the voltage In any of the power down modes, where the V pin OUT OUT represented by the volatile DAC Register’s value is not externally connected (sinking or sourcing and configuration bits current), the power down current will typical be 60nA (see Section1.0 “Electrical Characteristics”). The VOUT output signal will require time as these circuits are powered up and the output voltage is driven Section6.0 “MCP47X6 I2C Commands” describes to the specified value as determined by the volatile the I2C commands for writing the power-down bits. The DAC register and configuration bits. commands that can update the volatile PD1:PD0 bits are: Note: Since the op amp and resistor ladder were • Write Volatile DAC Register powered off (0V), the op amp’s input • Write Volatile Memory voltage (V ) can be considered 0V. There W • Write All Memory is a delay (T ) between the PD1:PD0 PDD • Write Volatile Configuration bits bits updated to ‘00’ and the op amp driving • General Call Reset the V output. The op amp’s settling OUT • General Call Wake-up time (from 0V) needs to be taken into Note: The I2C serial interface circuit is not account to ensure the V voltage OUT affected by the Power-Down mode. This reflects the selected value. circuit remains active in order to receive The following events will change the PD1:PD0 bits to any command that might come from the ‘00’ and therefore exit the Power-Down mode. These I2C master device. are: • Any I2C write command for where the PD1:PD0 TABLE 4-2: POWER-DOWN BITS AND bits are ‘00’. OUTPUT RESISTIVE LOAD • I2C General Call Wake-up Command. PD1 PD0 Function • I2C General Call Reset Command. 0 0 Normal operation (if nonvolatile PD1:PD0 bits are ‘00’). 0 1 1kΩ resistor to ground 1 0 125kΩ resistor to ground 1 1 640kΩ resistor to ground © 2011 Microchip Technology Inc. DS22272A-page 39

MCP4706/4716/4726 4.6 Device Resets 4.7 DAC Registers, Configuration Bits, and Status Bits Device Resets can be grouped into two types. Resets due to change in voltage (POR/BOR Reset), and resets The MCP47X6 devices have both volatile and caused by the system master (such as a nonvolatile (EEPROM) memory. Figure4-6 shows the microcontroller). volatile and nonvolatile memory and their interaction After a device reset, and when V ≥ V , the due to a POR event. DD DD(MIN) device memory may be written or read. There are five configuration bits in both the volatile and nonvolatile memory, the DAC registers in both the 4.6.1 POR/BOR RESET OPERATION volatile and nonvolatile memory, and two volatile status The POR and BOR trip points are at the same voltage, bits. The DAC registers (volatile and nonvolatile) will be and is determined if the V voltage is rising or falling either 12-bits (MCP4726), 10-bits (MCP4716), or 8-bits DD (see Figure4-1). What occurs is different depending if (MCP4706) wide. the reset is a POR or BOR reset. When the device is first powered up, it automatically uploads the EEPROM memory values to the volatile POR Reset (VDD Rising) memory. The volatile memory determines the analog output (V ) pin voltage. After the device is powered On a POR Reset, the nonvolatile memory values (DAC OUT up, the user can update the device memory. Register and Configuration bits) are latched into the volatile memory. This configures the analog output The I2C interface is how this memory is read and (V ) circuitry. Also a reset delay timer starts. During written. Refer to Section5.0 “I2C Serial Interface” OUT this delay time, the I2C interface will not accept and Section6.0 “MCP47X6 I2C Commands” for commands. more details on the reading and writing the device’s memory. BOR Reset (V Falling) When the nonvolatile memory is written (using the I2C DD Write All Memory command), the volatile memory is On a BOR Reset, the device is forced into a power written with the same values. The device starts writing down state. The volatile PD1:PD0 bits forced to ‘11’ and the EEPROM cell at the acknowledge pulse of the all other volatile memory forced to ‘0’. The I2C interface EEPROM write command. will not accept commands. Table4-3 shows the operation of the device status bits, 4.6.2 RESET COMMANDS Table4-4 shows the operation of the device configuration bits, and Table4-5 shows the factory When the MCP47X6 is in the valid operating voltage, default value of a POR/BOR event for the device the I2C General Call Reset command will force a reset configuration bits. event. This is similar to the POR reset, except that the reset delay timer is not started. There are two Status bits. These are only in volatile memory and give indication on the status of the device. In the case where the I2C Interface bus does not seem The POR bit indicates if the device V is above or to be responsive, the technique shown in Section8.9, DD below the POR trip point. During normal operation, this Software I2C Interface Reset Sequence can be used bit should be ‘1’. The RDY/BSY bit indicates if an to force the I2C interface to be reset. EEPROM write cycle is in progress. While the RDY/ BSY bit is low (during the EEPROM writing), all commands are ignored, except for the Read Command command. Config Bits DAC Register Value (1) V V PD1 PD0 G D D D N.V. Memory REF1 REF0 MAX 1 0 POR Event Status Bits (2) V V PD1 PD0 G RDY/BSY POR D D D Vol. Memory REF1 REF0 MAX 1 0 Note 1: The D value depends on the device. For the MCP4706: D = D , MCP4716: D = D , MAX MAX 7 MAX 9 and the MCP4726: D = D . MAX 11 2: Status bits are read only FIGURE 4-6: DAC Memory and POR Interaction. DS22272A-page 40 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 TABLE 4-3: STATUS BITS OPERATION Name Function RDY/BSY This bit indicates the state of the EEPROM program memory 1 = EEPROM is not in a programming cycle 0 = EEPROM is in a programming cycle POR Power-On-Reset status indicator (flag) 1 = Device is powered on with VDD > VPOR. Ensure that V is above V to ensure proper operation. DD DD(MIN) 0 = Device is in powered off state. If this value is read, VDD < VDD(MIN) < VPOR. Unreliable device operation should be expected. TABLE 4-4: CONFIGURATION BITS Name Function VREF1:VREF0 Resistor Ladder Voltage Reference (VRL) selection bits 0x = VDD (Unbuffered) 10 = VREF pin (Unbuffered) 11 = VREF pin (Buffered) PD1:PD0 Power-Down selection bits When the DAC is powered down, most of the internal circuits are powered off and the op amp is disconnected from the V pin. OUT 00 = Not Powered Down (Normal operation) 01 = Powered Down - VOUT is loaded with 1kΩ resistor to ground. 10 = Powered Down - VOUT is loaded with 100kΩ resistor to ground. 11 = Powered Down - VOUT is loaded with 500kΩ resistor to ground. Note: See Table4-2 and Figure4-5 for more details. G Gain selection bit 0 = 1x (gain of 1) 1 = 2x (gain of 2). Not applicable when VDD is used as VRL Note: If V = V , the device uses a gain of 1 only, regardless of the gain selection bit (G) REF DD setting. TABLE 4-5: CONFIGURATION BIT VALUES AFTER POR/BOR EVENT R/W R/W R/W R/W R/W Comment Bit Name VREF1 VREF0 PD1 PD0 G POR Event 0(1) 0(1) 0(1) 0(1) 0(1) When V transitions from V < V to V > V DD DD POR DD POR BOR Event 0 0 1 1 0 When V transitions from V > V to V < V DD DD BOR DD BOR Note 1: Default configuration when the device is shipped to customer. The POR/BOR value may be modified by writing the corresponding nonvolatile configuration bit. REGISTER 4-1: DAC REGISTER BITS R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Comment —(2) —(2) —(2) —(2) D7 D6 D5 D4 D3 D2 D1 D0 MCP4706 Bit Name —(2) —(2) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCP4716 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCP4726 POR/BOR Event 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) Note 1: Default configuration when the device is shipped to customer. The POR/BOR value may be modified by writing the corresponding nonvolatile configuration bit. 2: This device does not implement this bit, so there is no corresponding POR/BOR value. © 2011 Microchip Technology Inc. DS22272A-page 41

MCP4706/4716/4726 NOTES: DS22272A-page 42 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 5.0 I2C SERIAL INTERFACE 5.2 Signal Descriptions The MCP47X6 devices support the I2C serial protocol. The I2C interface uses up to two pins (signals). These The MCP47X6 I2C’s module operates in Slave mode are: (does not generate the serial clock). • SDA (Serial Data) • SCL (Serial Clock) 5.1 Overview 5.2.1 SERIAL DATA (SDA) This I2C interface is a two-wire interface. Figure5-1 shows a typical I2C Interface connection. The Serial Data (SDA) signal is the data signal of the device. The value on this pin is latched on the rising The I2C interface specifies different communication bit edge of the SCL signal when the signal is an input. rates. These are referred to as standard, fast or high speed modes. The MCP47X6 supports these three With the exception of the START and STOP conditions, modes. The bit rates of these modes are: the high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. During the • Standard Mode: bit rates up to 100kbit/s high period of the clock, the SDA pin’s value (high or • Fast Mode: bit rates up to 400kbit/s low) must be stable. Changes in the SDA pin’s value • High Speed Mode (HS mode): bit rates up to while the SCL pin is HIGH will be interpreted as a 3.4Mbit/s START or a STOP condition. A device that sends data onto the bus is defined as 5.2.2 SERIAL CLOCK (SCL) transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which The Serial Clock (SCL) signal is the clock signal of the generates the serial clock (SCL), controls the bus device. The rising edge of the SCL signal latches the access and generates the START and STOP value on the SDA pin. conditions. The MCP47X6 device works as slave. Both The MCP47X6 will not stretch the clock signal (SCL) master and slave can operate as transmitter or since memory read access occurs fast enough. receiver, but the master device determines which mode Depending on the clock rate mode, the interface will is activated. Communication is initiated by the master display different characteristics. (microcontroller) which sends the START bit, followed by the slave address byte. The first byte transmitted is always the slave address byte, which contains the device code, the address bits, and the R/W bit. Typical I2C Interface Connections Host MCP4XXX Controller SCL SCL SDA SDA FIGURE 5-1: Typical I2C Interface. The I2C serial protocol only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. For details on the frame content (commands/data) refer to Section6.0. Refer to the NXP I2C document for more details on the I2C specifications. © 2011 Microchip Technology Inc. DS22272A-page 43

MCP4706/4716/4726 5.3 I2C Operation 5.3.1.3 Acknowledge (A) Bit The MCP47X6’s I2C module is compatible with the The A bit (see Figure5-4) is typically a response from NXP I2C specification. The following lists some of the the receiving device to the transmitting device. module’s features: Depending on the context of the transfer sequence, the A bit may indicate different things. Typically the Slave • 7-bit slave addressing device will supply an A response after the Start bit and • Supports three clock rate modes: 8 “data” bits have been received. An A bit has the SDA - Standard mode, clock rates up to 100kHz signal low. - Fast mode, clock rates up to 400kHz - High-speed mode (HS mode), clock rates up to 3.4MHz SDA D0 A • Support Multi-Master Applications • General call addressing (Reset and Wake-Up SCL 8 9 commands) The I2C 10-bit addressing mode is not supported. FIGURE 5-4: Acknowledge Waveform. The NXP I2C specification only defines the field types, field lengths, timings, etc. of a frame. The frame Not A (A) Response content defines the behavior of the device. The frame content for the MCP47X6 is defined in Section6.0. The A bit has the SDA signal high. Table5-1 shows some of the conditions where the Slave Device will 5.3.1 I2C BIT STATES AND SEQUENCE issue a Not A (A). Figure5-8 shows the I2C transfer sequence. The serial If an error condition occurs (such as an A instead of A), clock is generated by the master. The following then a START bit must be issued to reset the command definitions are used for the bit states: state machine. • Start bit (S) • Data bit TABLE 5-1: MCP47X6 A / A RESPONSES • Acknowledge (A) bit (driven low) / Acknowledge No Acknowledge (A) bit (not driven low) Event Bit Comment • Repeated Start bit (Sr) Response • Stop bit (P) General Call A 5.3.1.1 Start Bit Slave Address A The Start bit (see Figure5-2) indicates the beginning of valid a data transfer sequence. The Start bit is defined as the Slave Address A SDA signal falling when the SCL signal is “High”. not valid Communication A After device has during received address 1st Bit 2nd Bit SDA EEPROM write and command, cycle and valid SCL conditions for S EEPROM write FIGURE 5-2: Start Bit. Bus Collision N.A. I2C Module Resets, or a 5.3.1.2 Data Bit “Don’t Care” if The SDA signal may change state while the SCL signal the collision is Low. While the SCL signal is High, the SDA signal occurs on the MUST be stable (see Figure5-5). Master’s “Start bit” 1st Bit 2nd Bit SDA SCL Data Bit FIGURE 5-3: Data Bit. DS22272A-page 44 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 5.3.1.4 Repeated Start Bit 5.3.1.5 Stop Bit The Repeated Start bit (see Figure5-5) indicates the The Stop bit (see Figure5-6) Indicates the end of the current Master Device wishes to continue I2C Data Transfer Sequence. The Stop bit is defined as communicating with the current Slave Device without the SDA signal rising when the SCL signal is “High”. releasing the I2C bus. The Repeated Start condition is A Stop bit resets the I2C interface of all MCP47X6 the same as the Start condition, except that the devices. Repeated Start bit follows a Start bit (with the Data bits + A bit) and not a Stop bit. The Start bit is the beginning of a data transfer SDA A / A sequence and is defined as the SDA signal falling when the SCL signal is “High”. SCL Note1: A bus collision during the Repeated Start P condition occurs if: FIGURE 5-6: Stop Condition Receive or Transmit Mode. • SDA is sampled low when SCL goes from low to high. 5.3.2 CLOCK STRETCHING • SCL goes low before SDA is asserted “Clock Stretching” is something that the receiving low. This may indicate that another Device can do, to allow additional time to “respond” to master is attempting to transmit a the “data” that has been received. data"1". The MCP47X6 will not stretch the clock signal (SCL) since memory read access occurs fast enough. SDA 1st Bit 5.3.3 ABORTING A TRANSMISSION If any part of the I2C transmission does not meet the command format, it is aborted. This can be intentionally accomplished with a START or STOP condition. This is SCL done so that noisy transmissions (usually an extra START or STOP condition) are aborted before they Sr = Repeated Start corrupt the device. FIGURE 5-5: Repeat Start Condition Waveform. SDA SCL S 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A / A P FIGURE 5-7: Typical 8-Bit I2C Waveform Format. SDA SCL START Data allowed Data or STOP Condition to change A valid Condition FIGURE 5-8: I2C Data States and Bit Sequence. © 2011 Microchip Technology Inc. DS22272A-page 45

MCP4706/4716/4726 5.3.4 SLOPE CONTROL TABLE 5-2: I2C ADDRESS / ORDER CODE The MCP47X6 implements slope control on the SDA 7-bit I2C Device Order Code Comment output. Address As the device transitions from HS mode to FS mode, MCP47x6A0-E/xx the slope control parameter will change from the HS ‘1100000’ MCP47x6A0T-E/xx Tape and Reel specification to the FS specification. MCP47x6A1-E/xx For Fast (FS) and High-Speed (HS) modes, the device ‘1100001’ MCP47x6A1T-E/xx Tape and Reel has a spike suppression and a Schmidt trigger at SDA and SCL inputs. MCP47x6A2-E/xx ‘1100010’ MCP47x6A2T-E/xx Tape and Reel 5.3.5 DEVICE ADDRESSING MCP47x6A3-E/xx The address byte is the first byte received following the ‘1100011’ MCP47x6A3T-E/xx Tape and Reel START condition from the master device. The MCP47X6’s slave address consists of a 4-bit fixed code MCP47x6A4-E/xx ‘1100100’ (‘1100’) and a 3-bit code that is user specified when the MCP47x6A4T-E/xx Tape and Reel device is ordered. This allows up to eight MCP47X6 MCP47x6A5-E/xx devices on a single I2C bus. ‘1100101’ MCP47x6A5T-E/xx Tape and Reel Figure5-9 shows the I2C slave address byte format, MCP47x6A6-E/xx which contains the seven address bits and a read/write ‘1100110’ (R/W) bit. Table5-2 shows the eight I2C Slave address MCP47x6A6T-E/xx Tape and Reel options and their respective device order code. MCP47x6A7-E/xx ‘1100111’ MCP47x6A7T-E/xx Tape and Reel Acknowledge bit Note 1: The sample center will generally stock I2C Start bit Read/Write bit address ‘1100000’, other addresses may be available. Slave Address R/W ACK 2: ‘xx’ in the order code is the device package code (CH for SOT-23 and MA for Address Byte DFN) Slave Address (7-bits) Fixed User Specified 1 1 0 0 A2 A1 A0 Note:Address Bits (A2:A0) specified at time of device order, see Table5-2. FIGURE 5-9: Slave Address Bits in the I2C Control Byte. DS22272A-page 46 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 5.3.6 HS MODE After switching to the High-Speed mode, the next The I2C specification requires that a high-speed mode transferred byte is the I2C control byte, which specifies the device to communicate with, and any number of device must be ‘activated’ to operate in high-speed data bytes plus acknowledgements. The Master (3.4Mbit/s) mode. This is done by the Master sending Device can then either issue a Repeated Start bit to a special address byte following the START bit. This address a different device (at High-Speed) or a Stop bit byte is referred to as the high-speed Master Mode to return to Fast/Standard bus speed. After the Stop bit, Code (HSMMC). any other Master Device (in a Multi-Master system) can The MCP47X6 device does not acknowledge this byte. arbitrate for the I2C bus. However, upon receiving this command, the device See Figure5-10 for illustration of HS mode command switches to HS mode. The device can now sequence. communicate at up to 3.4Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the For more information on the HS mode, or other I2C next STOP condition. modes, please refer to the NXP I2C specification. The master code is sent as follows: 5.3.6.1 Slope Control 1. START condition (S) The slope control on the SDA output is different 2. High-Speed Master Mode Code (0000 1XXX), between the Fast/Standard Speed and the High-Speed The XXX bits are unique to the high-speed (HS) clock modes of the interface. mode Master. 3. No Acknowledge (A) 5.3.6.2 Pulse Gobbler The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes < 10ns during HS mode. F/S-mode HS-mode P F/S-mode S ‘0 0 0 0 1 X X X’b A Sr‘Slave Address’R/W A “Data” A/A HS-mode continues Sr‘Slave Address’R/W A HS Select Byte Control Byte Command/Data Byte(s) S = Start bit Control Byte Sr = Repeated Start bit A = Acknowledge bit A = Not Acknowledge bit R/W = Read/Write bit P = Stop bit (Stop condition terminates HS Mode) FIGURE 5-10: HS Mode Sequence. © 2011 Microchip Technology Inc. DS22272A-page 47

MCP4706/4716/4726 5.3.7 GENERAL CALL The MCP47X6 has two General Call Commands. The function of these commands are: The General Call is a method that the “Master” device can communicate with all other “Slave” devices. In a • Reset the device(s) (Software Reset) Multi-Master application, the other Master devices are • Wake-Up the device(s) operating in Slave mode. The General Call address For details on the operation of the MCP47X6’s General has two documented formats. These are shown in Call Commands, see Section6.6. Figure5-11. Note: Only one General Call command per issue of the General Call control byte. Any additional General Call commands are ignored and Not Acknowledged. Second Byte S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A P General Call Address “7-bit Command” Reserved 7-bit Commands (By I2C Specification - NXP specification # UM10204, Rev. 03 19 June 2007) ‘0000 011’b - Reset and write programmable part of slave address by hardware. ‘0000 010’b - Write programmable part of slave address by hardware. ‘0000 000’b - NOT Allowed The Following is a “Hardware General Call” Format Second Byte n occurrences of (Data + A) S 0 0 0 0 0 0 0 0 A X X X X X X X 1 A X X X X X X X X A P General Call Address “Master Address” This indicates a “Hardware General Call” FIGURE 5-11: General Call Formats. DS22272A-page 48 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 6.0 MCP47X6 I2C COMMANDS TABLE 6-1: I2C COMMANDS - NUMBER OF CLOCKS The I2C protocol does not specify how commands are formatted, so this section specifies the MCP47X6’s I2C Command # of Bit Clocks command formats and operation. Operation Mode (1) The commands can be grouped into the following Write Volatile DAC Register Single 29 categories: Command (2) Continuous 18n + 11 • Write memory Write Volatile Memory Single 38 • Read memory Command Continuous 27n + 11 • General Call commands Write All Memory Command Single 38 The supported commands are shown in Table6-2. Continuous 27n + 11 Many of these commands allow for continuous operation. This means that the I2C Master does not Write Volatile Configuration Single 20 generate a Stop bit but repeats the required data/ bits Command Continuous 9n + 11 clocks. This allows faster updates since the overhead Read Command (12 and 10-bit Single 65 of the I2C control byte is removed. Table6-1 shows the DAC register) (2) Continuous 54n + 11 supported commands and the required number of bit Read Command (8-bit DAC Single 47 clocks for both single and continuous commands. register) (2) Continuous 36n + 11 Write commands, determined by the R/W bit = ‘0’, use Note 1: “n” indicates the number of times the up to three command codes bits (C2:C0) to determine command operation is to be repeated. the write’s operation. 2: This command is useful to determine when The Read command is strictly determined by the R/W an EEPROM programming cycle has bit = ‘1’. There are two formats of the command. One completed (RDY/BSY status bit) for 12-bit and 10-bit devices and a second for 8-bit devices. 6.0.1 ABORTING A TRANSMISSION The General Call commands utilize the I2C A Restart or Stop condition in an expected data bit specification reserved General Call command address position will abort the current command sequence and and command codes. data will not be written to the MCP47X6. TABLE 6-2: MCP47X6 SUPPORTED COMMANDS Command Writes Volatile Writes Command Code EEPROM (Note1) Command Name Memory? Memory? during Comment EEPROM C2 C1 C0 Config. DAC Config. DAC Write Cycle? 0 0 X Write Volatile DAC Register PD1:PD Yes No No No Writes volatile Power Command (Note2) 0 only Down bits so can also be used to exit a power down state. 0 1 0 Write Volatile Memory Command Yes Yes No No No 0 1 1 Write All Memory Command Yes Yes Yes Yes No 1 0 0 Write Volatile Configuration bits Yes No No No No Command 1 0 1 N.A. N.A. N.A. N.A. Reserved (Note3) 1 1 0 Reserved N.A. 1 1 1 N.A. N.A. N.A. N.A. Reserved (Note3) Read Command N.A. N.A. N.A. N.A. Yes Determined by R/W bit in I2C Control byte General Call Reset N.A. N.A. N.A. N.A. No Determined by General N.A. General Call Wake-up N.A. N.A. N.A. N.A. No Call command byte after the I2C General Call address. Note 1: These bits are the MSb of the 2nd byte in the I2C write command. See Figure6-1 to Figure6-4. 2: X = Don’t Care bit. This command format does not use C0 bit. 3: Device operation is not specified. © 2011 Microchip Technology Inc. DS22272A-page 49

MCP4706/4716/4726 6.1 Write Volatile DAC Register After this ACK bit, the I2C Master should generate a (C2:C0 = ‘00x’) Stop bit or the I2C Master can repeat the 2nd (2 command bits + 2 power down bits + 4 data bits This command is used to update the volatile DAC (b11:b08)) and the 3rd byte (8 data bits (b07:b00)). Register value and the two Power-down configuration Repeating the 2nd and 3rd bytes allows a continuous bits (PD1:PD0). This command is typically used for a command where the volatile DAC register can be quick update of the analog output by modifying the updated without the communication overhead of the minimum parameters. The EEPROM values are not device addressing byte (1st byte). affected by this command. The device updates the V at the falling edge of the OUT Figure6-1 shows an example of the command format, Acknowledge pulse of the 3rd byte. where a stop bit completes the command. The volatile DAC register and Power-down configuration bits are updated with the written date at the completion of the ACK bit (falling edge of SCL). Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) ACK bit (3) Stop bit S R/W A A A P SDA 1 1 0 0 A2 A1 A0 0 0 0 0 PD1PD0 b11 b10 b09 b08 0 b07 b06 b05 b04 b03 b02 b01 b00 0 SCL Device Addressing Command Power Data bits (4 bits) Data bits (8 bits) bits Down bits Data bits (12 bits) Note 1 Note 2 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X MCP4706 X X X X D07 D06 D05 D04 D03 D02 D01 D00 Note 1: The device updates V at the falling edge of the SCL at the end of this ACK pulse. OUT 2: The 2nd - 3rd bytes can be repeated after the 3rd byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: X = don’t care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device FIGURE 6-1: Write Volatile DAC Register Command. DS22272A-page 50 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 6.2 Write Volatile Memory After this ACK bit, the I2C Master should generate a (C2:C0 = ‘010’) Stop bit or the I2C Master can repeat the 2nd (3 command bits + 5 configuration bits), and the 3rd byte This write command is used to update the volatile DAC (8 data bits (b15:b08)), and the 4th byte (8 data bits Register value and configuration bits. The EEPROM is (b07:b00)). Repeating the 2nd through 4th bytes allows not affected by this command. Figure6-2 shows an a continuous command where the volatile DAC register example of this write command. and configuration bits can be updated without the The volatile DAC register and configuration bits are communication overhead of the device addressing updated with the written date at the completion of the byte (1st byte). ACK bit (falling edge of SCL). Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) ACK bit (3) S R/W A VREF1 VREF0 A A SDA 1 1 0 0 A2 A1 A0 0 0 0 1 0 PD1PD0 G 0 b15 b14 b13 b12 b11 b10 b09 b08 0 SCL Device Addressing Command Ref. Power Gain Data bits (8 bits) (3rd byte) bits Voltage Down bit Select bits bits ACK bit (3) Stop bit A P b07 b06 b05 b04 b03 b02 b01 b00 0 Data bits (8 bits) (4th byte) Data bits (16 bits) (3rd + 4th bytes) Note 1 b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 Note 2 MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X MCP4706 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X Note 1: The device updates V at the falling edge of the SCL at the end of this ACK pulse. OUT 2: The 2nd - 4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: X = don’t care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device FIGURE 6-2: Write Volatile Memory Command. © 2011 Microchip Technology Inc. DS22272A-page 51

MCP4706/4716/4726 6.3 Write All Memory Note: RDY/BSY bit toggles to “low” and back to (C2:C0 = ‘011’) “high” after the EEPROM write is This write command is used to update the volatile and completed. The state of the RDY/BSY bit nonvolatile (EEPROM) DAC Register value and can be monitored by a read command. configuration bits. Figure6-3 shows an example of this Write commands which only update volatile memory write command. (C2:C0 = ‘00x’ or ‘010’) can be issued. Read • V update: At the falling edge of the commands and the General Call commands may not OUT Acknowledge pulse of the 4th byte. be issued. • EEPROM update: At the falling edge of the Acknowledge pulse of the 4th byte. The DAC register and Power-down configuration bits (volatile and EEPROM) are updated with the written date at the completion of the ACK bit (falling edge of SCL). The EEPROM memory requires time (T ) for WC the values to be written. Another Write All memory command should not be issued until the EEPROM write is complete. Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) ACK bit (3) S R/W A VREF1 VREF0 A A SDA 1 1 0 0 A2 A1 A0 0 0 0 1 1 PD1PD0 G 0 b15 b14 b13 b12 b11 b10 b09 b08 0 SCL Device Addressing Command Ref. Power Gain Data bits (8 bits) (3rd byte) bits Voltage Down bit Select bits bits ACK bit (3) Stop bit A P b07 b06 b05 b04 b03 b02 b01 b00 0 Data bits (8 bits) (4th byte) Data bits (16 bits) (3rd + 4th bytes) Note 1 b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 Note 2 MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X MCP4706 D07 D06 D05 D04 D03 D02 D01 D00 X X X X X X X X Note 1: The device updates V at the falling edge of the SCL at the end of this ACK pulse. OUT 2: The 2nd - 4th bytes can be repeated after the 4th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: X = don’t care D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device D07:D00 = 8-bit data for MCP4706 device FIGURE 6-3: Write All Memory Command. DS22272A-page 52 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 6.4 Write Volatile Configuration bits (C2:C0 = ‘100’) This write command is used to update the volatile configuration register bits only. This command is a quick method to modify the configuration of the DAC, such as the selection of the resistor ladder reference voltage, the op amp gain, and the Power Down state. Figure6-4 shows an example of this write command. Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) Stop bit S R/W A VREF1 VREF0 A P SDA 1 1 0 0 A2 A1 A0 0 0 1 0 0 PD1PD0 G 0 SCL Device Addressing Command Configuration bits bits Note 1 Note 2 Note 1: The device updates V at the falling edge of the SCL at the end of this ACK pulse. OUT 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. FIGURE 6-4: Write Volatile Configuration Bits Command. © 2011 Microchip Technology Inc. DS22272A-page 53

MCP4706/4716/4726 6.5 READ COMMAND This command has two different formats based on the resolution of the device. The 12-bit and 10-bit devices This command reads all the device memory. This use the format in Figure6-5, while the 8-bit device uses includes the volatile and nonvolatile (EEPROM) DAC the format in Figure6-6. Register values and configuration bits, and the volatile The 2nd byte (configuration bits) indicates the current status bits. condition of the device operation. The RDY/BSY bit This command is executed when the I2C control byte’s indicates EEPROM writing status. Read/Write bit is a ‘1’ (read). Read/Write bit (Read) Start bit ACK bit (3) S R/W A SDA 1 1 0 0 A2 A1 A0 1 0 SCL Device Addressing ACK bit (4) ACK bit (4) ACK bit (4) VREF1 VREF0 A A A RDYPOR 0 PD1 PD0 G 0 b15 b14 b13 b12 b11 b10 b09 b08 0 b07 b06 b05 b04 b03 b02 b01 b00 0 Vol. Vol. Configuration Vol. Data bits (8 bits) (3rd byte) Vol. Data bits (8 bits) (4th byte) Status bits bits ACK bit (4) ACK bit (4) ACK/NACK bit (5) Stop bit VREF1 VREF0 A A A/N P RDYPOR 1 PD1 PD0 G 0 b15 b14 b13 b12 b11 b10 b09 b08 0 b07 b06 b05 b04 b03 b02 b01 b00 0/1 Vol. NV Configuration NV Data bits (8 bits) (6th byte) NV Data bits (8 bits) (7th byte) Status bits bits Data bits (16 bits) (3rd + 4th bytes, and 6th + 7th bytes) b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 Note 1 MCP4726 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 0 0 MCP4716 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 0 0 0 0 0 0 Note 1: The 2nd - 7th bytes can be repeated after the 7th byte by continued clocking before issuing Stop bit. 2: ACK bit generated by MCP47X6. 3: ACK bit generated by I2C Master. 4: ACK/NACK bit generated by I2C Master. Legend: D11:D00 = 12-bit data for MCP4726 device D09:D00 = 10-bit data for MCP4716 device FIGURE 6-5: Read Command Format for 12-bit DAC (MCP4726) and 10-bit DAC (MCP4716). DS22272A-page 54 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Read/Write bit (Read) Start bit ACK bit (3) ACK bit (4) ACK bit (4) S R/W A VREF1 VREF0 A A SDA 1 1 0 0 A2 A1 A0 1 0 RDYPOR 0 PD1PD0 G 0 b07 b06 b05 b04 b03 b02 b01 b00 0 SCL Device Addressing Vol. Vol. Configuration Vol. Data bits (8 bits) (3rd byte) Status bits bits ACK bit (4) ACK/NACK bit (5) Stop bit VREF1 VREF0 A A/N P RDYPOR 1 PD1PD0 G 0 b07 b06 b05 b04 b03 b02 b01 b00 0/1 Vol. NV Configuration NV Data bits (8 bits) (5th byte) Status bits bits Data bits (8 bits) (3rd and 5th bytes) Note 1 b07 b06 b05 b04 b03 b02 b01 b00 Note 2 MCP4706 D07 D06 D05 D04 D03 D02 D01 D00 Note 1: a 2: The 2nd - 5th bytes can be repeated after the 5th byte by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. Legend: D07:D00 = 8-bit data for MCP4706 device FIGURE 6-6: Read Command Format for 8-bit DAC (MCP4706). © 2011 Microchip Technology Inc. DS22272A-page 55

MCP4706/4716/4726 6.6 I2C General Call Commands 6.6.1 GENERAL CALL RESET The device acknowledges the general call address The device performs General Call Reset if the second command (0x00 in the first byte). The meaning of the byte is “00000110” (06h). At the acknowledgement of general call address is always specified in the second this byte, the device will abort the current conversion byte. The I2C specification does not allow “00000000” and perform the following tasks: (00h) in the second byte. Please refer to the Phillips I2C • Internal reset similar to a Power-On-Reset (POR). document for more details on the General Call The contents of the EEPROM are loaded into the specifications. DAC registers and analog output is available The MCP47X6 devices support the following I2C immediately. general calls: • This is a similar event to the POR. The VOUT will be available immediately, but after a short time • General Call Reset delay following the Acknowledgement pulse. The • General Call Wake-Up V value is determined by the EEPROM OUT contents. This command allows multiple MCP47X6 devices to be reset synchronously. Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) Stop bit S R/W A A P SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 SCL General Call Address General Call Reset Command Note 1 Note 2 Note 1: At the falling edge of the SCL at the end of this ACK pulse a reset occurs (startup timer starts and DAC register latched). 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. FIGURE 6-7: General Call Reset Command. DS22272A-page 56 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 6.6.2 GENERAL CALL WAKE-UP Note: This command does not adhere to the I2C If the second byte is “00001001” (09h), the device specification where if the LSb of the 2nd forces the volatile power-down bits to ‘00’. The byte is a ‘1’, it is a ‘Hardware General Call’ nonvolatile (EEPROM) power-down bit values are not (see the NXP I2C Specification). affected by this command. This command allows multiple MCP47X6 devices to wake-up synchronously. Read/Write bit (Write) Start bit ACK bit (3) ACK bit (3) Stop bit S R/W A A P SDA 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 SCL General Call Address General Call Wake-Up Command Note 1 Note 2 Note 1: At the falling edge of the SCL, at the end of this ACK pulse, the volatile PD1:PD0 bits are forced to ‘00’. 2: The 2nd byte can be repeated after the 2nd by continued clocking before issuing Stop bit. 3: ACK bit generated by MCP47X6. FIGURE 6-8: General Call Wake-Up Command. © 2011 Microchip Technology Inc. DS22272A-page 57

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MCP4706/4716/4726 7.0 TERMINOLOGY 7.5 Zero-Scale Error (ZSE) The Zero-Scale Error (see Figure7-4) is the difference 7.1 Resolution between the ideal and measured V voltage with the OUT volatile DAC Register equal to 000h. The Zero-Scale The resolution is the number of DAC output states that Error is the same as the Offset Error for this case divide the full-scale range. For the 12-bit DAC, the resolution is 212, meaning the DAC code ranges from 0 (volatile DAC Register = 000h). to 4095. EQUATION 7-3: ZERO SCALE ERROR 7.2 Least Significant bit (LSb) V OUT(@ZS) ZSE = Normally this is thought of as the ideal voltage VLSb difference between two successive codes. This bit has Where: the smallest value or weight of all bits in the register. FSE is expressed in LSb V is the V voltage when the DAC For a given output voltage range, which is typically the OUT(@ZS) OUT register code is at Zero-scale. voltage between the Full-Scale voltage and the Zero- V is the delta voltage of one DAC register code Scale voltage (V - V ), it is divided by the LSb OUT(FS) OUT(ZS) step (such as code 000h to code 001h). resolution of the device (Equation7-1). EQUATION 7-1: LSb VOLTAGE 7.6 Offset Error CALCULATION The Offset error (see Figure7-1) is the deviation from V - V zero voltage output when the volatile DAC Register VLSb = OUT(F2SN) - 1O UT(ZS) value = 000h (zero scale voltage). This error affects all codes by the same amount. The offset error can be 2N = 4096 (MCP4726) calibrated by software in application circuits. 1024 (MCP4716) 256 (MCP4706) Actual Transfer Function 7.3 Monotonicity Analog Normally this is thought of as the V voltage never Output OUT decreasing, as the DAC Register code is continuously incremented by 1 code step (LSb). 7.4 Full-Scale Error (FSE) Offset Ideal Transfer Function Error The Full-scale error (see Figure7-4) is the sum of (ZSE) offset error plus gain error. It is the difference between 0 DAC Input Code the ideal and measured DAC output voltage with all bits FIGURE 7-1: Offset Error Example. set to one (DAC input code = FFFh for 12-bit DAC). EQUATION 7-2: FULL SCALE ERROR V - V OUT(@FS) IDEAL(@FS) FSE = V LSb Where: FSE is expressed in LSb V is the V voltage when the DAC OUT(@FS) OUT register code is at Full-scale. V is the ideal output voltage when the IDEAL(@FS) DAC register code is at Full-scale. V is the delta voltage of one DAC register code LSb step (such as code 000h to code 001h). © 2011 Microchip Technology Inc. DS22272A-page 59

MCP4706/4716/4726 7.7 Integral Nonlinearity (INL) 7.8 Differential Nonlinearity (DNL) The Integral nonlinearity (INL) error is the maximum The Differential nonlinearity (DNL) error (see Figure7- deviation of an actual transfer function from an ideal 3) is the measure of step size between codes in actual transfer function (straight line). transfer function. The ideal step size between codes is 1LSb. A DNL error of zero would imply that every code In the MCP47X6, INL is calculated using two end points is exactly 1LSb wide. If the DNL error is less than (zero and full scale). INL can be expressed as a per- 1LSb, the DAC guarantees monotonic output and no centage of full scale range (FSR) or in a fraction of an missing codes. The DNL error between any two LSb. INL is also called relative accuracy. Equation7-4 adjacent codes is calculated as follows: shows how to calculate the INL error in LSb and Figure7-2 shows an example of INL accuracy. EQUATION 7-5: DNL ERROR EQUATION 7-4: INL ERROR ΔV –LSb DNL = ---------O---U----T------------------ (V –V ) LSb OUT Ideal INL = --------------------------------------- LSb Where: Where: DNL is expressed in LSb. ΔV = The measured DAC output INL is expressed in LSb. OUT voltage difference between two V = Code*LSb Ideal adjacent input codes. V = The output voltage measured with OUT a given DAC input code 7 DNL = 0.5 LSb 7 6 INL = < -1 LSb 6 5 INL = - 1 LSb DNL = 2 LSb 5 Analog 4 Output Analog 4 (LSb) 3 Output (LSb) 3 INL = 0.5 LSb 2 2 1 1 0 0 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 DAC Input Code DAC Input Code Ideal Transfer Function Ideal Transfer Function Actual Transfer Function Actual Transfer Function FIGURE 7-3: DNL Accuracy Example. FIGURE 7-2: INL Accuracy Example. DS22272A-page 60 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 7.9 Gain Error 7.10 Gain Error Drift The Gain error (see Figure7-4) is the difference The Gain error drift is the variation in gain error due to between the actual full-scale output voltage from the a change in ambient temperature. The gain error drift is ideal output voltage of the DAC transfer curve. The typically expressed in ppm/oC. gain error is calculated after nullifying the offset error, or full scale error minus the offset error. 7.11 Offset Error Drift The gain error indicates how well the slope of the actual The Offset error drift is the variation in offset error due transfer function matches the slope of the ideal transfer to a change in ambient temperature. The offset error function. The gain error is usually expressed as percent drift is typically expressed in ppm/oC. of full-scale range (% of FSR) or in LSb. In the MCP4706/4716/4726, the gain error is not 7.12 Settling Time calibrated at the factory and most of the gain error is contributed by the output buffer (op amp) saturation The Settling time is the time delay required for the VOUT near the code range beyond 4000d. For the voltage to settle into its new output value. This time is applications that need the gain error specification less measured from the start of code transition, to when the than 1% maximum, the user may consider using the VOUT voltage is within the specified accuracy. DAC code range between 100d and 4000d instead of In the MCP47X6, the settling time is a measure of the using full code range (code 0 to 4095d). The DAC time delay until the V voltage reaches within 0.5 OUT output of the code range between 100d and 4000d is LSb of its final value, when the volatile DAC Register much more linear than full-scale range (0 to 4095d). changes from 400h to C00h. The gain error can be calibrated out by software in the application. 7.13 Major-Code Transition Glitch Major-code transition glitch is the impulse energy Actual Transfer Function injected into the DAC analog output when the code in the DAC register changes state. It is normally specified Full-Scale as the area of the glitch in nV-Sec, and is measured Error when the digital code is changed by 1 LSb at the major carry transition (Example: 011...111 to 100... 000, or 100... 000 to 011 ... 111). Gain Error Analog 7.14 Digital Feedthrough Output The Digital feedthrough is the glitch that appears at the Actual Transfer Function analog output caused by coupling from the digital input after Offset Error is removed pins of the device. The area of the glitch is expressed Ideal Transfer Function in nV-Sec, and is measured with a full scale change Zero-Scale Error (Example: all 0s to all 1s and vice versa) on the digital input pins. The digital feedthrough is measured when 0 DAC Input Code the DAC is not being written to the output register. FIGURE 7-4: Gain Error and Full-Scale Error Example. 7.15 Power-Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V to a change in V for full-scale OUT DD output of the DAC. The V is measured while the OUT V is varied +/- 10%, and expressed in dB or µV/V. DD © 2011 Microchip Technology Inc. DS22272A-page 61

MCP4706/4716/4726 NOTES: DS22272A-page 62 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 8.0 TYPICAL APPLICATIONS 8.1.1 DEVICE CONNECTION TEST The user can test the presence of the device on the I2C The MCP47X6 family of devices are general purpose, bus line using a simple I2C command. This test can be single channel voltage output DACs for various achieved by checking an acknowledge response from applications where a precision operation with the device after sending a read or write command. low-power and nonvolatile EEPROM memory is Figure8-1 shows an example with a read command. needed. The steps are: Since the devices include a nonvolatile EEPROM a) Set the R/W bit “High” in the device’s address memory, the user can utilize these devices for byte. applications that require the output to return to the previous set-up value on subsequent power-ups. b) Check the ACK bit of the address byte. If the device acknowledges (ACK = 0) the Applications generally suited for the devices are: command, then the device is connected, • Set Point or Offset Trimming otherwise it is not connected. • Sensor Calibration c) Send Stop bit. • Portable Instrumentation (Battery Powered) • Motor Control Address Byte 8.1 Connecting to I2C BUS using SCL 1 2 3 4 5 6 7 8 9 Pull-Up Resistors The SCL and SDA pins of the MCP47X6 devices are K open-drain configurations. These pins require a pull-up 1 1 0 1 A2 A1 A0 1 C SDA A resistor as shown in Figure8-2. Start Stop The pull-up resistor values (R1 and R2) for SCL and Bit Device Code Address bits Bit SDA pins depend on the operating speed (standard, R/W fast, and high speed) and loading capacitance of the I2C bus line. A higher value of the pull-up resistor Device Response consumes less power, but increases the signal transition time (higher RC time constant) on the bus FIGURE 8-1: I2C Bus Connection Test. line. Therefore, it can limit the bus operating speed. The lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1kΩ and 10kΩ ranges for standard and fast modes, and less than 1kΩ for high speed mode. © 2011 Microchip Technology Inc. DS22272A-page 63

MCP4706/4716/4726 8.2 Power Supply Considerations VDD The power source should be as clean as possible. The power supply to the device is also used for the DAC Optional voltage reference internally if the internal V is DD selected as the resistor ladders reference voltage Analog C3 Output (VREF1:VREF0 = 00 or 01). Any noise induced on the V line can affect the DAC DD performance. Typical applications will require a bypass VOUT 1 6 6 VREF R1R2 X cthaep aVcDitDo rli nine .o Trdheer n tooi sfielt ecra no ubte h iingdhu fcreedq uoenntocy t hneo pisoew oenr VSS 23 MCP47 45 SDA To MCU supply’s traces or as a result of changes on the DAC V SCL DD output. The bypass capacitor helps to minimize the C1 C2 effect of these noise sources on signal integrity. Figure8-2 shows an example of using two bypass (a) Circuit when V is selected as reference DD capacitors (a 10µF tantalum capacitor and a 0.1µF (Note: VDD is connected to the reference circuit internally.) ceramic capacitor) in parallel on the V line. These capacitors should be placed as close to DthDe V pin as VDD DD possible (within 4mm). If the application circuit has Optional Optional V separate digital and analog power supplies, the V REF DD and V pins of the device should reside on the analog Analog SS C3 Output C4 C5 plane. VOUT 1 6 6 VREF R1R2 X VSS 2 P47 5 SDA To MCU C 3 M 4 V SCL DD C1 C2 (b) Circuit when external reference is used. R1 and R2 are I2C pull-up resistors: R1 and R2: 5kΩ - 10kΩ for f = 100kHz to 400kHz SCL ~700Ω for f = 3.4MHz SCL C1: 0.1µF capacitor Ceramic C2: 10µF capacitor Tantalum C3: ~ 0.1µF Optional to reduce noise in VOUT pin. C4: 0.1µF capacitor Ceramic C5: 10µF capacitor Tantalum Note: Pin assignment is opposite in DFN-6 package. FIGURE 8-2: Example MCP47X6 Circuit with SOT-23 package. DS22272A-page 64 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 8.3 Application Examples 8.3.1 DC SET POINT OR CALIBRATION The MCP47X6 devices are rail-to-rail output DACs A common application for the devices is a designed to operate with a V range of 2.7V to 5.5V. digitally-controlled set point and/or calibration of DD The internal output op amplifier is robust enough to variable parameters, such as sensor offset or slope. drive common, small-signal loads directly, thus For example, the MCP4726 provides 4096 output eliminating the cost and size of external buffers for steps. If voltage reference is 4.096V, the LSb size is most applications. The user can use gain of 1 or 2 of 1mV. If a smaller output step size is desired, a lower the output op amplifier by setting the configuration external voltage reference is needed. register bits. Also, the user can use internal V as the DD 8.3.1.1 Decreasing Output Step Size reference or use external reference. Various user options and easy-to-use features make the devices If the application is calibrating the bias voltage of a suitable for various modern DAC applications. diode or transistor, a bias voltage range of 0.8V may be desired with about 200µV resolution per step. Two Application examples include: common methods to achieve small step size are using • Decreasing Output Step Size lower V pin voltage or using a voltage divider on the REF • Building a “Window” DAC DAC’s output. • Bipolar Operation Using an external voltage reference (V ) is an REF • Selectable Gain and Offset Bipolar Voltage Output option, if the external reference is available with the • Designing a Double-Precision DAC desired output voltage range. However, occasionally, • Building Programmable Current Source when using a low-voltage reference voltage, the noise floor causes a SNR error that is intolerable. Using a • Serial Interface Communication Times voltage divider method is another option, and provides • Software I2C Interface Reset Sequence some advantages when external voltage reference • Power Supply Considerations needs to be very low, or when the desired output • Layout Considerations voltage is not available. In this case, a larger value reference voltage is used, while two resistors scale the output range down to the precise desired level. Figure8-3 illustrates this concept. A bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. V DD Optional R SENSE VREF VDD VCC+ V R1 VTRIPComp. OUT MCP47X6 V O C V – R 1 CC 2 I2C™ 2-wire FIGURE 8-3: Example Circuit Of Set Point or Threshold Calibration. EQUATION 8-1: V AND V OUT TRIP CALCULATIONS DAC Register Value V = V • G • OUT REF 2N ⎛ R2 ⎞ V = V ⎜--------------------⎟ trip OUT⎝R1+R2⎠ © 2011 Microchip Technology Inc. DS22272A-page 65

MCP4706/4716/4726 8.3.1.2 Building a “Window” DAC 8.4 Bipolar Operation When calibrating a set point or threshold of a sensor, Bipolar operation is achievable by utilizing an external typically only a small portion of the DAC output range is operational amplifier. This configuration is desirable utilized. If the LSb size is adequate enough to meet the due to the wide variety and availability of op amps. This application’s accuracy needs, the unused range is allows a general purpose DAC, with its cost and sacrificed without consequences. If greater accuracy is availability advantages, to meet almost any desired needed, then the output range will need to be reduced output voltage range, power and noise performance. to increase the resolution around the desired threshold. Figure8-5 illustrates a simple bipolar voltage source If the threshold is not near VREF, 2 • VREF, or VSS then configuration. R1 and R2 allow the gain to be selected, creating a “window” around the threshold has several while R and R shift the DAC's output to a selected 3 4 advantages. One simple method to create this offset. Note that R4 can be tied to V , instead of V , DD SS “window” is to use a voltage divider network with a if a higher offset is desired. pull-up and pull-down resistor. Figure8-4 and Figure8- 6 illustrate this concept. Optional V V REF DD V + CC Optional RSENSE VCC+ MCP47X6 R3 VOA+ VO VREF VDD VCC+ VOUTR4 C1 R1 R3 VTRIPComp. VO I2C™ VCC– MCP47X6 2-wire V OUT R C1 VCC– R2 2 V I2C™ IN 2-wire VCC– R1 FIGURE 8-5: Digitally-Controlled Bipolar FIGURE 8-4: Single-Supply “Window” Voltage Source Example Circuit. DAC. EQUATION 8-3: V , V , AND V OUT OA+ O EQUATION 8-2: V AND V OUT TRIP CALCULATIONS CALCULATIONS DAC Register Value DAC Register Value V = V • G • VOUT = VREF • G • 2N OUT REF 2N V • R V R +V R OUT 4 OUT 23 23 1 V = VTRIP = ------------R--------+-----R-------------------- OA+ R3 + R4 1 23 R R R2 R2 R23 = R--------2+------R3----- VO = VOA+ • ( 1 + R ) - VDD • ( R ) Thevenin 2 3 1 1 Equivalent (V R )+(V R ) V = -------C---C---+-------2-------------------C---C----------3--- 23 R +R 2 3 R 1 VOUT VTRIP R 23 V 23 DS22272A-page 66 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 8.5 Selectable Gain and Offset Bipolar Voltage Output Optional V + CC In some applications, precision digital control of the Optional output range is desirable. Example8-6 illustrates how V V R to use the DAC devices to achieve this in a bipolar or REF DD 5 single-supply application. VCC+ This circuit is typically used for linearizing a sensor MCP4726 R3 VOA+ VOUT whose slope and offset varies. V O The equation to design a bipolar “window” DAC would R4 C1 be utilized if R , R and R are populated. I2C™ V – 3 4 5 CC 2-wire VCC– 8.5.1 BIPOLAR DAC EXAMPLE USING R MCP4726 2 V IN An output step size of 1mV, with an output range of R 1 ±2.05V, is desired for a particular application. FIGURE 8-6: Bipolar Voltage Source with Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V. Selectable Gain and Offset. Step 2: Calculate the resolution needed: EQUATION 8-4: V , V , AND V 4.1V/1mV = 4100 OUT OA+ O CALCULATIONS Since 212 = 4096, 12-bit resolution is desired. DAC Register Value Stepf u3ll-:s cTahlee Vampl if(i4e.r0 9g6aVin) , (mRu2/sRt 1b),e mequultiapll ietod thbey VOUT = VREF • G • 2N OUT desired minimum output to achieve bipolar V • R + V • R OUT 4 CC- 5 operation. Since any gain can be realized by V = OA+ R + R choosing resistor values (R +R ), the V value 3 4 1 2 REF must be selected first. If a VREF of 4.096V is used, R2 R2 solve for the amplifier’s gain by setting the DAC to VO = VOA+ • ( 1 + R ) - VIN • ( R ) 0, knowing that the output needs to be -2.05V. 1 1 The equation can be simplified to: Offset Adjust Gain Adjust –----R----2- = --–----2---.-0---5---- R----2-- = 1--- EQUATION 8-5: BIPOLAR “WINDOW” DAC R 4.096V R 2 1 1 USING R AND R 4 5 If R = 20kΩ and R = 10kΩ, the gain will be 0.5. 1 2 Thevenin V R +V R CC+ 4 CC- 5 V = --------------------------------------------- Step 4: Next, solve for R and R by setting the DAC to Equivalent 45 R +R 3 4 4 5 4096, knowing that the output needs to be +2.05V. V R +V R OUT 45 45 3 V = --------------------------------------------- ----------R----4---------- = 2---.--0---5---V------+-----(--0----.-5----⋅----4---.-0---9---6---V-----) = 2--- IN+ R3+R45 (R3+R4) 1.5⋅4.096V 3 R = ----R----4--R----5----- 45 R +R If R = 20kΩ, then R = 10kΩ 4 5 4 3 Figure8-6 (C1 = 0.1uF) V = V ⎛1+R----2--⎞ –V ⎛R----2--⎞ O IN+⎝ R ⎠ A⎝R ⎠ 1 1 Offset Adjust Gain Adjust © 2011 Microchip Technology Inc. DS22272A-page 67

MCP4706/4716/4726 8.6 Designing a Double-Precision 8.7 Building Programmable Current DAC Source Figure8-7 shows an example design of a single-supply Example8-8 shows an example of building voltage output capable of up to 24-bit resolution. This programmable current source using a voltage follower. requires two 12-bit DACs. This design is simply a The current sensor resistor is used to convert the DAC voltage divider with a buffered output. voltage output into a digitally-selectable current source. As an example, if a similar application to the one The smaller R is, the less power dissipated SENSE developed in Section8.5.1 “Bipolar DAC Example across it. However, this also reduces the resolution that Using MCP4726” required a resolution of 1µV instead the current can be controlled. of 1mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. V DD Step 1: Calculate the resolution needed: Optional (or VREF) 4.1V/1µV=4.1x106. Since 222=4.2x106, VREF VDD 22-bit resolution is desired. Since V + Load CC DNL=±0.75LSb, this design can be attempted V OUT I with the 12-bit DAC. MCP47X6 L Step 2: Since DAC ‘s V has a resolution of 1mV, B OUTB I b its output only needs to be “pulled” 1/1000 to meet the 1µV target. Dividing V by 1000 would I2C™ VCC– OUTA allow the application to compensate for DAC ‘s 2-wire B DNL error. I Step 3: If R2 is 100Ω, then R1 needs to be 100kΩ. Ib = -β--L- RSENSE Step 4: The resulting transfer function is shown in the VOUT β I = ---------------×------------- equation of Example8-6. L R β+1 sense where β = Common-Emitter Current Gain. Optional V V REF DD FIGURE 8-8: Digitally-Controlled Current Source. V OA MCP4726 (A) R I2C™ 1 V + CC 2-wire V Optional OUT VREF VDD 0.1µF R V – 2 CC MCP4726 (B) V OB I2C™ 2-wire FIGURE 8-7: Simple Double Precision DAC using MCP4726. EQUATION 8-6: V CALCULATION OUT V * R + V * R OA 2 OB 1 V = OUT R + R 1 2 Where: V = (V * G * DAC A Register Value)/4096 OA REF V = (V * G * DAC B Register Value)/4096 OB REF G = Selected Op Amp Gain DS22272A-page 68 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 8.8 Serial Interface Communication Times Table8-1 shows time/frequency of the supported operations of the I2C serial interface for the different serial interface operational frequencies. This, along with the V output performance (such as slew rate), OUT would be used to determine your applications volatile DAC register update rate. TABLE 8-1: SERIAL INTERFACE TIMES / FREQUENCIES Command Writes Volatile Writes EEPROM # of Command Frequency Code Memory? Memory? Serial Command Time (uS) (kHz) Interface C2 C1 C0 Function Config. DAC Config. DAC bits (2) 100kHz400kHz3.4MHz100kHz400kHz3.4MHz 0 0 X Write Volatile Yes(1) Yes No No 29 290 72.5 8.5 3.4 13.8 117.2 DAC 0 1 0 Write Volatile Yes Yes No No 38 380 95 11.2 2.6 10.5 89.5 Memory 0 1 1 Write All Yes Yes Yes Yes 38 380 95 11.2 2.6 10.5 89.5 Memory 1 0 0 Write NV Yes No No No 20 200 50 5.9 5.0 20.0 170.0 Configuration Bits N.A. Read N.A. N.A. N.A. N.A. 77 750 187.5 22.1 1.3 5.3 45.3 Note 1: Only the volatile PD1:PD0 bits of the Configuration bits are written. 2: Includes the Start or Stop bits. © 2011 Microchip Technology Inc. DS22272A-page 69

MCP4706/4716/4726 8.9 Software I2C Interface Reset The nine bits of ‘1’ are used to force a Reset of those Sequence devices that could not be reset by the previous Start bit. This occurs only if the MCP47X6 is driving an A bit on the I2C bus, or is in output mode (from a Read Note: This technique is documented in AN1028. command) and is driving a data bit of ‘0’ onto the I2C At times, it may become necessary to perform a bus. In both of these cases, the previous Start bit could Software Reset Sequence to ensure the MCP47X6 not be generated due to the MCP47X6 holding the bus device is in a correct and known I2C Interface state. low. By sending out nine ‘1’ bits, it is ensured that the This technique only resets the I2C state machine. device will see an A bit (the Master Device does not This is useful if the MCP47X6 device powers up in an drive the I2C bus low to acknowledge the data sent by incorrect state (due to excessive bus noise, etc), or if the MCP47X6), which also forces the MCP47X6 to the Master Device is reset during communication. reset. Figure8-9 shows the communication sequence to The 2nd Start bit is sent to address the rare possibility software reset the device. of an erroneous write. This could occur if the Master Device was reset while sending a Write command to the MCP47X6, AND then as the Master Device returns S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P to normal operation and issues a Start condition, while Nine bits of ‘1’ the MCP47X6 is issuing an Acknowledge. In this case, Start bit if the 2nd Start bit is not sent (and the Stop bit was sent) Start Stop bit the MCP47X6 could initiate a write cycle. bit Note: The potential for this erroneous write FIGURE 8-9: Software Reset Sequence ONLY occurs if the Master Device is reset Format. while sending a Write command to the The 1st Start bit will cause the device to reset from a MCP47X6. state in which it is expecting to receive data from the The Stop bit terminates the current I2C bus activity. The Master Device. In this mode, the device is monitoring MCP47X6 waits to detect the next Start condition. the data bus in Receive mode and can detect if the This sequence does not effect any other I2C devices Start bit forces an internal Reset. which may be on the bus, as they should disregard this as an invalid command. DS22272A-page 70 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 8.10 Design Considerations 8.10.2 LAYOUT CONSIDERATIONS In the design of a system with the MCP4706/4716/4726 Several layout considerations may be applicable to devices, the following considerations should be taken your application. These may include: into account: • Noise • Power Supply Considerations • PCB Area Requirements • Layout Considerations 8.10.2.1 Noise 8.10.1 POWER SUPPLY Inductively-coupled AC transients and digital switching CONSIDERATIONS noise can degrade the input and output signal integrity, potentially masking the MCP47X6’s performance. The typical application will require a bypass capacitor Careful board layout minimizes these effects and in order to filter high-frequency noise, which can be increases the Signal-to-Noise Ratio (SNR). Multi-layer induced onto the power supply's traces. The bypass boards utilizing a low-inductance ground plane, capacitor helps to minimize the effect of these noise isolated inputs, isolated outputs and proper decoupling sources on signal integrity. Figure8-10 illustrates an are critical to achieving the performance that the silicon appropriate bypass strategy. is capable of providing. Particularly harsh In this example, the recommended bypass capacitor environments may require shielding of critical signals. value is 0.1µF. This capacitor should be placed as Separate digital and analog ground planes are close (within 4mm) to the device power pin (V ) as DD recommended. In this case, the V pin and the ground possible. SS pins of the V capacitors should be terminated to the DD The power source supplying these devices should be analog ground plane. as clean as possible. If the application circuit has separate digital and analog power supplies, V and DD Note: Breadboards and wire-wrapped boards V should reside on the analog plane. SS are not recommended. 8.10.2.2 PCB Area Requirements V DD In some applications, PCB area is a criteria for device selection. Table8-2 shows the typical package 0.1µF dimensions and area for the different package options. The table also shows the relative area factor compared V DD to the smallest area. For space critical applications, the DFN package would be the suggested package. 0.1µF TABLE 8-2: PACKAGE FOOTPRINT (1) r e oll Package Package Footprint r t n VVOREUFT P47X6 SSDCAL TMC Microco Pins Type Code LDenimg(temhnmsWi)o indsth 2Area (mm) Relative Area C PI M 6 SOT-23 CH 2.90 2.70 7.83 1.96 6 DFN MA 2.00 2.00 4.00 1 Note1: Does not include recommended land pattern dimensions. Dimensions are typical values. V V SS SS FIGURE 8-10: Typical Microcontroller Connections. © 2011 Microchip Technology Inc. DS22272A-page 71

MCP4706/4716/4726 NOTES: DS22272A-page 72 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 9.0 DEVELOPMENT SUPPORT Development support can be classified into two groups. These are: • Development Tools • Technical Documentation 9.1 Development Tools Several development tools are available to assist in your design and evaluation of the MCP47X6 devices. The currently available tools are shown in Table9-1. These boards may be purchased directly from the Microchip web site at www.microchip.com. 9.1.1 MCP47X6 PICTAIL PLUS MCP47X6 PICtail Plus Explore 16 DAUGHTER BOARD Daughter Board inserted into PICtail Connector Development Board The MCP47X6 PICtail Plus Daughter Board (Order FIGURE 9-1: MCP47X6 PICtail Plus Number: ADM00317) is available from Microchip Daughter Board with PIC Explorer 16 Technology Inc. This board works with Microchip’s PICkit™ Serial Analyzer and PIC Explorer 16 Development Board. Development Board. The firmware example is also available for the Explore 16 Development Board with MCP47X6 PICtail Plus Daughter Board PIC24FJ128. Figure9-1 shows the MCP47X6 PICtail Plus Daughter Board being used with a PIC Explorer 16 Development Board (order #: ADM00317), while Figure9-2 shows the MCP47X6 PICtail Plus Daughter Board being used with a PICkit™ Serial Analyzer. The PICkit™ Serial Analyzer allows the user to quickly evaluate the DAC operation. Refer to the MCP47X6 PICtail Plus Daughter Board User’s Guide for detailed descriptions on operating the daughter board. Refer to www.microchip.com for further information on this product and related material for the users. FIGURE 9-2: MCP47X6 PICtail Plus Daughter Board with PICkit™ Serial Analyzer. TABLE 9-1: DEVELOPMENT TOOLS Board Name Part # Supported Devices 6-pin SC70 Evaluation Board SC70EV MCP4706, MCP4716, MCP4726 MCP4706/4716/4726 Evaluation Board(1, 2) ADM00317(3) MCP4726 Note1: Requires a PICDEM Demo board. See the User’s Guide for additional information and requirements. 2: Requires a PICkit Serial Analyzer. See the User’s Guide for additional information and requirements. 3: This board is currently in the manufacturing cycle, and should be available by end of March 2011. © 2011 Microchip Technology Inc. DS22272A-page 73

MCP4706/4716/4726 9.2 Technical Documentation Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table9-2 shows some of these documents. TABLE 9-2: TECHNICAL DOCUMENTATION Application Title Literature # Note Number AN1326 Using DAC for LDMOS Amplifier Bias Control Applications DS01326 — Signal Chain Design Guide DS21825 — Analog Solutions for Automotive Applications Design Guide DS01005 DS22272A-page 74 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 6-Lead SOT-23 Example XXNN DC25 Address Code Option MCP4706A0T-E/CH MCP4716A0T-E/CH MCP4726A0T-E/CH A0 (00) DBNN DFNN DKNN A1 (01) DCNN DGNN DLNN A2 (10) DDNN DHNN DMNN A3 (11) DENN DJNN DPNN 6-Lead DFN (2x2) Example XXX AAB NNN 425 Address Code Option MCP4706A0T-E/MA MCP4716A0T-E/MA MCP4726A0T-E/MA A0 (00) AAA AAE AAP A1 (01) AAB AAF AAQ A2 (10) AAC AAG AAR A3 (11) AAD AAH AAS Legend: XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn) * This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. DS22272A-page 75

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MCP4706/4716/4726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS22272A-page 77

MCP4706/4716/4726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22272A-page 78 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011 Microchip Technology Inc. DS22272A-page 79

MCP4706/4716/4726 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS22272A-page 80 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 APPENDIX A: REVISION HISTORY Revision A (February 2011) • Original Release of this Document. © 2011 Microchip Technology Inc. DS22272A-page 81

MCP4706/4716/4726 NOTES: DS22272A-page 82 © 2011 Microchip Technology Inc.

MCP4706/4716/4726 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO. XX X X /XX a)MCP4706A0T-E/CH:8-bit V resolution, OUT Device Address Tape and Temperature Package I2C Address “1100000”, Options Reel Range Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b)MCP4706A6T-E/CH:8-bit V resolution, OUT Device: MCP4706: Single Channel 8-Bit DAC I2C Address “1100110”, with EEPROM Memory Tape and Reel, Extended Temp., 6LD SOT-23 pkg. MCP4716: Single Channel 10-Bit DAC c)MCP4706A0T-E/MA:8-bit V resolution, with EEPROM Memory OUT I2C Address “1100000”, MCP4726: Single Channel 12-Bit DAC Tape and Reel, Extended with EEPROM Memory Temp., 6LD DFN pkg. d)MCP4706A6T-E/MA:8-bit V resolution, OUT Address Options: A0 = “1100000” I2C Address. I2C Address “1100110”, Tape and Reel, Extended Devices ordered from the Microchip Temp., 6LD DFN pkg. Sample center will have this address. A1 = “1100001” I2C Address. A2 = “1100010” I2C Address. a)MCP4716A0T-E/CH:10-bit VOUT resolution, A3 = “1100011” I2C Address. I2C Address “1100000”, Tape and Reel, Extended A4 = “1100100” I2C Address. Temp., 6LD SOT-23 pkg. A5 = “1100101” I2C Address. b)MCP4716A6T-E/CH:10-bit V resolution, I2C OUT A6 = “1100110” I2C Address. Address “1100110”, Tape and Reel, Extended A7 = “1100111” I2C Address. Temp., 6LD SOT-23 pkg. c)MCP4716A0T-E/MA:10-bit V resolution, OUT Tape and Reel: T = Tape and Reel I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD DFN pkg. d)MCP4716A6T-E/MA:10-bit V resolution, OUT Temperature Range: E = -40°C to +125°C I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD DFN pkg. Package: CH = Plastic Small Outline Transistor (SOT-23-6), 6-lead MA = Plastic Dual Flat, No Lead Package a)MCP4726A0T-E/CH:12-bit VOUT resolution, (2x2 DFN), 6-lead I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. b)MCP4726A6T-E/CH:12-bit V resolution, OUT I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD SOT-23 pkg. c)MCP4726A0T-E/MA:12-bit V resolution, OUT I2C Address “1100000”, Tape and Reel, Extended Temp., 6LD DFN pkg. d)MCP4726A6T-E/MA:12-bit V resolution, OUT I2C Address “1100110”, Tape and Reel, Extended Temp., 6LD DFN pkg. © 2011 Microchip Technology Inc. DS22272A-page 83

MCP4706/4716/4726 NOTES: DS22272A-page 84 © 2011 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device Trademarks applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC, and may be superseded by updates. It is your responsibility to KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, ensure that your application meets with your specifications. PIC32 logo, rfPIC and UNI/O are registered trademarks of MICROCHIP MAKES NO REPRESENTATIONS OR Microchip Technology Incorporated in the U.S.A. and other WARRANTIES OF ANY KIND WHETHER EXPRESS OR countries. IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, INCLUDING BUT NOT LIMITED TO ITS CONDITION, MXDEV, MXLAB, SEEVAL and The Embedded Control QUALITY, PERFORMANCE, MERCHANTABILITY OR Solutions Company are registered trademarks of Microchip FITNESS FOR PURPOSE. Microchip disclaims all liability Technology Incorporated in the U.S.A. arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard, devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial hold harmless Microchip from any and all damages, claims, Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified suits, or expenses resulting from such use. No licenses are logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code conveyed, implicitly or otherwise, under any Microchip Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, intellectual property rights. PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-896-2 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2011 Microchip Technology Inc. DS22272A-page 85

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: ADM00317 MCP4706A0T-E/CH MCP4706A0T-E/MAY MCP4706A1T-E/CH MCP4706A1T-E/MAY MCP4706A2T- E/CH MCP4706A2T-E/MAY MCP4706A3T-E/CH MCP4706A3T-E/MAY MCP4716A0T-E/CH MCP4716A0T-E/MAY MCP4716A1T-E/CH MCP4716A1T-E/MAY MCP4716A2T-E/CH MCP4716A2T-E/MAY MCP4716A3T-E/CH MCP4716A3T-E/MAY MCP4726A0T-E/CH MCP4726A0T-E/MAY MCP4726A1T-E/CH MCP4726A1T-E/MAY MCP4726A2T-E/CH MCP4726A2T-E/MAY MCP4726A3T-E/CH MCP4726A3T-E/MAY MCP4716A0T-E/CHVAO