MC74HC541A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS http://onsemi.com The MC74HC541A is identical in pinout to the LS541. The device inputs are compatible with Standard CMOS outputs. External pull−up resistors make them compatible with LSTTL outputs. The HC541A is an octal noninverting buffer/line driver/line receiver designed to be used with 3−state memory address drivers, SOIC−20 TSSOP−20 clock drivers, and other bus−oriented systems. This device features DW SUFFIX DT SUFFIX inputs and outputs on opposite sides of the package and two ANDed CASE 751D CASE 948E active−low output enables. PIN ASSIGNMENT The HC541A is similar in function to the HC540A, which has inverting outputs. VCC OE2Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 20 19 18 17 16 15 14 13 12 11 Features • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1 (cid:2)A 1 2 3 4 5 6 7 8 9 10 • High Noise Immunity Characteristic of CMOS Devices OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND • In Compliance With the JEDEC Standard No. 7A Requirements MARKING DIAGRAMS • Chip Complexity: 134 FETs or 33.5 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring 20 20 Unique Site and Control Change Requirements; AEC−Q100 HC Qualified and PPAP Capable HC541A 541A • AWLYYWWG ALYW(cid:2) These Devices are Pb−Free and are RoHS Compliant (cid:2) 1 1 A1 2 18 Y1 SOIC−20 TSSOP−20 A = Assembly Location 3 17 A2 Y2 WL, L = Wafer Lot YY, Y = Year 4 16 A3 Y3 WW, W = Work Week G or (cid:2) = Pb−Free Package 5 15 Data A4 Y4 Noninverting (Note: Microdot may be in either location) Inputs Outputs 6 14 A5 Y5 FUNCTION TABLE 7 13 A6 Y6 Inputs Output Y OE1 OE2 A 8 12 A7 Y7 L L L L 9 11 L L H H A8 Y8 H X X Z Output OE1 1 PIN 20 = VCC X H X Z Enables OE2 PIN 10 = GND 19 X = Don’t Care Z = High Impedance Figure 1. Logic Diagram ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: August, 2014 − Rev. 9 MC74HC541A/D

MC74HC541A MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC Supply Voltage −0.5 to +7.0 V VI DC Input Voltage −0.5 ≤ VI ≤ VCC + 0.5 V VO DC Output Voltage (Note 1) −0.5 ≤ VO ≤ VCC + 0.5 V IIK DC Input Diode Current ±20 mA IOK DC Output Diode Current ±35 mA IO DC Output Sink Current ±35 mA ICC DC Supply Current per Supply Pin ±75 mA IGND DC Ground Current per Ground Pin ±75 mA TSTG Storage Temperature Range −65 to +150 (cid:3)C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 (cid:3)C TJ Junction Temperature under Bias +150 (cid:3)C (cid:3)JA Thermal Resistance SOIC 96 (cid:3)C/W TSSOP 128 PD Power Dissipation in Still Air at 85(cid:3)C SOIC 500 mW TSSOP 450 MSL Moisture Sensitivity Level 1 FR Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in VESD ESD Withstand Voltage Human Body Model (Note 2) > 4000 V Machine Model (Note 3) > 300 Charged Device Model (Note 4) > 1000 ILatchup Latchup Performance Above VCC and Below GND at 85(cid:3)C (Note 5) ±300 mA Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. 2. Tested to EIA/JESD22−A114−A. 3. Tested to EIA/JESD22−A115−A. 4. Tested to JESD22−C101−A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V VOUT TA Operating Temperature Range, All Package Types −55 +125 (cid:3)C tr, tf Input Rise/Fall Time VCC = 2.0 V 0 1000 ns (Figure 2) VCC = 4.5 V 0 500 VCC = 6.0 V 0 400 Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. 6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level. http://onsemi.com 2

MC74HC541A DC CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit VCC −55 to Symbol Parameter Condition V 25(cid:2)C ≤85(cid:2)C ≤125(cid:2)C Unit VIH Minimum High−Level Input Voltage VOUT = 0.1 V 2.0 1.50 1.50 1.50 V |IOUT| ≤ 20 (cid:2)A 3.0 2.10 2.10 2.10 4.5 3.15 3.15 3.15 6.0 4.20 4.20 4.20 VIL Maximum Low−Level Input Voltage VOUT = VCC − 0.1 V 2.0 0.50 0.50 0.50 V |IOUT| ≤ 20 (cid:2)A 3.0 0.90 0.90 0.90 4.5 1.35 1.35 1.35 6.0 1.80 1.80 1.80 VOH Minimum High−Level Output Voltage VIN = VIL 2.0 1.9 1.9 1.9 V |IOUT| ≤ 20 (cid:2)A 4.5 4.4 4.4 4.4 6.0 5.9 5.9 5.9 VIN = VIL |IOUT| ≤ 3.6 mA 3.0 2.48 2.34 2.20 |IOUT| ≤ 6.0 mA 4.5 3.98 3.84 3.70 |IOUT| ≤ 7.8 mA 6.0 5.48 5.34 5.20 VOL Maximum Low−Level Output Voltage VIN = VIH 2.0 0.1 0.1 0.1 V |IOUT| ≤ 20 (cid:2)A 4.5 0.1 0.1 0.1 6.0 0.1 0.1 0.1 VIN = VIH |IOUT| ≤ 3.6 mA 3.0 0.26 0.33 0.40 |IOUT| ≤ 6.0 mA 4.5 0.26 0.33 0.40 |IOUT| ≤ 7.8 mA 6.0 0.26 0.33 0.40 IIN Maximum Input Leakage Current VIN = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 (cid:2)A IOZ Maximum 3−State Leakage Current Output in High Impedance State 6.0 ±0.5 ±5.0 ±10.0 (cid:2)A VIN = VIL or VIH VOUT = VCC or GND ICC Maximum Quiescent Supply VIN = VCC or GND 6.0 4 40 160 (cid:2)A Current (per Package) IOUT = 0 (cid:2)A AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Guaranteed Limit VCC −55 to Symbol Parameter V 25(cid:2)C ≤85(cid:2)C ≤125(cid:2)C Unit tPLH, Maximum Propagation Delay, Input A to Output Y 2.0 80 100 120 ns tPHL (Figures 2 and 4) 3.0 30 40 55 4.5 18 23 28 6.0 15 20 25 tPLZ, Maximum Propagation Delay, Output Enable to Output Y 2.0 110 140 165 ns tPHZ (Figures 3 and 5) 3.0 45 60 75 4.5 25 31 38 6.0 21 26 31 tPZL, Maximum Propagation Delay, Output Enable to Output Y 2.0 110 140 165 ns tPZH (Figures 3 and 5) 3.0 45 60 75 4.5 25 31 38 6.0 21 26 31 tTLH, Maximum Output Transition Time, Any Output 2.0 60 75 90 ns tTHL (Figures 2 and 4) 3.0 22 28 34 4.5 12 15 18 6.0 10 13 15 CIN Maximum Input Capacitance 10 10 10 pF COUT Maximum 3−State Output Capacitance (High Impedance State Output) 15 15 15 pF Typical @ 25°C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer) (Note 7) 35 pF 7. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. http://onsemi.com 3

MC74HC541A tr tf VCC 90% INPUT A 50% 10% GND tPLH tPHL 90% 50% OUTPUT Y 10% tTLH tTHL Figure 2. Switching Waveform VCC OE1 or OE2 50% 50% GND tPZL tPLZ HIGH IMPEDANCE OUTPUT Y 50% 10% VOL tPZH tPHZ 90% VOH OUTPUT Y 50% HIGH IMPEDANCE Figure 3. Switching Waveform TEST POINT OUTPUT DEVICE UNDER TEST CL* *Includes all probe and jig capacitance Figure 4. Test Circuit TEST POINT 1 k(cid:4) CONNECT TO VCC WHEN OUTPUT TESTING tPLZ AND tPZL. DEVICE CONNECT TO GND WHEN UTNEDSETR CL* TESTING tPHZ and tPZH. *Includes all probe and jig capacitance Figure 5. Test Circuit http://onsemi.com 4

MC74HC541A PIN DESCRIPTIONS INPUTS device functions as an non−inverting buffer. When a high A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9) voltage is applied to either input, the outputs assume the high Data input pins. Data on these pins appear in non−inverted impedance state. form on the corresponding Y outputs, when the outputs are OUTPUTS enabled. Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, CONTROLS 13, 12, 11) OE1, OE2 (PINS 1, 19) Device outputs. Depending upon the state of the output Output enables (active−low). When a low voltage is enable pins, these outputs are either non−inverting outputs applied to both of these pins, the outputs are enabled and the or high−impedance outputs. To 7 Other Buffers One of Eight VCC Buffers INPUT A OUTPUT Y OE1 OE2 Figure 6. Logic Detail ORDERING INFORMATION Device Package Shipping† MC74HC541ADWG SOIC−20 WIDE 38 Units / Rail (Pb−Free) MC74HC541ADWR2G SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) NLV74HC541ADWR2G* SOIC−20 WIDE 1000 Tape & Reel (Pb−Free) MC74HC541ADTG TSSOP−20 75 Units / Rail (Pb−Free) MC74HC541ADTR2G TSSOP−20 2500 Tape & Reel (Pb−Free) NLV74HC541ADTR2G* TSSOP−20 2500 Tape & Reel (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable. http://onsemi.com 5

MC74HC541A PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX CASE 948E−02 ISSUE C NOTES: 20X K REF K 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 0.15 (0.006) T U S 0.10 (0.004) M T U S V S ÍÍKÍ1 Í 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE ÍÍÍÍ MOLD FLASH, PROTRUSIONS OR GATE 20 11 J J1 BURRS. MOLD FLASH OR GATE BURRS 2X L/2 ÍÍÍÍ SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE B SECTION N−N INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION L −U− SHALL NOT EXCEED 0.25 (0.010) PER SIDE. PIN 1 0.25 (0.010) 5. DIMENSION K DOES NOT INCLUDE IDENT N DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 1 10 (0.003) TOTAL IN EXCESS OF THE K M DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR 0.15 (0.006) T U S REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE A N DETERMINED AT DATUM PLANE −W−. −V− F MILLIMETERS INCHES DIM MIN MAX MIN MAX DETAIL E A 6.40 6.60 0.252 0.260 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 −W− D 0.05 0.15 0.002 0.006 C F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC G H 0.27 0.37 0.011 0.015 D H J 0.09 0.20 0.004 0.008 DETAIL E J1 0.09 0.16 0.004 0.006 0.100 (0.004) K 0.19 0.30 0.007 0.012 −T− SPELAATNIENG KML1 00.61 (cid:3).940 BSC08.2 (cid:3)5 0.0000 (cid:3).2752 B0S.C081 (cid:3)0 SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 16X 16X 0.36 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 6

MC74HC541A PACKAGE DIMENSIONS SOIC−20 DW SUFFIX CASE 751D−05 ISSUE G D NOTES: A (cid:2) 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD 20 11 M PROTRUSION. B 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. (cid:3) 5. DIMENSION B DOES NOT INCLUDE DAMBAR H M 45 PROTRUSION. ALLOWABLE PROTRUSION 10X 0.25 E hX SDCHIOMANELDNLI STBIIOEO NN0.. 1A3T TMOATXAILM IUNM E MXCATEESRSI AOLF B 1 10 MILLIMETERS DIM MIN MAX A 2.35 2.65 B A1 0.10 0.25 20X B B 0.35 0.49 C 0.23 0.32 0.25 M T A S B S D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 A L 0.50 0.90 L (cid:2) 0 (cid:3) 7 (cid:3) SEATING 18X e A1 TPLANE C ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com MC74HC541A/D 7

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