(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4)(cid:7)(cid:8)(cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:5)(cid:5)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:21)(cid:22)(cid:17)(cid:18)(cid:1) (cid:23)(cid:21)(cid:12)(cid:24)(cid:8)(cid:25)(cid:26)(cid:1)(cid:12)(cid:13)(cid:12)(cid:17)(cid:8)(cid:10)(cid:16)(cid:12)(cid:27)(cid:16)(cid:12)(cid:1) SDFS063A − D2932, MARCH 1987 − REVISED OCTOBER 1993 • 3-State Outputs Drive Bus Lines or Buffer SN54F244...J PACKAGE Memory Address Registers SN74F244...DB, DW, OR N PACKAGE • (TOP VIEW) Package Options Include Plastic Small-Outline (SOIC) and Shrink 1OE 1 20 VCC Small-Outline (SSOP) Packages, Ceramic 1A1 2 19 2OE Chip Carriers, and Plastic and Ceramic 2Y4 3 18 1Y1 DIPs 1A2 4 17 2A4 2Y3 5 16 1Y2 description 1A3 6 15 2A3 These octal buffers and line drivers are designed 2Y2 7 14 1Y3 specifically to improve both the performance and 1A4 8 13 2A2 density of 3-state memory address drivers, clock 2Y1 9 12 1Y4 drivers, and bus-oriented receivers and GND 10 11 2A1 transmitters. Taken together with the ′F240 and ′F241, these devices provide the choice of SN54F244...FK PACKAGE selected combinations of inverting and (TOP VIEW) noninverting outputs, symmetrical OE (active-low output-enable) inputs, and complementary OE Y4 A1 OE CCOE and OE inputs. 2 1 1V 2 The ′F244 is organized as two 4-bit buffers/line 1A2 43 2 1 20 1918 1Y1 drivers with separate output enable (OE) inputs. 2Y3 5 17 2A4 When OE is low, the device passes data from the 1A3 6 16 1Y2 A inputs to the Y outputs. When OE is high, the 2Y2 7 15 2A3 outputs are in the high-impedance state. 1A4 8 14 1Y3 9 10 11 12 13 The SN74F244 is available in TI’s shrink small-outline package (DB), which provides the 1 D 14 2 Y N AY A same I/O pin count and functionality of standard 2 G 21 2 small-outline packages in less than half the printed-circuit-board area. The SN54F244 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74F244 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each buffer) INPUTS OOUUTTPPUUTT OE A Y L H H L L L H X Z (cid:27)(cid:18)(cid:10)(cid:20)(cid:16)(cid:11)(cid:12)(cid:21)(cid:10)(cid:2) (cid:20)(cid:13)(cid:12)(cid:13) (cid:28)(cid:29)(cid:30)(cid:31)!"#$(cid:28)(cid:31)(cid:29) (cid:28)% &’!!((cid:29)$ #% (cid:31)(cid:30) )’*+(cid:28)&#$(cid:28)(cid:31)(cid:29) ,#$(- Copyright  1993, Texas Instruments Incorporated (cid:27)!(cid:31),’&$% &(cid:31)(cid:29)(cid:30)(cid:31)!" $(cid:31) %)(&(cid:28)(cid:30)(cid:28)&#$(cid:28)(cid:31)(cid:29)% )(! $.( $(!"% (cid:31)(cid:30) (cid:12)(/#% (cid:21)(cid:29)%$!’"((cid:29)$% %$#(cid:29),#!, 0#!!#(cid:29)$1- (cid:27)!(cid:31),’&$(cid:28)(cid:31)(cid:29) )!(cid:31)&(%%(cid:28)(cid:29)2 ,(cid:31)(% (cid:29)(cid:31)$ (cid:29)(&(%%#!(cid:28)+1 (cid:28)(cid:29)&+’,( $(%$(cid:28)(cid:29)2 (cid:31)(cid:30) #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2−1 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4)(cid:7)(cid:8)(cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:5)(cid:5)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:21)(cid:22)(cid:17)(cid:18)(cid:1) (cid:23)(cid:21)(cid:12)(cid:24)(cid:8)(cid:25)(cid:26)(cid:1)(cid:12)(cid:13)(cid:12)(cid:17)(cid:8)(cid:10)(cid:16)(cid:12)(cid:27)(cid:16)(cid:12)(cid:1) SDFS063A − D2932, MARCH 1987 − REVISED OCTOBER 1993 logic symbol† logic diagram (positive logic) 1 1 1OE 1OE EN 2 18 2 18 1A1 1Y1 1A1 1Y1 4 16 1A2 1Y2 1A3 6 14 1Y3 1A2 4 16 1Y2 8 12 1A4 1Y4 14 6 1A3 1Y3 19 2OE EN 8 12 1A4 1Y4 11 9 2A1 2Y1 13 7 2A2 2Y2 15 5 19 2A3 2Y3 2OE 17 3 2A4 2Y4 11 9 †This symbol is in accordance with ANSI/IEEE Std 91-1984 2A1 2Y1 and IEC Publication 617-12. 7 13 2Y2 2A2 15 5 2A3 2Y3 17 3 2A4 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −1.2 V to 7 V I Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −30 mA to 5 mA Voltage range applied to any output in the disabled or power-off state . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V CC Current into any output in the low state:SN54F244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74F244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Operating free-air temperature range: SN54F244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C SN74F244 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed. 2−2 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4)(cid:7)(cid:8)(cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:5)(cid:5)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:21)(cid:22)(cid:17)(cid:18)(cid:1) (cid:23)(cid:21)(cid:12)(cid:24)(cid:8)(cid:25)(cid:26)(cid:1)(cid:12)(cid:13)(cid:12)(cid:17)(cid:8)(cid:10)(cid:16)(cid:12)(cid:27)(cid:16)(cid:12)(cid:1) SDFS063A − D2932, MARCH 1987 − REVISED OCTOBER 1993 recommended operating conditions SN54F244 SN74F244 UUNNIITT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IIK Input clamp current −18 −18 mA IOH High-level output current −12 −15 mA IOL Low-level output current 48 64 mA TA Operating free-air temperature −55 125 0 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54F244 SN74F244 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = −18 mA −1.2 −1.2 V IOH = −3 mA 2.4 3.3 2.4 3.3 VVCCCC == 44..55 VV IOH = −12 mA 2 3.2 VVOOHH VV IOH = −15 mA 2 3.1 VCC = 4.75 V, IOH = −3 mA 2.7 IOL = 48 mA 0.38 0.55 VVOOLL VVCCCC == 44..55 VV VV IOL = 64 mA 0.42 0.55 IOZH VCC = 5.5 V, VO = 2.7 V 50 50 µA IOZL VCC = 5.5 V, VO = 0.5 V −50 −50 µA II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 µA OE −1 −1 IIIILL VVCCCC == 55..55 VV,, VVII == 00..55 VV mmAA Any A −1.6 −1.6 IOS‡ VCC = 5.5 V, VO = 0 −100 −225 −100 −225 mA Outputs high 40 60 40 60 IICCCC VVCCCC == 55..55 VV,, Outputs low 60 90 60 90 mmAA OOuuttppuuttss ooppeenn Outputs disabled 60 90 60 90 †All typical values are at VCC = 5 V, TA = 25°C. ‡Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 2−3 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4)(cid:7)(cid:8)(cid:1)(cid:2)(cid:9)(cid:4)(cid:5)(cid:6)(cid:4)(cid:4) (cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:8)(cid:15)(cid:16)(cid:5)(cid:5)(cid:17)(cid:18)(cid:1)(cid:19)(cid:20)(cid:18)(cid:21)(cid:22)(cid:17)(cid:18)(cid:1) (cid:23)(cid:21)(cid:12)(cid:24)(cid:8)(cid:25)(cid:26)(cid:1)(cid:12)(cid:13)(cid:12)(cid:17)(cid:8)(cid:10)(cid:16)(cid:12)(cid:27)(cid:16)(cid:12)(cid:1) SDFS063A − D2932, MARCH 1987 − REVISED OCTOBER 1993 switching characteristics (see Note 2) VCC = 5 V, VCC = 4.5 V to 5.5 V, CL = 50 pF, CL = 50 pF, FROM TO RL = 500 Ω, RL = 500Ω, PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = 25°C TA = MIN to MAX† UNIT ′F244 SN54F244 SN74F244 MIN TYP MAX MIN MAX MIN MAX tPLH 1.7 3.6 5.2 2 6.5 1.7 6.2 AA YY nnss tPHL 1.7 3.6 5.2 2 7 1.7 6.5 tPZH 1.2 3.9 5.7 2 7 1.2 6.7 OOEE YY nnss tPZL 1.2 5 7 2 8.5 1.2 8 tPHZ 1.2 4.1 6 2 7 1.2 7 OOEE YY nnss tPLZ 1.2 4.1 6 2 7.5 1.2 7 †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. NOTE 2: Load circuits and waveforms are shown in Section 1. 2−4 POST OFFICE BOX 65•5303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9758601Q2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9758601Q2A SNJ54F 244FK 5962-9758601QRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QR A SNJ54F244J 5962-9758601QRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QR A SNJ54F244J 5962-9758601QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QS A SNJ54F244W 5962-9758601QSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QS A SNJ54F244W JM38510/33203B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 33203B2A JM38510/33203B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 33203B2A JM38510/33203BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BRA JM38510/33203BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BRA JM38510/33203BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BSA JM38510/33203BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BSA M38510/33203B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 33203B2A M38510/33203B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 33203B2A M38510/33203BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BRA Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) M38510/33203BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BRA M38510/33203BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BSA M38510/33203BSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 33203BSA SN54F244J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54F244J SN54F244J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54F244J SN74F244DB ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM F244 & no Sb/Br) SN74F244DB ACTIVE SSOP DB 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM F244 & no Sb/Br) SN74F244DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DBR ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DWG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 F244 & no Sb/Br) SN74F244N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74F244N (RoHS) SN74F244N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74F244N (RoHS) SN74F244NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74F244N (RoHS) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74F244NE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74F244N (RoHS) SN74F244NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F244 & no Sb/Br) SN74F244NSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F244 & no Sb/Br) SN74F244NSRE4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F244 & no Sb/Br) SN74F244NSRE4 ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74F244 & no Sb/Br) SNJ54F244FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9758601Q2A SNJ54F 244FK SNJ54F244FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9758601Q2A SNJ54F 244FK SNJ54F244J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QR A SNJ54F244J SNJ54F244J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QR A SNJ54F244J SNJ54F244W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QS A SNJ54F244W SNJ54F244W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9758601QS A SNJ54F244W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54F244, SN74F244 : •Catalog: SN74F244 •Military: SN54F244 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74F244DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74F244DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74F244NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 7-Oct-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74F244DBR SSOP DB 20 2000 367.0 367.0 38.0 SN74F244DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74F244NSR SO NS 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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