19-4252; Rev 1; 10/08 12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor General Description Features M The MAX1329/MAX1330 are smart data acquisition sys- ♦ 1.8V to 3.6V Single Digital Supply Operation A tems (DASs) based on a successive approximation ♦ Internal Charge Pump for Analog Circuits (2.7V to register (SAR) analog-to-digital converter (ADC). These X devices are highly integrated, offering an ADC, digital- 5.5V) 1 to-analog converters (DACs), operational amplifiers (op ♦ 12-Bit SAR ADC amps), voltage reference, temperature sensors, and 3 12 Bits, 312ksps, No Missing Codes analog switches in the same device. 2 16 Bits, 1000sps, DSP Mode The MAX1329/MAX1330 offer a single ADC with a refer- 16-Word FIFO and 20-Bit Accumulator 9 ence buffer. The ADC is capable of operating in one of PGA with Gains of 1, 2, 4, and 8 / two user-programmable modes. In normal mode, the M Unipolar and Bipolar Modes ADC provides up to 12 bits of resolution at 312ksps. In DSP mode, the ADC provides up to 16 bits of resolution 16-Input Differential Multiplexer A at 1000sps. The ADC accepts one external differential ♦ Dual 12-Bit Force-Sense DACs X input or two external single-ended inputs as well as 16-Word FIFO (DACA Only) inputs from other circuitry on-board. An on-chip pro- 1 grammable gain amplifier (PGA) follows the analog ♦ Independent Voltage References for ADC and DACs 3 inputs, reducing external circuitry requirements. The Internal 2.5V Reference 3 PGA gain is adjustable from 1V/V to 8V/V. Adjustable Reference Buffers Provide 1.25V, The MAX1329/MAX1330 operate from a 1.8V to 3.6V dig- 2.048V, or 2.5V 0 ital power supply. Shutdown and sleep modes are avail- ♦ System Support able for power-saving applications. Under normal ADC Alarm Register operation, an internal charge pump boosts the supply Uncommitted Op Amps voltage for the analog circuitry when the supply is < 2.7V. Dual SPDT Analog Switches The MAX1329/MAX1330 offer four analog programmable Internal/External Temperature Sensor I/Os (APIOs) and four digital programmable I/Os Internal Oscillator with Clock I/O (DPIOs). The APIOs can be configured as general-pur- Digital Programmable I/O pose logic inputs and outputs, as a wake-up function, or as a buffer and level shifter for the serial interface to Analog Programmable I/O communicate with slave devices powered by the analog Programmable Interrupts supply, AVDD. The DPIOs can be configured as general- Accurate Supply Voltage Measurement purpose logic inputs and outputs as well as inputs to Programmable Dual Voltage Monitors directly control the ADC conversion rate, the analog ♦ SPI-/QSPI-/MICROWIRE-Compatible, 4-Wire Serial switches, the loading of the DACs, wake-up, sleep, and Interface shutdown modes, and as an interrupt for when the ana- log-to-digital conversion is complete. ♦ Space-Saving, 6mm x 6mm, 40-Pin Thin QFN The MAX1329 includes dual 12-bit force-sense DACs Package with a programmable reference buffer and one op amp. The MAX1330 provides one 12-bit force-sense DAC with Ordering Information a programmable reference buffer and two op amps. For the MAX1329/MAX1330, a 16-word DAC FIFO can be PART TEMP RANGE PIN-PACKAGE used with the DACA for direct digital synthesis (DDS) M AX 13 29 BET L+ -40°C to +85°C 40 Thin QFN-EP** of waveforms. The 4-wire serial interface is compatible with SPI™, M AX 13 30 BET L+* -40°C to +85°C 40 Thin QFN-EP** QSPI™, and MICROWIRE™. *Future product—contact factory for availability. Applications **EP = Exposed pad. +Denotes a lead-free/RoHS-compliant package. Battery-Powered and Portable Devices Electrochemical and Optical Sensors Pin Configurations appear at end of data sheet. Medical Instruments Industrial Control Data Acquisition Systems Low-Cost CODECs SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________Maxim Integrated Products 1 For pricing delivery, and ordering information please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ABSOLUTE MAXIMUM RATINGS 3 AVDDto AGND.........................................................-0.3V to +6V AGND to DGND....................................................-0.3V to +0.3V 3 DVDDto DGND.........................................................-0.3V to +6V Continuous Current into Any Pin.......................................±50mA Analog Inputs to AGND....................................-0.3V to the lower Continuous Power Dissipation (TA= +70°C) 1 of (AVDD+ 0.3V) or +6V 40-Pin Thin QFN (derate 37mW/°C above +70°C)....2963mW X Digital Inputs to DGND.....................................-0.3V to the lower Operation Temperature Range............................-40°C to +85°C A of (DVDD+ 0.3V) or +6V Storage Temperature Range.............................-65°C to +150°C Analog Outputs to AGND.................................-0.3V to the lower Junction Temperature......................................................+150°C M of (AVDD+ 0.3V) or +6V Lead Temperature (soldering, 10s) ................................+300°C Digital Outputs to DGND..................................-0.3V to the lower 9/ of (DVDD+ 0.3V) or 6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional 2 operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to 3 absolute maximum rating conditions for extended periods may affect device reliability. 1 ELECTRICAL CHARACTERISTICS X (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; A 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) M PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC Resolution No missing codes 12 Bits DSP-Mode Resolution 256 oversampling, dither enabled 16 Bits Integral Nonlinearity INL Normal mode (Note 1) ±1 LSB12 Differential Nonlinearity DNL Normal mode (Note 1) ±1 LSB12 Offset Error (Note 1) ±4 mV Offset Drift ±1.5 µV/°C Gain = 1 ±0.1 Gain Error (Excluding Reference) Gain = 2, 4 ±1.5 % FS (Note 1) Gain = 8 ±2.5 Gain Temperature Coefficient Excluding reference ±0.8 ppm/°C +V R EF AD C/ Unipolar mode, gain = 1, 2, 4, 8 0 Gain Voltage Range V -VREFADC/ +V R EF AD C/ Bipolar mode, gain = 1, 2, 4, 8 (2 x Gain) (2 x Gain) Absolute Input Voltage Range AGND AVDD V Input Leakage Current into (Note 2) ±0.5 ±1 nA Analog Inputs Gain = 1, 2 24 Input Capacitance pF Gain = 4, 8 48 Gain = 1, 2 0.6 Acquisition Time tACQ µs Gain = 4, 8 1.2 Conversion Time tCONV 12 clocks 2.4 µs Conversion Clock Frequency 0.1 5.0 MHz Normal operation mode, 325 ADC converting at 234ksps ADC Supply Current (Note 3) µA Fast power-down mode, 210 ADC converting at 234ksps Aperture Delay tAD 30 ns 2 _______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) M (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; A 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 Aperture Jitter tAJ 50 ps 3 Gain = 1, 2; DVDD ≥ 2.7V, AVDD ≥ 5.0V 312 2 Gain = 4, 8; DVDD ≥ 2.7V, AVDD ≥ 5.0V 263 9 Sample Rate ksps Gain = 1, 2 234 / M Gain = 4, 8 200 Power-Supply Rejection PSR AVDD = 2.7V to 5.5V, full-scale input ±0.06 ±0.5 mV/V A Turn-On Time Supply and reference have settled 1 µs X ADC DYNAMIC ACCURACY (10kHz sine wave, VIN = 2.5VP-P, fSAMPLE = 234ksps, gain = 1) 1 Signal-to-Noise Plus Distortion SINAD 71 dB 3 Total Harmonic Distortion THD Up to the 5th harmonic 82 dB 3 Spurious-Free Dynamic Range SFDR 84 dB 0 Channel-to-Channel Crosstalk 100 dB Full-Power Bandwidth FPBW -3dB point 4 MHz DAC (RL = 5kΩ, CL = 200pF, tested in unity gain, unless otherwise noted) Resolution 12 Bits Differential Nonlinearity DNL Guaranteed monotonic (Note 4) ±1.0 LSB Integral Nonlinearity INL (Note 4) ±1 ±8 LSB Offset Error Code = 0x000 (tested at 0x032) ±2.5 ±30 mV Offset-Error Temperature Due to amplifier ±7 µV/°C Coefficient Gain Error Code = 0xFFF 0 ±5 % FS Gain-Error Temperature Excluding reference drift ±7 ppm/°C Coefficient Output Voltage Range No load AGND AVDD V Output Slew Rate CL = 200pF 0.5 V/µs Output Settling Time Code = 0x400 to 0xC00 (Note 2) 4 10 µs FB_ Input Bias Current (Note 2) ±0.1 1 nA FB_ Switch Resistance 200 Ω FB_ Switch Turn-On/-Off Time 40 ns FB_ Switch Off Isolation f = 10kHz 100 dB FB_ Switch Charge Injection 1 pC DAC-to-DAC Crosstalk 0.5 nV-s Sink 13 Short-Circuit Current mA Source 50 DC Output Impedance Code = 0x800 0.8 Ω Power-Up Time 0.5 LSB settling to 0x800 5 µs Power-Supply Rejection PSR AVDD = 2.7V to 5.5V ±1 mV/V Charge-Pump Output Code = 0x800, buffer on, RL = 5kΩ, 100 µVRMS Feedthrough CL = 200pF _______________________________________________________________________________________ 3

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ELECTRICAL CHARACTERISTICS (continued) 3 (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; 3 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X Power-Down Output Leakage A ±100 nA Current M Supply Current per DAC No load (Note 3) 70 µA / INTERNAL REFERENCE (10µF capacitor at REFADC and REFDAC, 0.01µF capacitor at REFADJ) 9 TA = +2 5° C, ARE F<1 :0> = DR E F<1 :0> = 01 1.225 1.250 1.275 2 Output Voltage at REFADC and 3 REFDAC TA = +2 5° C, ARE F<1 :0> = DR E F<1 :0> = 10 2.007 2.048 2.089 V 1 TA = +2 5° C, ARE F<1 :0> = DR E F<1 :0> = 11 2.450 2.500 2.550 Output-Voltage Temperature (Note 2) ±10 ±75 ppm/°C X REFADC and REFDAC Source 40 A mA Output Short-Circuit Current Sink 13 M REFADC and REFDAC ±100 ±600 µV/V Line Regulation ISOURCE = 0µA to 500µA, TA = +25°C 10 Load Regulation µV/µA ISINK = 0µA to 80µA, TA = +25°C 10 ppm/ Long-Term Stability TA = +25°C ±100 1000hrs Turn-On Time At REFADJ 2 ms Turn-Off Time 100 ns Internal reference 445 Refere nce Su pp l y Cu r re nt (N o te 3) REFADC buffer 270 µA REFDAC buffer 270 EXTERNAL REFERENCE AT REFADJ AVDD AREF<1:0> = DREF<1:0> = 11 1.225V - 0.1V External Reference Input Voltage 1.496V to AREF<1:0> = DREF<1:0> = 10 V Range AVDD - 0.1V 2.450V to AREF<1:0> = DREF<1:0> = 01 AVDD - 0.1V Input Resistance 50 75 kΩ AREF<1:0> = 01 1 REFADC Buffer Gain AREF<1:0> = 10 0.8192 V/V AREF<1:0> = 11 0.5 DREF<1:0> = 01 1 REFDAC Buffer Gain DREF<1:0> = 10 0.8192 V/V DREF<1:0> = 11 0.5 Minimum Capacitive Bypass REFADJ to AGND 10 nF 4 _______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) M (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; A 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 EXTERNAL REFERENCE AT REFADC 3 External Reference Input Voltage 2 AGND AVDD V Range 9 REFADC Input Resistance 50 75 kΩ / M REFADC Input Current VREFADC = 2.5V, 300ksps 30 40 µA Turn-On Time REFADC buffer, CREFADC = 1µF 75 µs A Shutdown REFADC Input Current 0.01 1.0 µA X Minimum Capacitive Bypass REFADC to AGND 10 µF 1 EXTERNAL REFERENCE AT REFDAC 3 REFDAC Input Voltage Range AGND AVDD V 3 MAX1329 64 90 180 0 REFDAC Input Resistance kΩ MAX1330 128 180 360 MAX1329, VREFDAC = 2.5V 28 86 REFDAC Input Current µA MAX1330, VREFDAC = 2.5V 14 43 Turn-On Time REFDAC buffer 75 µs Shutdown REFDAC Input Current 0.1 1 µA Minimum Capacitive Bypass REFDAC to AGND 10 µF MULTIPLEXER Absolute Input Voltage Range AGND AVDD V ( AG ND + 100m V ) < VA IN _ < (A VD D - 100m V ) Absolute Input Leakage Current ±0.01 ±1 nA ( No te 2) ADC gain = 1, 2 24 Input Capacitance pF ADC gain = 4, 8 48 On Resistance 340 Ω INTERNAL TEMPERATURE SENSOR Internal Sensor Measurement TA = +25°C ±0.25 °C Error ( No te 5) TA = -40°C to +85°C ±3 TA = +25°C ±0.4 External Sensor Measurement TA = 0°C to +70°C ±2 °C Error ( No te 5) TA = -40°C to +85°C ±3 _______________________________________________________________________________________ 5

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ELECTRICAL CHARACTERISTICS (continued) 3 (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; 3 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X Temperature Resolution VREFADC = 2.5V 1/8 °C/LSB A External-Diode Drive Ratio IDRIVEMIN = 4µA, IDRIVEMAX = 68µA 17:1 M Temperature-Sensor Supply Not including ADC current (Note 3) 100 µA / Current 9 Temperature-Sensor Conversion 307 clocks per measurement, master clock 2 65 µs Time = 5.00MHz 3 CHARGE PUMP 1 X Input Voltage DVDD 1.8 3.6 V DVDD = 1.8V to 3.0V, VM2CP<2:0> = 001 2.85 3.0 3.20 A No-Load Output Voltage AVDD DVDD = 2.2V to 3.6V, VM2CP<2:0> = 010 3.75 4.0 4.30 V M DVDD = 2.7V to 3.6V, VM2CP<2:0> = 011 4.80 5.0 5.40 Output Current Including internal current (Table 32) 25 mA No-Load Supply Current DVDD = 2.7V, AVDD = 4V, 39kHz clock 250 µA Switching Frequency 39 78 kHz Switch Turn-On/-Off Time Between DVDD to AVDD, charge pump off 40 ns Switch Impedance Shorts DVDD to AVDD, charge pump off 25 50 Ω 25mA load, DVDD = 1.8V, AVDD = 3.0V, Efficiency 80 % 39kHz clock DVDD VOLTAGE MONITOR (VM1) Supply Voltage Range 1.0 3.6 V VM1<1:0> = 0x, RST1 input 1.80 1.865 1.93 Trip Threshold (DVDD Falling) VDTH V VM1<1:0> = x0, RST2 input 2.65 2.750 2.90 VM1<1:0> = 0x, RST1 input 15 Hysteresis VDHYS mV VM1<1:0> = x0, RST2 input 22.5 Reset Timeout Period VDVDD = VDTH + VDHYS 170 ms Turn-On Time DVDD = 1.8V, enabled by VM1 <1:0> 2 ms AVDD VOLTAGE MONITOR (VM2) Supply Voltage Range 1.0 5.5 V VM2CP<1:0> = 01 2.53 2.775 2.975 Trip Threshold (AVDD Falling) VATH VM2CP<1:0> = 10 3.4 3.700 3.925 V (Note 6) VM2CP<1:0> = 11 4.25 4.625 4.925 VM2CP<1:0> = 01 22.5 Hysteresis VAHYS VM2CP<1:0> = 10 30 mV VM2CP<1:0> = 11 37.5 6 _______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) M (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; A 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 Turn-On Time AVDD = 2.7V, enabled by VM2CP<1:0> 2 ms 3 INTERNAL OSCILLATOR 2 Clock Frequency TA = TMIN to TMAX 3.5758 3.6864 3.7970 MHz 9 Turn-Off Delay Using clock at CLKIO pin, ODLY = 1 1024 Clocks / M Turn-On Time 200 ns Supply Current (Note 7) 120 µA A SWITCHES (SPDT) X On Resistance AVDD = 2.7V to 5.5V 140 200 Ω 1 AVDD = 4.5V to 5.5V 90 120 3 On-Resistance Match 15 Ω 3 On-Resistance Flatness Over analog voltage range 12 Ω 0 Analog Voltage Range AGND AVDD V Turn-On/-Off Time Break-before-make for SPDT configuration 50 ns AGND + 100mV < VSN_ < AVDD - 100mV Leakage Current 0.08 ±1 nA (Note 2) Off Isolation f = 10kHz 100 dB Charge Injection 1 pC Input Capacitance 2 pF OPERATIONAL AMPLIFIER (RL = 10kΩ, CL = 200pF) Input Bias Current (Note 2) 0.3 ±1 nA Input Offset Voltage VOS 2 ±20 mV Input Offset Drift ∆VOS ±10 µV/°C Common-Mode Rejection Ratio CMRR AGND + 100mV < VCM < AVDD - 100mV 75 dB Phase Margin 60 degrees Charge-Pump Output 100 µVP-P Feedthrough Common-Mode Input Voltage AGND AVDD V Range No load AGND AVDD 10kΩ load 0.1 AVDD Output Voltage Range - 0.1 V 100kΩ load 0.1 AVDD - 0.1 Gain Bandwidth Product 1 MHz Slew Rate 0.5 V/µs OSW_ Switch Resistance AVDD = 2.7V to 5.5V 140 200 Ω AVDD = 4.5V to 5.5V 90 120 OSW_ Switch Turn-On/-Off Time 50 ns _______________________________________________________________________________________ 7

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ELECTRICAL CHARACTERISTICS (continued) 3 (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; 3 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) 1 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X OSW_ Switch Charge Injection 1 pC A Input Noise Voltage Density fIN_ = 1kHz 330 nV/√Hz M Input Noise Voltage fIN_ = 0.1Hz to 10Hz 9 µVRMS / Power-Down Output Leakage ±10 nA 9 2 Power-Supply Rejection Ratio AVDD = 2.7V to 5.5V 65 100 dB Supply Current per Amplifier (Note 3) 70 µA 3 Turn-On Time 5 µs 1 X Source 50 Short-Circuit Current mA Sink 13 A DC Output Impedance AV = 1V/V 0.2 Ω M DIGITAL INPUTS (DIN, SCLK, CS) 0.7 x Input High Voltage VIH V DVDD 0.3 x Input Low Voltage VIL V DVDD Input Hysteresis DVDD = 3V 200 mV Input Leakage Current VIN = 0 or DVDD ±0.01 ±10 µA DIGITAL OUTPUTS (DOUT, RST1, RST2) ISINK = 1mA, DVDD = 2.7V to 3.6V 0.4 Output Low Voltage VOL V ISINK = 200µA, DVDD = 1.8V to 3.6V 0.4 0.8 x ISOURCE = 0.2mA, DVDD = 2.7V to 3.6V DVDD Output High Voltage VOH V 0.8 x ISOURCE = 100µA, DVDD = 1.8V to 3.6V DVDD DOUT Three-State Leakage ±0.01 ±10 µA DOUT Three-State Capacitance (Note 2) 15 pF RST1, RST2 Open-Drain Output ISINK = 1mA, DVDD = 2.7V to 3.6V 0.4 V Low Voltage ISINK = 200µA, DVDD = 1.8V to 3.6V 0.4 RST1, RST2 Open-Drain Output (Note 2) 0.13 100 nA Leakage Current DIGITAL I/O (DPIO1–DPIO4, CLKIO) ISINK = 2mA, DVDD = 2.7V to 3.6V 0.4 Output Low Voltage V ISINK = 1mA, DVDD = 1.8V to 3.6V 0.4 0.8 x ISOURCE = 2mA, DVDD = 2.7V to 3.6V DVDD Output High Voltage V 0.8 x ISOURCE = 1mA, DVDD = 1.8V to 3.6V DVDD 8 _______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor ELECTRICAL CHARACTERISTICS (continued) M (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, VREFDAC= VREFADC= 2.5V, external reference; 10µF capacitor at REFADC and REFDAC; A 0.01µF capacitor at REFADJ; TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25°C.) X PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 Input High Voltage 0.7 x V 3 DVDD 2 DPIO1–DPIO4 0.3 x 9 DVDD / Input Low Voltage V M 0.25 x CLKIO DVDD A Input Hysteresis DVDD = 3V 110 mV X Three-State Leakage ±0.01 ±1 µA 1 Three-State Capacitance (Note 2) 15 pF 3 DPIO_ Pullup Resistance 0.5 MΩ 3 ANALOG I/O (APIO1–APIO4) 0 ISINK = 2mA, AVDD = 2.7V to 5.5V 0.4 Output Low Voltage V ISINK = 1mA, AVDD = 1.8V to 5.5V 0.4 0.8 x ISOURCE = 2mA, AVDD = 2.7V to 5.5V AVDD Output High Voltage V 0.8 x ISOURCE = 1mA, AVDD = 1.8V to 5.5V AVDD 0.7 x AVDD = 2.7V to 5.5V AVDD Input High Voltage V 0.7 x AVDD = DVDD = 1.8V to 3.6V AVDD 0.3 x AVDD = 2.7V to 5.5V AVDD Input Low Voltage V 0.3 x AVDD = DVDD = 1.8V to 3.6V AVDD AVDD = 3V 120 Input Hysteresis mV AVDD = 5V 160 Three-State Leakage ±0.01 ±10 µA Three-State Capacitance (Note 2) 15 pF Pullup Resistance 0.5 MΩ POWER REQUIREMENTS DVDD Supply Voltage Range 1.8 3.6 V AVDD Supply Voltage Range 2.7 5.5 V Run (all on, except charge pump) 3.75 7.5 mA Supply Current (Note 8) Sleep (1.8V or 2.7V monitor on) 1 2.5 µA Shutdown Current All off 0.5 1 µA _______________________________________________________________________________________ 9

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 TIMING CHARACTERISTICS 3 (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, TA= TMINto TMAX, unless otherwise noted.) 3 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 X SERIAL-INTERFACE TIMING PARAMETERS (DVDD = 2.7V to 3.6V) (Figures 1 and 2) SCLK Operating Frequency fOP 0 20 MHz A SCLK Cycle Time tCYC 50 ns M DIN to SCLK Setup tDS 15 ns 9/ DIN to SCLK Hold tDH 0 ns 2 SCLK Fall to Output Data Valid tDO 20 ns 3 CS Fall to Output Enable tDV 24 ns 1 CS Rise to Output Disable tTR 24 ns X CS to SCLK Rise Setup tCSS 15 ns A CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse-Width High tCH 20 ns M SCLK Pulse-Width Low tCL 20 ns SERIAL-INTERFACE TIMING PARAMETERS (DVDD = 1.8V to 3.6V) (Figures 1 and 2) SCLK Operating Frequency fOP 0 10 MHz SCLK Cycle Time tCYC 100 ns DIN to SCLK Setup tDS 30 ns DIN to SCLK Hold tDH 0 ns SCLK Fall to Output Data Valid tDO 40 ns CS Fall to Output Enable tDV 48 ns CS Rise to Output Disable tTR 48 ns CS to SCLK Rise Setup tCSS 30 ns CS to SCLK Rise Hold tCSH 0 ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1–DPIO4, DVDD = 2.7V to 3.6V, CL = 20pF) SPI Write to DPIO Output Valid tSD From last SCLK rising edge 50 ns DPIO Rise/Fall Input to Interrupt tDI Interrupt programmed on RST1 and/or 55 ns Asserted Delay RST2, corresponding status bits unmasked DPIO Input to Analog Block Delay tDA When controlling ADC, DACs, or switches 40 ns DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1–DPIO4, DVDD = 1.8V to 3.6V, CL = 20pF) SPI Write to DPIO Output Valid tSD From last SCLK rising edge 100 ns DPIO Rise/Fall Input to Interrupt tDI Interrupt programmed on RST1 and/or 150 ns Asserted Delay RST2, corresponding status bits unmasked DPIO Input to Analog Block Delay tDA When controlling ADC, DACs, or switches 50 ns ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1–APIO4, DVDD = 2.7V to 3.6V, AVDD = 2.7V to 5.5V, CL = 20pF) SPI Write to APIO Output Valid tSD From last SCLK rising edge 50 ns APIO Rise/Fall Input to Interrupt tDI Interrupt programmed on RST1 and/or 50 ns Asserted Delay RST2, corresponding status bits unmasked CS to APIO4 Propagation Delay tDCA AP4MD<1:0> = 11 35 ns 10 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor TIMING CHARACTERISTICS (continued) M (DVDD= 1.8V to 3.6V, AVDD= 2.7V to 5.5V, TA= TMINto TMAX, unless otherwise noted.) A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS X SCLK to APIO3 Propagation tDSA AP3MD<1:0> = 11, CS is high 30 ns 1 Delay 3 DIN to APIO2 Propagation Delay tDDA AP2MD<1:0> = 11, CS is high 25 ns 2 APIO1 to DOUT Propagation tDAD AP1MD<1:0> = 11, CS is high 20 ns 9 Delay / M SMPaIt-cMhoindge Propagation Delay tDM Among APIO4, APIO3, APIO2, and APIO1 ±10 ns A ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1–APIO4, DVDD = 1.8V to 3.6V, AVDD = 2.7V to 5.5V, CL = 20pF) X SPI Write to APIO Output Valid tSD From last SCLK rising edge 100 ns 1 APIO Rise/Fall Input to Interrupt tDI Interrupt programmed on RST1 and/or 175 ns 3 Asserted Delay RST2, corresponding status bits unmasked 3 CS to APIO4 Propagation Delay tDCA AP4MD<1:0> = 11 60 ns 0 SCLK to APIO3 Propagation tDSA AP3MD<1:0> = 11, CS is high 50 ns Delay DIN to APIO2 Propagation Delay tDDA AP2MD<1:0> = 11, CS is high 50 ns APIO1 to DOUT Propagation tDAD AP1MD<1:0> = 11, CS is high 80 ns Delay SPI-Mode Propagation Delay tDM Among APIO4, APIO3, APIO2, and APIO1 ±30 ns Matching Note 1: ADC INL and DNL, offset, and gain are tested at DVDD= 1.8V, AVDD= 2.7V, fSAMPLE= 234ksps to guarantee performance at fSAMPLE= 312ksps, DVDD≥2.7V and AVDD≥5.0V. Note 2: Guaranteed by design. Not production tested. Note 3: AVDDsupply current contribution for this module. Note 4: DNL and INL are measured between code 115 and 4095. Note 5: Temperature sensor accuracy is tested using a 2.5084V reference applied to REFADJ. Note 6: The maximum trip levels for the AVDDmonitor are 5% below the typical charge-pump output value. The charge-pump output voltage and the trip thresholds track to prevent tripping at -5% below the typical charge-pump output value. Note 7: DVDDsupply current contribution for this module. Note 8: The normal operation and sleep mode supply currents are measured with no load on DOUT, SCLK idle, and all digital inputs at DGND or DVDD. CLKIO runs in normal mode operation and idle in sleep mode. ______________________________________________________________________________________ 11

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Characteristics 3 (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) 3 1 STATIC DIGITAL SUPPLY CURRENT STATIC DIGITAL SUPPLY CURRENT STATIC DIGITAL SUPPLY CURRENT X vs. DIGITAL SUPLY VOLTAGE (EVERYTHING ON) vs. DIGITAL SUPPLY VOLTAGE (ONLY VM1A ON) vs. DIGITAL SUPPLY VOLTAGE (SHUTDOWN) MA 01..80 MAX1329 toc01 12..7050 MAX1329 toc02 12..7050 MAX1329 toc03 TA = -40°C 1.50 1.50 / 1329 I (mA)DVDD 00..64 TA = +85°C TA = +25°C μI (A)DVDD101...072055 TA = +85°CTA = +25°C TA = -40°C μI (A)DVDD101...072055 TA = +85°C TA = +25°C TA = -40°C X 0.50 0.50 0.2 A 0.25 0.25 M 0 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 DVDD (V) DVDD (V) DVDD (V) STATIC ANALOG SUPPLY CURRENT STATIC ANALOG SUPPLY CURRENT vs. ANALOG STATIC ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE (EVERYTHING ON) SUPPLY VOLTAGE (ONLY VM1A AND VM1B ON) vs. ANALOG SUPPLY VOLTAGE (SHUTDOWN) 11..6750 MAX1329 toc04 1800000 TA = +85°C MAX1329 toc05 1800000 TA = +85°C MAX1329 toc06 1.60 A)1.55 TA = -40°C TA = +85°C A) 600 TA = +25°C A) 600 TA = +25°C I (mAVDD11..4550 I (nAVDD400 I (nAVDD400 1.40 TA = +25°C 200 TA = -40°C 200 TA = -40°C 1.35 1.30 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVDD (V) AVDD (V) AVDD (V) fOSC ERROR ADC INTEGRAL NONLINEARITY ADC INTEGRAL NONLINEARITY vs. DIGITAL SUPPLY VOLTAGE vs. TEMPERATURE vs. TEMPERATURE 001...680 NOMINAL fOSC = 3.6864MHz (0% VALUE) MAX1329 toc07 00..78 fCONV = 234ksps MAX1329 toc08 00..78 fCONV = 312ksps MAX1329 toc09 0.4 %) TA = +25°C 0.6 0.6 OR ( 0.2 TA = +85°C SB) AVDD = 2.7V SB) f ERROSC-0.20 INL (L 00..45 AVDD = 5.5V INL (L 00..45 AAVVDDDD == 55..50VV -0.4 TA = -40°C -0.6 AVDD = 5.0V 0.3 0.3 -0.8 -1.0 0.2 0.2 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 -40 -15 10 35 60 85 -40 -15 10 35 60 85 DVDD (V) TEMPERATURE (°C) TEMPERATURE (°C) 12 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Typical Operating Characteristics (continued) M (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) A X ADC DIFFERENTIAL NONLINEARITY ADC INTEGRAL NONLINEARITY ADC SUPPLY CURRENT vs. DIGITAL INPUT CODE (AVDD = 3.0V) vs. DIGITAL INPUT CODE (AVDD = 3.0V) vs. ANALOG SUPPLY VOLTAGE 1 001...680 fSAMPLE = 234ksps MAX1329 toc10 001...680 fSAMPLE = 234ksps MAX1329 toc11 111250 MAX1329 toc12 329 0.4 0.4 110 /M DNL (LSB) -00..202 INL (LSB) -00..202 I (A)µAVDD105 AX 100 -0.4 -0.4 1 -0.6 -0.6 95 3 -0.8 -0.8 3 -1.0 -1.0 90 0 1024 2048 3072 4096 0 1024 2048 3072 4096 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 DIGITAL INPUT CODE DIGITAL INPUT CODE AVDD (V) ADC SUPPLY CURRENT ADC OFFSET VOLTAGE ADC OFFSET ERROR vs. CONVERSION RATE vs. TEMPERATURE vs. SUPPLY VOLTAGE 345000 B C MAX1329 toc13 00..45 MAX1329 toc14 00..4580 MAX1329 toc15 300 I (A)µAVDD122550000 A F OFFSET (mV) 00..32 AVDD = 2.7V AVDD = 5.5V OFFSET (mV)00..4464 E 100 0.1 0.42 50 D 0 0 0.40 0 50 100 150 200 250 300 -40 -15 10 35 60 85 2.7 3.7 4.7 CONVERSION RATE (ksps) TEMPERATURE (°C) AVDD (V) A = FAST POWER-DOWN B = NORMAL MODE C = BURST MODE AVDD = 5V, VREFDAC = 2.5V AVDD = 5V, VREFDAC = 2.5V AVDD = 5V, VREFDAC = 2.5V D = FAST POWER-DOWN E = NORMAL MODE F = BURST MODE AVDD = 3V, VREFADC = 1.25VAVDD = 3V, VREFADC = 1.25V AVDD = 3V, VREFADC = 1.25V ______________________________________________________________________________________ 13

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Characteristics (continued) 3 (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) 3 1 ADC GAIN ERROR ADC GAIN ERROR X vs. TEMPERATURE vs. SUPPLY VOLTAGE MA 00..0045 AV = 1 MAX1329 toc16 0.023 AV = 1 MAX1329 toc17 / 9 AVDD = 5.5V %)0.022 32 RROR (%)0.03 N ERROR ( 1 E0.02 GAI0.021 X 0.01 AVDD = 2.7V A M 0 0.020 -40 -15 10 35 60 85 2.7 3.7 4.7 TEMPERATURE (°C) AVDD (V) ADC 4096-POINT FFT PLOT ADC ENOB vs. FREQUENCY -200 fFTINSH D== 1=20 58.322.6.98156kkdHsBpzs MAX1329 toc18 NOB)1123..50 MAX1329 toc19 AGE (dB) --4600 SSFINDARD = = 8 740.7.948ddBB BER OF BITS (E1121..05 VOLT -80 VE NUM11.0 TI C E F -100 EF10.5 -120 10.0 0 20 40 60 80 100 120 120 170 220 270 320 FREQUENCY (kHz) CONVERSION RATE (ksps) 14 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Typical Operating Characteristics (continued) M (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) A X ADC REFERENCE VOLTAGE (1.25V) ADC REFERENCE VOLTAGE (2.048V) 1 vs. LOAD CURRENT vs. LOAD CURRENT 3 11..22551250 AB MAX1329 toc20 22..005546 MAX1329 toc21 29 1.2510 C 2.052 / M 1.2505 2.050 V) D V) A V (REFADC11..22459050 V (REFADC 22..004468 B CD AX E E 1 1.2490 2.044 F 3 1.2485 F 2.042 3 1.2480 2.040 0 -100 0 100 200 300 400 500 -100 0 100 200 300 400 500 IREFADC (µA) IREFADC (µA) A: TA = -40°C, AVDD = 5V, DVDD = 3V D: TA = +25°C, AVDD = 3V, DVDD = 2V A: TA = -40°C, AVDD = 5V, DVDD = 3V D: TA = +25°C, AVDD = 3V, DVDD = 2V B: TA = -40°C, AVDD = 3V, DVDD = 2V E: TA = +85°C, AVDD = 5V, DVDD = 3V B: TA = -40°C, AVDD = 3V, DVDD = 2V E: TA = +85°C, AVDD = 5V, DVDD = 3V C: TA = +25°C, AVDD = 5V, DVDD = 3V F: TA = +85°C, AVDD = 3V, DVDD = 2V C: TA = +25°C, AVDD = 5V, DVDD = 3V F: TA = +85°C, AVDD = 3V, DVDD = 2V ADC REFERENCE VOLTAGE (2.5V) ADC REFERENCE VOLTAGE (1.25V) vs. LOAD CURRENT vs. ANALOG SUPPLY VOLTAGE 222...555001680 MAX1329 toc22 111...222555345 MAX1329 toc23 2.504 1.252 TA = -40°C V (V)REFADC222...455900802 BA DC V (V)REFADC111...222455901 TA = +25°C E 2.496 1.248 2.494 F 1.247 TA = +85°C 2.492 1.246 2.490 1.245 -100 0 100 200 300 400 500 2.5 3.0 3.5 4.0 4.5 5.0 5.5 IREFADC (µA) AVDD SUPPLY VOLTAGE (V) A: TA = -40°C, AVDD = 5V, DVDD = 3V D: TA = +25°C, AVDD = 3V, DVDD = 2V B: TA = -40°C, AVDD = 3V, DVDD = 2V E: TA = +85°C, AVDD = 5V, DVDD = 3V C: TA = +25°C, AVDD = 5V, DVDD = 3V F: TA = +85°C, AVDD = 3V, DVDD = 2V ______________________________________________________________________________________ 15

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Characteristics (continued) 3 (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) 3 1 ADC REFERENCE VOLTAGE (2.048V) ADC REFERENCE VOLTAGE (2.5V) ADC REFERENCE LINE TRANSIENT X vs. ANALOG SUPPLY VOLTAGE vs. ANALOG SUPPLY VOLTAGE (VADCREF = +1.25V) MA 2222....000055552345 MAX1329 toc24 222...555001680 MAX1329 toc25 MAX1329 toc26 / 2.051 2.504 500mV/div 29 (V)C22..004590 TA = -40°C (V)C2.502 TA = -40°C AVDD 3V 13 VREFAD222...000444678 TA = +25°C VREFAD22..459080 TA = +25°C VADCREF 1.1205mVV/div 2.045 2.496 X A 22..004434 TA = +85°C 2.494 TA = +85°C 2.492 2.042 M 2.041 2.490 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1ms/div AVDD SUPPLY VOLTAGE (V) AVDD SUPPLY VOLTAGE (V) ADC REFERENCE LINE TRANSIENT ADC REFERENCE LINE TRANSIENT (VADCREF = +2.048V) (VADCREF = +2.5V) MAX1329 toc27 MAX1329 toc28 500mV/div 500mV/div AVDD 3V AVDD 3V 10mV/div 10mV/div VADCREF 2.048V VADCREF 2.5V 1ms/div 1ms/div ADC REFERENCE LINE TRANSIENT ADC REFERENCE LINE TRANSIENT (VADCREF = +1.25V) (VADCREF = +2.048V) MAX1329 toc29 MAX1329 toc30 500mV/div 500mV/div AVDD 5V AVDD 5V 20mV/div 20mV/div VADCREF 1.25V VADCREF 2.048V 1ms/div 1ms/div 16 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Typical Operating Characteristics (continued) M (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) A X ADC REFERENCE LINE TRANSIENT ADC REFERENCE SUPPLY CURRENT ADC REFERENCE TURN-ON TIME 1 (VADCREF = +2.5V) vs. ANALOG SUPPLY VOLTAGE vs. ANALOG SUPPLY VOLTAGE MAX1329 toc31 444456 MAX1329 toc32 180 MAX1329 toc33 329 AVDD 5V500mV/div A)µ 444 2.5V ME (ms) 6 2.5V /M 20mV/div (DD 443 N TI 2.048V A VADCREF 2.5V IAV 2.048V RN-O 4 X 442 U T 1 1.25V 441 2 1.25V 3 3 440 0 0 1ms/div 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 AVDD SUPPLY VOLTAGE (V) AVDD SUPPLY VOLTAGE (V) DAC INTEGRAL NONLINEARITY DAC INTEGRAL NONLINEARITY DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE (AVDD = 3V) vs. DIGITAL INPUT CODE (AVDD = 5V) vs. DIGITAL INPUT CODE (AVDD = 3V) 21..05 VREFDAC = 2.5V MAX1329 toc34 21..05 VREFDAC = 2.5V MAX1329 toc35 21..05 VREFDAC = 2.5V MAX1329 toc36 1.0 1.0 1.0 0.5 0.5 0.5 INL (LSB) 0 INL (LSB) 0 DNL (LSB) 0 -0.5 -0.5 -0.5 -1.0 -1.0 -1.0 -1.5 -1.5 -1.5 -2.0 -2.0 -2.0 0 500 1000 1500 20002500 300035004000 0 500 1000 1500 20002500 300035004000 0 500 1000 1500 20002500 300035004000 DIGITAL INPUT CODE DIGITAL INPUT CODE DIGITAL INPUT CODE DAC DIFFERENTIAL NONLINEARITY DAC SUPPLY CURRENT DAC OFFSET VOLTAGE vs. DIGITAL INPUT CODE (AVDD = 5V) vs. ANALOG SUPPLY VOLTAGE vs. TEMPERATURE 21..05 VREFDAC = 2.5V MAX1329 toc37 778050 MAX1329 toc38 22..4600 AVDD = 5.5V MAX1329 toc39 1.0 65 2.20 DNL (LSB)-00..055 I (A)µAVDD 556050 VREFDAC = 2.5V, DACB OFFSET (mV)21..0800 45 1.60 -1.0 40 VREFDAC = 2.5V, DACA AVDD = 2.7V -1.5 35 1.40 -2.0 30 1.20 0 500 1000 1500 20002500300035004000 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 DIGITAL INPUT CODE AVDD (V) TEMPERATURE (°C) ______________________________________________________________________________________ 17

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Characteristics (continued) 3 (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) 3 1 DAC GAIN ERROR DAC SLEW RATE/CROSSTALK TRANSIENT DAC SLEW RATE/CROSSTALK TRANSIENT X vs. TEMPERATURE RESPONSE (VREFDAC = +1.25V) RESPONSE (VREFDAC = +2.048V) MA --00..882050 MAX1329 toc40 AVDD = +5.0V MAX1329 toc41 1.25V AVDD = +5.0V MAX1329 toc42 2.048V 9/ -0.850 AVDD = 2.7V VOUTA 1V/div VOUTA 1V/div 2 %)-0.875 3 ROR (-0.900 1 ER-0.925 VOUTB 1mV/div VOUTB 1mV/div AVDD = 5.5V X -0.950 A -0.975 M -1.000 -40 -15 10 35 60 85 4µs/div 4µs/div TEMPERATURE (°C) DAC SLEW RATE/CROSSTALK TRANSIENT DAC DIGITAL FEEDTHROUGH TRANSIENT RESPONSE (VREFDAC = +2.5V) RESPONSE (VREFDAC = +2.50V) MAX1329 toc43 MAX1329 toc44 2.5V AVDD = +5.0V 1V/div VOUTA 0V VSCLK 2V/div VOUTB 1mV/div VOUTA 20mV/div AVDD = +5.0V 4µs/div 200ns/div OP-AMP INPUT OFFSET VOLTAGE OP-AMP INPUT OFFSET VOLTAGE vs. TEMPERATURE vs. COMMON-MODE VOLTAGE 1890 VCM = AVDD/2 MAX1329 toc45 1890 MAX1329 toc46 7 AVDD = 5V 7 AVDD = 5V mV) 6 mV) 6 V (OS 45 V (OS 45 AVDD = 3V 3 AVDD = 3V 3 2 2 1 1 0 0 -40 -15 10 35 60 85 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 TEMPERATURE (°C) VCM (V) 18 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Typical Operating Characteristics (continued) M (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) A X OP-AMP SUPPLY CURRENT OP-AMP PSRR OP-AMP OUTPUT IMPEDANCE vs. ANALOG SUPPLY VOLTAGE vs. FREQUENCY vs. FREQUENCY 1 1990050 MAX1329 toc47 8700 AVDD = 5.0V MAX1329 toc48 544050000 MAX1329 toc49 329 85 60 AVDD = 3.0V )Ω350 /M I (A)µAVDD 778050 PSRR (dB) 50 PEDANCE ( 322050000 A M X 40 I 65 150 1 60 100 30 3 55 50 3 50 20 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.01 0.1 1 10 100 1000 0 1 10 100 1000 0 AVDD (V) FREQUENCY (kHz) FREQUENCY (kHz) OP-AMP MAXIMUM OUTPUT VOLTAGE OP-AMP MAXIMUM OUTPUT VOLTAGE vs. TEMPERATURE vs. TEMPERATURE 4500 RL TO AVDD/2 MAX1329 toc50 112400 RRLL TTOO AAVVDDDD//22 MAX1329 toc51 A 100 AV - V (mA)DDOUT 2300 AC B D AV - V (mA)DDOUT 468000 B CD 10 F 20 E F E 0 0 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) A: = RL = 5kΩ, AVDD = 5V, DVDD = 3V B: = RL = 5kΩ, AVDD = 3V, DVDD = 2V A: = RL = 5kΩ, AVDD = 5V, DVDD = 3V B: = RL = 5kΩ, AVDD = 3V, DVDD = 2V C: = RL = 10kΩ, AVDD = 5V, DVDD = 3V D: = RL = 10kΩ, AVDD = 3V, DVDD = 2V C: = RL = 10kΩ, AVDD = 5V, DVDD = 3V D: = RL = 10kΩ, AVDD = 3V, DVDD = 2V E: = RL = 100kΩ, AVDD = 5V, DVDD = 3V F: = RL = 100kΩ, AVDD = 3V, DVDD = 2V E: = RL = 100kΩ, AVDD = 5V, DVDD = 3V F: = RL = 100kΩ, AVDD = 3V, DVDD = 2V ______________________________________________________________________________________ 19

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Characteristics (continued) 3 (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) 3 1 OP-AMP GAIN AND PHASE ANALOG SWITCH ON-RESISTANCE ANALOG SWITCH ON-RESISTANCE X vs. FREQUENCY vs. COM VOLTAGE (AVDD = 3V) vs. COM VOLTAGE (AVDD = 5V) MA 6300 GAIN CAVL D=D 0 =p F5,V 2, 230VpF MAX1329 toc52 111334050 TA = +25°C TA = +85°C MAX1329 toc53 111250 TA = +25°C TA = +85°C MAX1329 toc54 110 / g) 0 125 1329 AIN/PHASE (dB/de ---369000 PHASE CAVL D=D 0 CA=p VFL3 D=VD 0 =p F5V R ()ΩON 111112050 R ()ΩON 11900505 G 105 X -120 AVDD = 3V 90 A -150 CL = 220pF CAVL D=D 2 =2 03pVF 19050 TA = -40°C 85 TA = -40°C M -180 90 80 0.1 1 10 100 1000 0 0.5 1.0 1.5 2.0 2.5 3.0 1 2 3 4 5 6 FREQUENCY (kHz) COM VOLTAGE (V) COM VOLTAGE (V) ANALOG SWITCH TURN-ON/-OFF TIME ANALOG SWITCH TURN-ON/-OFF TIME ANALOG SWITCH LEAKAGE CURRENT vs. ANALOG SUPPLY VOLTAGE vs. TEMPERATURE vs. TEMPERATURE 6700 RL = 1kΩ tON, DVDD = 3VtON, DVDD = 2V MAX1329 toc55 7800 RL = 1kΩ tON, AVDD = 3V MAX1329 toc56 112680000 MAX1329 toc57 60 50 tON, AVDD = 5V 140 t/t(ns)ONOFF 3400 tOFF, DVDD = 2V tt (ns)ON/OFF 345000 tOFF, AVDD = 3V I (pA)LEAKAGE 11802000 OFF LEAKAGE 20 60 20 40 10 tOFF, DVDD = 3V 10 tOFF, AVDD = 5V 20 ON LEAKAGE 0 0 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 85 -40 -15 10 35 60 85 AVDD (V) TEMPERATURE (°C) TEMPERATURE (°C) ANALOG SWITCH ON-RESPONSE ANALOG SWITCH CROSSTALK AND OFF ANALOG SWITCH CROSSTALK AND OFF vs. FREQUENCY ISOLATION vs. FREQUENCY (AVDD = 3V) ISOLATION vs. FREQUENCY (AVDD = 5V) -40 -40 42 AVDD = 5V MAX1329 toc58 --5600 MAX1329 toc59 --5600 MAX1329 toc60 GAIN (dB) --204 AVDD = 3V OFF ISOLATION (dB)-1---89070000 OFF ISOLATION OFF ISOLATION (dB)-1---08970000 OFF ISOLATION -6 CROSSTALK -110 -110 CROSSTALK -8 -120 -120 -10 -130 -130 0 0.1 1 10 100 0.1 1 10 100 1000 10,000 0.1 1 10 100 1000 10,000 FREQUENCY (kHz) FREQUENCY (kHz) FREQUENCY (kHz) 20 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Typical Operating Characteristics (continued) M (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) A X TEMPERATURE-SENSOR ACCURACY TEMPERATURE-SENSOR THERMAL INTERNAL TEMPERATURE-SENSOR SUPPLY vs. TEMPERATURE STEP RESPONSE (+25°C TO +85°C) CURRENT vs. SUPPLY VOLTAGE 1 11..05 MAX1329 toc61 18000 τ = 11s MAX1329 toc62 111250 ICANDLTKCEI ROCN L=AO 3LC. 62K8. 5D6V4IV MR =EH F1zERENCE MAX1329 toc63 329 110 CONVERSION RATE = 4ksps ERROR (C)° 0.05 INTERNAL MPERATURE (C)° 6400 I (A)µAVDD 11900505 /MAX -0.5 TE EXTERNAL 90 1 20 -1.0 85 3 3 -1.5 0 80 -40 -15 10 35 60 85 -5 15 35 55 75 95 115 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 TEMPERATURE (°C) TIME (s) AVDD (V) CHARGE-PUMP EFFICIENCY CHARGE-PUMP EFFICIENCY CHARGE-PUMP EFFICIENCY vs. OUTPUT CURRENT (AVDD = 3V) vs. OUTPUT CURRENT (AVDD = 4V) vs. OUTPUT CURRENT (AVDD = 5V) 1890000 DDVVDDDD == 21..08VV MAX1329 toc64 1890000 DVDD D= V2D.2DV = 2.5V MAX1329 toc65 1890000 DVDD = 2.7VDVDDD =V3D.0DV = 3.3V MAX1329 toc66 %) 70 DVDD = 2.5V %) 70 DVDD = 3.0V %) 70 CIENCY ( 5600 DVDD = 3.0V CIENCY ( 5600 DVDD = 3.6V CIENCY ( 5600 DVDD = 3.6V EFFI 40 EFFI 40 EFFI 40 30 30 30 20 20 20 10 10 10 0 0 0 0 5 10 15 20 25 0 5 10 15 20 25 0 5 10 15 20 25 IOUT (mA) IOUT (mA) IOUT (mA) CHARGE-PUMP OUTPUT VOLTAGE CHARGE-PUMP OUTPUT VOLTAGE vs. OUTPUT CURRENT (AVDD = 3V) vs. OUTPUT CURRENT (AVDD = 4V) 33..12 DVDD = 3.0V MAX1329 toc67 44..12 DVDD = 3.6V MAX1329 toc68 3.0 4.0 DVDD = 2.5V DVDD = 3.0V V) 2.9 V) 3.9 AV (DD 2.8 DVDD = 2.0V AV (DD 3.8 2.7 3.7 DVDD = 2.5V 2.6 DVDD = 1.8V 3.6 DVDD = 2.2V 2.5 3.5 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 IOUT (mA) IOUT (mA) ______________________________________________________________________________________ 21

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Characteristics (continued) 3 (AVDD= 5.0V, VREFADC= VREFDAC= 2.5V for DVDD= 3.0V; TA= +25°C, unless otherwise noted.) 3 1 CHARGE-PUMP OUTPUT VOLTAGE CHARGE-PUMP RIPPLE (IOUT = 5mA, CHARGE-PUMP LOAD TRANSIENT X vs. OUTPUT CURRENT (AVDD = 5V) DVDD = 2V, CHARGE-PUMP CLOCK = 78kHz) RESPONSE FOR 0.1mA TO 1.0mA LOAD 5.2 MAX1329 toc70 MAX1329 toc71 MA 5.1 DVDD = 3.6V MAX1329 toc69 AVDD = +3.0V, DVDD = +2.0V AVDD = +3.0V, DVDD = +2.0V / 5.0 9 2mV/div 2 (V)DD 4.9 DVDD = 3.3V AVDD 3 AV 4.8 DVDD = 3.0V AVDD 1 4.7 1mA X 1mV/div A 4.6 DVDD = 2.7V IAVDD 0 M 4.5 0 5 10 15 20 25 30 35 40 45 50 4µs/div 1ms/div IOUT (mA) CHARGE-PUMP LINE TRANSIENT RESPONSE CHARGE-PUMP SUPPLY CURRENT FOR +2.0V TO +2.5V STEP INPUT vs. SUPPLY VOLTAGE DVDD AVDD = +3.0V, 3.0kΩ LOAD MAX1329 toc72 2.5V 334860000 AVDD = 5V MAX1329 toc73 500mV/div 340 2V A) 320 (µD 300 AVDD = 4.0V D IDV 280 AVDD 100mV/div 260 AVDD = 3.0V 240 220 200 2ms/div 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 DVDD (V) 22 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Pin Description M A PIN NAME FUNCTION X MAX1329 MAX1330 1 1 DPIO1 Digital Programmable Input/Output 1 1 2 2 DPIO2 Digital Programmable Input/Output 2 3 3 3 DPIO3 Digital Programmable Input/Output 3 2 9 4 4 DPIO4 Digital Programmable Input/Output 4 / Serial-Data Output. DOUT outputs serial data from the data register. DOUT changes on the M 5 5 DOUT falling edge of SCLK and is valid on the rising edge of SCLK. When CS is high, DOUT is high impedance, unless APIO1 is programmed for SPI mode. A Serial-Clock Input. Apply an external serial clock to transfer data to and from the device. X 6 6 SCLK When CS is high, SCLK is inactive unless APIO3 is configured for SPI mode. Then the input 1 on SCLK is level-shifted and output at APIO3. 3 Serial-Data Input. Data on DIN is clocked in on the rising edge of SCLK when CS is low. 3 7 7 DIN When CS is high, DIN is inactive unless APIO2 is configured for SPI mode. Then the input on DIN is level-shifted and output at APIO2. 0 Active-Low Chip-Select Input. Drive CS low to transfer data to and from the device. When 8 8 CS CS is high and APIO4 is configured for SPI mode, APIO4 is low. Open-Drain Reset Output 1. RST1 remains low while DVDD is below 1.8V. RST1 can be 9 9 RST1 reprogrammed as a push-pull, active-high, or active-low Status register interrupt output. Open-Drain Reset Output 2. RST2 remains low while DVDD is below 2.7V. RST2 can be 10 10 RST2 reprogrammed as a push-pull, active-high, or active-low Status register interrupt output. 11 11 APIO1 Analog Programmable Input/Output 1 12 12 APIO2 Analog Programmable Input/Output 2 13 13 APIO3 Analog Programmable Input/Output 3 14 14 APIO4 Analog Programmable Input/Output 4 15 15 SNO1 Analog Switch 1 Normally-Open Terminal 16 16 SCM1 Analog Switch 1 Common Terminal 17 17 SNC1 Analog Switch 1 Normally-Closed Terminal 18 18 IN1+ Operational Amplifier 1 Noninverting Input 19 19 IN1- Operational Amplifier 1 Inverting Input. Also internally connected to ADC mux. 20 20 OUT1 Operational Amplifier 1 Output. Also internally connected to ADC mux. 21 — N.C. No Connection. Not internally connected. 22 — FBB DACB Force-Sense Feedback Input. Also internally connected to ADC mux. 23 — OUTB DACB Force-Sense Output. Also internally connected to ADC mux. — 21 IN2+ Operational Amplifier 2 Noninverting Input — 22 IN2- Operational Amplifier 2 Inverting Input. Also internally connected to ADC mux. — 23 OUT2 Operational Amplifier 2 Output. Also internally connected to ADC mux. ______________________________________________________________________________________ 23

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Pin Description (continued) 3 3 PIN NAME FUNCTION 1 MAX1329 MAX1330 X 24 24 OUTA DACA Force-Sense Output. Also internally connected to ADC mux. A 25 25 FBA DACA Force-Sense Feedback Input. Also internally connected to ADC mux. DAC Internal Reference Buffer Output/DAC External Reference Input. In internal reference M mode, REFDAC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In 26 26 REFDAC / external DAC reference buffer mode, disable internal reference buffer. Bypass REFDAC to 9 AGND with a 1µF capacitor. 2 27 27 SNC2 Analog Switch 2 Normally-Closed Terminal 3 28 28 SCM2 Analog Switch 2 Common Terminal 1 29 29 SNO2 Analog Switch 2 Normally-Open Terminal X 30 30 AIN2 Analog Input 2. Also internally connected to ADC mux. A 31 31 AIN1 Analog Input 1. Also internally connected to ADC mux. M ADC Internal Reference Buffer Output/ADC External Reference Input. In internal reference mode, REFADC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In 32 32 REFADC external ADC reference buffer mode, disable internal reference buffer. Bypass REFADC to AGND with a 1µF capacitor. Internal Reference Output/Reference Buffer Amplifiers Input. In internal reference mode, 33 33 REFADJ bypass REFADJ to AGND with a 0.01µF capacitor. In external reference mode, disable internal reference. 34 34 AGND Analog Ground Analog Supply Input. Bypass AVDD to AGND with at least a 0.01µF capacitor. With the 35 35 AVDD charge pump enabled, see Table 32 for required capacitor values. Charge-Pump Capacitor Input B. Connect CFLY across C1A and C1B. See Table 32 for 36 36 C1B required capacitor values. Charge-Pump Capacitor Input A. Connect CFLY across C1A and C1B. See Table 32 for 37 37 C1A required capacitor values. Digital Supply Input. Bypass DVDD to DGND with at least a 0.01µF capacitor. When using 38 38 DVDD charge pump, see Table 32 for required capacitor values. 39 39 DGND Digital Ground Clock Input/Output. In internal clock mode, enable CLKIO output for external use. In 40 40 CLKIO external clock mode, apply a clock signal at CLKIO for the ADC and charge pump. Exposed Pad. The exposed pad is located on the package bottom and is internally — — EP connected to AGND. Connect EP to the analog ground plane. Do not route any PCB traces under the package. 24 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M CS A X tCSH tCYC tCH tCSH tCSS 1 tCL SCLK 3 2 tDS tDH 9 DIN / M tDV tDO tTR A X DOUT 1 3 Figure 1. Detailed Serial-Interface Timing Diagram 3 0 Detailed Description DVDD The MAX1329/MAX1330 smart DASs are based on a 312ksps, 12-bit SAR ADC with a 1ksps, 16-bit DSP 3kΩ mode. The ADC includes a differential multiplexer, a pro- grammable gain amplifier (PGA) with gains of 1, 2, 4, DOUT DOUT and 8, a 20-bit accumulator, internal dither, a 16-word FIFO, and an alarm register. The MAX1329/MAX1330 3kΩ CLOAD = 20pF CLOAD = 20pF operate with a digital supply down to 1.8V and feature an internal charge pump to boost the supply voltage for the analog circuitry that requires 2.7V to 5.5V. a) FOR ENABLE, HIGH IMPEDANCE b) FOR ENABLE, HIGH IMPEDANCE The MAX1329/MAX1330 include an internal reference TO VOH AND VOL TO VOH. TO VOL AND VOH TO VOL. with programmable buffer for the ADC, two analog exter- FOR DISABLE, VOH TO HIGH IMPEDANCE. FOR DISABLE, VOL TO HIGH IMPEDANCE. nal inputs as well as inputs from other internal circuitry, Figure 2. DOUT Enable and Disable Time Load Circuits an internal/external temperature sensor, internal oscilla- tor, dual single-pole, double-throw (SPDT) switches, four Register Bit Descriptionssection for the default values digital programmable I/Os, four analog programmable after a power-on reset. I/Os, and dual programmable voltage monitors. Power-On Setup The MAX1329 features dual 12-bit force-sense DACs with programmable reference buffer and one opera- After applying power to AVDD: tional amplifier. The MAX1330 includes one 12-bit force- 1) Write to the Reset register. This initializes the tem- sense DAC with programmable reference buffer and perature sensor and voltage reference trim logic. dual op amps. DACA can be sequenced with a 16-word 2) Within 3ms following the reset, configure the charge FIFO. The DAC buffers and op amps have internal ana- pump as desired by writing to the CP/VM Control log switches between the output and the inverting input. register. The details of programming the charge Power-On Reset pump are described in the Charge Pumpsection. After a power-on reset, the DVDD voltage supervisor is Charge Pump enabled with thresholds at 1.8V and 2.7V. All digital Power AVDD and DVDD by any one of the following and analog programmable I/Os (DPIOs and APIOs) are ways: drive AVDD and DVDD with a single external configured as inputs with pullups enabled. The internal power supply, drive AVDD and DVDD with separate oscillator is enabled and is output at CLKIO once the external power supplies, or drive DVDDwith an external 1.8V reset trip threshold has been exceeded and the supply and enable the internal charge pump to gener- subsequent timeout period has expired. See the ate AVDDor short DVDDto AVDDinternally. ______________________________________________________________________________________ 25

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 DPIO configured as SLPor SHDNinputs. In normal mode, 3 each analog and digital block can be powered up or shut 3 OISNCTIELRLNATAOLR CLOCK OUTPUT down individually through its respective control register. 1 4(.O91F5F,2 OMNH)z (OFDF,I V/1ID, /E2R, /4) CLKIO Voltage Supervisors X OSCE = 1 The MAX1329/MAX1330 provide two programmable volt- A age supervisors, one for DVDD and one for AVDD. The DVDDvoltage supervisor has two thresholds (set to 1.8V M CLOCK INPUT DIVIDER and 2.7V by default) that are both enabled after a power- (OFF, /1, /2, /4) on reset. On initial power-up, RST1 is assigned the 1.8V / 9 OSCE = 0 monitor output and RST2 is assigned the 2.7V monitor 2 output, both for DVDD. If DVDD falls below the 1.8V or 13 OSCE 1 MUX 0 2th.7eV S ttharteussh oreldg,i sthteer VisM 1seAt .b Tit hoer VVMM11BA baitn, dre VspMe1cBti vsetlayt,u ins bits can also be mapped to the interrupt generator. X CHARGE-PUMP CHARGE PUMP The default states of RST1 and RST2 are open-drain CLOCK DIVIDER A (/32, /64, /128, /256) (OFF, 3V, 4V, 5V) outputs but can be programmed as push-pull Status register interrupts through the CP/VM Control register. M The AVDD voltage supervisor provides three program- ADC CLOCK DIVIDER ADC mable thresholds. If AVDD falls below the programmed (/1, /2, /4, /8) (ACQUIRE CLKS) threshold, the VM2 bit is set in the Status register. The MUX (ADC CONTROL) VM2 status bit can also be mapped to the interrupt (ADC SETUP) generator. SCLK Interrupt Generator The interrupt generator accepts inputs from other internal Figure 3. Clock-Divider Block Diagram circuits to provide an interrupt to an external microcontroller (µC). The sources for generating an interrupt are program- Upon a power-on reset, the charge pump is disabled. mable through the serial interface. Possible sources Enable the charge pump through the CP/VM Control include a rising or falling edge on the digital and analog register. When the charge pump is in its off state, AVDD programmable inputs, ADC alarms, an ADC conversion is isolated from DVDD unless the bypass switch is complete, an ADC FIFO full, an ADC accumulator full, and enabled. To bypass the charge pump and directly con- the voltage-supervisor outputs. The interrupt causes RST1 nect DVDD to AVDD, enable (close) the bypass switch and/or RST2to assert when configured as an interrupt out- through the CP/VM Control register (see Tables 21 and put. The interrupt remains asserted until the Status register 22). During the on mode, the charge pump boosts is read. See the CP/VM Control register for programming DVDD and regulates the voltage to generate the select- the RST1and RST2 outputs as interrupts and the Interrupt ed output voltage at AVDD. The charge-pump output Mask register for programming the interrupt sources. voltage selections are 3.0V, 4.0V, or 5.0V. The charge-pump clock and ADC clock are synchro- Internal Oscillator and Programmable nized from the same master clock. The charge pump Clock Dividers uses a pulse-width-modulation (PWM) scheme to regu- The MAX1329/MAX1330 feature an internal oscillator, late the output voltage. The charge pump supports a which operates at a fixed frequency of 3.6864MHz. When maximum load of 25mA of current to an external device enabled, the internal oscillator provides the master clock including what is required for internal circuitry. source for the ADC and charge pump. To allow external devices to use the internally generated clock, configure Power Modes CLKIO as an output through the Clock Control register. Three power modes are available for the MAX1329/ The CLKIO output frequency is configurable for MAX1330: shutdown, sleep, and normal operation. In shut- 0.9216MHz, 1.8432MHz, and 3.6864MHz. When the inter- down mode, all functional blocks are powered down except nal oscillator is enabled, and regardless of the CLKIO out- the serial interface, data registers, and wake-up circuitry (if put frequency, the ADC and charge-pump clock dividers enabled). Sleep mode is identical to shutdown mode always receive a 3.6864MHz clock signal (see Figure 3). except the DVDD voltage monitors (if enabled) remain After a power-on reset, CLKIO defaults to an output with active. Global sleep or shutdown mode is initiated through a the divider set to 2 (resulting in 1.8432MHz). 26 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor For external clock mode, disable the internal oscillator, Table 1. Temperature vs. ADC Output M which then configures CLKIO as an input. Apply an external clock at CLKIO with a frequency up to 20MHz. TEMPERATURE ADC OUTPUT DATA A The input clock divider can be set to 1, 2, or 4. The out- (°C) TWO’S COMPLEMENT HEX X put of the CLKIO input divider goes to the input of +85.000 0010 1010 1000 2A8 1 charge pump and ADC clock dividers. +70.000 0010 0011 0000 230 3 Note:When using the internally generated clock, enter- +25.000 0000 1100 1000 0C8 2 ing shutdown or sleep mode causes CLKIO to become an input. To prevent crowbar current, connect a 500kΩ +0.250 0000 0000 0010 002 9 resistor from CLKIO to DGND. +0.125 0000 0000 0001 001 / M Digital and Analog Programmable I/Os 0 0000 0000 0000 000 A The MAX1329/MAX1330 provide four digital programma- -0.125 1111 1111 1111 FFF ble I/Os (DPIO1–DPIO4) and four analog programmable -0.250 1111 1111 1110 FFE X I/Os (APIO1–APIO4). The DPIOs and APIOs can be con- -25.000 1111 0011 1000 F38 1 figured as logic inputs or outputs through the DPIO and -40.000 1110 1100 0000 EC0 3 APIO Control registers. The DPIOs are powered by 3 DVDD. Likewise, the APIOs are powered by AVDD. When where ADC output data is the decimal value of the configured as inputs, internal pullups can be enabled 0 two’s complement result. through the DPIO and APIO Setup registers. The MAX1329/MAX1330 support external single-ended Digital Programmable I/O and differential temperature measurements using a diode DPIO1–DPIO4 are powered by DVDDand are program- connected transistor between AIN1 and AGND, AIN2 and mable as the following: AGND, or AIN1 and AIN2. Select the appropriate channel • General-purpose input for conversion through the ADC Setup register. • Wake-up input (internal oscillator enable) Voltage References • Power-down mode (sleep or shutdown) control input The internal unbuffered 2.5V reference is externally accessible at REFADJ. Separate ADC and DAC refer- • DAC loading or sequencing input ence buffers are programmable to output 1.25V, 2.048V, • ADC acquisition and conversion control input or 2.5V REFADC and REFDAC. The reference and • DAC, op amp, and SPDT switch control input buffers can be individually controlled through the ADC • ADC data-ready output Control and DAC Control registers. Power down the internal reference to apply an external reference at • General-purpose output REFADJ as an input to the ADC and DAC reference Analog Programmable I/O buffers. Power down the reference buffers to apply exter- APIO1–APIO4 are powered by AVDD and are program- nal references directly at REFADC and REFDAC. mable as the following: Note: All temperature sensor measurements use the • General-purpose input voltage at REFADJ as a reference and require a 2.5V ref- • Wake-up input (internal oscillator enable) erence for accurate results. • General-purpose output Operational Amplifiers • Digital input/output for signals to be level-shifted The MAX1329 includes one uncommitted operational from/to the SPI interface amplifier. The MAX1330 includes two op amps. These op amps feature rail-to-rail inputs and outputs, with a Temperature Sensor bandwidth of 1MHz. The op amps are powered down An internal temperature sensor measures the device through the DAC Control register. An internal analog temperature of the MAX1329/MAX1330. The ADC con- switch shorts the negative input to the output when verts the analog measurement from the internal temper- enabled through the Switch Control register or a DPIO ature sensor to a digital output (see Table 1). The configured as a switch control input. When powered temperature measurement resolution is +0.125°C for down, the outputs of the op amps go high impedance. each LSB and the measured temperature can be calcu- lated using the following equation: T = ADC output data/8°C ______________________________________________________________________________________ 27

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Single-Pole/Double-Throw (SPDT) Switches 3 The MAX1329/MAX1330 provide two uncommitted SPDT ADC FIFO 3 switches that can also be configured as a double- WRITE POINTER 0 READ POINTER pole/single-throw (DPST) switch (see Tables 28 and 29). 1 1 X Each switch has a typical on-resistance of 115Ωat AVDD 2 = 3V. The switch is controlled through the Switch Control 3 A register or a DPIO configured to control the switches. 4 M Analog-to-Digital Converter (ADC) 5 The MAX1329/MAX1330 include a 12-bit SAR ADC with 6 INTERRUPT POINTER / 9 a programmable-gain amplifier (PGA), input multiplex- 7 2 er, and digital post-processing. The analog input signal DEPTH POINTER 8 3 feeds into the differential input multiplexer and then into 9 1 the PGA with gain settings of 1, 2, 4, or 8. The tempera- 10 ture sensor and supply voltage measurements bypass 11 X the PGA. Both unipolar and bipolar transfer functions 12 A are selectable. 13 M The ADC done status bit (ADD in the Status register) 14 can be programmed to provide an interrupt. Any of the 15 DPIOs can be configured as a CONVST input to directly control the acquisition time and synchronize the conver- Figure 4. ADC FIFO sions. A 16-word FIFO stores the ADC results until the 12-bit data is read by the external µC. Every time a conversion completes, the data is written to Analog Inputs the present location of the write pointer, which then incre- The MAX1329/MAX1330 provide two external analog ments by 1. The write pointer continues to increment until inputs: AIN1 and AIN2. The inputs are rail-to-rail and the depth pointer location has been written. The write can be used differentially or single-ended to ground. pointer then moves to location 0 and continues to incre- The analog inputs can also be used for remote temper- ment but must remain behind the read pointer. Once the ature sensing with external diodes. last valid FIFO location has been written, no further ADC results are written to the FIFO until the next FIFO location AIN1 and AIN2 feed directly into a differential multiplexer. is cleared by a read. This 16-channel multiplexer is segmented into an upper and a lower multiplexer (see Tables 7 and 8 for configu- When the ADC FIFO is enabled, the read pointer points ration). to location 0. When a read occurs, the pointer then increments by 1 only if 15 of the 16 bits are clocked out ADC FIFO Register successfully. Reading the FIFO is done in 16-bit words The ADC writes its results in the ADC FIFO, which stores consecutively as long as a serial clock is present. The up to sixteen 16-bit words. Each 16-bit word in the FIFO read pointer must stay one location behind the write includes a 4-bit FIFO address and the 12-bit data result pointer. When the write pointer is one location ahead of from the ADC. The ADC FIFO includes four pointers: the read pointer and the read continues, it clocks out depth, interrupt, write, and read configured by writing to the current read location over and over again until the the ADC FIFO register (see Figure 4). write pointer increments. A depth pointer sets the working depth of the FIFO such The FIFO can be accessed simultaneously by the serial that locations beyond the depth pointer are inaccessible interface to read a result and by the ADC to write a for writing or reading. The interrupt pointer sets the loca- result, but the read and write pointers are never at the tion that causes an interrupt every time data has been same address. written to that location. Set the interrupt pointer to the same or lower location than the depth pointer. The inter- ADC Accumulator, Decimation, and Dither Mode rupt pointer is set equal to the depth pointer if written The accumulator is used for oversampling. In this mode, with a value greater than the depth pointer. A write to the up to 256 samples are accumulated in the ADC ADC FIFO register causes the write and read pointers to Accumulator register. This is a 24-bit read register with reset to location 0. Setting the depth pointer to location 0 1 bit for dither enable, 3 bits for the accumulator count, disables the FIFO. and 20 bits for the accumulated ADC conversions. The 28 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M VREFADC/GAIN (2V RxE GFAADINC) (2V RxE GFAADINC) A 1111 1111 1111 FULL-SCALE TRANSITION 0111 1111 1111 X 1111 1111 1110 0111 1111 1110 1 ARY OUTPUT CODE11111111 11111111 11110010 1 LSB =(GAVIRNE FxA 4D0C96) V/GAINREFADC MPLEMENT OUTPUT CODE0001001110010011 0011100100110011 1001001100011011 1 LSB = (GAVINRE xFA 4D0C96) VREFADC(2 x GAIN) 329/MA BIN00000000 00000000 00001101 TWO'S CO1000 0000 0010 VREFADC(2 x GAIN) X1 0000 0000 0001 1000 0000 0001 3 0000 0000 0000 1000 0000 0000 3 0 1 2 3 4093 4095 -2048 -2046 -1 0 +1 +2045 +2047 0 INPUT VOLTAGE (LSB) INPUT VOLTAGE (LSB) Figure 5. Unipolar Transfer Function Figure 6. Bipolar Transfer Function accumulator is functional for the normal, fast power- format is binary for unipolar mode and two’s comple- down, and burst modes, but cannot be used for ment for bipolar mode. Calculate 1 LSB using the temperature-sensor conversions. following equation: The 20-bit binary accumulator provides up to 256 times 1 LSB = VREFADC/(gain x 4096) oversampling and binary digital filtering. The digital filter for both unipolar and bipolar modes, has a sinc response and the notch locations are deter- mined by the sampling rate and the oversampling ratio where VREFADC is the reference voltage at REFADC and gain is the PGA gain. In unipolar mode, the output (see the Applying a Digital Filter to ADC Data Using the code ranges from 0 to 4095 for inputs from zero to full- 20-Bit Accumulatorsection). There is a digital-signal- scale. In bipolar mode, the output code ranges from processing mode where dither is added to the over- -2048 to +2047 for inputs from negative full-scale to sampling to extend the resolution from 12 to 16 bits. In positive full-scale. this mode, a sample rate of 1220sps can be main- tained. The oversampling rate (OSR) required to Digital-to-Analog Converter (DAC) achieve an increase in resolution is OSR = 22N, where The MAX1329 includes two 12-bit DACs (DACA and N is the additional bits of resolution. See the ADC DACB) and the MAX1330 includes one 12-bit DAC Accumulator Registersection. (DACA). The DACs feature force-sense outputs and DACA includes a 16-word FIFO. Each DAC is double- ADC Alarm Mode buffered with an input and output register (see Figure 7). The ADC Greater-Than (GT) and Less-Than (LT) Alarm The DACA(B)PD<1:0> bits in the DAC Control register registers can be used to generate an interrupt once the control the power and write modes for DACA and DACB. ADC result exceeds the alarm register value. The alarm registers also control the number of alarm trips required With the DAC(s) powered-up, the three possible com- and whether or not they need to be consecutive to gen- mands are a write to both the input and output registers, erate an interrupt. The GT and LT alarms are pro- a write to the input register only, or a shift of data from grammed through the ADC GT and LT Alarm registers. the input register to the output register. With the DAC(s) The alarms are functional for the normal, fast power- powered-down, only a simultaneous write to both input down, and burst modes. and output registers is possible. DPIO_ can be programmed to shift the input register data to the output ADC Transfer Functions register for each DAC individually or simultaneously Figures 5 and 6 provide the ADC transfer functions for (MAX1329 only). The value in the output register unipolar and bipolar mode. The digital output code ______________________________________________________________________________________ 29

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 3 FROM 3 REFDAC 1 X A FSREORIMAL I/O DRAECG IISNTPEURT DARCEG OISUTTEPRUT 1D2-ABCIT TOOU TDPAUCT BUFFER M / 9 2 3 1 FIFOA 16-WORD DAC DDS CONTROL FOR DACA ONLY X REGISTER FIFO LOGIC A M Figure 7. Detailed DAC and FIFO Block Diagram determines the analog output voltage. An internal switch configures the force-sense output for unity gain config- 16 uration when it is closed. 12 In power-down mode, the DAC outputs and feedback inputs are high impedance. 8 DACA FIFO and Direct PHASE 1 PHASE 2 DAC INPUT REGISTER Digital Synthesis (DDS) Logic TION 4 DAC INPUT VLOALCUAET IMONIN 1U VSA FLIFUOE The DACA FIFO and DDS logic can be used for wave- CA 0 REGISTER VALUE O form synthesis by loading the FIFO and configuring the L PLUS FIFO DDS mode through the FIFOA Control register. The FIFO -4 LOCATION 1 VALUE PHASE 3 PHASE 4 FIFO is sequenced by writing to the FIFO Sequence DAC INPUT register address or by toggling a DPIO configured for -8 REGISTER VALUE this function. DAC INPUT REGISTER -12 The input register value, in conjunction with the FIFOA VALUE MINUS FIFO LOCATION 16 VALUE Data register values, can be used to create waveforms. -16 The FIFOA Data register values are added to or sub- 0 16 32 48 64 tracted from the Input register value before shifting to SEQUENCE NUMBER the output register. The FIFO data is straight binary (0 to +4095) when the bipolar bit (BIPA) is not asserted Figure 8. DAC FIFO Waveform Phases and as sign magnitude (-2047 to +2047) when BIPA is asserted. In sign magnitude mode, the MSB represents ister. For each subsequent sequence, the FIFOA Data the sign bit, where 0 indicates a positive number and 1 register value is added to the input register before shift- indicates a negative number. The 11 LSBs provide the ing to the output register until the programmed FIFO magnitude in sign magnitude. depth has been reached (see Figure 9a). The FIFO The type of waveform generated is determined by the depth (DPTA<3:0>) can be set to any integer value from asymmetric/symmetric mode bit (SYMA), unipolar/bipo- 1 to 16 and the FIFO always starts at location 1. lar mode bit (BIPA), and the single/continuous mode bit Asserting the SYMA bit creates phase two by causing (CONA). All waveforms are generated in phases (see the FIFO to reverse direction at the end of phase 1 with- Figure 8). For all bit combinations, phase 1 is created out repeating the final value before sequencing back to by first shifting the input register value to the output reg- the beginning (see Figure 9c). 30 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M (a) (b) (c) OUTPUT WAVEFORM OUTPUT WAVEFORM OUTPUT WAVEFORM A (UNIPOLAR, ASYMMETRIC, SINGLE) (UNIPOLAR, ASYMMETRIC, CONTINUOUS) (UNIPOLAR, SYMMETRIC, SINGLE) 16 16 16 X 1 3 12 12 12 2 FIFO LOCATION 8 FIFO LOCATION 8 FIFO LOCATION 8 9/M A 4 4 4 X 1 0 0 0 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 3 SEQUENCE NUMBER SEQUENCE NUMBER SEQUENCE NUMBER 3 (d) (e) (f) 0 OUTPUT WAVEFORM OUTPUT WAVEFORM OUTPUT WAVEFORM (UNIPOLAR, SYMMETRIC, CONTINUOUS) (UNIPOLAR, ASYMMETRIC, SINGLE) (BIPOLAR, ASYMMETRIC, CONTINUOUS) 16 16 16 12 12 12 8 8 FIFO LOCATION 8 FIFO LOCATION -440 FIFO LOCATION -440 4 -8 -8 -12 -12 0 -16 -16 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER SEQUENCE NUMBER SEQUENCE NUMBER (g) (h) OUTPUT WAVEFORM OUTPUT WAVEFORM (BIPOLAR, SYMMETRIC, SINGLE) (BIPOLAR, SYMMETRIC, CONTINUOUS) 16 16 12 12 8 8 N N CATIO 4 CATIO 4 O LO 0 O LO 0 FIF -4 FIF -4 -8 -8 -12 -12 -16 -16 0 16 32 48 64 80 96 112 128 0 16 32 48 64 80 96 112 128 SEQUENCE NUMBER SEQUENCE NUMBER Figures 9a–9h. Waveform Examples Using the DAC FIFO ______________________________________________________________________________________ 31

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Table 2. Direct-Mode Definitions 3 3 COMMAND NAME START CONTROL 1 ADC Convert 1 MUX<3:0> GAIN<1:0> BIP X DACA Write 0 1 R/W 0 DACA<11:0> A DACB Write 0 1 R/W 1 DACB<11:0> M DATA (D<255:0>, D<23:0>, D<15:0>, or Register Mode* 0 0 R/W ADDRESS (ADR<4:0>) D<7:0>) / 9 *See Table 3. 2 3 Asserting the BIPA bit with SYMA = 1 creates phases falling edge of SCLK. The serial interface is compatible 1 three and four (see Figure 9g). Phases three and four with SPI modes CPOL = 0, CPHA = 0 and CPOL = 1, X repeat the same sequence as in phases one and two, CPHA = 1. A write operation takes effect on the rising respectively, but the FIFO data is subtracted from the edge of SCLK used to shift in the LSB (or last bit of the A input register data this time through. The final value in data word being written). If CS goes high before the M phase two is not repeated before proceeding with complete transfer, the write is ignored. CS must be phase three. The resulting waveform is composed of all forced high between commands. four phases. Direct-Mode Commands Asserting the BIPA bit with SYMA = 0 creates phase The direct-mode commands include the ADC Convert four (see Figure 9e). Phase four repeats the same command and DACA and DACB Read and Write com- sequence as in phase one in reverse order, but the mands. The ADC Convert command is an 8-bit com- FIFO data is subtracted from the input register data. In mand that initiates an ADC conversion, selects the this case, the last location in the FIFO is repeated conversion channel through the multiplexer, sets the before sequencing back to the beginning. PGA gain, and selects bipolar or unipolar mode. If an When the CONA bit is not asserted, the output is static ADC Convert command is issued during a conversion once the end of the programmed pattern has been in progress, the current conversion aborts and a new reached. Asserting the CONA bit causes the patterns one begins. The MUX<3:0>, GAIN<1:0>, and BIP bits described above to repeat without repeating the final settings in the ADC Setup register are overwritten by value (see Figures 9b, 9d, 9f, and 9h). the values in the ADC Convert command. The FIFO Enable bit (FFEA) enables the ability to create The DACA and DACB Data Write commands set the waveforms. The FFEA must be disabled to write to the DACA and DACB input and/or output register values, FIFOA Data register. Any change in the FIFOA Control respectively. The DACA and DACB data write modes register reinitializes the FIFO sequencing logic and the are determined by the DAC Control register. The DACA next sequence loads the input register value. The and DACB data read commands read the DACA and DACA Input and/or Output registers can be written DACB input register data, respectively. directly and not affect the sequencing logic. Writing to In register mode, an address byte identifies each regis- the DACA input register effectively moves the DC offset ter. The data registers are 8, 16, or 24 bits wide. The of the waveform on the next sequence and writing to ADC and DACA FIFO Data registers are variable length the DACA output register immediately changes the out- up to 256 bits wide. Figures 10–17 provide example put level independent of the FIFO. timing diagrams for various commands. Serial Interface ADC Conversion Timing The MAX1329/MAX1330 feature a 4-wire serial interface Configure the ADC Control and Setup registers before consisting of a chip select (CS), serial clock (SCLK), attempting any conversions. Initiate an ADC conver- data in (DIN), and data out (DOUT). CS must be low to sion with the 8-bit ADC Convert command (see Table allow data to be clocked into or out of the shift register. 2) or by toggling a DPIO input configured for an ADC DOUT is high-impedance while CS is high, unless conversion-start function. When a conversion com- APIO1 is programmed for SPI mode. The data is pletes, the result is ready to be read in the data regis- clocked in at DIN into the shift register on the rising ter. In burst mode, the ADC data is delivered real time edge of SCLK. Data is clocked out at DOUT on the on DOUT. 32 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M CS A X SCLK 1 3 2 DIN X 0 0 0 A4 A3 A2 A1 A0 DN-1 DN -2 DN-3 DN-4 D2 D1 D0 X 9 / DOUT M X = DON’T CARE. A X Figure 10. Variable Length Register-Mode Data-Write Operation 1 3 3 CS 0 SCLK DIN X 0 0 1 A4 A3 A2 A1 A0 X X X X X X X X DOUT DN-1 DN-2 DN-3 DN-4 D2 D1 D0 X = DON’T CARE. Figure 11. Variable Length Register-Mode Data-Read Operation CS SCLK DIN X 1 M3 M2 M1 M0 G1 G0 BIP X X 0 0 1 0 0 0 1 0 X X X X X DOUT DN-1 DN-2 D1 D0 X = DON'T CARE. Figure 12. Write Command to Start a Normal or Fast Power-Down ADC Conversion Followed by ADC Data Register Read ______________________________________________________________________________________ 33

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 3 CS 3 1 X SCLK A M DIN X 0 1 0 AB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X / 9 2 DOUT 3 1 X = DON'T CARE. X A Figure 13. Write to DACA (AB = 0) or DACB (AB = 1). The DAC Control register programs the write mode. M CS SCLK DIN X 0 1 1 AB X X X X X X X X X X X X X DOUT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X = DON'T CARE. Figure 14. Read of DACA (AB = 0) or DACB (AB = 1) Input Register RST1/RST2* INTERRUPT ASSERTED REASSERTS IF NEW INTERRUPT OCCURS DURING READ CS SCLK DIN X X X 0 0 1 1 0 1 0 0 X X X X X X X X X X X X X DOUT D23 D22 D1 D0 *RST1 AND RST2 ARE ACTIVE-HIGH (INTP = 1). X = DON'T CARE. Figure 15. Read of Status Register to Clear Asserted Interrupt (RST1/RST2) 34 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M CS A X SCLK 1 3 DIN X 0 1 0 AB D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X 2 9 DAC PREVIOUS OUTPUT NEW OUTPUT / M A DPIO RISING EDGE TRIGGERED X X = DON'T CARE. 1 Figure 16. Write to DACA (AB = 0) or DACB (AB = 1) Input Register Followed by a DPIO DACA or DACB Load 3 3 0 WRITE TO MAX1329/MAX1330 TO CS ENABLE SPI MODE WRITE THROUGH MAX1329/MAX1330 TO NORMAL WRITE TO MAX1329/MAX1330 APIO DEVICE SCLK DIN DN DN-1 DN-2 DN-3 D3 D2 D1 D0 EN EN-1 EN-2 EN-3 X X X X D7 D6 D5 D4 D3 D2 D1 D0 DOUT E3 E2 E1 E0 APIO4 INVERTED CS SET BY APIO CONTROL REGISTER APIO3 SET TO GPO SET BY APIO CONTROL REGISTER APIO2 SET BY APIO CONTROL REGISTER EN EN-1 EN-2 EN-3 X X X X SET TO GPO APIO1 SET BY APIO CONTROL REGISTER E3 E2 E1 E0 SET TO GPI X = DON'T CARE. Figure 17. Write to Program and Use APIO SPI Mode The four conversion modes programmed by the Burst mode is initiated with one ADC convert com- APD<1:0> and AUTO<2:0> bits in the ADC Control mand and continuously converts on the same channel register are: autoconvert, fast power-down, normal, and sending the data directly to DOUT as long as there is burst modes. In normal and fast power-down modes, activity on SCLK and CS is low. Burst mode aborts single conversions are initiated with the ADC convert when CS goes high. In burst mode, SCLK directly command or by toggling a configured DPIO. In fast clocks the ADC. For best performance, synchronize power-down mode, the PGA and ADC power down SCLK with the CLKIO clock (see Figure 18). A mini- between conversions to reduce power. A minimum of mum of 14 clock cycles is required to complete a con- 16 clock cycles is required to complete a conversion in version in burst mode. normal or fast power-down mode. ______________________________________________________________________________________ 35

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 3 CS 3 1 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 X A DIN X 1 M3 M2 M1 M0 G1 G0 BIP X X X X X X X X X X X X X X X X X M DOUT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 / 9 2 ADC MODE TRACK CONVERT TRACK CONVERT 3 1 ADCDONE* X *ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE OF ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. A X = DON'T CARE. M Figure 18. Write Command to Start ADC Burst Conversions Clocked by SCLK with Real-Time Data Read (ACQCK<1:0> = 00, GAIN<1:0> = 00) CS SCLK 1 2 3 4 5 6 7 8 DIN X 1 M3 M2 M1 M0 G1 G0 BIP CLKIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ADC MODE TRACK CONVERT PD* ADCDONE** *PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED-DOWN. **ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. X = DON'T CARE. Figure 19. Write Command to Start ADC Normal or Fast Power-Down, with Autoconvert Disabled (AUTO<2:0> = 000) and Conversions Clocked by CLKIO (OSCE = 0, ADDIV<1:0> = 00, CLKIO<1:0> = 11) 36 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Once configured, autoconvert mode initiates with one When writing to the ADC Control register in fast power- M ADC Convert command. Conversions continue at the down mode with autoconvert disabled, acquisition rate selected by the ADC Autoconvert bits (see Table 4) begins on the 1st rising ADC clock edge after CS tran- A until disabled by writing to the ADC Control register. The sitions high, and ends after the programmed number of X Autoconvert mode can run only in the normal or fast clock cycles. The conversion completes a minimum 14 1 power-down modes. The autoconvert function must be clock cycles after acquisition ends. When autoconvert disabled to use burst mode or DPIO CONVST mode. is enabled, an additional three ADC clock cycles are 3 added prior to acquisition to allow the ADC to wake up. 2 See Figures 19 and 20 for timing diagrams. 9 / M A CS X 1 SCLK 1 2 3 4 5 6 7 8 3 3 DIN X 1 M3 M2 M1 M0 G1 G0 BIP 0 CLKIO 1 2 3 4 5 6 7 8 9 10 11 12 13 18 19 ADC MODE TRACK CONVERT PD* ADCDONE** *PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN. **ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. X = DON'T CARE. Figure 20. Write Command to Start ADC Normal or Fast Power-Down, with Autoconvert Enabled and Conversions Clocked by CLKIO (OSCE = 0, ADDIV<1:0> = 00, CLKIO<1:0> = 11) CLKIO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 ADC MODE TRACK CONVERT TRACK CONVERT DPIO (CONVST) EDGE TRIGGERED PD* ADCDONE** *PD IS AN INTERNAL SIGNAL. WHEN PD IS HIGH, THE ADC IS POWERED DOWN. **ADCDONE IS AN INTERNAL SIGNAL. RISING EDGE ADCDONE SETS THE ADD BIT IN THE STATUS REGISTER. ADDIV = 00. Figure 21. DPIO-Controlled ADC Conversion Start ______________________________________________________________________________________ 37

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 3 3 CS TEMP CONVERT COMMAND THERE ARE TWO ADC CONVERSIONS PER TEMPERATURE CONVERSION. 1 (SCLK, DIN, DOUT NOT SHOWN) X A WAIT PERIOD 1ST AQUISITION 1ST CONVERSION 2ND AQUISITION 2ND CONVERSION M 93.5 CLOCKS 90 CLOCKS 19 CLOCKS 87 CLOCKS 17.5 CLOCKS / 9 2 3 ADC MODE TRACK CONVERT TRACK CONVERT 1 X A 1 CLOCK = 1/(ADC MASTER CLOCK FREQUENCY) M START STOP Figure 22. Temperature-Conversion Timing See Figure 21 for performing an ADC conversion using q = charge of electron = 1.602 ✕10-19coulombs a DPIO input programmed as CONVST. Allow at least k = Boltzman constant = 1.38 ✕ 10-23J/K 600ns for acquisition while the DPIO input is low and the acquisition ends on the rising edge of the DPIO. n = ideality factor (slightly greater than 1) The conversion requires an additional 14 ADC clock The temperature measurement process is fully automat- cycles. If the PGA gain is set to 4 or 8, the minimum ed in the MAX1329/MAX1330. All steps are sequenced acquisition time is 1.2µs due to the increase of the input and executed by the MAX1329/MAX1330 each time an sampling capacitor. input channel (or an input channel pair) configured for temperature measurement is scanned. Temperature Measurement The MAX1329/MAX1330 perform temperature measure- The resulting 12-bit, two’s complement number repre- ment by measuring the voltage across a diode-con- sents the sensor temperature in degrees Celsius, with nected transistor at two different current levels. The 1 LSB = +0.125°C. Figure 22 shows the timing for a following equation illustrates the algorithm used for tem- temperature measurement. perature calculations: An external 2.500V reference can be applied to q REFADJ, provided the internal reference is disabled first. Use the temperature correction equation to obtain k temperature=(VHIGH- VLOW)x the correct temperature: ⎡IHigh⎤ nxln ⎣⎢ILOW⎦⎥ TACT= 0.997 x TMEAS- 0.91°C Use the following equation when using the internal ref- where: erence: VHIGH = sensor-diode voltage with high current flowing 2.500V (IHIGH) TACT =TMEAS+(TMEAS+ 270.63)×(1− )°C V VLOW = sensor-diode voltage with low current flowing RREFADJ (ILOW) 38 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Register Definitions M Table 3. Register Summary A READ/ X REGISTER ADDRESS DATA START WRITE 1 NAME (ADR<4:0>) (D<255:0>, D<23:0>, D<15:0>, OR D<7:0>) (R/W) 3 ADC Control 0 0 R/W 0 0 0 0 0 AUTO<2:0> APD<1:0> AREF<1:0> REFE 2 ADC Setup 0 0 R/W 0 0 0 0 1 MSEL MUX<3:0> GAIN<1:0> BIP 9 ADC Data 0 0 1 0 0 0 1 0 ADCDATA<11:0> X X X X / M 0 AFFD<3:0> AFFI<3:0> ADC FIFO 0 0 0 0 0 1 1 A 1 AFFDATA<11:0>* AFFA<3:0>* 0 DITH ACCC<2:0> X X X X X ADC Accumulator 0 0 0 0 1 0 0 1 DITH ACCC<2:0> ACCDATA<19:0> 1 ADC GT Alarm 0 0 R/W 0 0 1 0 1 GTAM GTAC<2:0> GTAT<11:0> 3 ADC LT Alarm 0 0 R/W 0 0 1 1 0 LTAM LTAC<2:0> LTAT<11:0> 3 0 DAPD0/ DBPD0/ DAC Control 0 0 R/W 0 0 1 1 1 DAPD1 DBPD1 OA1E DREF<1:0> REFE OA3E OA2E FIFOA Control 0 0 R/W 0 1 0 0 0 FFAE BIPA SYMA CONA DPTA<3:0> Reserved 0 0 X 0 1 0 0 1 RESERVED, DO NOT USE FIFOA Data 0 0 R/W 0 1 0 1 0 FFADATA<11:0> X X X X Reserved 0 0 X 0 1 0 1 1 RESERVED, DO NOT USE FIFO Sequence 0 0 W 0 1 1 0 0 X X X X X X X X Clock Control 0 0 R/W 0 1 1 0 1 ODLY OSCE CLKIO<1:0> ADDIV<1:0> ACQCK<1:0> CP/VM Control 0 0 R/W 0 1 1 1 0 INTP VM1<1:0> VM2CP<2:0> CPDIV<1:0> DSWA/ Switch Control 0 0 R/W 0 1 1 1 1 DSWB OSW1 OSW2 SPDT1<1:0> SPDT2<1:0> OSW3 APIO Control 0 0 R/W 1 0 0 0 0 AP4MD<1:0> AP3MD<1:0> AP2MD<1:0> AP1MD<1:0> APIO Setup 0 0 R/W 1 0 0 0 1 AP4PU AP3PU AP2PU AP1PU AP4LL AP3LL AP2LL AP1LL DP4MD<3:0> DP3MD<3:0> DPIO Control 0 0 R/W 1 0 0 1 0 DP2MD<3:0> DP1MD<3:0> DPIO Setup 0 0 R/W 1 0 0 1 1 DP4PU DP3PU DP2PU DP1PU DP4LL DP3LL DP2LL DP1LL VM1A VM1B VM2 ADD AFF ACF GTA LTA Status 0 0 R 1 0 1 0 0 APR<4:1> APF<4:1> DPR<4:1> DPF<4:1> MV1A MV1B MV2 MADD MAFF MACF MGTA MLTA Interrupt Mask 0 0 R/W 1 0 1 0 1 MAPR<4:1> MAPF<4:1> MDPR<4:1> MDPF<4:1> Reserved 0 0 X 1 0 1 1 0 RESERVED, DO NOT USE Reserved 0 0 X 1 0 1 1 1 RESERVED, DO NOT USE Reserved 0 0 X 1 1 0 0 0 RESERVED, DO NOT USE Note:R/W= 0 for write, R/W= 1 for read, X = don’t care. *Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits). ______________________________________________________________________________________ 39

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Table 3. Register Summary (continued) 3 3 REGISTER READ/ ADDRESS DATA START WRITE 1 NAME (ADR<4:0>) (D<255:0>, D<23:0>, D<15:0>, OR D<7:0>) (R/W) X Reserved 0 0 X 1 1 0 0 1 RESERVED, DO NOT USE A Reserved 0 0 X 1 1 0 1 0 RESERVED, DO NOT USE M Reserved 0 0 X 1 1 0 1 1 RESERVED, DO NOT USE / Reserved 0 0 X 1 1 1 0 0 RESERVED, DO NOT USE 9 Reserved 0 0 X 1 1 1 0 1 RESERVED, DO NOT USE 2 3 Reserved 0 0 X 1 1 1 1 0 RESERVED, DO NOT USE 1 Reset 0 0 W 1 1 1 1 1 X X X X X X X X X Note:R/W= 0 for write, R/W= 1 for read, X = don’t care. *Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits). A Register Bit Descriptions The burst mode outputs data to DOUT directly in real M time as the bit decision is made on the falling edge of ADC Control Register SCLK and the latest conversion result is also stored in The ADC Control register configures the autoconvert the ADC Data register. For this mode, the conversion mode, the ADC power-down modes, the ADC reference rate is controlled by the SCLK frequency, which is limited buffer, and the internal reference voltage. Changes to 5MHz. If the charge pump is enabled, synchronize made to the ADC Control register settings are applied SCLK with the CLKIO clock to prevent charge-pump immediately. If changes are made during a conversion noise from corrupting the ADC result. Initiate the conver- in progress, discard the results of that conversion to sion by writing to the ADC Control register. SCLK is ensure a valid conversion result. required to run continuously during the conversion peri- AUTO<2:0>: ADC Autoconvert bits (default = 000). The od. For ADC gains of 1 or 2, a total of 14 to 28 clocks AUTO<2:0> bits configure the ADC to continuously con- (two to 16 for acquisition and 12 for conversion) are vert at the selected interval (see Table 4). Calculate the required to complete the conversion. For ADC gains of 4 conversion rate by dividing the ADC master clock fre- or 8, a total of 16 to 44 clocks (four to 32 for acquisition, quency by the selected number of clock cycles. For and 12 for conversion) are required to complete the con- example, if the ADC master clock frequency is version. Bringing CShigh aborts burst mode. 3.6864MHz and the selected value is 256, the conversion AREF<1:0>: ADC Reference Buffer bits (default = 00). rate is 3.6864MHz/256 or 14.4ksps. The conversion can The AREF<1:0> bits set the ADC reference buffer gain be started with the ADC Direct Write command and runs when REFE = 0 and the REFADC output voltage when continuously using the ADC master clock. Write 000 to REFE = 1 (see Table 6). Set AREF<1:0> to 00 to dis- the AUTO<2:0> bits to disable autoconvert mode. When able the ADC reference buffer and drive REFADC the autoconvert ADC master clock cycle rate is set to 32 directly with an external reference. and the acquisition time is set to 32 (AUTO<2:0> = 001, ACQCK<1:0> = 11, and GAIN<1:0> = 1X), the acquisi- REFE: Internal Reference Enable bit (default = 0). REFE tion time is automatically reduced to 16 clocks so that the = 1 enables the internal reference and sets REFADJ to ADC throughput is less than the autoconversion interval. 2.5V. REFE = 0 disables the internal reference, allowing The automode operation is unavailable in burst mode. an external reference to be applied at REFADJ, which drives the inputs to the ADC and DAC reference APD<1:0>: ADC Power-Down bits (default = 00). The buffers. The voltage at REFADJ is also used for temper- APD<1:0> bits control the power-down states of the ature measurement and must be 2.5V for accurate ADC and PGA (see Table 5). When a direct-mode ADC results. See the Temperature Sensorsection. This bit is conversion command is received, the ADC and PGA mirrored in the DAC Control register so that writing power up except when APD<1:0> = 00. either location updates both bits. MSB LSB NAME AUTO2 AUTO1 AUTO0 APD1 APD0 AREF1 AREF0 REFE DEFAULT 0 0 0 0 0 0 0 0 40 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Table 4. ADC Autoconvert Bit M Configuration (AUTO<2:0>) A X ADC MASTER CLOCK AUT02 AUTO1 AUTO0 CYCLES 1 0 0 0 Autoconvert disabled 3 0 0 1 32 2 0 1 0 64 9 / 0 1 1 128 M 1 0 0 256 A 1 0 1 512 X 1 1 0 1024 1 1 1 1 2048 3 3 Table 5. ADC Power-Down Bit Configuration 0 APD1 APD0 ADC MODE COMMENTS 0 0 Power-down ADC/PGA off 0 1 Fast power-down ADC/PGA off between conversions 1 0 Normal ADC/PGA on ADC/PGA on, SCLK clocks conversion, data clocked out on DOUT in real time on 1 1 Burst the falling edge of SCLK Table 6. ADC Reference-Buffer Bit Configuration ADC REFERENCE-BUFFER GAIN (V/V) REFADC VOLTAGE (V) AREF1 AREF0 (REFE = 0) (REFE = 1) 0 0 Buffer off High-impedance 0 1 0.5 1.25 1 0 0.8192 2.048 1 1 1 2.5 ______________________________________________________________________________________ 41

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ADC Setup Register MUX<3:0>: Multiplexer Input Select bits (default = 3 The ADC Setup register configures the input multiplexer, 0000). The MUX<3:0> bits plus the MSEL bit select the ADC gain, and unipolar/bipolar modes to perform a data inputs to the ADC (see Tables 7 and 8). 3 conversion. Changes made to the ADC Setup register 1 GAIN<1:0>: ADC Gain bits (default = 00). The settings are applied immediately. If changes are made GAIN<1:0> bits select the gain of the ADC (see Table 9). X during a conversion in progress, discard the results of BIP: Unipolar-/Bipolar-Mode Selection bit (default = 0). A that conversion to ensure a valid conversion result. For unipolar mode, set BIP = 0. For bipolar mode, set M MSEL: Multiplexer Select bit (default = 0). The MSEL bit BIP = 1. For temperature-sensor conversions, use the selects the upper or lower multiplexer. MSEL = 0 selects default GAIN = 00 and BIP = 0. 9/ the upper mux and MSEL = 1 selects the lower mux. 2 3 MSB LSB 1 NAME MSEL MUX3 MUX2 MUX1 MUX0 GAIN1 GAIN0 BIP X DEFAULT 0 0 0 0 0 0 0 0 A M Table 7. Upper Multiplexer Bit Configuration (MSEL = 0) POSITIVE INPUT NEGATIVE INPUT MUX3 MUX2 MUX1 MUX0 MAX1329 MAX1330 MAX1329 MAX1330 0 0 0 0 AIN1 AGND 0 0 0 1 AIN2 AGND 0 0 1 0 OUTA AGND 0 0 1 1 FBA AGND 0 1 0 0 OUT1 AGND 0 1 0 1 IN1- AGND 0 1 1 0 OUTB OUT2 AGND 0 1 1 1 FBB IN2- AGND 1 0 0 0 AIN1 AIN2 1 0 0 1 AIN2 AIN1 1 0 1 0 OUTA FBA 1 0 1 1 FBA OUTA 1 1 0 0 OUT1 IN1- 1 1 0 1 IN1- OUT1 1 1 1 0 OUTB OUT2 FBB IN2- 1 1 1 1 FBB IN2- OUTB OUT2 42 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Table 8. Lower Multiplexer Bit Configuration (MSEL = 1) M A POSITIVE INPUT NEGATIVE INPUT MUX3 MUX2 MUX1 MUX0 MAX1329 MAX1330 MAX1329 MAX1330 X 0 0 0 0 AIN1 REFADC 1 0 0 0 1 OUTA REFADC 3 0 0 1 0 OUT1 REFADC 2 0 0 1 1 OUTB OUT2 REFADC 9 / 0 1 0 0 AIN1 REFDAC M 0 1 0 1 OUTA REFDAC A 0 1 1 0 OUT1 REFDAC X 0 1 1 1 OUTB OUT2 REFDAC 1 TEMP1+ TEMP1- 1 0 0 0 (Internal diode anode) (Internal diode cathode) 3 3 TEMP2+ TEMP2- 1 0 0 1 0 (External diode anode at AIN1) (External diode cathode at AIN2) TEMP3+ 1 0 1 0 AGND (External diode anode at AIN1) TEMP4+ 1 0 1 1 AGND (External diode anode at AIN2) 1 1 0 0 DVDD/4 AGND 1 1 0 1 AVDD/4 AGND 1 1 1 0 REFADC AGND 1 1 1 1 REFDAC AGND Table 9. ADC Gain Bit Configuration GAIN1 GAIN0 ADC GAIN SETTING (V/V) 0 0 1 0 1 2 1 0 4 1 1 8 ______________________________________________________________________________________ 43

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ADC Data Register 3 The ADC Data register contains the result from the most recently completed analog-to-digital conversion. The 3 12-bit result is stored in the ADCDATA<11:0> bits. The 1 data format is binary for unipolar mode and two’s com- X plement for bipolar mode. The ADC Data register con- A tents are the same as the ADC FIFO contents at the last written address, unless writes to the ADC FIFO have M been inhibited. / 9 MSB 2 NAME ADCDATA11 ADCDATA10 ADCDATA9 ADCDATA8 ADCDATA7 ADCDATA6 ADCDATA5 ADCDATA4 3 DEFAULT 0 0 0 0 0 0 0 0 1 X LSB A NAME ADCDATA3 ADCDATA2 ADCDATA1 ADCDATA0 X X X X M DEFAULT 0 0 0 0 X X X X X = Don’t care. ADC FIFO Register The ADC FIFO register contents are different for write AFFI<3:0>: ADC FIFO Interrupt Address bits (default = and read modes. In write mode, the ADC FIFO register 0000). AFFI<3:0> sets the FIFO address. After each sets the working depth of the FIFO and the address that successful ADC conversion, the conversion results are generates an interrupt. In read mode, the ADC FIFO transferred from the ADC Data register to the FIFO register holds the ADC FIFO data and FIFO address. location indicated by the FIFO write pointer, and the FIFO write pointer is incremented. When the FIFO write pointer exceeds the value in AFFI<3:0>, the AFF bit in Write Format the Status register (Table 11) is asserted. Set the A serial interface write to the ADC FIFO register moves AFFI<3:0> value equal to or less than the AFFD<3:0> the FIFO write and read pointers to address 0. value. If set to a value greater than AFFD<3:0>, AFFD<3:0>: ADC FIFO Depth bits (default = 0000). AFFI<3:0> is forced to the AFFD<3:0> value. If AFFD<3:0> sets the working depth of the FIFO (see AFFD<3:0> is set to 0000 (depth of zero), the ADC Table 10). If set to a depth of zero, the ADC FIFO is dis- FIFO is disabled and writes to the AFF bit are also dis- abled and writes to the AFF (ADC FIFO Full) bit in the abled. AFFI<3:0> are write-only bits. Status register are also disabled. AFFD<3:0> are write- only bits. MSB LSB NAME AFFD3 AFFD2 AFFD1 AFFD0 AFFI3 AFFI2 AFFI1 AFFI0 DEFAULT 0 0 0 0 0 0 0 0 44 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Read Format pointer increments after each complete 16-bit word M A single read from the ADC FIFO register returns the read. It does not increment if the read is aborted by ADC FIFO data and the 4-bit FIFO address (AFFA<3:0>) bringing CS high before clocking out all 16 bits. Any A corresponding to the location read. read operation on the ADC FIFO register resets the X interrupt flag (AFF). After clocking out the 16-bit word, the read pointer 1 increments and continual clock shifts out the 16-bit AFFDATA<11:0>: ADC FIFO Read Data bits (default = 3 word at the location pointed to by the ADC FIFO read 0000 0000 0000). AFFDATA<11:0> returns the data 2 pointer. If trying to read from the ADC FIFO at a location written by the ADC at the current read pointer location. 9 pointed to by the ADC FIFO write pointer, the FIFO AFFA<3:0>: ADC FIFO Read Address bits (default = / repeats the last ADC conversion result and correspond- 0000). AFFA<3:0> returns the address of the current M ing ADC FIFO address equivalent to the ADC FIFO read pointer location. AFFA<3:0> is never greater than write pointer. To stop reading, bring CS high after the AFFD<3:0> programmed value. A clocking out the 16th bit of a complete word. The read X 1 MSB 3 NAME AFFDATA11 AFFDATA10 AFFDATA9 AFFDATA8 AFFDATA7 AFFDATA6 AFFDATA5 AFFDATA4 3 0 DEFAULT 0 0 0 0 0 0 0 0 LSB NAME AFFDATA3 AFFDATA2 AFFDATA1 AFFDATA0 AFFA3 AFFA2 AFFA1 AFFA0 DEFAULT 0 0 0 0 0 0 0 0 Note:Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits). Table 10. ADC FIFO Depth Bit Table 11. ADC FIFO Interrupt-Address Bit Configuration Configuration ADC FIFO WRITE ADC FIFO AFFD3 AFFD2 AFFD1 AFFD0 WORD POINTER AFFI3 AFFI2 AFFI1 AFFI0 INTERRUPT DEPTH RANGE ADDRESS 0 0 0 0 FIFO disabled 0 0 0 0 0 0 0 0 1 2 0-1 0 0 0 1 1 0 0 1 0 3 0-2 0 0 1 0 2 0 0 1 1 4 0-3 0 0 1 1 3 0 1 0 0 5 0-4 0 1 0 0 4 0 1 0 1 6 0-5 0 1 0 1 5 0 1 1 0 7 0-6 0 1 1 0 6 0 1 1 1 8 0-7 0 1 1 1 7 1 0 0 0 9 0-8 1 0 0 0 8 1 0 0 1 10 0-9 1 0 0 1 9 1 0 1 0 11 0-10 1 0 1 0 10 1 0 1 1 12 0-11 1 0 1 1 11 1 1 0 0 13 0-12 1 1 0 0 12 1 1 0 1 14 0-13 1 1 0 1 13 1 1 1 0 15 0-14 1 1 1 0 14 1 1 1 1 16 0-15 1 1 1 1 15 ______________________________________________________________________________________ 45

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor ADC Accumulator Register effective resolution to a maximum of 16 bits and provide 0 The ADC Accumulator register contains the bits to digital filtering. 3 enable dither, set the accumulator count, and set the ACCC<2:0> ADC Accumulator Count bits (default = 3 20-bit accumulator data. The dither and accumulator 000). The ACCC<2:0> bits set the number of ADC data 1 count bits are read/write and the accumulator data is conversion results to be accumulated and then written to X read only. A write to the register resets the accumulator the ACCDATA register before the ACF Status bit is set data (ACCDATA<19:0>) to 0x00000 and starts new A (see Table 12). The ACF status bit is set in the Status accumulation. The ACCDATA<19:0> bits remain register when the data is written to the ACCDATA regis- M unchanged until the programmed count of conver- ter. If the accumulator count is set to 1, the accumulator sions is completed. The accumulator is functional for does not accumulate and the ACCDATA<11:0> is the / 9 the normal, fast power-down, and burst modes. same as ADCDATA<11:0> in the ADC Data register. 2 DITH: Dither bit (default = 0). When DITH = 0, the dither ACCDATA<19:0>: ADC Accumulator Data bits (default = 3 generator is disabled and the accumulator can be used 0x00000). The ACCDATA<19:0> bits are the summation for oversampling and providing digital filtering (see the 1 of up to 256 ADC conversion results. When the count set Applying a Digital Filter to ADC Data Using the 20-Bit X by ACCC<2:0> has been reached, the ACF status bit is Accumulatorsection). When DITH = 1, the dithering for set and the accumulated data is written to this register. A the ADC is enabled. Use dithering with the accumulator The data is written to the register at a rate of the ADC to oversample data and decimate the result to extend the M conversion rate divided by the accumulator count. The accumulator does not exceed 0xFFFFF. Write Format MSB LSB NAME DITH ACCC2 ACCC1 ACCC0 X X X X DEFAULT 0 0 0 0 X X X X X = Don’t care. Read Format MSB NAME DITH ACCC2 ACCC1 ACCC0 ACCDATA19 ACCDATA18 ACCDATA17 ACCDATA16 DEFAULT 0 0 0 0 0 0 0 0 NAME ACCDATA15 ACCDATA14 ACCDATA13 ACCDATA12 ACCDATA11 ACCDATA10 ACCDATA9 ACCDATA8 DEFAULT 0 0 0 0 0 0 0 0 LSB NAME ACCDATA7 ACCDATA6 ACCDATA5 ACCDATA4 ACCDATA3 ACCDATA2 ACCDATA1 ACCDATA0 DEFAULT 0 0 0 0 0 0 0 0 Table 12. ADC Accumulator-Count Bit Configuration ACCC2 ACCC1 ACCC0 ACCUMULATOR COUNT 0 0 0 1 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 46 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor ADC GT Alarm Register results needed to be greater than the alarm threshold M The ADC GT Alarm register contains the greater-than before the GTA Status bit is set (see Table 13). mode, trip count, and threshold settings. A write to this A GTAT<11:0>: ADC Greater-Than Alarm Threshold bits register address resets the trip counters to zero. The (default = 0xFFF). When the required number of conver- X GT alarm is functional for the normal, fast power-down, sion results greater than the threshold set by the 1 and burst modes. GTAT<11:0> bits have been completed, the GTA Status 3 GTAM: ADC Greater-Than Alarm Mode bit (default = 0). bit is set in the Status register. Clearing the GTA Status 2 GTAM = 0 means that the alarm trips do not need to be bit by reading the Status register or writing to the ADC consecutive before the GTA Status bit is set. When GT Alarm register restarts the trip count. The 9 GTAM = 1, the alarm trips must be consecutive to set GTAT<11:0> bits are in binary format when the ADC is in / M the GTA Status bit. unipolar mode and two’s complement format when the GTAC<2:0>: ADC Greater-Than Alarm Trip Count bits ADC is in bipolar mode. Disable the GT alarm by setting A GTAT<11:0> to 0xFFF when the ADC is in unipolar mode (default = 000). GTAC<2:0> set the number of conversion X and 0x7FF when the ADC is in bipolar mode. 1 3 MSB 3 NAME GTAM GTAC2 GTAC1 GTAC0 GTAT11 GTAT10 GTAT9 GTAT8 0 DEFAULT 0 0 0 0 1 1 1 1 LSB NAME GTAT7 GTAT6 GTAT5 GTAT4 GTAT3 GTAT2 GTAT1 GTAT0 DEFAULT 1 1 1 1 1 1 1 1 Table 13a. ADC Greater-Than Alarm Trip Count Bit Configuration GTAC2 GTAC1 GTAC0 NUMBER OF TRIPS 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 ______________________________________________________________________________________ 47

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 ADC LT Alarm Register LTAT<11:0>: ADC Less-Than Alarm Threshold bits 3 The ADC LT Alarm register contains the less-than (default = 0x000). When the required number of ADC mode, trip count, and threshold settings. Writing the conversions results less than the threshold set by the 3 register address resets the trip counters to zero. The LT LTAT<11:0> bits have been completed, the LTA Status 1 alarm is functional for the normal, fast power-down, and bit is set in the Status register. Clearing the LTA Status X burst modes. bit by reading the Status register or writing to the ADC LT A Alarm register restarts the trip count. The LTAT<11:0> LTAM: ADC Less-Than Alarm Mode bit (default = 0). bits are in binary format when the ADC is in unipolar M LTAM = 0 means that the alarm trips need not be con- mode and two’s complement format when the ADC is in secutive to cause the LTA Status bit to be set. LTAM = 1 9/ means that the alarm trips must be consecutive before bipolar mode. Disable the LT alarm by setting LTAT<11:0> to 0x000 when the ADC is in unipolar mode the LTA Status bit is set. 2 and 0x800 when the ADC is in bipolar mode. LTAC<2:0>: ADC Less-Than Alarm Trip Count bits 3 (default = 000). LTAC<2:0> set the number of conver- 1 sion results needed to be less than the alarm threshold X before the LTA Status bit is set. A M MSB NAME LTAM LTAC2 LTAC1 LTAC0 LTAT11 LTAT10 LTAT9 LTAT8 DEFAULT 0 0 0 0 0 0 0 0 LSB NAME LTAT7 LTAT6 LTAT5 LTAT4 LTAT3 LTAT2 LTAT1 LTAT0 DEFAULT 0 0 0 0 0 0 0 0 Table 13b. ADC Less-Than Alarm Trip Count Bit Configuration LTAC2 LTAC1 LTAC0 NUMBER OF TRIPS 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 48 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor DAC Control Register OA1E: Op Amp 1 Enable bit (default = 0). Set OA1E = 1 M The DAC Control register configures the power states for to power up op amp 1. DACA, DACB, the op amps, DAC reference buffer, and A OA2E (MAX1330 only): Op Amp 2 Enable bit (default = the internal reference. The DAC Control register also 0). Set OA2E = 1 to power up op amp 2. X controls the DACA and DACB input and output register DREF<1:0>: DAC Reference Buffer bits (default = 00). 1 write modes. At power-up, all DACs and op amps are powered down. When powered down, the outputs of the DREF<1:0> sets the DAC reference buffer gain when 3 DAC buffers and op amps are high impedance. REFE = 0 (see Table 16). DREF<1:0> sets the REFDAC 2 voltage when the REFE = 1. DAPD<1:0>: DACA Power-Down bits (default = 00). 9 REFE: Internal Reference Enable bit (default = 0). REFE DAPD<1:0> control the power-down states and write / = 1 enables the internal reference and sets REFADJ to M modes for DACA (see Table 14). 2.5V. REFE = 0 disables the internal reference so an DBPD<1:0>: (MAX1329 only) DACB Power-Down bits A external reference can be applied at REFADJ, which (default = 00). DBPD<1:0> control the power-down states drives the inputs to the ADC and DAC reference X and write modes for a DACB write as shown in Table 15. buffers. This bit is mirrored in the ADC Control register 1 so that writing either location updates both bits. 3 3 MAX1329 0 MSB LSB NAME DAPD1 DAPD0 DBPD1 DBPD0 OA1E DREF1 DREF0 REFE DEFAULT 0 0 0 0 0 0 0 0 MAX1330 MSB LSB NAME DAPD1 DAPD0 X OA2E OA1E DREF1 DREF0 REFE DEFAULT 0 0 X 0 0 0 0 0 Table 14. DACA Power-Down Bit Table 15. DACB Power-Down Bit Configuration Configuration (MAX1329 Only) DACA POWER DACB POWER DACB WRITE DAPD1 DAPD0 DACA WRITE MODE DBPD1 DBPD0 MODE MODE MODE Write input and output Write input and 0 0 Powered down 0 0 Powered down register output register Write input and output Write input and 0 1 Powered up 0 1 Powered up register output register 1 0 Powered up Write input register 1 0 Powered up Write input register Shift input to output Shift input to output 1 1 Powered up 1 1 Powered up register register ______________________________________________________________________________________ 49

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 FIFOA Control Register subtracted from the DACA input register data (during 3 The FIFOA Control register enables the DACA FIFO, phases 3 and 4). configures the bipolar, symmetry, and continuous 3 SYMA: DACA FIFO Symmetry bit (default = 0). Set modes, and sets the depth of the FIFO. Any change to 1 SYMA = 0 to generate an asymmetrical waveform, con- the contents of this register resets the FIFOA sequence sisting of phase 1 (BIPA = 0) or phases 1 and 4 (BIPA X to the starting location. If the FIFO operation is enabled = 1). Set SYMA = 1 to generate symmetry phases 1 A (FFAE = 1), the next sequence command transfers the and 2 (BIPA = 0) or phases 1–4 (BIPA = 1). DACA input register data to the output register. The M CONA: DACA FIFO Continuous bit (default = 0). Set DACA input or output register can be written to when CONA = 0 to generate a single waveform or set CONA / the FIFO is enabled without affecting the FIFOA 9 = 1 to generate a periodic or continuous waveform. sequence, but the DACA output and/or input register 2 data is changed. DPTA<3:0>: DACA FIFO Depth bits (default = 0000). 3 The DPTA<3:0> bits set the depth of the FIFOA data FFAE: DACA FIFO Enable bit (default = 0). Set FFAE = 1 1 to enable the sequencing function. FFAE must be set to register to be used for waveform generation (see Table 17). The entire FIFOA data register can be filled with 16 X 0 to write to the FIFO. Writes to the FIFO when FFAE = 1 words but only the number programmed by are ignored. A DPTA<3:0> are used. During waveform generation, the BIPA: DACA FIFO Bipolar bit (default = 0). Set BIPA = 0 M FIFOA words are added to the DACA input register to generate a unipolar waveform or set BIPA = 1 to gen- value before being sent to the DACA output register. erate a bipolar waveform. For a unipolar waveform, the The first output is the DACA input register value. The FIFOA data is added to the DACA input register data following value is the DACA input register value during phases 1 and 2 (see Figures 8 and 9). summed with the FIFOA location 1 value. The FIFOA For a bipolar waveform, the FIFOA data is added to the locations are incremented until the FIFO depth speci- DACA input register data (during phases 1 and 2) and fied by the DPTA<3:0> bits has been reached. MSB LSB NAME FFAE BIPA SYMA CONA DPTA3 DPTA2 DPTA1 DPTA0 DEFAULT 0 0 0 0 0 0 0 0 Table 16. DAC Reference Buffer Bit Configuration DAC REFERENCE REFDAC DREF1 DREF0 BUFFER GAIN (V/V) VOLTAGE (V) (REFE = 0) (REFE = 1) 0 0 N/A Buffer disabled 0 1 0.5 1.25 1 0 0.8192 2.048 1 1 1.0 2.5 50 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor FIFOA Data Register A write to the FIFOA Data register is possible only when M The FIFOA Data register stores up to 16 12-bit words that the FFAE bit in the FIFOA Control register is 0. If FFAE can be used by DACA to generate a waveform. = 1, any write to the FIFOA Data register is ignored. A A FFADATA<11:0>: FIFOA Data bits (default = 0xXXX). read command is possible at any time. If BIPA = 0, the X data is interpreted as binary (0 to 4095). If BIPA = 1, FFADATA<11:0> represents a 12-bit word that is left 1 the data is interpreted as sign magnitude (-2047 to justified with 4 don’t-care LSBs. A write or read opera- +2047). In sign magnitude, the MSB represents the 3 tion always starts at location 1 and ends at the full FIFO sign bit, where 0 indicates a positive number and 1 2 depth. Any attempt to write past the full FIFO depth does not overwrite the data just written. Any attempt to indicates a negative number. The 11 LSBs provide the 9 magnitude in sign magnitude. read past the full FIFO depth returns zeroes on DOUT. / M A MSB NAME FFADATA11 FFADATA10 FFADATA9 FFADATA8 FFADATA7 FFADATA6 FFADATA5 FFADATA4 X DEFAULT 0 0 0 0 0 0 0 0 1 3 LSB 3 NAME FFADATA3 FFADATA2 FFADATA1 FFADATA0 X X X X 0 DEFAULT 0 0 0 0 X X X X X = Don’t care. Table 17. DACA FIFO Depth Bit Configuration DPTA3 DPTA2 DPTA1 DPTA0 FIFOA DEPTH 0 0 0 0 1 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 ______________________________________________________________________________________ 51

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 FIFO Sequence Register CLKIO<1:0>: CLKIO Configuration bits (default = 10). 3 A write to the FIFO Sequence register steps DACA to the CLKIO<1:0> control the CLKIO input and output divider next FIFOA word. A valid write consists of the 8-bit settings. See Table 18 for the CLKIO configurations. 3 address and 8 bits of data, where the data bits are don’t- Changes to the CLKIO<1:0> bits occur on the falling 1 care bits. The FIFO location increments on the 16th rising edge of CLKIO. The ODLY bit is ignored and has no X edge of SCLK. Successive writes sequence the entire effect when the CLKIOis disabled. When OSCE = 1, A contents of the FIFOA Data register to the DACA output changing the CLKIO output frequency does not change register. The FIFO can also be sequenced with the the frequency of the clock to the ADC and charge- M DPIOs configured as DLDA or DLAB. The FIFO pump clock dividers. When OSCE = 0, the output of the / Sequence register is a write-only register. CLKIO input dividers is applied to the ADC and charge- 9 pump clock dividers. The changes can take up to four 2 Clock Control Register CLKIO clock cycles due to internal synchronization. 3 The Clock Control register enables the internal oscilla- ADDIV<1:0>: ADC Clock Divider bits (default = 00). tor and the CLKIO output, sets the ADC acquisition 1 ADDIV<1:0> configures the ADC clock divider (see time, and controls the CLKIO, ADC, and charge-pump X Table 19), and the output is the ADC master clock programmable dividers. (Figure 3). If OSCE = 1, the input to the ADC clock A ODLY: Oscillator Turn-Off Delay bit (default = 0). Set divider is the output of the 3.6864MHz oscillator. If M ODLY = 0 to allow the oscillator to turn off immediately OSCE = 0 and CLKIO<1:0> ≠ 00, the output of the when powered down by the OSCE bit. If ODLY = 1, the CLKIO input divider is applied to the input of the ADC oscillator turns off 1024 CLKIO clock cycles after it is clock divider. powered down by the OSCE bit. ODLY also affects ACQCK<1:0> ADC Acquisition Clock bits (default = DPIO sleep mode (SLPB). When ODLY = 1, OSCE = 1, 01). ACQCK<1:0> set the number of ADC master and CLKIO<1:0> does not equal 00b, SLPB is delayed clocks used for the ADC acquisition (see Table 20). For by 1024 CLKIO clocks. gains of 1 or 2 (GAIN<1:0> = 0X in the ADC Control OSCE: Internal Oscillator Enable bit (default = 1). Set register), the number of acquisition clocks can be set OSCE = 1 to enable the internal 3.6864MHz oscillator. for 2, 4, 8, or 16. For gains of 4 or 8 (GAIN<1:0> = 1X), Set OSCE = 0 to disable the internal oscillator and the number of acquisition clocks can be programmed apply an external oscillator at CLKIO. When turning off, to be 4, 8, 16, or 32. CLKIO drives low before becoming an input. Do not leave CLKIO unconnected when configured as an input. The APIOs and DPIOs can be configured as a wake-up to set the OSCE bit. MSB LSB NAME ODLY OSCE CLKIO1 CLKIO0 ADDIV1 ADDIV0 ACQCK1 ACQCK0 DEFAULT 0 1 1 0 0 0 0 1 Table 18. CLKIO Bit Configuration Table 19. ADC Clock Divider Bit Configuration CLKIO INPUT CLKIO OUTPUT CLKIO1 CLKIO0 MODE MODE (MHz) ADDIV1 ADDIV0 ADC CLOCK DIVIDER (OSCE = 0) (OSCE = 1) 0 0 Divide by 1 Disabled 0 1 Divide by 2 0 0 Input (output low) 1 0 Divide by 4 0 1 fCLKIO/4 1.2288 1 1 Divide by 8 1 0 fCLKIO/2 2.4567 1 1 fCLKIO 4.9152 52 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor CP/VM Control Register VM2CP<2:0>: Voltage Monitor 2 (VM2) and Charge- M The CP/VM (Charge Pump/Voltage Monitor) Control Pump Control bits (default = 000). VM2CP<2:0> control register configures the interrupt polarity, charge-pump the charge pump, the bypass switch, and the AVDDvolt- A output voltage settings and power-down, supply volt- age monitor. The charge pump generates a regulated X age bypass switch state, and the voltage monitor set- AVDDsupply voltage from a DVDDinput. When activated 1 tings for DVDDand AVDD. (VM2CP = 100), the bypass switch internally shorts INTP: Interrupt Polarity bit (default = 0). INTP controls DVDD to AVDD. VM2 monitors the voltage on AVDD and 3 the output polarity for RST1 and RST2 when configured sets the VM2 Status bit when AVDD drops below 2 as interrupt outputs. INTP = 0 results in active-low oper- the threshold. 9 ation and INTP = 1 selects active-high operation. CPDIV<1:0>: Charge-Pump Clock Divider bits (default = / M 00). The CPDIV<1:0> bits set the divider value for the VM1<1:0>: Voltage Monitor 1 (VM1) Control bits (default = 00). VM1 monitors the voltage on DVDD. The input clock to the charge pump (see Table 23). If OSCE A = 1, the input to the charge-pump clock divider is the VM1<1:0> bits control the threshold and output settings X 3.6864MHz oscillator output. If OSCE = 0 and of VM1 (see Table 21). RST1 and RST2 are open-drain outputs when configured as voltage monitor outputs CLKIO<1:0> ≠ 00, the output of the CLKIO input divider 1 and are push-pull when configured as interrupt outputs. is applied to the input of the charge-pump clock divider. 3 The charge pump is optimized to operate with a clock The VM1A status bit is set when DVDD drops below the 3 rate between 39kHz and 78kHz. Set the CPDIV<1:0> 1.8V threshold and the VM1B status bit is set when 0 and CLKIO<1:0> bits to provide the optimal clock DVDDdrops below the 2.7V threshold. frequency for the charge pump. MSB LSB NAME INTP VM11 VM10 VM2CP2 VM2CP1 VM2CP0 CPDIV1 CPDIV0 DEFAULT 0 0 0 0 0 0 0 0 Table 20. ADC Acquisition Clock Bit Configuration ADC ACQUISITION CLOCKS ACQCK1 ACQCK0 GAIN = 1, 2 GAIN = 4, 8 0 0 2 4 0 1 4 8 1 0 8 16 1 1 16 32 Table 21. Voltage Monitor 1 Control Bit Configuration VM1A STATE VM1B STATE VM11 VM10 RST1 OUTPUT RST2 OUTPUT (1.8V MONITOR) (2.7V MONITOR) 0 0 1.8V monitor 2.7V monitor On On 0 1 1.8V monitor Interrupt On Off 1 0 Interrupt 2.7V monitor Off On 1 1 Interrupt Interrupt Off Off ______________________________________________________________________________________ 53

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Table 22. Voltage Monitor 2 and Charge-Pump Control Bit Configuration 3 VM2 STATE 3 VM2CP2 VM2CP1 VM2CP0 CHARGE-PUMP STATE BYPASS SWITCH STATE (THRESHOLD VOLTAGE) 1 0 0 0 Off Open Off X 0 0 1 On (3V) Open On (2.7V) A 0 1 0 On (4V) Open On (3.8V) M 0 1 1 On (5V) Open On (4.5V) / 1 0 0 Off Closed Off 9 2 1 0 1 Off Open On (2.7V) 3 1 1 0 Off Open On (3.6V) 1 1 1 1 Off Open On (4.5V) X A Table 23. Charge-Pump Clock Divider Bit M Configuration CPDIV1 CPDIV0 CHARGE-PUMP CLOCK DIVIDER 0 0 Divide by 32 0 1 Divide by 64 1 0 Divide by 128 1 1 Divide by 256 54 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Switch Control Register OSW1: Op Amp 1 Switch Control bit (default = 0). The M The Switch Control register controls the two SPDT OSW1 bit and DPIO_ configured in OSW1 mode control switches and the feedback switches for DACA, DACB, the state of the op amp 1 switch. If DPIO_ is not config- A op amp 1, and op amp 2. The switches are controlled ured for OSW1 mode, it is set to 0 as shown in Table 26. X through the serial interface or by a configured DPIO. OSW2 (MAX1330 only): Op Amp 2 Switch Control bit 1 DSWA: DACA Switch Control bit (default = 0). The (default = 0). The OSW2 bit and DPIO_ configured in 3 DSWA bit controls the state of the DACA switch. A OSW2 mode control the state of the op amp 2 switch. If 2 logic-high in DSWA or on any DPIO_ configured as a DPIO_ is not configured for OSW2 mode, it is set to 0 DACA switch control input causes the DACA switch to as shown in Table 27. 9 close. The switch remains open when DSWA = 0 and / SPDT1<1:0>: Single-Pole, Double-Throw Switch 1 M all DPIO_ pins configured as DACA switch control (SPDT1) Control bits (default = 00). The SPDT1<1:0> inputs are logic-low. DPIO_ pins not configured as bits and DPIO_ configured for SPDT1 mode control the A DACA switch control inputs are treated as logic zeros. state of the switch. If DPIO_ is not configured for SPDT1 X See Table 24. mode, it is set to 0 as shown in Table 28. 1 DSWB (MAX1329 only): DACB Switch Control bit SPDT2<1:0>: Single-Pole, Double-Throw Switch 2 (default = 0). A logic-high in DSWB or an any DPIO_ 3 (SPDT2) Control bits (default = 00). The SPDT2<1:0> configured as a DACB switch control input causes the 3 bits and DPIO_ configured for SPDT2 mode control the DACB switch to close. The switch remains open when state of the switch. If DPIO_ is not configured for SPDT2 0 DSWB = 0 and all DPIO_s configured as DACB switch mode, it is set to 0 as shown in Table 29. control inputs are logic-low. DPIO_s not configured as DACB switch control inputs are treated as logic zeros. See Table 25. MAX1329 MSB LSB NAME DSWA DSWB OSW1 X SPDT11 SPDT10 SPDT21 SPDT20 DEFAULT 0 0 0 X 0 0 0 0 MAX1330 MSB LSB NAME DSWA X OSW1 OSW2 SPDT11 SPDT10 SPDT21 SPDT20 DEFAULT 0 X 0 0 0 0 0 0 X = Don’t care. Table 24. DACA Switch Control Table 25. DACB Switch Control Configuration Configuration DSWA DACA SWITCH DSWB DACB SWITCH DPIO4 DPIO3 DPIO2 DPIO1 DPIO4 DPIO3 DPIO2 DPIO1 BIT STATE (DSWA) BIT STATE (DSWB) 0 0 0 0 0 Open 0 0 0 0 0 Open X X X X 1 Closed X X X X 1 Closed X X X 1 X Closed X X X 1 X Closed X X 1 X X Closed X X 1 X X Closed X 1 X X X Closed X 1 X X X Closed 1 X X X X Closed 1 X X X X Closed X = Don’t care. X = Don’t care. ______________________________________________________________________________________ 55

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Table 26. Op Amp 1 Switch Control Table 27. Op Amp 2 Switch Control 3 Configuration Configuration 3 1 OP AMP 1 OP AMP 2 OSW1 OSW2 X DPIO4 DPIO3 DPIO2 DPIO1 SWITCH STATE DPIO4 DPIO3 DPIO2 DPIO1 SWITCH STATE BIT BIT (OSW1) (OSW2) A 0 0 0 0 0 Open 0 0 0 0 0 Open M X X X X 1 Closed X X X X 1 Closed / 9 X X X 1 X Closed X X X 1 X Closed 2 X X 1 X X Closed X X 1 X X Closed 3 X 1 X X X Closed X 1 X X X Closed 1 1 X X X X Closed 1 X X X X Closed X X = Don’t care. X = Don’t care. A M Table 28. SPDT1 Switch Control Configuration SPDT11 SPDT10 SPDT1 SWITCH STATE DPIO4 DPIO3 DPIO2 DPIO1 BIT BIT SNO1-TO-SCM1 STATE SNC1-TO-SCM1 STATE 0 0 0 0 0 0 Open Open 0 X X X X 1 Closed Closed 0 X X X 1 X Closed Closed 0 X X 1 X X Closed Closed 0 X 1 X X X Closed Closed 0 1 X X X X Closed Closed 1 0 0 0 0 0 Open Closed 1 X X X X 1 Closed Open 1 X X X 1 X Closed Open 1 X X 1 X X Closed Open 1 X 1 X X X Closed Open 1 1 X X X X Closed Open X = Don’t care. 56 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Table 29. SPDT2 Switch Control Configuration M A SPDT21 SPDT20 SPDT2 SWITCH STATE DPIO4 DPIO3 DPIO2 DPIO1 BIT BIT SNO2-TO-SCM2 STATE SNC2-TO-SCM2 STATE X 0 0 0 0 0 0 Open Open 1 0 X X X X 1 Closed Closed 3 0 X X X 1 X Closed Closed 2 0 X X 1 X X Closed Closed 9 0 X 1 X X X Closed Closed /M 0 1 X X X X Closed Closed A 1 0 0 0 0 0 Open Closed X 1 X X X X 1 Closed Open 1 1 X X X 1 X Closed Open 3 1 X X 1 X X Closed Open 3 1 X 1 X X X Closed Open 0 1 1 X X X X Closed Open APIO Control Register active-low wake-up input, general-purpose output, or seri- The Analog Programmable Input/Output (APIO) Control al-interface, level-shifted buffered I/O. register configures the modes of APIO1–APIO4. AP_MD<1:0>: APIO_ Mode Configuration bits (default APIO1–APIO4 I/O logic levels are referenced to AVDDand = 00). AP_MD<1:0> configures the APIO_ mode AGND (see Analog I/O in the Electrical Characteristics according to Table 30. table). APIO_ is configurable as a general-purpose input, MSB LSB NAME AP4MD1 AP4MD0 AP3MD1 AP3MD0 AP2MD1 AP2MD0 AP1MD1 AP1MD0 DEFAULT 0 0 0 0 0 0 0 0 Table 30. APIO_ Mode Bit Configuration AP_MD1 AP_MD0 MODE DESCRIPTION 0 0 GPI Digital input. APIO_ logic level read from AP_LL register bit. 0 1 WUL Digital input. A falling edge on APIO_ sets the OSCE bit to 1 enabling the oscillator. 1 0 GPO Digital output. Set the APIO_ logic level by writing to the AP_LL register bit. Digital input or output. The SPI mode functions differ for each APIO1–APIO4. • APIO1 digital input. DOUT outputs the APIO1 logic level when CS is high, and APIO1 is a GPI, when CS is low. Set the resistor pullup configuration with the AP1PU bit. 1 1 SPI • APIO2 digital output. APIO2 outputs the DIN logic level when CS is high and becomes a GPO with the level set by AP2LL bit when CS is low. • APIO3 digital output. APIO3 outputs the SCLK logic level when CS is high and becomes a GPO with the level set by the AP3LL bit when CS is low. • APIO4 digital output. APIO4 inverts and then outputs the CS logic level. ______________________________________________________________________________________ 57

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 APIO Setup Register 3 The APIO Setup register programs the resistor pullup and the logic level for APIO1–APIO4. 3 1 AP<4:1>PU: APIO Resistor Pullup bits (default = 1111). X AP_PU controls the internal 500kΩ (typ) pullup resistor on the corresponding APIO_. AP_PU = 0 disables the A pullup resistor and AP_PU = 1 connects the pullup M resistor to AVDD. The pullup resistor is active only when the corresponding APIO_ is configured as an input. / 9 AP<4:1>LL: APIO Logic-Level bits (default = 0000). If 2 APIO_ is programmed as a GPO, set the corresponding AP_LL = 0 to set APIO_ to a logic-low level or set AP_LL 3 = 1 to set APIO_ to a logic-high level. A read from AP_LL 1 returns the logic level at the corresponding APIO_ when X the register is read, regardless of the APIO mode. A MSB LSB M NAME AP4PU AP3PU AP2PU AP1PU AP4LL AP3LL AP2LL AP1LL DEFAULT 1 1 1 1 0 0 0 0 DPIO Control Register The Digital Programmable Input/Output (DPIO) Control register programs the modes of the DPIO1–DPIO4. DPIO1–DPIO4 are referenced to DVDD and DGND (see Digital I/O in the Electrical Characteristicstable). DP_MD<3:0>: DPIO_ Mode Configuration bits (default = 0000). DP_MD<3:0> configures the corresponding DPIO_ (see Table 31). MSB NAME DP4MD3 DP4MD2 DP4MD1 DP4MD0 DP3MD3 DP3MD2 DP3MD1 DP3MD0 DEFAULT 0 0 0 0 0 0 0 0 LSB NAME DP2MD3 DP2MD2 DP2MD1 DP2MD0 DP1MD3 DP1MD2 DP1MD1 DP1MD0 DEFAULT 0 0 0 0 0 0 0 0 DPIO Setup Register The DPIO Setup register configures the pullup resistor and logic level on DPIO1–DPIO4. DP<4:1>LL: DPIO Logic-Level bits (default = 0000). If DP<4:1>PU: DPIO Resistor Pullup bits (default = 1111). DPIO_ is programmed as a GPO, set the correspond- DP_PU controls the internal 500kΩ (typ) pullup resistor ing DP_LL = 0 to set DPIO_ to a logic-low level or set on the corresponding DPIO_. DP_PU = 0 disables the DP_LL = 1 to set DPIO_ to a logic-high level. A read pullup resistor and DP_PU = 1 connects the pullup from DP_LL returns the logic level at the corresponding resistor to DVDD. The pullup resistor is active only when DPIO_ when the register is read, regardless of the the corresponding DPIO_ is configured as an input. DPIO mode. MSB LSB NAME DP4PU DP3PU DP2PU DP1PU DP4LL DP3LL DP2LL DP1LL DEFAULT 1 1 1 1 0 0 0 0 58 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Table 31. DPIO_ Mode Bit Configuration M MODE A DP _M D 3 DP _M D 2 DP _M D 1 DP _M D 0 DESCRIPTION MAX1329 MAX1330 X 0 0 0 0 GPI GPI Digital input. DPIO_ logic-level read from DP_LL register bit. 1 Digital input. A falling edge on WUL sets the OSCE bit enabling 3 0 0 0 1 WUL WUL the oscillator. 2 Digital input. A rising edge on WUH sets the OSCE bit enabling 9 0 0 1 0 WUH WUH the oscillator. / M Di g it al in pu t. A lo gi c-l o w on SLP overr i d e s the re gi s ter settin gs and A po we rs do wn all cir c uit s except VM 1 and all the re g is ters . A lo gi c - 0 0 1 1 SLP SLP hig h on SLP tra nsfers the p owe r contro l ba ck to the re gi s ter X settin gs . Se e the Cl o ck Co ntro l Regi s ter sectio n. 1 3 Digital input. A logic-low on SHDN overrides the register 0 1 0 0 SHDN SHDN settings and powers down all circuits. A logic-high on SHDN 3 transfers the power control back to the register settings. 0 Digital input. A rising edge on DLAB shifts DACA and DACB data from the input register to the output register or sequences 0 1 0 1 DLAB DLAB through FIFOA if enabled. For the MAX1330, this applies only to DACA. Digital input. CONVST controls acquisition time and conversion 0 1 1 0 CONVST CONVST start. A falling edge on CONVST puts the ADC in acquisition mode. A rising edge on CONVST starts a single conversion. Digital input. A rising edge on DLDA shifts DACA data from the 0 1 1 1 DLDA DLDA input to output register or sequences through FIFOA if enabled. Digital input. DSWA and OSW3 control the DACA and op amp 3 1 0 0 0 DSWA DSWA switches, respectively. See the Switch Control Register section. Digital input. A rising edge on DLDB shifts DACB data from the 1 0 0 1 DLDB — input to output register. Digital input. DACB and op amp 2 control the DACB and op 1 0 1 0 DSWB OSW2 amp 2 switches, respectively. See the Switch Control Register section. Digital input. Op amp 1 switch control. See the Switch Control 1 0 1 1 OSW1 OSW1 Register section. Digital input. SPDT1 controls the SPDT1 switch. See the Switch 1 1 0 0 SPDT1 SPDT1 Control Register section. ______________________________________________________________________________________ 59

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Table 31. DPIO_ Mode Bit Configuration (continued) 3 3 MODE DP _M D 3 DP _M D 2 DP _M D 1 DP _M D 0 DESCRIPTION 1 MAX1329 MAX1330 X Digital input. SPDT2 controls the SPDT2 switch. See the Switch 1 1 0 1 SPDT2 SPDT2 Control Register section. A M Digital output. DRDY goes high when a conversion is complete and valid ADC data is available in the ADC Data register. If the / 1 1 1 0 DRDY DRDY ADC Data or Status register is read, DRDY returns low. If high, 9 DRDY pulses low for one ADC master clock cycle while 2 updating the ADC Data register before returning high. 3 Digital output. Write to the DP_LL register bits to set the GPO 1 1 1 1 1 GPO GPO level. X A M Status Register VM2: AVDD Voltage-Monitor Status bit (default = 0). The Status register is a 24-bit register that contains VM2 indicates the status of the AVDD voltage monitor. Status bits from all blocks. Setting a Status bit causes VM2 = 1 when the AVDD voltage drops below the the interrupt output to assert when the corresponding threshold programmed by the VM2CP<2:0> bits. VM2 Interrupt Mask bit in the Interrupt Mask register is clears to 0 when the Status register is read and only if cleared. If a Status bit is set and an event occurs to set the condition is no longer true. When the AVDD voltage it again, the Status bit and interrupt output remain monitor is powered down, the previous state of the bit is asserted. All Status bits clear once the Status register maintained until it is read and it cannot be set to 1 in has been read successfully. Updating of the Status reg- this state. ister is delayed during a read until the Status register ADD: ADC Done Status bit (default = 0). The ADD bit read has been completed. indicates when an ADC conversion has completed and VM1A: 1.8V DVDD Voltage-Monitor Status bit (default = the data is ready to be read from the ADC Data regis- 0). VM1A indicates the status of the 1.8V DVDD voltage ter. ADD is set to 1 after the data from an ADC conver- monitor. The VM1A = 1 when the DVDD voltage drops sion has been written to the ADC Data register. ADD below the 1.8V threshold. The VM1A bit clears to 0 clears to 0 when the Status register or the ADC Data when the Status register is read and only if the condi- register is read. tion is no longer true. When the 1.8V DVDD voltage AFF: ADC FIFO Full Status bit (default = 0). The AFF bit monitor is powered down, the previous state of the bit is indicates that the ADC has written data to the ADC maintained until it is read and it cannot be set to 1 in FIFO address programmed by the AFFI<3:0> bits. The this state. AFF bit is set to 1 when the address has been written. Note: The default state is 0. However, at power-up, the AFF clears to 0 when the Status register is read or when voltage monitor asserts VM1A. Read the Status register the ADC FIFO register is read (any number of ADC data after power-up to reset VM1A to 0. words) or written. VM1B: 2.7V DVDD Voltage-Monitor Status bit (default = ACF: ADC Accumulator Full Status bit (default = 0). The 0). VM1B indicates the status of the 2.7V DVDD voltage ACF bit indicates that the programmed number of ADC monitor. VM1B = 1 when the DVDD voltage drops below conversion results have been accumulated. The result the 2.7V threshold. The VM1B bit clears to 0 when the is saved in the ACCDATA<19:0> bits in the ADC Status register is read and only if the condition is no Accumulator register for the next programmed number longer true. When the 2.7V DVDDvoltage monitor is pow- of accumulations before it is overwritten. The ACF bit ered down, the previous state of the bit is maintained sets to 1 when the ADC Accumulator is filled to the pro- until it is read and it cannot be set to 1 in this state. grammed address. The ACF bit clears to 0 when the Status register is read or when the ADC Accumulator Note: The default state is 0. However, at power-up, the register is read or written. voltage monitor asserts VM1B. Read the Status register after power-up to reset VM1B to 0. 60 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M MSB NAME VM1A VM1B VM2 ADD AFF ACF GTA LTA A DEFAULT 0* 0* 0 0 0 0 0 0 X 1 NAME APR4 APR3 APR2 APR1 APF4 APF3 APF2 APF1 3 DEFAULT 0 0 0 0 0 0 0 0 2 9 LSB / NAME DPR4 DPR3 DPR2 DPR1 DPF4 DPF3 DPF2 DPF1 M DEFAULT 0 0 0 0 0 0 0 0 A *The default states for VM1A and VM1B are 0. However, at power-up, the voltage monitor asserts VM1A and VM1B. X 1 GTA: ADC Greater-Than (GT) Alarm Status bit (default APF<4:1>: APIO Falling-Edge Status bit (default = 0). A 3 = 0). GTA = 1 indicates that ADC GT alarm has been logic-high in the APF<4:1> bits indicate that a falling 3 tripped. The GTA bit clears to 0 by reading the Status edge has been detected on the corresponding APIO_. 0 register or by writing the ADC GT Alarm register. APF_ clears to 0 when the Status register is read. LTA: ADC Less-Than (LT) Alarm Status bit (default = 0). DPR<4:1>: DPIO Rising-Edge Status bit (default = 0). A LTA = 1 indicates that the ADC LT alarm has been logic-high in the DPR<4:1> bits indicate that a rising tripped. The LTA bit clears to 0 by reading the Status edge has been detected on the corresponding DPIO_. register or by writing the ADC LT Alarm register. DPR_ clears to 0 when the Status register is read. APR<4:1>: APIO Rising-Edge Status bit (default = 0). A DPF<4:1>: DPIO Falling-Edge Status bit (default = 0). A logic-high in the APR<4:1> bits indicate that a rising logic-high in the DPF<4:1> bits indicate that a falling edge has been detected on the corresponding APIO_. edge has been detected on the corresponding DPIO_. APR_ clears to 0 when the Status register is read. DPF_ clears to 0 when the Status register is read. ______________________________________________________________________________________ 61

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Interrupt Mask Register MAFF: ADC FIFO Full Mask bit (default = 1). Set MAFF = 3 The Interrupt Mask register bits enable the Status bits 0 to unmask the AFF Status bit to generate an interrupt. to generate an interrupt on RST1 and/or RST2 if pro- 3 MACF: ADC Accumulator Full Mask bit (default = 1). grammed as interrupts (configured by VM1<1:0> in the 1 Set MACF = 0 to unmask the MACF Status bit to gener- CP/VM Control register). Clearing a mask bit to 0 ate an interrupt. X enables the corresponding bit in the Status register to MGTA: ADC GT Alarm Mask bit (default = 1). Set MGTA A generate an interrupt. Setting a mask bit to 1 prevents = 0 to unmask the GTA Status bit to generate an interrupt. the Status bit from generating an interrupt. If the inter- M rupt output is asserted and another interrupt occurs, MLTA: ADC LT Alarm Mask bit (default = 1). Set MLTA = / the interrupt output remains asserted. Interrupt condi- 0 to unmask the LTA Status bit to generate an interrupt. 9 tions on RST1 and/or RST2 are released after recogniz- MAPR<4:1>: APIO Rising-Edge Mask bits (default = 2 ing a read to the Status register. Updating of the Status 1111). Set MAPR_ = 0 to unmask the corresponding 3 register is delayed until after the Status register has APIO_ Status bit to generate an interrupt. 1 been read. If the Status register read was aborted or if MAPF<4:1>: APIO Falling-Edge Mask bits (default = a new unmasked Status bit is set during the read, the X 1111). Set MAPF_ = 0 to unmask the corresponding interrupt output reasserts at the end of the read (see A Figure 15). APIO_ Status bit to generate an interrupt. M MV1A: 1.8V DVDD Voltage-Monitor Mask bit (default = MDPR<4:1>: DPIO Rising-Edge Mask bits (default = 1111). Set MDPR_ = 0 to unmask the corresponding 1). Set MV1A = 0 to unmask the VM1A Status bit to DPIO_ Status bit to generate an interrupt. generate an interrupt. MDPF<4:1>: DPIO Falling-Edge Mask bits (default = MV1B: 2.7V DVDD Voltage-Monitor Mask bit (default = 1111). Set MDPF_ = 0 to unmask the corresponding 1). Set MV1B = 0 to unmask the VM1B Status bit to DPIO_ Status bit to generate an interrupt. generate an interrupt. MVM2: AVDD Voltage-Monitor Mask bit (default = 1). Reset Register Set MVM2 = 0 to unmask the VM2 Status bit to gener- A write to the Reset register resets all registers to their ate an interrupt. default values. A valid write consists of the 8-bit address and 8 don’t-care bits of data. The reset occurs MADD: ADC Done Mask bit (default = 1). Set MADD = 0 on the 16th rising edge of SCLK. to unmask the ADD Status bit to generate an interrupt. MSB NAME MV1A MV1B MVM2 MADD MAFF MACF MGTA MLTA DEFAULT 1 1 1 1 1 1 1 1 NAME MAPR4 MAPR3 MAPR2 MAPR1 MAPF4 MAPF3 MAPF2 MAPF1 DEFAULT 1 1 1 1 1 1 1 1 LSB NAME MDPR4 MDPR3 MDPR2 MDPR1 MDPF4 MDPF3 MDPF2 MDPF1 DEFAULT 1 1 1 1 1 1 1 1 62 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M POWER 2.7V TO 3.6V POWER 2.7V TO 3.6V A SUPPLY SUPPLY 5.0V X 0.1µF 0.1µF 0.1µF CDVDD CFLY CAVDD 0.1µF 1 3 DVDD C1A C1B AVDD VDD DVDD C1A C1B AVDD VDD 2 9 RST1 INTERRUPT RST1 INTERRUPT / MAX1329 MAX1329 M MAX1330 µC MAX1330 µC RST2 RESET RST2 RESET A X DGND AGND DGND DGND AGND DGND 1 3 3 Figure 23. Power-Supply Circuit Using an External 3.0V Power Figure 24. Power-Supply Circuit Using an External 3.0V Power Supply for DVDDand AVDD Supply for DVDDand Internal Charge Pump Set to 5V for AVDD 0 Applications Information 1.8V TO 3.6V Power-Supply Considerations 3.0V The circuit in Figure 23 applies an external 3.0V power CDVDD CFLY CAVDD 0.1µF supply to both DVDD and AVDD. To drive AVDD directly, disable the internal charge pump through the CP/VM E1 Control register. The bypass switch between DVDD and DVDD C1A C1B AVDD VDD AVDDcan be either open or closed in this configuration. Figure 24 shows the charge pump enabled to supply RST1 RESET MAX1329 AVDD. The charge-pump output voltage is set to 5.0V MAX1330 µC through the CP/VM Control register. See the Charge- RST2 INTERRUPT Pump Component Selection section. Figure 25 shows DVDD is powered from a battery with DGND AGND DGND the charge-pump output set to 3.0V. The charge pump can draw high peak currents from DVDD under maxi- mum load. Select an appropriately sized bypass capac- Figure 25. Power-Supply Circuit Using a Battery for DVDDand itor for DVDD (≥ 10 times CFLY). Supply ripple can be Internal Charge Pump Set to 3.0V for AVDD reduced by increasing CAVDD and/or the charge-pump Digital-Interface Connections clock frequency. Figure 26 provides standard digital-interface connections Running Directly Off Batteries between the MAX1329/MAX1330 and a µC. The µC gen- The MAX1329/MAX1330 can be powered directly from erates its own 32kHz clock for timekeeping and the two alkaline cells, two silver oxide button cells, or a lithi- MAX1329/MAX1330 provide the high-frequency clock um-coin cell. DVDD requires 1.8V to 3.6V and AVDD required by the µC. See the Clock Control Register sec- requires 2.7V to 5.5V for proper operation. Save power tion to program the CLKIO output and frequency and set by running DVDD directly off the battery and shorting to the ODLY bit to delay the turn-off time to enable the µC AVDD by closing the internal bypass switch. Use the time to go to sleep. During sleep, CLKIO becomes an 2.7V AVDD voltage monitor to detect when it drops to input and requires a weak pulldown resistor (≤1MΩ) to 2.7V. Power is saved during this time because the inter- minimize power dissipation. See the DPIO Setup and nal charge pump is off. Once the battery voltage drops DPIO Control registers to program DPIO1–DPIO4 as to 2.7V, open the bypass switch and enable the internal wake-ups. Upon wake-up, the internal oscillator starts and charge pump as long as DVDD is between 1.8V and outputs to CLKIO. See the CP/VM Control Registersec- 2.7V. Following this procedure optimizes the battery life. tion to program the RST1and RST2as a reset or interrupt. ______________________________________________________________________________________ 63

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Communication with a Peripheral Device 3 Powered by the MAX1329/MAX1330 XIN 3 The circuit in Figure 27 shows the MAX1329/MAX1330 1 providing an interface between a µC and a peripheral 32.768kHz device powered by different supply voltages. This elimi- X nates the need for external level-translation circuitry due MAX1329 XOUT A to the different supply voltages. The internal charge MAX1330 µC M pump boosts the µC supply voltage (DVDD) to the periph- CLKIO HCLKIN eral device supply voltage (AVDD). See the APIO Control CS OUTPUT / and APIO Setup registers to program APIO2–APIO4 as 9 DIN, SCLK, and CS outputs to the peripheral device, SCLK SCK 2 respectively, and APIO1 as the DOUT input from the 3 peripheral device. The digital inputs at DIN, SCLK, and DIN MOSI 1 CSare level-translated from DVDDto AVDDand output at DOUT MISO X the configured APIO2, APIO3, and APIO4 outputs. The digital output at DOUT is level-translated from AVDD to A DVDDfrom the configured APIO1 input. RST1 RESET M RST2 INTERRUPT DPIO1 INTERRUPT DPIO2 INTERRUPT Figure 26. Digital-Interface Connections 3.0V/4.0V/5.0V EXTERNAL 1.8V TO 3.6V CAVDD POWER SUPPLY CFLY CDVD D DVDD C1A C1B AVDD DVDD AVDD MAX1329 PERIPHERAL OUTPUT CS MAX1330 APIO4 CS DEVICE µC SCK SCLK APIO3 SCLK MOSI DIN APIO2 DIN MISO DOUT APIO1 DOUT DGND DGND AGND AGND Figure 27. Communication with a Peripheral Device Powered by the MAX1329/MAX1330 64 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M REFDAC A X OUTA DACA 1 3 DSWA 2 9 VBAT FBA / M LED SNO1 A SPDT1 SCM1 Q1 X 1 SNC1 3 VBAT 3 MAX1329 0 LED SNC2 SCM2 SPDT2 Q2 SNO2 REFDAC RB OUTB DACB DSWB IF RF FBB PHOTO DIODE 1μF AV = 0.5, 0.82, 1 REFADC 1.25V 2.5V REFADJ REF 0.01μF REFDAC 2.50V AV = 0.5, 0.82, 1 1μF Figure 28. Optical Reflectometry Application with Dual LED and Single Photodiode Optical Reflectometry Application with The DSWA and DSWB switches are open in this configu- Dual LED and Single Photodiode ration. The LED bias current is calculated as ILED = Figure 28 illustrates the MAX1329 in an optical reflectom- VOUTA/RB. REFADC is used as an analog ground and etry application with two transmitting LEDs and one DACB is set to ensure that the photodiode is not forward receiving photodiode. The LEDs transmit light at specific biased. The IF current is converted to a voltage through frequencies onto the sample strip and the photodiode the RF resistor and measured by the internal ADC. receives the reflections from the strip. Set the DACA out- SPDT1 and SPDT2 are configured as single-pole put to provide the appropriate bias currents for the LEDs. double-throw switches and enable switching between ______________________________________________________________________________________ 65

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 the two LEDs. The LEDs can be powered directly from Two-Electrode Potentiostat with AC and 3 VBAT or from AVDD powered by the internal charge DC Excitation 3 pump if the VD of the LEDs require a higher or regulat- The circuit in Figure 30 shows the MAX1330 in a two- ed voltage. Ambient light rejection is performed in the electrode potentiostat application with both AC and DC 1 digital domain in this configuration by digitizing the excitation to the sensor. The DSWA can be open or X photodiode current with the internal ADC while both closed and OSW1 and OSW2 should be normally open A LEDs are off and subtracting this from the result when although OSW1 can be closed during high sensor the LEDs are turned on. current to keep op amp 1 in compliance. REFADC is M analog ground and the working electrode (WE) is con- Three-Electrode Potentiostat with / nected to analog ground through op amp 1. The sensor 9 Software-Switchable Single- or Dual- current to be measured is converted to a voltage 2 Channel Connection through RF and measured by the internal ADC. For DC 3 The MAX1329 is used in a software switchable single- operation, the bias voltage between WE and the 1 or dual-channel three-electrode potentiostat application counter electrode (CE) is set by DACA. For AC opera- X (see Figure 29). In both configurations, the DAC buffer tion, DACA is configured to generate a waveform by feedback switches, DSWA and DSWB, are normally programming the FIFOA Control and FIFOA Data regis- A open but can be closed during high sensor current to ters for the desired operation. Op amp 2 is configured M keep the DAC buffer outputs compliant. In the dual- as a 2nd-order Sallen Key lowpass filter to smooth the channel configuration, the SPDT1 switch is open and steps in the AC waveform going to the sensor. The the OSW1 switch is closed. DACA biases the working DACA can be sequenced to create an AC waveform electrode (WE) and DACB biases the reference elec- through the SPI interface or by configuring one of the trode (RE) both relative to the counter electrode (CE). DPIOs and driving it with a clock. The internal ADC The CE is shared by the two channels. In this configura- includes a 16-word FIFO to facilitate data gathering tion, RE is really a second working electrode and IA during this mode of operation. and IB are the two sensor currents being measured. IA and IB are converted to voltages through RA and RB Temperature Measurement with Two and measured by the internal ADC. In the single-chan- Remote Sensors nel configuration, the SPDT1 switch is closed and the For external measurements, select single-ended AIN1 OSW1 switch is open. DACA biases the WE relative to and AIN2 temperature measurement relative to AGND the RE and the RE is set by IN1-. Op amp 1’s force- in the lower multiplexer. Two diode-connected 2N3904 sense configuration holds RE constant while the CE transistors are used as external temperature sensing swings up and down depending on the sensor current diodes in Figure 31. For internal temperature sensor and the sensor impedance. In this configuration, IA is measurements, select internal temperature measure- the sensor current being measured. The R1 resistor is ment in the lower multiplexer. During all temperature typically a large value to keep op amp 1 stable when measurements, autoconvert and burst modes are the sensor is not present or not active. unavailable. Divide the ADC result by eight to obtain the measured temperature. When using an external reference at REFADJ, disable the internal reference and use the temperature correction equation in the Temperature Measurementsection. 66 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M A MAX1329 X REFDAC 1 3 OUTA DACA 2 DSWA IA RA 9 / M A FBA REFDAC X 1 OUTB DACB 3 DSWB 3 IB RB WE 0 RE FBB SNO1 CE SCM1 SPDT1 SNC1 IN1- OSW1 R1 OA1 OUT1 IN1+ 1.25V 1μF AV = 0.5, 0.82, 1 REFADC 2.5V REFADJ REF 0.01μF REFDAC 2.50V AV = 0.5, 0.82, 1 1μF Figure 29. Three-Electrode Potentiostat Software-Switchable Single- or Dual-Channel Connection ______________________________________________________________________________________ 67

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 3 3 MAX1330 1 IN1- X A OSW1 RF M OA1 OUT1 / 9 2 IN1+ 3 1.25V WE 1 1μF X AV = 0.5, 0.82, 1 REFADC A 2.5V REFADJ M REF CE 0.1μF REFDAC 2.50V SENSOR AV = 0.5, 0.82, 1 1μF IN2- OSW2 R3 OA2 OUT2 C1 R2 IN2+ C2 REFDAC OUTA R1 DACA DSWA FBA Figure 30. Two-Electrode Potentiostat with AC and DC Excitation 68 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor M A AIN1 AIN1 X AIN2 CAIN1* OUTA/OUT3 PGA 12-BIT ADC REFADC 1 FBA/IN3- 3 MUX AGND OUT1 AV = 1, 2, 4, 8 2 2N3904 IN1- 9 OUTB/OUT2 FBB/IN2- DITHER /M AIN2 TEMP1 ACCUMULATOR TEMP2 A CAIN2* TEMP3 ALARM X DVDD/4 AVDD/4 MUX ADC FIFO 1 AGND REFADC 2N3904 3 REFDAC 3 AGND 1μF AV = 0.5, 0.82, 1 REFADC 0 MAX1329 TEMP 2.5V REFADJ TEMP1 MAX1330 SENSOR REF 0.01μF REFDAC AV = 0.5, 0.82, 1 1μF *FOR BEST RESULTS, LIMIT CAIN1 AND CAIN2 TO 10pF. Figure 31. Temperature Measurement with Two Remote Sensors Programmable-Gain Instrumentation Amplifier Two op amps and two SPDT switches are configured as a programmable-gain instrumentation amplifier in Figure 32. It includes a differential input and a single- ended output. SPDT1 and SPDT2 are configured as single-pole, double-throw switches. The gain is set by the following equations: VOUT =⎛⎜R2+R3 +1⎞⎟(VIN+−VIN−) ⎝ R1 ⎠ for switch position 1, and ⎛ R ⎞ VOUT =⎜ 3 +1⎟(VIN+−VIN−) ⎝R1+R2 ⎠ for switch position 2. ______________________________________________________________________________________ 69

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Round the FIFOA_DATA(n) values to the nearest inte- 3 ger and write these values to the FIFOA Data register. 3 Figure 33 shows a sine wave with a 2VP-P output and IN1+ 1 VIN+ OUT1 with a 1.25V offset. Write the DAC Control register with OA1 VOUT 0x43 to enable DACA, enable the internal reference, X IN1- and to set REFDAC to 2.5V. Write to the DACA input A R3 and output register by performing a direct mode write OSW1 SNO1 with 0x4800 to set DACA to midscale or 1.25V. Write M the FIFOA Control register with 0x7F to disable FIFOA / SCM1 R2 and allow a write to the FIFOA Data register, enabling 9 SPDT1 SNC1 bipolar, symmetry, and continuous modes, and setting 2 the depth to 16. 3 IN2+ R1 The FIFOA data calculated from the above equation is 1 VIN- OUT2 161, 320, 476, 627, 772, 910, 1039, 1159, 1267, 1362, OA2 X IN2- 1445, 1514, 1568, 1607, 1631, and 1638 decimal. Write the FIFOA Data register with 0x0A10 1400 1DC0 2730 A R1 3040 38E0 40F0 4870 4F30 5520 5A50 5EA0 6200 M OSW2 SNO2 6470 65F0 6660 as a contiguous bit stream to fill the FIFOA Data register with data. Write to the FIFOA SCM2 R2 Control register with 0xFF to enable FIFOA and to disal- SPDT2 SNC2 low writes to the FIFOA Data register. Write to the DPIO Control register with 0x0007 to program DPIO1 as an MAX1330 R3 input to sequence the DACA FIFO on each rising edge. Write to the Switch Control register with 0x80 to close the DACA switch to put the buffer into unity gain. Input a continuous clock to DPIO1 that is 4 x N times (N = 16) the desired frequency of the synthesized waveform. Figure 32. Programmable-Gain Instrumentation Amplifier, Figure 33 should be observable on OUTA. Switch Position 1 Synthesizing a Sine Wave SINE WAVE The MAX1329/MAX1330 can easily create up to a 2.50 64-point single or periodic sine wave using the DACA and FIFOA. The 16-word FIFO or memory is used to 2.25 create the first quarter of the waveform and symmetry is 2.00 used to extend the waveform to produce a complete 1.75 period. See the DAC FIFO and Direct Digital Synthesis T (V) 1.50 (DDS) Logicsection for detailed waveform generation. PU The first data point is the DACA input register data. The OUT 1.25 FIFOA data is offset from this initial data. To determine AC 1.00 D the values to be written to the FIFOA Data register use 0.75 the following equation. 0.50 FIFOA_DATA(n) = A x sin((n/N) x 90°) 0.25 where 0 0 10 20 30 40 50 60 70 n = 1 to N, DAC SEQUENCES N = DPTA<3:0>, A = (VPEAK/VREFDAC) x 4096, Figure 33. Example Sine-Wave Output VPEAKis the desired peak voltage of the sine wave, and VREFDAC is the DAC reference voltage pro- grammed at REFDAC. 70 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Charge-Pump Component Selection Operating the Analog Switches M Optimize the charge-pump circuit for size, quiescent The MAX1329/MAX1330 include two single-pole double- current, and output ripple by properly selecting the throw (SPDT) and three single-pole single-throw (SPST) A operating frequency and capacitors CDVDD, CFLY, and analog switches. The two SPDT analog switches are X CAVDD (Table 32). The charge pump is capable of pro- uncommitted and the three SPST analog switches are 1 viding a maximum of 25mA including what is used connected between the DAC buffer or op amp outputs 3 internally. If less than 25mA is required, smaller capaci- and the inverting inputs. tor values can be utilized. 2 The analog switches can be controlled using the Switch For lowest ripple, select 117kHz operation (CPDIV<1:0> Control register or any of the DPIOs. See the DPIO 9 = 00 and OSCE = 1 when using the internal oscillator). In Control and DPIO Setup registers to program the / M addition, increasing CAVDD relative to CFLY further DPIOs. The DPIOs should be used when direct control reduces ripple. For highest efficiency, select 14.6kHz is critical such as synchronizing with another event or if A operation (CPDIV<1:0> = 11 and OSCE = 1 when using the SPI bus bandwidth is not sufficient for the intended X the internal oscillator) and select the largest practical application. The register bit for the analog switch is log- values for CAVDD and CFLY while maintaining at least a ically OR’d with DPIOs enabled to control that switch. 1 30-to-1 ratio. For smallest size, select 117kHz operation. The SPDT1 and SPDT2 analog switches can be operat- 3 See Table 32 for some suggested values and resulting ed as a SPDT or as a double-pole single-throw (DPST). 3 ripple for 25mA load current. See Figure 34 for load cur- In the DPST mode, both switches can be opened or 0 rent vs. flying capacitor value when optimizing for other closed together. This is useful when connecting two load currents. external nodes to a common point. If a lower on-resis- Note that the capacitors must have low ESR to main- tance is required, NO_ and NC_ can be connected tain low ripple. The CFLY flying capacitor ESR needs together externally and be used as a SPST analog to be < 0.1Ω; and the CAVDD and CDVDD filter capaci- switch with half the on-resistance. tor ESR needs to be < 0.3Ω. The CFLY flying capacitor The SPST analog switches are intended to be used to can easily be a ceramic capacitor; and the CAVDD and set the DAC buffers and op amps to unity gain internal- CDVDD filter capacitor can be a low-ESR tantalum or ly by software control. When the DAC buffers and op may need to be a combination of a small ceramic and a amps are used as transimpedance amplifiers, the SPST larger tantalum capacitor. analog switches can be used to short the external tran- simpedance resistor during high current periods to When DVDDis lower than AVDD, the charge pump always keep the amplifier output in compliance. operates in voltage-doubler mode. It regulates the output voltage using a pulse-width-modulation (PWM) scheme. Using a PWM scheme ensures that the charge pump is synchronous with the internal ADC preventing corruption of the conversion results. CHARGE-PUMP LOAD CURRENT Table 32. External Component Selection vs. FLYING CAPACITOR VALUE 50 fVoArV 2D5Dm≥A0 O.4uVtp (uFtig Cuurerr e2n5)t and 2VDVDD - 4405 fCfPC =P 5=7 1.61k5H.2zkHz MAX1329 fig34 35 ILOAD, CHARGE-PUMP MAX CFLY CAVDD CDVDD RIPPLE mA) 30 CLOCK (kHz) (mA) (µF) (µF) (µF) (mV) OAD ( 25 fCP = 28.8kHz IL 20 25 1.7 55.6 17.4 14.4 32 15 12.5 0.9 27.8 8.7 10 fCP = 14.4kHz 25 0.9 27.8 8.7 5 28.8 32 12.5 0.4 13.9 4.3 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 25 0.4 13.9 4.3 57.6 32 CFLY (µF) 12.5 0.2 6.9 2.2 25 0.2 6.9 2.2 115.2 32 12.5 0.1 3.5 1.1 Figure 34. Load Current vs. CFLY Value for 2VDVDD- VAVDD≥0.4V ______________________________________________________________________________________ 71

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Using the Internal Reference and 3 Reference Buffers DIGITAL-FILTER TRANSFER FUNCTION 3 The MAX1329/MAX1330 include a precision 2.5V internal 0 1 reference and two independent programmable buffers for -5 the ADC and DACs. See the ADC Control and DAC X -10 Control registers to enable the internal reference and pro- A gram the buffers. The REFADJ output is fixed at 2.5V dB) -15 E ( M (REFE = 1) and the REFADC and REFDAC connect to the NS -20 O internal ADC reference input and the internal DAC refer- SP -25 E 9/ egnracmem inepdu ttos , oruetsppuet c1t.i2v5eVly, . 2T.0h4e8sVe, bour f2fe.5rsV cinadne pbeen dperon-t TER R -30 2 of each other. This allows the dynamic range of the ADC FIL -35 3 and DACs to be optimized or set differently. This is useful -40 1 if one of the reference voltages is needed to be approxi- -45 X mately AVDD/2 to be used as an analog ground. -50 0 60 120 180 240 300 360 420 480 The flexibility of the reference circuit allows the internal A FREQUENCY (Hz) reference to be shutdown (REFE = 0) and an external M voltage reference applied to REFADJ. If either REFADC Figure 35. Plot of the Digital Filter with 60Hz Notch or REFDAC requires a different or more accurate volt- age, an external reference can be applied directly to REFADC or REFDAC and the corresponding reference Figure 35 is a plot showing a notch at 60Hz by accumu- buffer must be disabled. lating 256 samples at 15.36ksps. The final step is to read the data in the ADC Accumulator Applying a Digital Filter to ADC Data Using register and divide by the number of samples that were the 20-Bit Accumulator accumulated. Shift the data right for each binary multi- The MAX1329/MAX1330 incorporate a 20-bit accumula- ple of accumulated data. For example, for 256 samples tor that can sum up to 256 results of the 12-bit ADC the data should be shifted right eight times. automatically. See the ADC Accumulator Registersec- tion to set the number of samples to be summed. Once Increasing ADC Resolution using the the accumulator is full, the ACF bit in the Status register Accumulator with Dither is asserted. The MAX1329/MAX1330 incorporate an internal dither The accumulator provides a digital filtering sync func- function that can be used along with the 20-bit accumu- tion, with an effective data rate equal to fEDR = fS/n lator to easily increase the resolution of the 12-bit ADC where fSis the ADC sample rate and n is the number of to up to 16 bits. The oversampling along with the dither samples accumulated. There is a notch at every integer increases the resolution with the penalty of a lower multiple of fEDR. The following equation provides the effective data rate. Use the following equation to deter- transfer function of the filter: mine the number of samples required to increase the resolution by N number of bits: sin⎛nπf⎞ Samples = 22N ⎜ ⎟ H(f)= ⎝ fs ⎠ =sinc⎛⎜nπf⎞⎟ To increase the resolution by 4 bits, from 12 to 16 bits, ⎛nπf⎞ ⎝ fs ⎠ 256 samples are required. After accumulating the ⎜ ⎟ required number of samples, read the data from the ⎝ fs ⎠ ADC Accumulator register and shift right by 4 bits with the 16 LSBs as the increased resolution result. 72 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Using the ADC with the ADC LT Layout, Grounding, and Bypassing M (Less-Than) and GT (Greater-Than) For best performance, use PCBs. Do not use wire-wrap Digital Alarms boards. Board layout should ensure that digital and ana- A The ADC LT and GT alarms compare the latest ADC log signal lines are separated from each other. Do not run X result to the values programmed in the ADC LT Alarm analog and digital (especially clock) signals parallel to 1 and ADC GT Alarm registers, if enabled, and assert the one another or run digital lines underneath the 3 appropriate GTA or LTA status bit in the Status register MAX1329/MAX1330 package. High-frequency noise in once the threshold has been exceeded. The digital the VDDpower supply can affect the MAX1329/MAX1330 2 alarms can be used as a safeguard during normal ADC performance. Bypass the AVDD and DVDD supplies with 9 conversions to signify an event. Change the GT and LT a 0.1µF capacitor to GND, close to the AVDD and DVDD / alarm thresholds, if needed, when selecting a new mux pins (see Table 32 for recommended capacitor values). M input channel. The ADC can be put into autoconversion Minimize capacitor lead lengths for best supply-noise A mode to continuously convert without user intervention. rejection. X See the AUTO<2:0> bits in the ADC Control Register section to enable the auto mode and to program the 1 ADC conversion rate. 3 3 0 Selector Guide INTERNAL TEMP SENSOR REFERENCE TEMP TEMP PART NO. OF DACS NO. OF OP AMPS ACCURACY (°C) COEFFICIENT RANGE (ppm/°C max) MAX1329BETL+ 2 1 ±3 ±75 -40°C to +85°C MAX1330BETL+ 1 2 ±3 ±75 -40°C to +85°C +Denotes a lead-free/RoHS-compliant package. ______________________________________________________________________________________ 73

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Functional Diagrams 3 3 1 DVDD CLKIO RST1 RST2 C1A C1B AVDD X A M CS INTERNAL VOLTAGE DPIO1 CHARGE CLOCK AND SUPERVISORS AND / PUMP 9 SCLK DIVIDER INTERRUPTS DPIO2 SERIAL 2 I/O DPIO DIN DPIO3 3 1 DOUT AIN1 DPIO4 X AIN2 PGA 12-BIT ADC REFADC OUTA A AIN1 FBA UPPER AV = 1, 2, 4, 8 M OUT1 MUX APIO1 AIN2 IN1- OUTB DITHER APIO2 FBB ACCUMULATOR APIO APIO3 TEMP TEMP1 ALARM SENSOR TEMP2 ADC FIFO APIO4 TEMP3 DAVVDDDD//44 LOMWUEXR A V = 0.5, 0.8192, 1.0 REFADC REFADC SNO1 REFDAC 2.50V REFADJ BANDGAP AGND SNC1 SPDT1 REFDAC A V = 0.5, 0.8192, 1.0 SCM1 REFDAC 12-BIT OUTA SNO2 DACA DACA FIFO SNC2 SPDT2 DSWA SCM2 FBA IN1+ OA1 12-BIT IN1- REFDAC OUTB DACB OSW1 DSWB MAX1329 OUT1 FBB DGND AGND 74 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Functional Diagrams (continued) M A DVDD CLKIO RST1 RST2 C1A C1B AVDD X 1 3 2 CS INTERNAL VOLTAGE CHARGE DPIO1 9 CLOCK AND SUPERVISORS AND SCLK DIVIDER INTERRUPTS PUMP DPIO2 /M SERIAL I/O DPIO DIN DPIO3 A X DOUT AIN1 DPIO4 1 AIN2 PGA 12-BIT ADC REFADC OUTA 3 AIN1 FBA UPPER AV = 1, 2, 4, 8 3 MUX OUT1 APIO1 0 AIN2 IN1- OUT2 DITHER APIO2 IN2- ACCUMULATOR APIO APIO3 TEMP TEMP1 ALARM SENSOR TEMP2 ADC FIFO APIO4 TEMP3 DAVVDDDD//44 LOMWUEXR AV = 0.5, 0.8192, 1.0 REFADC REFADC SNO1 REFDAC 2.50V REFADJ BANDGAP AGND SNC1 SPDT1 REFDAC AV = 0.5, 0.8192, 1.0 SCM1 REFDAC 12-BIT OUTA SNO2 DACA DACA FIFO SNC2 SPDT2 DSWA SCM2 FBA IN1+ OA1 IN1- OA2 OUT2 OSW1 OSW2 MAX1330 OUT1 IN2- DGND IN2+ AGND ______________________________________________________________________________________ 75

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Typical Operating Circuit 3 3 1.8V TO 3.6V 1 X 3.0V E1 10µF A 0.1µF 33µF 0.1µF 1µF M 9/ DVDD C1A C1B AVDD VDD 2 AIN1 XIN 3 32.768kHz 1 MAX1329 X AIN2 XOUT 2N3904 CLKIO HCLKIN A 1µF REFADC µC M REFADJ CS OUTPUT 0.01µF REFDAC SCLK SCK 1µF DIN MOSI DOUT MISO OUTA RST1 RESET RF RST2 INTERRUPT FBA WE DPIO1 INTERRUPT SENSOR RE FBB DPIO2 INTERRUPT CE OUTB AGND DGND DGND 76 ______________________________________________________________________________________

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor Pin Configurations M A X TOP VIEW TOP VIEW AIN2 SNO2 SCM2 SNC2 REFDAC FBA OUTA OUTB FBB N.C. AIN2 SNO2 SCM2 SNC2 REFDAC FBA OUTA OUT2 IN2- IN2+ 13 30 29 28 27 26 25 24 23 22 21 30 29 28 27 26 25 24 23 22 21 2 9 AIN1 31 20 OUT1 AIN1 31 20 OUT1 / REFADC 32 19 IN1- REFADC 32 19 IN1- M REFADJ 33 18 IN1+ REFADJ 33 18 IN1+ A AGND 34 17 SNC1 AGND 34 17 SNC1 AVDD 35 16 SCM1 AVDD 35 16 SCM1 X C1B 36 MAX1329 15 SNO1 C1B 36 MAX1330 15 SNO1 1 C1A 37 14 APIO4 C1A 37 14 APIO4 3 DVDD 38 EXPOSED PAD— 13 APIO3 DVDD 38 EXPOSED PAD— 13 APIO3 DGND 39 CONNECT TO AGND 12 APIO2 DGND 39 CONNECT TO AGND 12 APIO2 3 CLKIO 40 11 APIO1 CLKIO 40 11 APIO1 0 + + 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 DPIO1 DPIO2 DPIO3 DPIO4 DOUT SCLK DIN CS RST1 RST2 DPIO1 DPIO2 DPIO3 DPIO4 DOUT SCLK DIN CS RST1 RST2 THIN QFN THIN QFN Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 40 TQFN-EP T4066-5 21-0141 ______________________________________________________________________________________ 77

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs, Reference, Voltage Monitors, and Temp Sensor 0 Revision History 3 3 REVISION REVISION PAGES DESCRIPTION 1 NUMBER DATE CHANGED X 0 8/08 Initial release — A 1 10/08 Corrected Absolute Maximum Ratings table 2 M / 9 2 3 1 X A M Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 78 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M axim Integrated: MAX1329BETL+ MAX1329BETL+T