DSILC6-4xx ESD Protection for high speed interface Main applications I/O3 VCC Where transient over-voltage protection in ESD I/O4 I/O2 sensitive equipment is required, such as: GND ■ Computers I/O1 ■ Printers SOT-666 Flip-Chip ■ Communication systems DSILC6-4P6 DSILC6-4F2 ■ Cell phone handsets and accessories ■ Video equipment Functional diagram Description I/O4 VCC I/O3 I/O1 VCC I/O2 The DSILC6-4xx is a monolithic application specific discrete dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet, display and camera serial interfaces (LVDS). I/O4 GND I/O3 I/O1 GND I/O2 The device is ideal for applications where both SOT-666 Flip-Chip reduced printed circuit board space and power Top-side view Top-side view absorption capability are required. Features I/O1 VCC I/O2 Diode array topology I/O4 GND I/O3 ■ 4 line protection ■ 5 V V protection Flip-Chip CC Top-side view ■ Very low capacitance: 1 pF typ. ■ Lead-free pacakge ■ RoHS compliant Order Code Benefits Part Number Marking DSILC6-4P6 G ■ Very low capacitance between lines to GND for DSILC6-4F2 EI optimized data integrity ■ Low PCB space consumption: 2.9 mm² max for Complies with the following standards: SOT-666 and 1.5 mm² max for Flip-Chip ■ Cut-off frequency > 2 GHz IEC 61000-4-2 level 4: ■ High reliability offered by monolithic integration 8 kV (contact discharge) ■ MDDI, SMIA, MIPI specification compliant 15 kV (air discharge) MIL STD 883G-Method 3015-7: class 3B May 2007 Rev 3 1/11 www.st.com 11

Characteristics DSILC6-4xx 1 Characteristics Table 1. A bsolute ratings Symbol Parameter Value Unit IEC 61000-4-2 contact discharge 8 V Peak pulse voltage kV PP IEC 61000-4-2 air discharge 15 SOT-666 5 I Peak pulse current A PP I/O to GND Flip-Chip 7 Pulse waveform = 8/20 µs SOT-666 90 P Peak pulse power W PP Flip-Chip 120 T Storage temperature range -55 to +150 °C stg T Maximum junction temperature 125 °C j T Lead solder temperature (10 seconds duration) 260 °C L Table 2. E lectrical characteristics (T = 25° C) amb Symbol Parameter V Reverse stand-off voltage RM I Leakage current RM V Breakdown voltage BR V Forward voltage F V Clamping voltage CL I Peak pulse current PP Value Symbol Parameter Test Conditions Unit Min Typ Max I Leakage current V = 5 V 0.5 µA RM RM Breakdown voltage V I = 1 mA 6 V BR between V and GND R BUS V Forward voltage I = 10 mA 1 V F F SOT-666 2 2.5 V = 0 V, F = 1 MHz, V = 30 mV I/O OSC Capacitance between Flip-Chip 2.5 3 C i/o-GND I/O and GND V = 1.65 V, V = 4.3 V, SOT-666 1.5 1.8 I/O CC F = 1 MHz, VOSC = 400 mV Flip-Chip 1.8 2.0 SOT-666 1.0 1.25 V = 0 V, F = 1 MHz, V = 30 mV pF I/O OSC Capacitance Flip-Chip 1.25 1.5 C i/o-i/o between I/O V = 1.65 V, V = 4.3 V, SOT-666 0.75 0.9 I/O CC F = 1 MHz, VOSC = 400 mV Flip-Chip 0.9 1.20 ΔC V = 0 V, F = 1 MHz, V = 30 mV 0.06 i/o-GND I/O OSC ΔC V = 0 V, F = 1 MHz, V = 30 mV 0.05 i/o-i/o I/O OSC 2/11

DSILC6-4xx Characteristics Figure 1. R elative variation of leakage Figure 2. Relative variation of leakage current versus junction current versus junction temperature - SOT-666 (typical temperature Flip-Chip (typical values) values) IRM[Tj] /IRM[Tj=25°C] IRM[Tj] /IRM[Tj=25°C] 100 100 VR= 5V VR= 5V 10 10 Tj(°C) Tj(°C) 1 1 25 50 75 100 125 25 50 75 100 125 F igure 3. Remaining voltage after Figure 4. Remaining voltage after DSILC6-4P6 during ESD DSILC6-4F2 during ESD 15 kV positive surge (air discharge) 15 kV positive surge (air discharge) V/div V/div 10 10 50 ns/div 50 ns/div F igure 5. Remaining voltage after Figure 6. Remaining voltage after DSILC6-4P6 during ESD DSILC6-4F2 during ESD 15 kV negative surge (air discharge) 15 kV negative surge (air discharge) V/div V/div 5 5 50 ns/div 50 ns/div 3/11

Characteristics DSILC6-4xx Figure 7. F requency responses of all lines Figure 8. Frequency response of all lines DSILC6-4P6 DSILC6-4F2 S21(dB) S21 (dB) 0.00 0.00 -5.00 -5.00 -10.00 -10.00 -15.00 -15.00 -20.00 F(Hz) F (Hz) -20.00 -25.00 100.0k 1.0M 10.0M 100.0M 1.0G 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G Line 1 Line 2 Line 1 Line 2 Line 3 Line 4 Line 3 Line 4 Figure 9. C rosstalk results for lines Figure 10. Crosstalk results for lines 1/2 and 1/3 DSILC6-4P6 1/2 and 1/3 DSILC6-4F2 S21(dB) S21 (dB) 0.00 0.00 -20.00 -20.00 -40.00 -40.00 -60.00 -60.00 -80.00 -80.00 -100.00 -100.00 -120.00 -120.00 F(Hz) F (Hz) -140.00 -140.00 100.0k 1.0M 10.0M 100.0M 1.0G 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G 3.0G Xtalk 1/2 Xtalk 1/3 Xtalk 1/2 Xtalk 1/3 4/11

DSILC6-4xx Application examples 2 Application examples 2.1 MDDI Lower Clamshell Upper Clamshell Hinge Analog Earpiece Audio Power Power DSILC6-4xx Data+ MDDI Data (Host) MDDI Client PRIMARY Data- & LCD LCD Controller Strobe+ MDDI Strobe (Host) Chip (With Strobe- Frame Base band IC Buffer) SECONDARY GND GND LCD 2.2 SMIA DSILC6-4xx DATA1+ DATA1- CLOCK+ CLOCK- SMIA device SCL SDA ESDALC6V1P3 5/11

Application examples DSILC6-4xx 2.3 Ethernet 1 Gb +5V SMP75-8 BI_DA+ BI_DA- SMP75-8 BI_DB+ BI_DB- DSILC6-4xx +5V DATATRANSCEIVER DSILC6-4xx SMP75-8 BI_DC+ BI_DC- SMP75-8 BI_DD+ BI_DD- 2.4 USB 2.0 DEVICE- + 3.3V + 5V HUB- UPSTREAM RPU Protecting DOWNSTREAM TRANSCEIVER USB Bus Switch TRANSCEIVER SW2 SW1 connector VBUS VBUS RX LS/FS+ VBUS RX LS/FS+ RXRT LXXS HH/FSSS++ - D+ RTRXXX HHLSSS/+F+S - RTXX HHSS -- D- RTXX HHSS -- TX LS/GFSND+ RS USBLC6-2SC6 GND RS TGXN LDS/FS+ TX LS/FS - RS RS TX LS/FS - RPD RPD DEVICE- + 3.3V UPSTREAM RPU TRANSCEIVER USB SW2 SW1 connector RRXXR TL LXXSVS /HHF/BFSSSUS+++S - VDB+US RRTRXXXX HLHLSSSS//+FF+SS -+ RTXX HHSS -- D- RTXX HHSS -- TX LS/GFSND+ RS USBLC6-2P6 GND DSILC6-4xx RS TGXN LDS/FS+ RS RS TX LS/FS - TX LS/FS - RPD RPD Mode SW1 SW2 Low Speed LS Open Closed Full Speed FS Closed Open High Speed HS Closed then open Open 6/11

DSILC6-4xx Ordering information scheme 3 Ordering information scheme DSI LC 6 - 4 xx Product Designation Low capacitance BreakdownVoltage 6 = 6Volts Number of lines protected 4 = 4 lines Packages P6 = SOT-666 F2 = Flip-Chip 7/11

Package information DSILC6-4xx 4 Package information ● Epoxy meets UL94, V0 T able 3. SOT-666 Dimensions Dimensions b1 Ref. Millimeters Inches L1 Min. Typ. Max. Min. Typ. Max. A 0.45 0.60 0.018 0.024 L3 A3 0.08 0.18 0.003 0.007 b b 0.17 0.34 0.007 0.013 D E1 b1 0.19 0.27 0.34 0.007 0.011 0.013 D 1.50 1.70 0.059 0.067 A E 1.50 1.70 0.059 0.067 L2 E A3 E1 1.10 1.30 0.043 0.051 e 0.50 0.020 L1 0.19 0.007 L2 0.10 0.30 0.004 0.012 e L3 0.10 0.004 F igure 11. SOT-666 footprint Figure 12. SOT-666 marking 0.50 G 0.62 2.60 0.99 0.30 8/11

DSILC6-4xx Package information Figure 13. Flip-Chip Dimensions 650 µm ± 65 500 µm ± 50 0 5 ± m µ m 0 µ 0 0 5 5 ± m m 7 5 1. 1.1 mm ± 50 µm 315 µm ± 50 Figure 14. Flip-Chip footprint Figure 15. Flip-Chip marking Copper pad Diameter : Dot, ST logo 220µm recommended xx = marking z = manufacturing location E Solder stencil opening : yww = datecode 330µmrecommended (y = year x x z ww = week) Solder mask opening recommendation : y w w 300µmrecommended Figure 16. Flip-Chip tape and reel specifications Dot identifying Pin A1 location Ø 1.5 +/- 0.1 4 +/- 0.1 1 .7 5 + /- 0 .1 3 .5 + 8 +/- 0.3 ywwxxz ST ywwxxz ST ywwxxz ST /- 0.1 E E E 0.73 +/- 0.05 4 +/- 0.1 User direction of unreeling All dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 9/11

Ordering information DSILC6-4xx 5 Ordering information Ordering code Marking Package Weight Base qty Delivery mode DSILC6-4P6 G SOT-666 2.9 mg 3000 Tape and reel DSILC6-4F2 EI Flip-Chip 2.22 mg 5000 Tape and reel 6 Revision history Date Revision Description of Changes 10-Aug-2006 1 Initial release. Added Flip-Chip package. Added applications examples for 04-Jan-2007 2 SMIA, Ethernet 1 Gb, and USB. Updated Tj max to 150. Added V line in Table 2. Modified MDDI example figure. RM Modified Functional diagram on page 1 to show Top side view instead of Bump side view of DSILC64F2. Removed V line in 28-May-2007 3 RM Table 2. Added characteristic curves specific to each package for ESD, Frequency response and Crosstalk 10/11

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