Rev 0; 6/06 Dual Log Audio Digital Potentiometer General Description Features D The DS1882 is a dual, nonvolatile (NV) digital poten- ♦ Dual, Audio Log Taper Potentiometers S tiometer designed to operate in audio systems that ♦ Low THD+N and Crosstalk 1 accomodate up to ±7V signal levels. The potentiometer ♦ ±7V Analog Supply (Independent of Digital 8 settings can be stored in EEPROM so that they are Supply) 8 retained when the power is cycled. The DS1882 has separate supplies for the potentiometers (VCC) and the ♦ 5V Digital Supply 2 communication circuitry (VDD). For clickless/popless ♦ Potentiometer Settings Configurable as operation, a zero-crossing detector allows the wiper Nonvolatile or Volatile position to change when there is no voltage across the ♦ Zero-Crossing Detector Eliminates Switching potentiometer. The DS1882 is also designed to mini- Noise mize crosstalk, and the two digital potentiometers pro- ♦ Two User-Configurable Attenuation Options vide 0.5dB channel-to-channel matching to prevent ♦ Configuration Option 1: 63 Positions Provide 1dB volume differences between channels. Total harmonic Attenuation Steps from 0dB to -62dB Plus Mute distortion (THD) is also minimal as long as the wiper drives a high-impedance load. ♦ Configuration Option 2: (Software-Compatible with the DS1808): 33 Positions Plus Mute as Two attenuation configuration options provide optimum Follows flexibility for the specific application. Configuration Positions 0–12: 1dB per Step for 12 Steps Option 1 provides 63 logarithmic tapered steps (0dB to Positions 13–24: 2dB per Step for 12 Steps -62dB, 1dB/step) plus a mute setting. Configuration Positions 25–32: 3dB per Step for 8 Steps Option 2 has 32 logarithmic steps plus mute and pro- ♦ I2C*-Compatible Serial Interface vides software compatibility with the DS1808. When Configuration Option 2 is used in combination with the ♦ Three Address Pins Allow Up to 8 Devices on 16-pin SO package, the DS1882 is both software and pin I2C Bus compatible with the DS1808 in 5V applications. ♦ 45kΩPotentiometer End-to-End Resistance ♦ Industrial Temperature Range (-40°C to +85°C) Applications ♦ 16-Pin TSSOP or SO Package Notebook and PC Audio Portable Audio Equipment Ordering Information Car Stereo TEMP VERSION PIN- Consumer Audio/Video PART RANGE (kΩ) PACKAGE Pin Configuration 16 TSSOP DS1882E-050+ -40°C to +85°C 45 (173 mils) TOP VIEW 16 TSS O P + GND 1 16 VDD DS1882E-050+T&R -40°C to +85°C 45 ( 173 mi l s) Tap e- and -R eel A2 2 15 VCC A1 3 14 SCL 16 SO DS1882Z-050+ -40°C to +85°C 45 ( 150 mi l s) V- 4 13 SDA A0 5 DS1882 12 CE 16 SO W0 6 11 W1 DS1882Z-050+T&R -40°C to +85°C 45 (1 50 mi l s ) Tap e- and -R eel L0 7 10 H1 +Denotes lead-free package. H0 8 9 L1 TSSOP/SO Typical Operating Circuit appears at end of data sheet. ______________________________________________Maxim Integrated Products 1 For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Dual Log Audio Digital Potentiometer 2 ABSOLUTE MAXIMUM RATINGS 8 Voltage on VDD, SDA, and SCL Relative to GND.....-0.5V to +6.0V Maximum Resistor Current.................................................±3mA 8 Voltage on A2, A1, A0, and CERelative Operating Temperature Range...........................-40°C to +85°C 1 to GND.................-0.5V to (VDD+ 0.5V), not to exceed +6.0V Programming Temperature Range.........................0°C to +70°C Voltage on VCCRelative to GND...........................-0.5V to +8.0V Storage Temperature Range.............................-55°C to +125°C S Voltage on H1, H0, W1, W0, L1, and L0 Relative Soldering Temperature...................See J-STD-020 Specification D to GND............................................(V- - 0.5V) to (VCC + 0.5V) Voltage on V- Relative to GND..............................-8.0V to +0.5V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (TA= -40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Supply Voltage VDD (Notes 1, 2) 4.5 5.5 V Analog Supply Range VCC (Notes 1, 2) 4.5 7.0 V Negative Supply Voltage V- (Notes 1, 2) -7.0 -4.5 V Potentiometer Voltages -V VCC V Wiper Current ±1 mA DC ELECTRICAL CHARACTERISTICS (VDD= +4.5V to +5.5V, VCC= +4.5V to +7.0V, V- = -4.5V to -7.0V, TA= -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Supply Current IDD (Note 3) 0.2 5 µA Analog Supply Current ICC (Note 4) 2.5 10 µA Input Logic 0 0.15 x VIL (Note 5) -0.3 V (CE, SDA, SCL, A0, A1, A2) VDD Input Logic 1 0.8 x VDD + VIH (Note 5) V (CE, SDA, SCL, A0, A1, A2) VDD 0.3 IOL = 4mA 0.4 Output-Voltage Low (SDA) VOL V IOL = 6mA 0.6 Input Leakage Current ILI -1 +1 µA I/O Pin Input Current (SDA) 0.4V < VSDA < (0.9 x VDD) -10 +10 µA I/O Capacitance CI/O (Note 6) 10 pF Power-Up Time tPU 1 ms 2 _____________________________________________________________________

Dual Log Audio Digital Potentiometer ANALOG POTENTIOMETER CHARACTERISTICS D (VDD= +4.5V to +5.5V, VCC= +4.5V to +7.0V, V- = -4.5V to -7.0V, TA= -40°C to +85°C.) S PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 End-to-End Resistance REE +25°C 45 kΩ 8 8 End-to-End Resistance Tolerance +25°C -20 +20 % 2 Ratiometric Temperature Coefficient (Note 6) 30 ppm/°C End-to-End Resistance Temperature (Note 6) 750 ppm/°C Coefficient Wiper Resistance RW 160 250 Ω Absolute Attenuation Tolerance (Note 7) -0.5 +0.5 dB Mute Position Attenuation 100 dB Step Size Deviation from Nominal (Note 7) -0.25 +0.25 dB Interchannel Matching (Note 7) -0.5 +0.5 dB -3dB Cutoff Frequency 10pF load 5 MHz 20Hz to 20kHz, grounded input, Output Noise 2.2 µVRMS tap = -6dB Crosstalk 1kHz, grounded input, tap = -6dB -120 dB 1kHz, tap = -6dB, CL = 10pF THD+N 0.005 % (Note 8) Zero-Crossing Detection tZCD 38 50 ms I2C CHARACTERISTICS (See Figure 4) (VDD= +4.5V to +5.5V, VCC= +4.5V to +7.0V, V- = -4.5V to -7.0V, TA= -40°C to +85°C. Timing referenced to VIL(MAX)and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency fSCL (Note 9) 0 400 kHz Bus Free Time Between STOP and tBUF 1.3 µs START Conditions Hold Time (Repeated) START Condition tHD:STA 0.6 µs Low Period of SCL tLOW 1.3 µs High Period of SCL tHIGH 0.6 µs Data Hold Time tHD:DAT 0 0.9 µs Data Setup Time tSU:DAT 200 ns START Setup Time tSU:STA 0.6 µs 20 + SDA and SCL Rise Time tR (Note 10) 300 ns 0.1CB 20 + SDA and SCL Fall Time tF (Note 10) 300 ns 0.1CB STOP Setup Time tSU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 10) 400 pF EEPROM Write Time tW (Note 11) 5 10 ms _____________________________________________________________________ 3

Dual Log Audio Digital Potentiometer 2 NV MEMORY CHARACTERISTICS 8 (VDD= +4.5V to +5.5V, VCC= +4.5V to +7.0V, V- = -4.5V to -7.0V, TA= 0°C to +70°C.) 8 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1 Writes +70°C (Note 6) 50,000 S D Note 1: All voltages are referenced to ground. Note 2: The value of VDDshould never exceed VCC, including during power-ups. VCCmust be applied before VDD. Note 3: IDDis specified with SDA = SCL = CE= VDD, resistor pins floating, and digital inputs connected to VDDor GND. Note 4: ICCis specified with SDA = SCL = CE= VDD, resistor pins floating, and digital inputs connected to VDDor GND, after zero- crossing detection has timed out. Note 5: The DS1882 will not obstruct the SDA and SCL lines if VDDis switched off as long as the voltages applied to these inputs do not violate their minimum and maximum input voltage levels. Note 6: Guaranteed by design. Note 7: Above Position 50, these are typical maximum. Guaranteed by characterization. Note 8: Load is representative of the input of a low-noise audio amp. Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard-mode timing. Note 10: CB—Total capacitance of one bus line in picofarads. Note 11: If zero-crossing detection is enabled, the EEPROM write does not begin until the current zero-crossing detection is com- plete. Otherwise, EEPROM write begins after a STOP condition occurs. Typical Operating Characteristics (VDD= VCC= +5.0V, V- = -5.0V, TA= +25°C.) POTENTIOMETER 0 (CONFIGURATON 1) POTENTIOMETER 0 (CONFIGURATON 2) POTENTIOMETER 1 (CONFIGURATON 1) ATTENUATION vs. SETTING ATTENUATION vs. SETTING ATTENUATION vs. SETTING 0 0 0 -20.0 DS1882 toc01 -20.0 DS1882 toc02 -20.0 DS1882 toc03 B) B) B) d d d N (-40.0 N (-40.0 N (-40.0 O O O TI TI TI A A A U U U N N N E-60.0 E-60.0 E-60.0 T T T T T T A A A -80.0 -80.0 -80.0 -100.0 -100.0 -100.0 0 9 18 27 36 45 54 63 0 3 6 9 12 15 18 21 24 27 30 33 0 9 18 27 36 45 54 63 SETTING (DEC) SETTING (DEC) SETTING (DEC) 4 _____________________________________________________________________

Dual Log Audio Digital Potentiometer Typical Operating Characteristics (continued) D (VDD= VCC= +5.0V, V- = -5.0V, TA= +25°C.) S 1 POTENTIOMETER 1 (CONFIGURATON 2) END-TO-END RESISTANCE PERCENT 8 ATTENUATION vs. SETTING CHANGE FROM +25°C vs. TEMPERATURE RESISTANCE vs. POWER-UP VOLTAGE 8 -20.00 DS1882 toc04 °25C) 33445.....05050 DS1882 toc05 18000 HIGH IMPEDANCE DS1882 toc06 2 M + 2.5 ATTENUATION (dB)--6400..00 CE % CHANGE (FRO ----21100112........050505050 POTENTIOMETER 1 ΩRESISTANCE (k) 4600 PRRESOIGSRTAANMCMEE (D6dBh) N A -2.5 -80.0 ST -3.0 20 RESI --43..05 POTENTIOMETER 0 MUTE -4.5 -100.0 -5.0 0 0 3 6 9 12 15 18 21 24 27 30 33 -40 -20 0 20 40 60 80 0 1 2 3 4 5 SETTING (DEC) TEMPERATURE (°C) POWER-UP VOLTAGE (V) RESISTANCE vs. POWER-DOWN VOLTAGE ICC vs. ZERO-CROSSING TIMING 18000 HIGH IMPEDANCE DS1882 toc07 1890000000 ZERO-CROSSING ZERO-CROSSING DS1882 toc08 DETECTION TIMEOUT OR ZERO- 700 Ω) ACTIVATED CROSSING EVENT SISTANCE (k 4600 PROGRAMMED µI (A)CC 456000000 RE RESISTANCE (6dBh) 300 TYPICAL TIMEOUT 20 200 OF 50ms MUTE 100 0 0 0 1 2 3 4 5 TIME (ms) POWER-DOWN VOLTAGE (V) THD+N vs. FREQUENCY (0dB) CROSSTALK vs. FREQUENCY (-6dB) 00..00001168 DS1882 toc09 -200 DS1882 toc10 0.0014 -40 THD+N (%) 000...000000011802 ROSSTALK (dB)-1--860000 0.0006 C -120 0.0004 0.0002 -140 0 -160 0.01 0.10 1.00 10.00 100.00 0.01 0.10 1.00 10.00 100.00 FREQUENCY (kHz) FREQUENCY (kHz) _____________________________________________________________________ 5

Dual Log Audio Digital Potentiometer 2 Pin Description 8 8 PIN NAME FUNCTION 1 1 GND Ground S 2 A2 I2C Address Inputs. Inputs A0, A1, and A2 determine the I2C slave address of the device. D 3 A1 4 V- Negative Analog Voltage Supply 5 A0 I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 6 W0 Wiper Terminal for Potentiometer 0 7 L0 Low Terminal for Potentiometer 0 8 H0 High Terminal for Potentiometer 0 9 L1 Low Terminal for Potentiometer 1 10 H1 High Terminal for Potentiometer 1 11 W1 Wiper Terminal for Potentiometer 1 12 CE Chip Enable. Enables SDA and SCL pins for I2C communication. 13 SDA I2C Serial-Data Open-Drain I/O 14 SCL I2C Serial-Clock Input 15 VCC Analog Voltage Supply 16 VDD Digital Voltage Supply Block Diagram VDD VCC SDA SCL CONFIGURATION VCC A2 I2C REGISTER VDD GND A1 INTERFACE POTENTIOMETER V- A0 SETTING CE REGISTERS DS1882 GND V- POTENTIOMETER 0 POTENTIOMETER 1 DECODER VALUE VALUE H0 H1 W0 W1 ZERO-CROSSING ZERO-CROSSING L0 DETECTOR DETECTOR L1 UPDATE UPDATE 6 _____________________________________________________________________

Dual Log Audio Digital Potentiometer Detailed Description Table 1. Configuration Option 1 D The DS1882 is a dual-channel, digitally controlled, S TAP POSITION ATTENUATION (dB) audio potentiometer. The Block Diagram illustrates the 1 0 0 features of the DS1882. The following sections discuss 8 these features in detail. 1 1 8 2 2 Potentiometer Configurations 2 3 3 The DS1882 potentiometers have two possible attenua- tion configuration options. The Configuration Register 4 4 section discusses how to change between the two 5 5 options. Note that both potentiometers are always set to 6 6 the same option. 7 7 The factory default for both potentiometers is Option 1 8 8 (see Table 1). Option 1 provides 64 positions with 1dB attenuation per step for positions 0 through 62 and … … mute as position 63. Option 2 (see Table 2) is a 34- 40 40 position configuration. From position 0, the first 12 41 41 steps have 1dB attenuation per step, the next 12 have 42 42 2dB attenuation per step, and the following 8 steps have 3dB attenuation per step. The last position, posi- 43 43 tion 33, is the mute setting. 44 44 45 45 Zero-Crossing Detection Zero-crossing detection is a user-selectable feature 46 46 used to help eliminate clicking or popping noises dur- 47 47 ing changes of potentiometer settings. See the 48 48 Configuration Register section to learn how to enable 49 49 the zero-crossing detection feature. 50 50 After the I2C master issues a command to change the 51 51 wiper position and the DS1882 has responded with an acknowledge (ACK) to the command, the DS1882 has 52 52 a 50ms window to change the wiper position. The 53 53 DS1882 constantly monitors the voltage of the high and 54 54 low terminals of both potentiometers. During the 50ms 55 55 window, if the zero-crossing detection is enabled, then each potentiometer’s wiper will change position if the 56 56 high and low terminals of the same potentiometer 57 57 become equal in potential (i.e., the magnitude of the 58 58 input signal is zero). If a zero-crossing event does not 59 59 occur within the 50ms window, then the wiper is allowed to change to the new position regardless of the 60 60 state of the input signal. When the zero-crossing detec- 61 61 tion feature is not enabled, the DS1882 will allow wiper 62 62 movement as soon as the DS1882 has issued the 63 90 acknowledge to the master-controlling device. _____________________________________________________________________ 7

Dual Log Audio Digital Potentiometer 2 Table 2. Configuration Option 2 Command Byte The Command Byte determines both the potentiometer 8 TAP POSITION ATTENUATION (dB) wiper settings and the configuration of both poten- 8 0 0 tiometers. This is done by setting the two MSBs of the 1 Command Byte to one of three values. If 00 is set as 1 1 S the value for the two MSBs, then the wiper setting for 2 2 D Potentiometer 0 is to be programmed. If 01 is set as the 3 3 value, then the wiper setting of Potentiometer 1 is to be 4 4 programmed. See the Potentiometer Wiper Setting sec- tion for more details about writing the wiper setting. A 5 5 value of 10 indicates that the Configuration Register is 6 6 to be programmed. A value of 11 is reserved and is not 7 7 to be used. See the Configuration Register section for 8 8 more information. Any values other than the three dis- cussed above will result in no action by the part. See 9 9 below for the Command Byte structure. 10 10 11 11 Command Byte Structure 12 12 13 14 CONFIGURATION REGISTER 14 16 SELECTION SETTINGS 15 18 16 20 17 22 18 24 MSB LSB 19 26 20 28 21 30 22 32 23 34 24 36 25 39 26 42 27 45 28 48 29 51 30 54 31 57 32 60 33 90 8 _____________________________________________________________________

Dual Log Audio Digital Potentiometer Potentiometer Wiper Setting the Command Byte are then used to store the wiper D If 00 or 01 are the values of the two MSBs of the settings for the selected potentiometer. See below for S Command Byte, then the wiper settings of the poten- the potentiometer wiper setting details. tiometers are to be programmed. The lower 6 LSBs of 1 8 8 POTENTIOMETER WIPER REGISTER 2 Factory Default: XX111111b Memory Type: NV (EEPROM) 0 X WIPER SETTING b7 b6 b5 b4 b3 b2 b1 b0 Configuration Selection: Selects which potentiometer will be programmed. bits 7, 6 00 = Potentiometer 0 will be programmed. 01 = Potentiometer 1 will be programmed. These bits determine the wiper setting of the selected potentiometer. Available wiper settings are determined by bits 5–0 the attenuation option as described in the Configuration Register section. _____________________________________________________________________ 9

Dual Log Audio Digital Potentiometer 2 Configuration Register Register control the NV/volatile wiper setting, the zero- If 10 is entered as the value of the two MSBs of the crossing detection feature, and the potentiometer atten- 8 Command Byte, then the Configuration Register is to uation configuration. 8 be modified. The three LSBs of the Configuration 1 S CONFIGURATION REGISTER D Factory Default: 87h Memory Type: NV (EEPROM) V/NV ZERO- POT 1 0 X X X CONTROL CROSSING CONFIG b7 b6 b5 b4 b3 b2 b1 b0 Configuration Selection: When bit 7 is set to a 1 and bit 6 is set to a 0, the following configuration bits can be set bits 7, 6 and stored in EEPROM. bits 5, 4, 3 These bits have no function. Volatile/Nonvolatile Potentiometer Register Control Bit: A control bit that sets the potentiometer registers to be either volatile or nonvolatile memory. bit 2 0 = Potentiometer registers are set to nonvolatile memory storage. 1 = Potentiometer registers are set to volatile memory storage. On power-up, the potentiometer wipers are in the mute position (default). Zero-Crossing Detection Enable Bit: A bit used to enable and disable the zero-crossing functionality. bit 1 0 = Zero-crossing detection is disabled. 1 = Zero-crossing detection is enabled (default). Potentiometer Position Configuration: A control bit used to select the number of positions both potentiometers have. bit 0 0 = Potentiometers have 63 positions and mute. 1 = Potentiometers have 33 positions and mute (default). 10 ____________________________________________________________________

Dual Log Audio Digital Potentiometer I2C Interface for the DS1882 the DS1882 is allowed to receive communications from D The CE pin serves as a communication enable pin. the I2C bus. S When active (CE= 0), the inputs SDA and SCL are rec- The I2C slave address byte is shown below. This is the ognized by the device. If inactive (CE = 1), pins SDA 1 first byte transmitted from the master to the DS1882. and SCL are disabled, making I2C communication 8 The upper nibble value is fixed to 0101. Bit values A2, impossible. A1, and A0 are determined by the states of the corre- 8 Three pins, A0, A1, A2, serve as slave address inputs. sponding pins. The LSB, R/W, determines whether a 2 For multidrop configurations, they allow eight such read or write will be performed. devices to be addressed by the same I2C bus. If the The next byte to be transmitted is the Command Byte I2C address matches the hardware levels of these bits, (see the Command Bytesection for details). SLAVE ADDRESS BYTE 0 1 0 1 A2 A1 A0 R/W MSB LSB Reading Pot Values of Potentiometer 0 is the first returned from the DS1882. As shown in Figure 1, the DS1882 provides one read It is then followed by the value of Potentiometer 1 and command operation. This operation allows the user to then the value of the Configuration Register. Once the 8 read both Potentiometer Wiper Setting Registers and bits of the Configuration Register have been sent, the the Configuration Register. To initiate a read operation, master needs to issue an acknowledge, unless it is the the R/W bit of the slave address byte is set to 1. last byte to be read, in which case the master issues a Communication to read the DS1882 begins with a not acknowledge. If desired, the master may stop the START condition, which is issued by the master device. communication transfer at this point by issuing the The slave address byte sent from the master device fol- STOP condition after the not acknowledge. However, if lows the START condition. Once a matching slave the value of the three registers is needed again, the address byte has been received by the DS1882, the transfer can continue by clocking the 8 bits of the DS1882 responds with an acknowledge. The master Potentiometer 0 value as described above. can then begin to receive data. The value of the wiper READ PROTOCOL SLAVE ADDRESS COMMAND COMMAND COMMAND BYTE BYTE BYTE BYTE MSB LSB MSB LSB MSB LSB MSB LSB START 0 1 0 1 A2 A1 A0 1 ACK 0 0 POT-0 ACK 0 1 POT-1 ACK 1 0 CORNEGFIG NACK STOP R/W = 1 DATA BYTES ARE READ IN THE ORDER SHOWN ABOVE. Figure1. Read Protocol ____________________________________________________________________ 11

Dual Log Audio Digital Potentiometer 2 Writing Command Byte Values I2C Definitions An example of writing to the DS1882 is shown in Figure 2. Master Device: The master device controls the slave 8 The DS1882 has one write command that is used to devices on the bus. The master device generates SCL 8 change the Potentiometer Wiper Setting Registers and clock pulses, START and STOP conditions. 1 the Configuration Register. All write operations begin with Slave Devices: Slave devices send and receive data S a START from the master, followed by a slave address at the master’s request. D byte. The R/W bit should be written to 0, which initiates Bus Idle or Not Busy:Time between STOP and START a write command. Once the slave address byte has conditions when both SDA and SCL are inactive and in been issued and the master receives the acknowledge their logic-high states. When the bus is idle it often initi- from the DS1882, potentiometer wiper data is transmit- ates a low-power mode for slave devices. ted to the DS1882 by the master device. START Condition: A START condition is generated by If the potentiometer has been configured to be written the master to initiate a new data transfer with a slave. in nonvolatile memory (see the Configuration Register Transitioning SDA from high to low while SCL remains section), then the acknowledge needs to be followed high generates a START condition. See the timing dia- with a STOP command. This command is required from gram for applicable timing. the master at the end of data transmission to initiate the EEPROM write. The STOP command is also accepted if STOP Condition: A STOP condition is generated by the user has configured the pot values to be written in the master to end a data transfer with a slave. volatile memory, but no EEPROM is written to. Transitioning SDA from low to high while SCL remains I2C Serial Interface Description high generates a STOP condition. See the timing dia- gram for applicable timing. I2C interface supports a bidirectional data transmission Repeated START Condition: The master can use a protocol with device addressing. A device that sends repeated START condition at the end of one data trans- data on the bus is defined as a transmitter, and a fer to indicate that it will immediately initiate a new data device receiving data as a receiver. The device that transfer following the current one. Repeated STARTs controls the message is called a master. The devices are commonly used during read operations to identify a that are controlled by the master are slaves. The bus specific memory address to begin a data transfer. A must be controlled by a master device that generates repeated START condition is issued identically to a nor- the serial clock (SCL), controls the bus access, and mal START condition. See the timing diagram for generates the START and STOP conditions. The applicable timing. DS1882 operates as a slave on the I2Cbus. Connections Bit Write: Transitions of SDA must occur during the low to the bus are made by the open-drain I/O lines, SDA and SCL. The following I/O terminals control the I2C state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the serial port: CE, SDA, SCL, A0, A1, and A2. A data setup and hold-time requirements (see Figure 4). Data is transfer protocol and a timing diagram are provided in shifted into the device during the rising edge of the SCL. Figures 3 and 4. The following terminology is commonly used to describe I2C data transfers. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of WRITE PROTOCOL SLAVE ADDRESS COMMAND COMMAND COMMAND BYTE BYTE BYTE BYTE MSB LSB MSB LSB MSB LSB MSB LSB START 0 1 0 1 A2 A1 A0 0 ACK 0 0 POT-0 ACK 0 1 POT-1 ACK 1 0 CORNEGFIG ACK STOP R/W = 0 DATA BYTES CAN BE WRITTEN IN ANY ORDER. Figure2. Write Protocol 12 ____________________________________________________________________

Dual Log Audio Digital Potentiometer setup time (see Figure 4) before the next rising edge of receiving data (the master during a read or the slave D SCL during a bit read. The device shifts out each bit of during a write operation) performs an ACK by transmit- S data on SDA at the falling edge of the previous SCL ting a zero during the 9th bit. A device performs a pulse, and the data bit is valid at the rising edge of the NACK by transmitting a one during the 9th bit. Timing 1 current SCL pulse. Remember that the master gener- (Figure 4) for the ACK and NACK is identical to all other 8 ates all SCL clock pulses, including when it is reading bit writes. An ACK is the acknowledgment that the 8 bits from the slave. device is properly receiving data. A NACK is used to 2 terminate a read sequence or as an indication that the Acknowledgement (ACK and NACK):An Acknowledge- device is not receiving data. ment (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device SDA MSB SLAVE ADDRESS R/W ACKNOWLEDGEMENT DIRECTION SIGNAL FROM RECEIVER BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 9 ACK ACK START STOP CONDITION CONDITION REPEATED IF MORE BYTES OR REPEATED ARE TRANSFERRED START CONDITION Figure3. Data Transfer Protocol SDA tBUF tHD:STA tSP tLOW tR tF SCL tHD:STA tHIGH tSU:STA STOP START tSU:DAT REPEATED tSU:STO START tHD:DAT NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN). Figure4. I2C Timing Diagram ____________________________________________________________________ 13

Dual Log Audio Digital Potentiometer 2 Byte Write: A byte write consists of 8 bits of informa- Writing Multiple Bytes to a Slave: To write multiple tion transferred from the master to the slave (most sig- bytes to a slave, the master generates a START condi- 8 nificant bit first) plus a 1-bit acknowledgement from the tion, writes the slave address byte (R/W= 0), writes the 8 slave to the master. The 8 bits transmitted by the mas- desired number of data bytes and generates a STOP 1 ter are done according to the bit write definition and the condition. The DS1882 is capable of writing both poten- S acknowledgement is read using the bit read definition. tiometer wiper settings and the Configuration Register D Byte Read: A byte read is an 8-bit information transfer with a single write transaction. from the slave to the master plus a 1-bit ACK or NACK Acknowledge Polling: Any time an EEPROM location from the master to the slave. The 8 bits of information is written, the DS1882 requires the EEPROM write time that are transferred (most significant bit first) from the (tW) after the STOP condition to write the contents of slave to the master are read by the master using the bit the byte of data to EEPROM. During the EEPROM write read definition, and the master transmits an ACK using time, the device will not acknowledge its slave address the bit write definition to receive additional data bytes. because it is busy. It is possible to take advantage of The master must NACK the last byte read to terminate that phenomenon by repeatedly addressing the communication so the slave will return control of SDA to DS1882, which allows the next page to be written as the master. soon as the DS1882 is ready to receive the data. The Slave Address Byte: Each slave on the I2C bus alternative to acknowledge polling is to wait for a maxi- responds to a slave addressing byte sent immediately mum period of tW to elapse before attempting to write again to the device. following a START condition. The slave address byte (Figure 5) contains the slave address in the most signif- EEPROM Write Cycles: When EEPROM writes occur to icant 7 bits and the R/Wbit in the least significant bit. the memory, the DS1882 will write to all three EEPROM memory locations, even if only a single byte was modi- The DS1882’s slave address is 0101 A2 A1 A0 (binary), fied. Because all three bytes are written, the bytes that where A2, A1, and A0 are the values of the address were not modified during the write transaction are still pins. The address pins allow the device to respond to subject to a write cycle. This can result in all three bytes one of eight possible slave addresses. By writing the being worn out over time by writing a single byte repeat- correct slave address with R/W = 0, the master indi- edly. The DS1882’s EEPROM write cycles are specified in cates it will write data to the slave. If R/W = 1, the mas- the NV Memory Characteristics table. The specification ter will read data from the slave. If an incorrect slave shown is at the worst-case temperature. If zero-crossing address is written, the DS1882 will assume the master is communicating with another I2C device and ignore the detection is enabled, EEPROM write cycles cannot begin until after the zero-crossing detection is complete. communications until the next START condition is sent. Reading a Single Byte from a Slave: To read a single I2C Communication byte from the slave, the master generates a START con- Writing a Single Byte to a Slave: The master must dition, writes the slave address byte with R/W= 1, reads generate a START condition, write the slave address the data byte with a NACK to indicate the end of the byte (R/W = 0), write the byte of data, and generate a transfer, and generates a STOP condition. When a single STOP condition. The master must read the slave’s byte is read, it will always be the Potentiometer 0 value. acknowledgement during all byte write operations. Reading Multiple Bytes from a Slave: The read oper- ation can be used to read multiple bytes with a single DETERMINES transfer. When reading bytes from the slave, the master READ OR WRITE simply ACKs the data byte if it desires to read another 7-BIT SLAVE FUNCTION byte before terminating the transaction. After the mas- ADDRESS ter reads the last byte, it NACKs to indicate the end of the transfer and generates a STOP condition. The first 0 1 0 1 A2 A1 A0 R/W byte read will be the Potentiometer 0 Wiper Setting. The next byte will be the Potentiometer 1 Wiper Setting. The MSB LSB third byte is the Configuration Register byte. If an ACK is issued by the master following the Configuration A2, A1, AND A0 Register byte, then the DS1882 will send the PIN VALUES Potentiometer 0 Wiper Setting again. This round robin reading will occur as long as each byte read is followed Figure5. DS1882’s Slave Address Byte by an ACK from the master. 14 ____________________________________________________________________

Dual Log Audio Digital Potentiometer Applications Information SDA and SCL Pullup Resistors D SDA is an open-collector output on the DS1882 that S Power-Supply Decoupling requires a pullup resistor to realize high logic levels. A To achieve best results, it is recommended that the master using either an open-collector output with a 1 power supplies are decoupled with a 0.01µF or a 0.1µF pullup resistor or a push-pull output driver can be uti- 8 capacitor. Use high-quality, ceramic, surface-mount lized for SCL. Pullup resistor values should be chosen 8 capacitors, and mount the capacitors as close as pos- to ensure that the rise and fall times listed in the AC 2 sible to the voltage supplies and GND pins to minimize Electrical Characteristicstable are within specification. lead inductance. Typical Operating Circuit 5V (VDD) 5V (VCC) VDD VCC DECOUPLING DECOUPLING 4.7kΩ 4.7kΩ CAPACITOR CAPACITOR GND SDA HOST SCL µC CE DS1882 H1 W1 A2 L1 AUDIO A1 OUT A0 H0 W0 -5V (V-) L0 V- DECOUPLING AUDIO IN CAPACITOR Chip Topology Package Information TRANSISTOR COUNT: 52,353 For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. SUBSTRATE CONNECTED TO GROUND Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________15 © 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation. Springer

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