CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Data sheet acquired from Harris Semiconductor SCHS183C High-Speed CMOS Logic Octal D-Type Flip-Flop, February 1998 - Revised May 2004 3-State Positive-Edge Triggered Features Description • Buffered Inputs The’HC374,’HCT374,’HC574,and’HCT574areoctalD-type flip-flops with 3-state outputs and the capability to drive 15 [ /Title • Common Three-State Output Enable Control LSTTLloads.Theeightedge-triggeredflip-flopsenterdatainto (CD74 • Three-State Outputs theirregistersontheLOWtoHIGHtransitionofclock(CP).The HC374 output enable (OE) controls the 3-state outputs and is • Bus Line Driving Capability independent of the register operation. When OE is HIGH, the , • Typical Propagation Delay (Clock to Q) = 15ns at outputsareinthehigh-impedancestate.The374and574are CD74 VCC = 5V, CL = 15pF, TA = 25oC identicalinfunctionanddifferonlyintheirpinoutarrangements. HCT37 • Fanout (Over Temperature Range) Ordering Information 4, - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads CD74 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads TEMP. RANGE HC574 PART NUMBER (oC) PACKAGE • Wide Operating Temperature Range . . .-55oC to 125oC , CD54HC374F3A -55 to 125 20 Ld CERDIP CD74 • Balanced Propagation Delay and Transition Times CD54HC574F3A -55 to 125 20 Ld CERDIP HCT57 • Significant Power Reduction Compared to LSTTL CD54HCT374F3A -55 to 125 20 Ld CERDIP Logic ICs CD54HCT574F3A -55 to 125 20 Ld CERDIP CD74HC374E -55 to 125 20 Ld PDIP • HC Types CD74HC374M -55 to 125 20 Ld SOIC - 2-V to 6-V Operation CD74HC374M96 -55 to 125 20 Ld SOIC - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC574E -55 to 125 20 Ld PDIP at VCC = 5V CD74HC574M -55 to 125 20 Ld SOIC • HCT Types CD74HC574M96 -55 to 125 20 Ld SOIC - 4.5-V to 5.5-V Operation CD74HCT374E -55 to 125 20 Ld PDIP - Direct LSTTL Input Logic Compatibility, CD74HCT374M -55 to 125 20 Ld SOIC VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT374M96 -55 to 125 20 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT574E -55 to 125 20 Ld PDIP CD74HCT574M -55 to 125 20 Ld SOIC CD74HCT574M96 -55 to 125 20 Ld SOIC CD74HCT574PWR -55 to 125 20 Ld TSSOP NOTE: Whenordering,usetheentirepartnumber.Thesuffixes 96and R denote tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated 1

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Pinouts CD54HC574, CD54HCT574 (CERDIP) CD54HC374, CD54HCT374 CD74HC574 (CERDIP) (PDIP, SOIC) CD74HC374, CD74HCT374 CD74HCT574 (PDIP, SOIC) (PDIP, SOIC, TSSOP) TOP VIEW TOP VIEW OE 1 20 VCC OE 1 20 VCC Q0 2 19 Q7 D0 2 19 Q0 D0 3 18 D7 D1 3 18 Q1 D1 4 17 D6 D2 4 17 Q2 Q1 5 16 Q6 D3 5 16 Q3 Q2 6 15 Q5 D4 6 15 Q4 D2 7 14 D5 D5 7 14 Q5 D3 8 13 D4 D6 8 13 Q6 Q3 9 12 Q4 D7 9 12 Q7 GND 10 11 CP GND 10 11 CP Functional Diagram D0 D1 D2 D3 D4 D5 D6 D7 D D D D D D D D CPQ CPQ CP Q CPQ CPQ CPQ CPQ CPQ CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 TRUTH TABLE INPUTS OUTPUT OE CP Dn Qn L ↑ H H L ↑ L L L L X Q0 H X X Z H = High Level (Steady State) L = Low Level (Steady State) X= Don’t Care ↑= Transition from Low to High Level Q0= The level of Q before the indicated steady-state input conditions were established Z = High Impedance State 2

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . .θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 DC Output Diode Current, IOK PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC DC Drain Current, per Output, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC Output Source or Sink Current per Output Pin, IO (SOIC - Lead Tips Only) For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyrating,andoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -6 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -7.8 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 6 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 7.8 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND 3

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND Three-StateLeakage VIL or VIH VO=VCC - 6 - - ±0.5 - ±5.0 - ±10 µA Current or GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage CMOS Loads High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCCand 0 5.5 - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Three-StateLeakage VIL or VIH VO=VCC - 6 - - ±0.5 - ±5.0 - ±10 µA Current or GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems, theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS INPUT HCT374 HCT574 D0 - D7 0.3 0.4 CP 0.9 0.75 OE 1.3 0.6 NOTE: UnitLoadis∆ICClimitspecificinDCElectricalSpecifications Table, e.g., 360µA max. at 25oC. 4

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Prerequisite for Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC(V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Maximum Clock fMAX 2 6 - - 5 - - 4 - - MHz Frequency 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz Clock Pulse Width tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns Setup Time tSU 2 60 - - 75 - - 90 - - ns Data to Clock 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns Hold Time tH 2 5 - - 5 - - 5 - - ns Data to Clock 4.5 5 - - 5 - - 5 - - ns 6 5 - - 5 - - 5 - - ns HCT TYPES Maximum Clock fMAX 4.5 30 - - 25 - - 20 - - MHz Frequency Clock Pulse Width tW 4.5 16 - - 20 - - 24 - - ns Setup Time tSU 4.5 12 - - 15 - - 18 - - ns Data to Clock Hold Time tH 4.5 5 - - 5 - - 5 - - ns Data to Clock Switching Specifications CL = 50pF, Input tr, tf= 6ns -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPLH, tPHL CL = 50pF Clock to Output 2 - - 165 - 205 - 250 ns 4.5 - - 33 - 41 - 50 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 28 - 35 - 43 ns Output Disable to Q tPLZ,tPHZ CL = 50pF 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 23 - 29 - 35 ns 5

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued) -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS Output Enable to Q tPZL,tPZH CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns Maximum Clock Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Output Transition Time tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output CO - - 20 - 20 - 20 - 20 pF Capacitance Power Dissipation Capacitance CPD CL = 15pF 5 - 39 - - - - - pF (Notes 3, 4) HCT TYPES Propagation Delay tPHL,tPLH Clock to Output CL = 50pF 4.5 - - 33 - 41 - 50 ns CL = 15pF 5 - 15 - - - - - ns Output Disable to Q tPLZ,tPHZ CL = 50pF 4.5 - - 28 - 35 - 42 ns CL = 15pF 5 - 11 - - - - - ns Output Enable to Q tPZL,tPZH CL = 50pF 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns Maximum Clock Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output CO - - 20 - 20 - 20 - 20 pF Capacitance Power Dissipation Capacitance CPD CL = 15pF 5 - 47 - - - - - pF (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD=CPDVCC2fi+∑VCC2fOCLwherefi=InputFrequency,fO=OutputFrequency,CL=OutputLoadCapacitance,VCC=Supply Voltage. 6

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCTRANSITIONTIMESANDPROPAGATION FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 Test Circuits and Waveforms (Continued) 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE7. HCTHREE-STATEPROPAGATIONDELAY FIGURE8. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8974201RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8974201RA CD54HCT574F3A CD54HC374F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407101RA CD54HC374F3A CD54HC574F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC574F CD54HC574F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC574F3A CD54HCT374F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8550701RA CD54HCT374F3A CD54HCT574F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT574F CD54HCT574F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8974201RA CD54HCT574F3A CD74HC374E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC374E (RoHS) CD74HC374M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC374M & no Sb/Br) CD74HC374M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC374M & no Sb/Br) CD74HC374M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC374M & no Sb/Br) CD74HC574E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC574E (RoHS) CD74HC574M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC574M & no Sb/Br) CD74HC574M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC574M & no Sb/Br) CD74HC574M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC574M & no Sb/Br) CD74HC574M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC574M & no Sb/Br) CD74HCT374E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT374E (RoHS) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HCT374EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT374E (RoHS) CD74HCT374M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT374M & no Sb/Br) CD74HCT374M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT374M & no Sb/Br) CD74HCT574E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT574E (RoHS) CD74HCT574M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M & no Sb/Br) CD74HCT574M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M & no Sb/Br) CD74HCT574M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M & no Sb/Br) CD74HCT574ME4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT574M & no Sb/Br) CD74HCT574PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK574 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC374, CD54HC574, CD54HCT374, CD54HCT574, CD74HC374, CD74HC574, CD74HCT374, CD74HCT574 : •Catalog: CD74HC374, CD74HC574, CD74HCT374, CD74HCT574 •Automotive: CD74HCT574-Q1, CD74HCT574-Q1 •Enhanced Product: CD74HCT574-EP, CD74HCT574-EP •Military: CD54HC374, CD54HC574, CD54HCT374, CD54HCT574 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC374M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CD74HC574M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CD74HCT374M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CD74HCT574M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CD74HCT574PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC374M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HC574M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT374M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT574M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT574PWR TSSOP PW 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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