SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 • Contains Eight Flip-Flops With Single-Rail SN54273, SN74LS273...J OR W PACKAGE Outputs SN74273...N PACKAGE • SN74LS273...DW OR N PACKAGE Buffered Clock and Direct Clear Inputs (TOP VIEW) • Individual Data Input to Each Flip-Flop • Applications Include: CLR 1 20 VCC Buffer/Storage Registers 1Q 2 19 8Q Shift Registers 1D 3 18 8D Pattern Generators 2D 4 17 7D 2Q 5 16 7Q description 3Q 6 15 6Q 3D 7 14 6D These monolithic, positive-edge-triggered flip- 4D 8 13 5D flops utilize TTL circuitry to implement D-type 4Q 9 12 5Q flip-flop logic with a direct clear input. GND 10 11 CLK Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock SN54LS273...FK PACKAGE (TOP VIEW) triggering occurs at a particular voltage level and is not directly related to the transition time of the C R C positive-going pulse. When the clock input is at D Q L Q 1 1 CV 8 either the high or low level, the D input signal has no effect ar the output. 3 2 1 20 19 2D 4 18 8D These flip-flops are guaranteed to respond to 2Q 5 17 7D clock frequencies ranging form 0 to 30 megahertz 3Q 6 16 7Q while maximum clock frequency is typically 40 3D 7 15 6Q megahertz. Typical power dissipation is 39 4D 8 14 6D milliwatts per flip-flop for the ′273 and 10 milliwatts 9 10 11 12 13 for the ′LS273. Q D KQ D 4 N L5 5 G C FUNCTION TABLE logic symbol† (each flip-flop) INPUTS OUTPUT 1 CLR EN CLEAR CLOCK D Q 11 CLK C1 L X X L H ↑ H H 3 2 1D 1D 1Q H ↑ L L 4 5 2D 2Q 7 6 H L X Q0 3D 3Q 8 9 4D 4Q 13 12 5D 5Q 14 15 6D 6Q 17 16 7D 7Q 18 19 8D 8Q †This symbol is in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, J, N, and W packages. PRODUCTION DATA information is current as of publication date. Copyright  1988, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 schematics of inputs and outputs ′273 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC VCC Req 100 W NOM INPUT OUTPUT Clear: Req = 3 kW NOM Clock: Req = 6 kW NOM All other inputs: Req = 8 kW NOM ′LS273 EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS VCC 120 W NOM VCC 20 kW NOM INPUT OUTPUT logic diagram (positive logic) 1D 2D 3D 4D 5D 6D 7D 8D 11 3 4 7 8 13 14 17 18 CLOCK 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 R R R R R R R R 1 CLEAR 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q Pin numbers shown are for the DW, J, N, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, T : SN54273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C A SN74273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54273 SN74273 UUNNIITT MIN NOM MAX MIN NOM MAX Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V High-level output current, IOH –800 –800 m A Low-level output current, IOL 16 16 mA Clock frequency, fclock 0 30 0 30 MHz Width of clock or clear pulse, tw 16.5 16.5 ns Data input 20↑ 20↑ SSeettuupp ttiimmee, ttsu nnss Clear inactive state 25↑ 25↑ Data hold time, th 5↑ 5↑ ns Operating free-air temperature, TA –55 125 0 70 °C ↑The arrow indicates that the rising edge of the clock pulse is used for reference. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS† MIN TYP‡ MAX UNIT VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VIK Input clamp voltage VCC = MIN, II = –12 mA –1.5 V VCC = MIN, VIH = 2 V, VOH High-level output voltage VIL = 0.8 V, IOH = –800 m A 2.4 3.4 V VCC = MIN, VIH = 2 V, VOL Low-level output voltage 0.4 V VIL = 0.8 V, IOH = 16 mA II Input current at maximum input voltage VCC = MAX, VI = 5.5 V 1 mA Clear 80 IIIIHH HHiigghh-lleevveell iinnppuutt ccuurrrreenntt VVCCCC == MMAAXX, VVII == 22.44 VV mm AA Clock or D 40 Clear –3.2 IIIILL LLooww-lleevveell iinnppuutt ccuurrrreenntt VVCCCC == MMAAXX, VVII == 00.44 VV mmAA Clock or D –1.6 IOS Short-circuit output current§ VCC = MAX –18 –57 mA ICC Supply current VCC = MAX, See Note 2 62 94 mA †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 switching characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Maximum clock frequency 30 40 MHz tPHL Propagation delay time, high-to-low-level output from clear CCRRLLL === 4140500 0p FWW ,, 18 27 ns tPLH Propagation delay time, low-to-high-level output from clock SSeeee NNoottee 33 17 27 ns tPHL Propagation delay time, high-to-low-level output from clock 18 27 ns NOTE 3: Load circuits and voltage waveforms are shown in Section 1. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, T : SN54LS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C A SN74LS273 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C NOTE 1: Voltage values are with respect to network ground terminal. recommended operating conditions SN54LS273 SN74LS273 UUNNIITT MIN NOM MAX MIN NOM MAX Supply voltage, VCC 4.5 5 5.5 4.75 5 5.25 V High-level output current, IOH –400 –400 m A Low-level output current, IOL 4 8 mA Clock frequency, fclock 0 30 0 30 MHz Width of clock or clear pulse, tw 20 20 ns Data input 20↑ 20↑ SSeettuupp ttiimmee, ttsu nnss Clear inactive state 25↑ 25↑ Data hold time, th 5↑ 5↑ ns Operating free-air temperature, TA –55 125 0 70 °C ↑The arrow indicates that the rising edge of the clock pulse is used for reference. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090 – OCTOBER 1976 – REVISED MARCH 1988 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LS273 SN74LS273 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS†† UUNNIITT MIN TYP‡ MAX MIN TYP‡ MAX VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V VIK Input clamp voltage VCC = MIN, II = –18 mA –1.5 –1.5 V VCC = MIN, VIH = 2 V, VOH High-level output voltage VIL = VILmax, IOH = –400 m A 2.5 3.4 2.7 3.4 V VVOOLL LLooww-lleevveell oouuttppuutt vvoollttaaggee VCCCC = MIN,, VIIHH = 2 V,, IOL = 4 mA 0.25 0.4 0.25 0.4 VV VIL = VILmax, IOL = 8 mA 0.35 0.5 Input current at II VCC = MAX, VI = 7 V 0.1 0.1 mA maximum input voltage IIH High-level input current VCC = MAX, VI = 2.7 V 20 20 m A IIL Low-level input current VCC = MAX, VI = 0.4 V –0.4 –0.4 mA Short-circuit output IOS current§ VCC = MAX –20 –100 –20 –100 mA ICC Supply current VCC = MAX, See Note 2 17 27 17 27 mA †For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. ‡All typical values are at VCC = 5 V, TA = 25°C. §Not more than one output should be shorted at a time and duration of short circuit should not exceed one second. NOTE 2: With all outputs open and 4.5 V applied to all data and clear inputs, ICC is measured after a momentary ground, then 4.5 V, is applied to clock. switching characteristics, V = 5 V, T = 25°C CC A PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fmax Maximum clock frequency 30 40 MHz tPHL Propagation delay time, high-to-low-level output from clear CCRRLLL === 1225 kk WWpF,, 18 27 ns tPLH Propagation delay time, low-to-high-level output from clock SSeeee NNoottee 33 17 27 ns tPHL Propagation delay time, high-to-low-level output from clock 18 27 ns NOTE 3: Load circuits and voltage waveforms are shown in Section 1. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74LS273DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74LS273NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74LS273DWR SOIC DW 20 2000 367.0 367.0 45.0 SN74LS273NSR SO NS 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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