CC1100 CC1100 Low-Cost Low-Power Sub- 1 GHz RF Transceiver Applications • Ultra low-power wireless applications • Wireless sensor networks operating in the 315/433/868/915 MHz • AMR – Automatic Meter Reading ISM/SRD bands • Home and building automation • Wireless alarm and security systems • Industrial monitoring and control Product Description The CC1100 is a low-cost sub- 1 GHz The main operating parameters and the 64- transceiver designed for very low-power byte transmit/receive FIFOs of CC1100 can be wireless applications. The circuit is mainly controlled via an SPI interface. In a typical intended for the ISM (Industrial, Scientific and system, the CC1100 will be used together with a Medical) and SRD (Short Range Device) microcontroller and a few additional passive frequency bands at 315, 433, 868, and 915 components. MHz, but can easily be programmed for operation at other frequencies in the 300-348 MHz, 400-464 MHz and 800-928 MHz bands. 20 19 18 17 16 The RF transceiver is integrated with a highly 1 15 configurable baseband modem. The modem 2 CC1100 14 supports various modulation formats and has 3 13 4 12 a configurable data up to 500 kBaud. 5 11 CC1100 provides extensive hardware support 6 7 8 9 10 for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio. This product shall not be used in any of the following products or systems without prior express written permission from Texas Instruments: (i) implantable cardiac rhythm management systems, including without limitation pacemakers, defibrillators and cardiac resynchronization devices, (ii) external cardiac rhythm management systems that communicate directly with one or more implantable medical devices; or (iii) other devices used to monitor or treat cardiac function, including without limitation pressure sensors, biochemical sensors and neurostimulators. Please contact lpw-medical-approval@list.ti.com if your application might fall within the category described above. SWRS038C Page 1 of 96

CC1100 Key Features RF Performance • Programmable Preamble Quality Indicator (PQI) for improved protection against • High sensitivity (–111 dBm at 1.2 kBaud, false sync word detection in random noise 868 MHz, 1% packet error rate) • Support for automatic Clear Channel • Low current consumption (14.4 mA in RX, Assessment (CCA) before transmitting 1.2 kBaud, 868 MHz) (for listen-before-talk systems) • Programmable output power up to +10 • Support for per-package Link Quality dBm for all supported frequencies Indication (LQI) • Excellent receiver selectivity and blocking • Optional automatic whitening and de- performance whitening of data • Programmable data rate from 1.2 to 500 kBaud Low-Power Features • Frequency bands: 300-348 MHz, 400-464 MHz and 800-928 MHz • 400nA SLEEP mode current consumption • Fast startup time: 240us from sleep to RX or TX mode (measured on EM reference Analog Features design [5] and [6]) • Wake-on-radio functionality for automatic • 2-FSK, GFSK, and MSK supported as low-power RX polling well as OOK and flexible ASK shaping • Separate 64-byte RX and TX data FIFOs • Suitable for frequency hopping systems (enables burst mode data transmission) due to a fast settling frequency synthesizer: 90us settling time General • Automatic Frequency Compensation (AFC) can be used to align the frequency • Few external components: Completely on- synthesizer to the received centre chip frequency synthesizer, no external frequency filters or RF switch needed • Integrated analog temperature sensor • Green package: RoHS compliant and no antimony or bromine • Small size (QLP 4x4 mm package, 20 Digital Features pins) • Flexible support for packet oriented • Suited for systems targeting compliance systems: On-chip support for sync word with EN 300 220 (Europe) and FCC CFR detection, address check, flexible packet Part 15 (US). length, and automatic CRC handling • Support for asynchronous and • Efficient SPI interface: All registers can be synchronous serial receive/transmit mode programmed with one “burst” transfer for backwards compatibility with existing • Digital RSSI output radio communication protocols • Programmable channel filter bandwidth • Programmable Carrier Sense (CS) indicator SWRS038C Page 2 of 96

CC1100 Abbreviations Abbreviations used in this data sheet are described below. ACP Adjacent Channel Power MSK Minimum Shift Keying ADC Analog to Digital Converter N/A Not Applicable AFC Automatic Frequency Compensation NRZ Non Return to Zero (Coding) AGC Automatic Gain Control OOK On-Off Keying AMR Automatic Meter Reading PA Power Amplifier ASK Amplitude Shift Keying PCB Printed Circuit Board BER Bit Error Rate PD Power Down BT Bandwidth-Time product PER Packet Error Rate CCA Clear Channel Assessment PLL Phase Locked Loop CFR Code of Federal Regulations POR Power-On Reset CRC Cyclic Redundancy Check PQI Preamble Quality Indicator CS Carrier Sense PQT Preamble Quality Threshold CW Continuous Wave (Unmodulated Carrier) PTAT Proportional To Absolute Temperature DC Direct Current QLP Quad Leadless Package DVGA Digital Variable Gain Amplifier QPSK Quadrature Phase Shift Keying ESR Equivalent Series Resistance RC Resistor-Capacitor FCC Federal Communications Commission RF Radio Frequency FEC Forward Error Correction RSSI Received Signal Strength Indicator FIFO First-In-First-Out RX Receive, Receive Mode FHSS Frequency Hopping Spread Spectrum SAW Surface Aqustic Wave 2-FSK Binary Frequency Shift Keying SMD Surface Mount Device GFSK Gaussian shaped Frequency Shift Keying SNR Signal to Noise Ratio IF Intermediate Frequency SPI Serial Peripheral Interface I/Q In-Phase/Quadrature SRD Short Range Devices ISM Industrial, Scientific, Medical TBD To Be Defined LC Inductor-Capacitor T/R Transmit/Receive LNA Low Noise Amplifier TX Transmit, Transmit Mode LO Local Oscillator UHF Ultra High frequency LSB Least Significant Bit VCO Voltage Controlled Oscillator LQI Link Quality Indicator WOR Wake on Radio, Low power polling MCU Microcontroller Unit XOSC Crystal Oscillator MSB Most Significant Bit XTAL Crystal SWRS038C Page 3 of 96

CC1100 Table Of Contents APPLICATIONS..................................................................................................................................................1 PRODUCT DESCRIPTION................................................................................................................................1 KEY FEATURES.................................................................................................................................................2 RF PERFORMANCE..........................................................................................................................................2 ANALOG FEATURES........................................................................................................................................2 DIGITAL FEATURES.........................................................................................................................................2 LOW-POWER FEATURES................................................................................................................................2 GENERAL............................................................................................................................................................2 ABBREVIATIONS...............................................................................................................................................3 TABLE OF CONTENTS.....................................................................................................................................4 1 ABSOLUTE MAXIMUM RATINGS.....................................................................................................7 2 OPERATING CONDITIONS.................................................................................................................7 3 GENERAL CHARACTERISTICS.........................................................................................................7 4 ELECTRICAL SPECIFICATIONS.......................................................................................................8 4.1 CURRENT CONSUMPTION............................................................................................................................8 4.2 RF RECEIVE SECTION..................................................................................................................................9 4.3 RF TRANSMIT SECTION.............................................................................................................................13 4.4 CRYSTAL OSCILLATOR..............................................................................................................................14 4.5 LOW POWER RC OSCILLATOR...................................................................................................................15 4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS..........................................................................................15 4.7 ANALOG TEMPERATURE SENSOR..............................................................................................................16 4.8 DC CHARACTERISTICS..............................................................................................................................16 4.9 POWER-ON RESET.....................................................................................................................................16 5 PIN CONFIGURATION........................................................................................................................17 6 CIRCUIT DESCRIPTION....................................................................................................................18 7 APPLICATION CIRCUIT....................................................................................................................19 8 CONFIGURATION OVERVIEW........................................................................................................22 9 CONFIGURATION SOFTWARE........................................................................................................24 10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE..................................................24 10.1 CHIP STATUS BYTE...................................................................................................................................26 10.2 REGISTER ACCESS.....................................................................................................................................26 10.3 SPI READ..................................................................................................................................................27 10.4 COMMAND STROBES.................................................................................................................................27 10.5 FIFO ACCESS............................................................................................................................................27 10.6 PATABLE ACCESS...................................................................................................................................28 11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION..........................................28 11.1 CONFIGURATION INTERFACE.....................................................................................................................28 11.2 GENERAL CONTROL AND STATUS PINS.....................................................................................................28 11.3 OPTIONAL RADIO CONTROL FEATURE......................................................................................................29 12 DATA RATE PROGRAMMING..........................................................................................................29 13 RECEIVER CHANNEL FILTER BANDWIDTH..............................................................................30 14 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION..................................30 14.1 FREQUENCY OFFSET COMPENSATION........................................................................................................30 14.2 BIT SYNCHRONIZATION.............................................................................................................................30 14.3 BYTE SYNCHRONIZATION..........................................................................................................................31 15 PACKET HANDLING HARDWARE SUPPORT..............................................................................31 15.1 DATA WHITENING.....................................................................................................................................31 15.2 PACKET FORMAT.......................................................................................................................................32 15.3 PACKET FILTERING IN RECEIVE MODE......................................................................................................34 15.4 PACKET HANDLING IN TRANSMIT MODE...................................................................................................34 15.5 PACKET HANDLING IN RECEIVE MODE.....................................................................................................35 SWRS038C Page 4 of 96

CC1100 15.6 PACKET HANDLING IN FIRMWARE.............................................................................................................35 16 MODULATION FORMATS.................................................................................................................36 16.1 FREQUENCY SHIFT KEYING.......................................................................................................................36 16.2 MINIMUM SHIFT KEYING...........................................................................................................................36 16.3 AMPLITUDE MODULATION........................................................................................................................36 17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION............................37 17.1 SYNC WORD QUALIFIER............................................................................................................................37 17.2 PREAMBLE QUALITY THRESHOLD (PQT)..................................................................................................37 17.3 RSSI..........................................................................................................................................................37 17.4 CARRIER SENSE (CS).................................................................................................................................39 17.5 CLEAR CHANNEL ASSESSMENT (CCA).....................................................................................................40 17.6 LINK QUALITY INDICATOR (LQI)..............................................................................................................40 18 FORWARD ERROR CORRECTION WITH INTERLEAVING.....................................................40 18.1 FORWARD ERROR CORRECTION (FEC)......................................................................................................40 18.2 INTERLEAVING..........................................................................................................................................41 19 RADIO CONTROL................................................................................................................................42 19.1 POWER-ON START-UP SEQUENCE.............................................................................................................42 19.2 CRYSTAL CONTROL...................................................................................................................................43 19.3 VOLTAGE REGULATOR CONTROL..............................................................................................................43 19.4 ACTIVE MODES.........................................................................................................................................44 19.5 WAKE ON RADIO (WOR)..........................................................................................................................44 19.6 TIMING......................................................................................................................................................45 19.7 RX TERMINATION TIMER..........................................................................................................................46 20 DATA FIFO............................................................................................................................................46 21 FREQUENCY PROGRAMMING........................................................................................................48 22 VCO.........................................................................................................................................................48 22.1 VCO AND PLL SELF-CALIBRATION..........................................................................................................48 23 VOLTAGE REGULATORS.................................................................................................................49 24 OUTPUT POWER PROGRAMMING................................................................................................49 25 SHAPING AND PA RAMPING............................................................................................................50 26 SELECTIVITY.......................................................................................................................................52 27 CRYSTAL OSCILLATOR....................................................................................................................53 27.1 REFERENCE SIGNAL..................................................................................................................................54 28 EXTERNAL RF MATCH.....................................................................................................................54 29 PCB LAYOUT RECOMMENDATIONS.............................................................................................54 30 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS.............................................................55 31 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION..............................................57 31.1 ASYNCHRONOUS OPERATION....................................................................................................................57 31.2 SYNCHRONOUS SERIAL OPERATION..........................................................................................................57 32 SYSTEM CONSIDERATIONS AND GUIDELINES.........................................................................57 32.1 SRD REGULATIONS...................................................................................................................................57 32.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS............................................................................58 32.3 WIDEBAND MODULATION NOT USING SPREAD SPECTRUM.......................................................................58 32.4 DATA BURST TRANSMISSIONS...................................................................................................................58 32.5 CONTINUOUS TRANSMISSIONS..................................................................................................................59 32.6 CRYSTAL DRIFT COMPENSATION..............................................................................................................59 32.7 SPECTRUM EFFICIENT MODULATION.........................................................................................................59 32.8 LOW COST SYSTEMS.................................................................................................................................59 32.9 BATTERY OPERATED SYSTEMS.................................................................................................................59 32.10 INCREASING OUTPUT POWER................................................................................................................59 33 CONFIGURATION REGISTERS........................................................................................................60 33.1 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE...............64 33.2 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOSE PROGRAMMING IN SLEEP STATE............84 33.3 STATUS REGISTER DETAILS.......................................................................................................................85 SWRS038C Page 5 of 96

CC1100 34 PACKAGE DESCRIPTION (QLP 20).................................................................................................88 34.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20)...........................................................................89 34.2 PACKAGE THERMAL PROPERTIES..............................................................................................................89 34.3 SOLDERING INFORMATION........................................................................................................................89 34.4 TRAY SPECIFICATION................................................................................................................................89 34.5 CARRIER TAPE AND REEL SPECIFICATION.................................................................................................90 35 ORDERING INFORMATION..............................................................................................................90 36 REFERENCES.......................................................................................................................................91 37 GENERAL INFORMATION................................................................................................................92 37.1 DOCUMENT HISTORY................................................................................................................................92 37.2 PRODUCT STATUS DEFINITIONS................................................................................................................94 38 ADDRESS INFORMATION.................................................................................................................95 39 TI WORLDWIDE TECHNICAL SUPPORT......................................................................................95 SWRS038C Page 6 of 96

CC1100 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Parameter Min Max Units Condition Supply voltage –0.3 3.9 V All supply pins must have the same voltage Voltage on any digital pin –0.3 VDD+0.3 V max 3.9 Voltage on the pins RF_P, RF_N, –0.3 2.0 V and DCOUPL Voltage ramp-up rate 120 kV/µs Input RF level +10 dBm Storage temperature range –50 150 °C Solder reflow temperature 260 °C According to IPC/JEDEC J-STD-020C ESD <500 V According to JEDEC STD 22, method A114, Human Body Model Table 1: Absolute Maximum Ratings 2 Operating Conditions The operating conditions for CC1100 are listed Table 2 in below. Parameter Min Max Unit Condition Operating temperature -40 85 °C Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage Table 2: Operating Conditions 3 General Characteristics Parameter Min Typ Max Unit Condition/Note Frequency range 300 348 MHz 400 464 MHz 800 928 MHz Data rate 1.2 500 kBaud 2-FSK 1.2 250 kBaud GFSK, OOK, and ASK 26 500 kBaud (Shaped) MSK (also known as differential offset QPSK) Optional Manchester encoding (the data rate in kbps will be half the baud rate) Table 3: General Characteristics SWRS038C Page 7 of 96

CC1100 4 Electrical Specifications 4.1 Current Consumption Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference designs ( [5] and [ 6]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 5 for additional details on current consumption and sensitivity. Parameter Min Typ Max Unit Condition Current consumption in power 400 nA Voltage regulator to digital part off, register values retained down modes (SLEEP state). All GDO pins programmed to 0x2F (HW to 0) 900 nA Voltage regulator to digital part off, register values retained, low- power RC oscillator running (SLEEP state with WOR enabled 95 µA Voltage regulator to digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) 160 µA Voltage regulator to digital part on, all other modules in power down (XOFF state) Current consumption 9.8 µA Automatic RX polling once each second, using low-power RC oscillator, with 460 kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1). 34.2 µA Same as above, but with signal in channel above carrier sense level, 1.95 ms RX timeout, and no preamble/sync word found. 1.5 µA Automatic RX polling every 15th second, using low-power RC oscillator, with 460kHz filter bandwidth and 250 kBaud data rate, PLL calibration every 4th wakeup. Average current with signal in channel below carrier sense level (MCSM2.RX_TIME_RSSI=1). 39.3 µA Same as above, but with signal in channel above carrier sense level, 29.3 ms RX timeout, and no preamble/sync word found. 1.6 mA Only voltage regulator to digital part and crystal oscillator running (IDLE state) 8.2 mA Only the frequency synthesizer is running (FSTXON state). This currents consumption is also representative for the other intermediate states when going from IDLE to RX or TX, including the calibration state. Current consumption, 15.1 mA Receive mode, 1.2 kBaud, reduced current, input at sensitivity 315MHz limit 13.9 mA Receive mode, 1.2 kBaud, reduced current, input well above sensitivity limit 14.9 mA Receive mode, 38.4 kBaud, reduced current, input at sensitivity limit 14.1 mA Receive mode,38.4 kBaud, reduced current, input well above sensitivity limit 15.9 mA Receive mode, 250 kBaud, reduced current, input at sensitivity limit 14.5 mA Receive mode, 250 kBaud, reduced current, input well above sensitivity limit 27.0 mA Transmit mode, +10 dBm output power 14.8 mA Transmit mode, 0 dBm output power 12.3 mA Transmit mode, –6 dBm output power SWRS038C Page 8 of 96

CC1100 Parameter Min Typ Max Unit Condition Current consumption, 15.5 mA Receive mode, 1.2 kBaud , reduced current, input at sensitivity 433MHz limit 14.5 mA Receive mode, 1.2 kBaud , reduced current, input well above sensitivity limit 15.4 mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity limit 14.4 mA Receive mode, 38.4 kBaud , reduced current, input well above sensitivity limit 16.5 mA Receive mode, 250 kBaud , reduced current, input at sensitivity limit 15.2 mA Receive mode, 250 kBaud , reduced current, input well above sensitivity limit 28.9 mA Transmit mode, +10 dBm output power 15.5 mA Transmit mode, 0 dBm output power 13.1 mA Transmit mode, –6 dBm output power Current consumption, 15.4 mA Receive mode, 1.2 kBaud , reduced current, input at sensitivity 868/915MHz limit 14.4 mA Receive mode, 1.2 kBaud , reduced current, input well above sensitivity limit 15.2 mA Receive mode, 38.4 kBaud , reduced current, input at sensitivity limit 14.4 mA Receive mode,38.4 kBaud , reduced current, input well above sensitivity limit 16.4 mA Receive mode, 250 kBaud , reduced current, input at sensitivity limit 15.1 mA Receive mode, 250 kBaud , reduced current, input well above sensitivity limit 31.1 mA Transmit mode, +10 dBm output power 16.9 mA Transmit mode, 0 dBm output power 13.5 mA Transmit mode, –6 dBm output power Table 4: Electrical Specifications 4.2 RF Receive Section Tc = 25°C, VDD = 3.0V if nothing else stated. All measurement results are obtained using the CC1100EM reference designs ( [5] and [ 6]). Parameter Min Typ Max Unit Condition/Note Digital channel filter 58 812 kHz User programmable. The bandwidth limits are proportional to bandwidth crystal frequency (given values assume a 26.0 MHz crystal). 315 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity -111 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.1 mA to 15.1 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm 315 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) -88 dBm SWRS038C Page 9 of 96

CC1100 Parameter Min Typ Max Unit Condition/Note 433 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth Receiver sensitivity –110 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.4 mA to 15.5 mA at sensitivity limit. The sensitivity is typically reduced to -108 dBm 433 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity –103 dBm 433 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver sensitivity –94 dBm 433 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver sensitivity –88 dBm 868 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 5.2 kHz deviation, 58 kHz digital channel filter bandwidth) Receiver sensitivity –111 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.4 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm Saturation –15 dBm Adjacent channel 33 dB Desired channel 3 dB above the sensitivity limit. 100 kHz rejection channel spacing Alternate channel 33 dB Desired channel 3 dB above the sensitivity limit. 100 kHz rejection channel spacing See Figure 25 for plot of selectivity versus frequency offset Image channel 30 dB IF frequency 152 kHz rejection, Desired channel 3 dB above the sensitivity limit. 868MHz 868 MHz, 38.4 kBaud data rate (2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity –103 dBm Saturation –16 dBm Adjacent channel 20 dB Desired channel 3 dB above the sensitivity limit. 200 kHz rejection channel spacing Alternate channel 28 dB Desired channel 3 dB above the sensitivity limit. 200 kHz rejection channel spacing See Figure 26 for plot of selectivity versus frequency offset Image channel 23 dB IF frequency 152 kHz rejection, Desired channel 3 dB above the sensitivity limit. 868MHz SWRS038C Page 10 of 96

CC1100 Parameter Min Typ Max Unit Condition/Note 868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver –93 dBm Sensitivity can be traded for current consumption by setting sensitivity MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.8 mA to 16.4 mA at sensitivity limit. The sensitivity is typically reduced to -91 dBm Saturation –16 dBm Adjacent channel 24 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel rejection spacing Alternate channel 37 dB Desired channel 3 dB above the sensitivity limit. 750 kHz channel rejection spacing See Figure 27 for plot of selectivity versus frequency offset Image channel 14 dB IF frequency 254 kHz rejection, Desired channel 3 dB above the sensitivity limit. 868MHz 868 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud ) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver –88 dBm sensitivity 868 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (OOK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver -86 dBm sensitivity 915 MHz, 1.2 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 5.2kHz deviation, 1% packet error rate, 20 bytes packet length, 58 kHz digital channel filter bandwidth) Receiver –111 dBm Sensitivity can be traded for current consumption by setting sensitivity MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 17.7 mA to 15.4 mA at sensitivity limit. The sensitivity is typically reduced to -109 dBm 915 MHz, 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver –104 dBm sensitivity 915 MHz, 250 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth) Receiver –93 dBm Sensitivity can be traded for current consumption by setting sensitivity MDMCFG2.DEM_DCFILT_OFF=1. The typical current consumption is then reduced from 18.8 mA to 16.4 mA at sensitivity limit. The sensitivity is typically reduced to -92 dBm 915 MHz, 500 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (MDMCFG2.DEM_DCFILT_OFF=1 cannot be used for data rates > 250 kBaud ) (MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth) Receiver –87 dBm sensitivity SWRS038C Page 11 of 96

CC1100 Parameter Min Typ Max Unit Condition/Note Blocking Blocking at ±2 MHz offset, -53 dBm Desired channel 3dB above the sensitivity limit. Compliant 1.2 kBaud, 868 MHz with ETSI EN 300 220 class 2 receiver requirement. Blocking at ±2 MHz offset, -51 dBm Desired channel 3dB above the sensitivity limit. Compliant 500 kBaud, 868 MHz with ETSI EN 300 220 class 2 receiver requirement. Blocking at ±10 MHz offset, -43 dBm Desired channel 3dB above the sensitivity limit. Compliant 1.2 kBaud, 868 MHz with ETSI EN 300 220 class 2 receiver requirement. Blocking at ±10 MHz offset, -43 dBm Desired channel 3dB above the sensitivity limit. Compliant 500 kBaud, 868 MHz with ETSI EN 300 220 class 2 receiver requirement. General Spurious emissions -68 –57 dBm 25 MHz – 1 GHz (Maximum figure is the ETSI EN 300 220 limit) -66 –47 dBm Above 1 GHz (Maximum figure is the ETSI EN 300 220 limit) RX latency 9 bit Serial operation. Time from start of reception until data is available on the receiver data output pin is equal to 9 bit. Table 5: RF Receive Section SWRS038C Page 12 of 96

CC1100 4.3 RF Transmit Section Tc = 25°C, VDD = 3.0V, +10dBm if nothing else stated. All measurement results are obtained using the CC1100EM reference designs ( [5] and [ 6]). Parameter Min Typ Max Unit Condition/Note Differential load Differential impedance as seen from the RF-port (RF_P and impedance RF_N) towards the antenna. Follow the CC1100EM reference design ( [5] and [ 6]) available from theTI website. 315 MHz 122 + j31 Ω 433 MHz 116 + j41 868/915 MHz 86.5 + j43 Output power, +10 dBm Output power is programmable, and full range is available in all highest setting frequency bands (Output power may be restricted by regulatory limits. See also Application Note AN039 [3]. Delivered to a 50Ω single-ended load via CC1100EM reference design ( [5] and [ 6]) RF matching network. Output power, -30 dBm Output power is programmable, and full range is available in all lowest setting frequency bands. Delivered to a 50Ω single-ended load via CC1100EM reference design( [5] and [ 6]) RF matching network. Harmonics, Measured on CC1100EM reference designs( [5] and [ 6]) with radiated CW, 10 dBm output power 2nd Harm, 433 MHz -50 dBm The antennas used during the radiated measurements (SMAFF- 3rd Harm, 433 MHz -40 433 from R.W.Badland and Nearson S331 868/915) plays a part in attenuating the harmonics 2nd Harm, 868 MHz -34 3rd Harm, 868 MHz -45 Harmonics, Measured with 10 dBm CW, TX frequency at 315.00 MHz, conducted 433.00 MHz, 868.00 MHz, or 915.00 MHz 315 MHz < -33 dBm Frequencies below 960 MHz < -38 Frequencies above 960 MHz 433 MHz < -51 Frequencies below 1 GHz < -34 Frequencies above 1 GHz 868 MHz < -32 915 MHz < -30 SWRS038C Page 13 of 96

CC1100 Spurious emissions, Measured with 10 dBm CW, TX frequency at 315.00 MHz, conducted 433.00 MHz, 868.00 MHz or 915.00 MHz Harmonics not included 315 MHz < -58 dBm Frequencies below 960 MHz < -53 Frequencies above 960 MHz 433 MHz < -50 Frequencies below 1 GHz < -54 Frequencies above 1 GHz < -56 Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz 868 MHz < -50 Frequencies below 1 GHz < -51 Frequencies above 1 GHz < -53 Frequencies within 47-74, 87.5-118, 174-230, 470-862 MHz. The peak conducted spurious emission is -53dBm @ 699 MHz, which is in an EN300220 restricted band limited to -54dBm. All radiated spurious emissions are within the limits of ETSI. 915 MHz < -51 Frequencies below 960 MHz < -51 Frequencies above 960 MHz General TX latency 8 bit Serial operation. Time from sampling the data on the transmitter data input DIO pin until it is observed on the RF output ports. Table 6: RF Transmit Section 4.4 Crystal Oscillator Tc = 25°C @ VDD = 3.0 V if nothing else is stated. Parameter Min Typ Max Unit Condition/Note Crystal frequency 26 26 27 MHz Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal loading, c) aging, and d) temperature dependence. The acceptable crystal tolerance depends on RF frequency and channel spacing / bandwidth. ESR 100 Ω Start-up time 150 µs Measured on the CC1100EM reference designs ( [5] and [ 6]) using crystal AT-41CD2 from NDK. This parameter is to a large degree crystal dependent. Table 7: Crystal Oscillator Parameters SWRS038C Page 14 of 96

CC1100 4.5 Low Power RC Oscillator Tc = 25°C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1100EM reference designs ( [5] and [6]). Parameter Min Typ Max Unit Condition/Note Calibrated frequency 34.7 34.7 36 kHz Calibrated RC Oscillator frequency is XTAL frequency divided by 750 Frequency accuracy after ±1 % calibration Temperature coefficient +0.5 % / °C Frequency drift when temperature changes after calibration Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes after calibration Initial calibration time 2 ms When the RC Oscillator is enabled, calibration is continuously done in the background as long as the crystal oscillator is running. Table 8: RC Oscillator Parameters 4.6 Frequency Synthesizer Characteristics Tc = 25°C @ VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1100EM reference designs ( [5] and [ 6]). Min figures are given using a 27 MHz crystal. Typ and max are given using a 26 MHz crystal. Parameter Min Typ Max Unit Condition/Note Programmed frequency 397 F / 412 Hz 26-27 MHz crystal. XOSC resolution 216 The resolution (in Hz) is equal for all frequency bands. Synthesizer frequency ±40 ppm Given by crystal used. Required accuracy tolerance (including temperature and aging) depends on frequency band and channel bandwidth / spacing. RF carrier phase noise –89 dBc/Hz @ 50 kHz offset from carrier RF carrier phase noise –89 dBc/Hz @ 100 kHz offset from carrier RF carrier phase noise –90 dBc/Hz @ 200 kHz offset from carrier RF carrier phase noise –98 dBc/Hz @ 500 kHz offset from carrier RF carrier phase noise –107 dBc/Hz @ 1 MHz offset from carrier RF carrier phase noise –113 dBc/Hz @ 2 MHz offset from carrier RF carrier phase noise –119 dBc/Hz @ 5 MHz offset from carrier RF carrier phase noise –129 dBc/Hz @ 10 MHz offset from carrier PLL turn-on / hop time 85.1 88.4 88.4 µs Time from leaving the IDLE state until arriving in the RX, FSTXON or TX state, when not performing calibration. Crystal oscillator running. PLL RX/TX settling time 9.3 9.6 9.6 µs Settling time for the 1·IF frequency step from RX to TX PLL TX/RX settling time 20.7 21.5 21.5 µs Settling time for the 1·IF frequency step from TX to RX PLL calibration time 694 721 721 µs Calibration can be initiated manually or automatically before entering or after leaving RX/TX. Table 9: Frequency Synthesizer Parameters SWRS038C Page 15 of 96

CC1100 4.7 Analog Temperature Sensor The characteristics of the analog temperature sensor at 3.0 V supply voltage are listed in Table 10 below. Note that it is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Parameter Min Typ Max Unit Condition/Note Output voltage at –40°C 0.651 V Output voltage at 0°C 0.747 V Output voltage at +40°C 0.847 V Output voltage at +80°C 0.945 V Temperature coefficient 2.45 mV/°C Fitted from –20 °C to +80 °C Error in calculated -2 * 0 2 * °C From –20 °C to +80 °C when using 2.45 mV / °C, temperature, calibrated after 1-point calibration at room temperature * The indicated minimum and maximum error with 1- point calibration is based on simulated values for typical process parameters Current consumption 0.3 mA increase when enabled Table 10: Analog Temperature Sensor Parameters 4.8 DC Characteristics Tc = 25°C if nothing else stated. Digital Inputs/Outputs Min Max Unit Condition Logic "0" input voltage 0 0.7 V Logic "1" input voltage VDD-0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current Logic "0" input current N/A –50 nA Input equals 0V Logic "1" input current N/A 50 nA Input equals VDD Table 11: DC Characteristics 4.9 Power-On Reset When the power supply complies with the requirements in Table 12 below, proper Power-On-Reset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 42 for further details. Parameter Min Typ Max Unit Condition/Note Power-up ramp-up time. 5 ms From 0V until reaching 1.8V Power off time 1 ms Minimum time between power-on and power-off Table 12: Power-On Reset Requirements SWRS038C Page 16 of 96

CC1100 5 Pin Configuration D R A S D U A D N G BI N SI G D R G 20 1918 1716 SCLK1 15AVDD SO (GDO1)2 14AVDD GDO23 13RF_N DVDD4 12RF_P DCOUPL5 11AVDD GND 6 7 8 9 10 Exposed die G C X A X D S O V O attach pad O n S D S 0 C D C (A _Q _Q T 1 2 E S T) Figure 1: Pinout Top View Note: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip. Pin # Pin Name Pin type Description 1 SCLK Digital Input Serial configuration interface, clock input 2 SO (GDO1) Digital Output Serial configuration interface, data output. Optional general output pin when CSn is high 3 GDO2 Digital Output Digital output pin for general use: • Test signals • FIFO status signals • Clear Channel Indicator • Clock output, down-divided from XOSC • Serial output RX data 4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core voltage regulator 5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling. NOTE: This pin is intended for use with the CC1100 only. It can not be used to provide supply voltage to other devices. 6 GDO0 Digital I/O Digital output pin for general use: (ATEST) • Test signals • FIFO status signals • Clear Channel Indicator • Clock output, down-divided from XOSC • Serial output RX data • Serial input TX data Also used as analog test I/O for prototype/production testing 7 CSn Digital Input Serial configuration interface, chip select 8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input 9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 10 XOSC_Q2 Analog I/O Crystal oscillator pin 2 SWRS038C Page 17 of 96

CC1100 Pin # Pin Name Pin type Description 11 AVDD Power (Analog) 1.8 -3.6 V analog power supply connection 12 RF_P RF I/O Positive RF input signal to LNA in receive mode Positive RF output signal from PA in transmit mode 13 RF_N RF I/O Negative RF input signal to LNA in receive mode Negative RF output signal from PA in transmit mode 14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection 16 GND Ground (Analog) Analog ground connection 17 RBIAS Analog I/O External bias resistor for reference current 18 DGUARD Power (Digital) Power supply connection for digital noise isolation 19 GND Ground (Digital) Ground connection for digital noise isolation 20 SI Digital Input Serial configuration interface, data input Table 13: Pinout Overview 6 Circuit Description RADIO CONTROL R O ADC T A O L F LNA DU XFI CU O R M ADC DEM AVER DLER E TO SSCOL (KGDO1) RRFF__NP 090 SFYRNETQH TERLE T HAN ERFAC SCISn N E T GDO0 (ATEST) PA OR FEC / I PACK TAL IN GDO2 DULAT TXFIFO DIGI O M RC OSC BIAS XOSC RBIAS XOSC_Q1 XOSC_Q2 Figure 2: CC1100 Simplified Block Diagram A simplified block diagram of CC1100 is shown frequency synthesizer includes a completely in Figure 2. on-chip LC VCO and a 90 degree phase shifter for generating the I and Q LO signals to CC1100 features a low-IF receiver. The the down-conversion mixers in receive mode. received RF signal is amplified by the low- noise amplifier (LNA) and down-converted in A crystal is to be connected to XOSC_Q1 and quadrature (I and Q) to the intermediate XOSC_Q2. The crystal oscillator generates the frequency (IF). At IF, the I/Q signals are reference frequency for the synthesizer, as digitised by the ADCs. Automatic gain control well as clocks for the ADC and the digital part. (AGC), fine channel filtering and demodulation A 4-wire SPI serial interface is used for bit/packet synchronization are performed configuration and data buffer access. digitally. The digital baseband includes support for The transmitter part of CC1100 is based on channel configuration, packet handling, and direct synthesis of the RF frequency. The data buffering. SWRS038C Page 18 of 96

CC1100 7 Application Circuit Only a few external components are required The balun and LC filter component values and for using the CC1100. The recommended their placement are important to keep the application circuits are shown in Figure 3 and performance optimized. It is highly Figure 4. The external components are recommended to follow the CC1100EM described in Table 14, and typical values are reference design [ 5] and [6]. given in Table 15. Crystal Bias Resistor The crystal oscillator uses an external crystal The bias resistor R171 is used to set an with two loading capacitors (C81 and C101). accurate bias current. See Section 2 7 on page 53 for details. Balun and RF Matching Additional Filtering The components between the RF_N/RF_P Additional external components (e.g. an RF pins and the point where the two signals are SAW filter) may be used in order to improve joined together (C131, C121, L121 and L131 the performance in specific applications. for the 315/433 MHz reference design [ 5]. Power Supply Decoupling L121, L131, C121, L122, C131, C122 and L132 for the 868/915 MHz reference design The power supply must be properly decoupled [6]) form a balun that converts the differential close to the supply pins. Note that decoupling RF signal on CC1100 to a single-ended RF capacitors are not shown in the application signal. C124 is needed for DC blocking. circuit. The placement and the size of the Together with an appropriate LC network, the decoupling capacitors are very important to balun components also transform the achieve the optimum performance. The impedance to match a 50 Ω antenna (or CC1100EM reference design ( [5] and [6]) cable). Suggested values for 315 MHz, 433 should be followed closely. MHz, and 868/915 MHz are listed in Table 15. Component Description C51 Decoupling capacitor for on-chip voltage regulator to digital part C81/C101 Crystal loading capacitors, see Section 27 on page 53 for details C121/C131 RF balun/matching capacitors C122 RF LC filter/matching filter capacitor (315 and 433 MHz). RF balun/matching capacitor (868/915 MHz). C123 RF LC filter/matching capacitor C124 RF balun DC blocking capacitor C125 RF LC filter DC blocking capacitor (only needed if there is a DC path in the antenna) L121/L131 RF balun/matching inductors (inexpensive multi-layer type) L122 RF LC filter/matching filter inductor (315 and 433 MHz). RF balun/matching inductor (868/915 MHz). (inexpensive multi-layer type) L123 RF LC filter/matching filter inductor (inexpensive multi-layer type) L124 RF LC filter/matching filter inductor (inexpensive multi-layer type) L132 RF balun/matching inductor. (inexpensive multi-layer type) R171 Resistor for internal bias current reference. XTAL 26MHz - 27MHz crystal, see Section 27 on page 53 for details. Table 14: Overview of External Components (excluding supply decoupling capacitors) SWRS038C Page 19 of 96

CC1100 1.8V-3.6V power supply R171 SI SI 20 ND 19 RD 18 AS 17 ND 16 Antenna SCLK G GUA RBI G (50 Ohm) 1 SCLK D AVDD 15 eface GS(GODDOO21) 2 (SGODO1)CC1100 AVDD 14 C1L31131 C125 nt (optional) 3 GDO2 RF_N 13 al I 4 DVDD DIE ATTACH PAD: RF_P 12 L122 L123 Digit C51 5 DCOUPL6 GDO0 7 CSn 8 XOSC_Q1 9 AVDD 10 XOSC_Q2 AVDD 11 CL112214C121 C122 C123 GDO0 (optional) CSn XTAL C81 C101 Figure 3: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply decoupling capacitors) 1.8V-3.6V power supply R171 SI 0 9 8 7 6 2 1 1 1 1 SI ND RD AS ND Antenna SCLK 1 SCLK G GUA RBI GAVDD 15 C131 (50 Ohm) D ace S(GODO1) 2 SO (GDO1) AVDD 14 L131 L132 al Intef G(oDptOio2nal) 34 GDVDDOD2 DIE ATTACH PAD: RRFF__NP 1132 C121 C122 L123 L124 C125 Digit 5 DCOUPL Q1 _Q2AVDD 11 C123 _ C L121 C51 6 GDO0 7 CSn 8 XOSC 9 AVDD 10 XOS L122 GDO0 C124 (optional) CSn XTAL C81 C101 Figure 4: Typical Application and Evaluation Circuit 868/915 MHz (excluding supply decoupling capacitors) SWRS038C Page 20 of 96

CC1100 Component Value at 315MHz Value at 433MHz Value at Manufacturer 868/915MHz C51 100 nF ± 10%, 0402 X5R Murata GRM1555C series C81 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C101 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C121 6.8 pF ± 0.5 pF, 3.9 pF ± 0.25 pF, 1.0 pF ± 0.25 Murata GRM1555C series 0402 NP0 0402 NP0 pF, 0402 NP0 C122 12 pF ± 5%, 0402 8.2 pF ± 0.5 pF, 1.5 pF ± 0.25 Murata GRM1555C series NP0 0402 NP0 pF, 0402 NP0 C123 6.8 pF ± 0.5 pF, 5.6 pF ± 0.5 pF, 3.3 pF ± 0.25 Murata GRM1555C series 0402 NP0 0402 NP0 pF, 0402 NP0 C124 220 pF ± 5%, 220 pF ± 5%, 100 pF ± 5%, Murata GRM1555C series 0402 NP0 0402 NP0 0402 NP0 C125 220 pF ± 5%, 220 pF ± 5%, 100 pF ± 5%, Murata GRM1555C series 0402 NP0 0402 NP0 0402 NP0 C131 6.8 pF ± 0.5 pF, 3.9 pF ± 0.25 pF, 1.5 pF ± 0.25 Murata GRM1555C series 0402 NP0 0402 NP0 pF, 0402 NP0 L121 33 nH ± 5%, 0402 27 nH ± 5%, 0402 12 nH ± 5%, Murata LQG15HS series monolithic monolithic 0402 monolithic L122 18 nH ± 5%, 0402 22 nH ± 5%, 0402 18 nH ± 5%, Murata LQG15HS series monolithic monolithic 0402 monolithic L123 33 nH ± 5%, 0402 27 nH ± 5%, 0402 12 nH ± 5%, Murata LQG15HS series monolithic monolithic 0402 monolithic L124 12 nH ± 5%, Murata LQG15HS series 0402 monolithic L131 33 nH ± 5%, 0402 27 nH ± 5%, 0402 12 nH ± 5%, Murata LQG15HS series monolithic monolithic 0402 monolithic L132 18 nH ± 5%, Murata LQG15HS series 0402 monolithic R171 56 kΩ ± 1%, 0402 Koa RK73 series XTAL 26.0 MHz surface mount crystal NDK, AT-41CD2 Table 15: Bill Of Materials for the Application Circuit The Gerber files for the CC1100EM reference designs ([ 5] and [6]) are available from the TI website. SWRS038C Page 21 of 96

CC1100 8 Configuration Overview CC1100 can be configured to achieve optimum • Forward Error Correction (FEC) with performance for many different applications. interleaving Configuration is done using the SPI interface. • Data Whitening The following key parameters can be • Wake-On-Radio (WOR) programmed: • Power-down / power up mode Details of each configuration register can be • Crystal oscillator power-up / power-down found in Section 33, starting on page 60. • Receive / transmit mode Figure 5 shows a simplified state diagram that • RF channel selection explains the main CC1100 states, together with • Data rate typical usage and current consumption. For • Modulation format detailed information on controlling the CC1100 • RX channel filter bandwidth state machine, and a complete state diagram, • RF output power see Section 19, starting on page 42. • Data buffering with separate 64-byte receive and transmit FIFOs • Packet radio hardware support SWRS038C Page 22 of 96

CC1100 Sleep Lowest power mode. Most SIDLE SPWD or wake-on-radio (WOR) register values are retained. Current consumption typ 400 nA, or typ 900 nA when Default state when the radio is not wake-on-radio (WOR) is receiving or transmitting. Typ. CSn = 0 enabled. current consumption: 1.6 mA. IDLE SXOFF Used for calibrating frequency SCAL synthesizer upfront (entering CSn = 0 All register values are receive or transmit mode can Manual freq. Crystal retained. Typ. current then be done quicker). synth. calibration oscillator off SRX or STX or SFSTXON or wake-on-radio (WOR) consumption; 0.16 mA. Transitional state. Typ. current consumption: 8.2 mA. Frequency Frequency synthesizer is turned on, can optionally be synthesizer startup, calibrated, and then settles to the correct frequency. SFSTXON optional calibration, Transitional state. Typ. current consumption: 8.2 mA. Frequency synthesizer is on, settling ready to start transmitting. Frequency Transmission starts very synthesizer on quickly after receiving the STX command strobe.Typ. current STX consumption: 8.2 mA. SRX or wake-on-radio (WOR) STX TXOFF_MODE = 01 SFSTXON or RXOFF_MODE = 01 Typ. current consumption: Typ. current 13.5 mA at -6 dBm output, Transmit mode STX or RXOFF_MODE=10 Receive mode consumption: 16.9 mA at 0 dBm output, from 14.4 mA (strong 30.7 mA at +10 dBm output. SRX or TXOFF_MODE = 11 input signal) to 15.4mA (weak input signal). TXOFF_MODE = 00 RXOFF_MODE = 00 Optional transitional state. Typ. In FIFO-based modes, current consumption: 8.2mA. In FIFO-based modes, transmission is turned off and reception is turned off and this this state entered if the TX TX FIFO Optional freq. RX FIFO state entered if the RX FIFO FIFO becomes empty in the underflow synth. calibration overflow overflows. Typ. current middle of a packet. Typ. consumption: 1.6 mA. current consumption: 1.6 mA. SFTX SFRX IDLE Figure 5: Simplified State Diagram, with Typical Current Consumption at 1.2 kBaud Data Rate and MDMCFG2.DEM_DCFILT_OFF=1 (current optimized). Freq. Band = 868 MHz SWRS038C Page 23 of 96

CC1100 9 Configuration Software CC1100 can be configured using the SmartRF® After chip reset, all the registers have default Studio software [ 7]. The SmartRF® Studio values as shown in the tables in Section 33. software is highly recommended for obtaining The optimum register setting might differ from optimum register settings, and for evaluating the default value. After a reset all registers that performance and functionality. A screenshot of shall be different from the default value the SmartRF® Studio user interface for CC1100 therefore needs to be programmed through is shown in Figure 6. the SPI interface. Figure 6: SmartRF® Studio [ 7] User Interface 10 4-wire Serial Configuration and Data Interface CC1100 is configured via a simple 4-wire SPI- The CSn pin must be kept low during transfers compatible interface (SI, SO, SCLK and CSn) on the SPI bus. If CSn goes high during the where CC1100 is the slave. This interface is transfer of a header byte or during read/write also used to read and write buffered data. All from/to a register, the transfer will be transfers on the SPI interface are done most cancelled. The timing for the address and data significant bit first. transfer on the SPI interface is shown in Figure 7 with reference to Table 16. All transactions on the SPI interface start with a header byte containing a R/W¯ bit, a burst When CSn is pulled low, the MCU must wait access bit (B), and a 6-bit address (A – A ). until CC1100 SO pin goes low before starting to 5 0 transfer the header byte. This indicates that the crystal is running. Unless the chip was in SWRS038C Page 24 of 96

CC1100 the SLEEP or XOFF states, the SO pin will low. always go low immediately after taking CSn Figure 7: Configuration Registers Write and Read Operations Parameter Description Min Max Units f SCLK frequency - 10 MHz SCLK 100 ns delay inserted between address byte and data byte (single access), or between address and data, and between each data byte (burst access). SCLK frequency, single access - 9 No delay between address and data byte SCLK frequency, burst access - 6.5 No delay between address and data byte, or between data bytes tsp,pd CSn low to positive edge on SCLK, in power-down mode 150 - µs t CSn low to positive edge on SCLK, in active mode 20 - ns sp t Clock high 50 - ns ch t Clock low 50 - ns cl t Clock rise time - 5 ns rise t Clock fall time - 5 ns fall t Setup data (negative SCLK edge) to Single access 55 - ns sd positive edge on SCLK (dtasdt aa pbpyltieess) between address and data bytes, and between Burst access 76 - t Hold data after positive edge on SCLK 20 - ns hd t Negative edge on SCLK to CSn high. 20 - ns ns Table 16: SPI Interface Timing Requirements Note: The minimum t figure in Table 16 can be used in cases where the user does not read the sp,pd CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-down depends on the start-up time of the crystal being used. The 150 us in Table 16 is the crystal oscillator start-up time measured on CC1100EM reference designs ( [5] and [ 6]) using crystal AT-41CD2 from NDK. SWRS038C Page 25 of 96

CC1100 10.1 Chip Status Byte when the chip is in receive mode. Likewise, TX is active when the chip is transmitting. When the header byte, data byte, or command strobe is sent on the SPI interface, the chip The last four bits (3:0) in the status byte con- status byte is sent by the CC1100 on the SO tains FIFO_BYTES_AVAILABLE. For read pin. The status byte contains key status operations (the R/W¯ bit in the header byte is signals, useful for the MCU. The first bit, s7, is set to 1), the FIFO_BYTES_AVAILABLE field the CHIP_RDYn signal; this signal must go low contains the number of bytes available for before the first positive edge of SCLK. The reading from the RX FIFO. For write CHIP_RDYn signal indicates that the crystal is operations (the R/W¯ bit in the header byte is running. set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be Bits 6, 5, and 4 comprise the STATE value. written to the TX FIFO. When This value reflects the state of the chip. The FIFO_BYTES_AVAILABLE=15, 15 or more XOSC and power to the digital core is on in bytes are available/free. the IDLE state, but all other modules are in power down. The frequency and channel Table 17 gives a status byte summary. configuration should only be updated when the chip is in this state. The RX state will be active Bits Name Description 7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using the SPI interface. 6:4 STATE[2:0] Indicates the current main state machine mode Value State Description 000 IDLE IDLE state (Also reported for some transitional states instead of SETTLING or CALIBRATE) 001 RX Receive mode 010 TX Transmit mode 011 FSTXON Fast TX ready 100 CALIBRATE Frequency synthesizer calibration is running 101 SETTLING PLL is settling 110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any useful data, then flush the FIFO with SFRX 111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with SFTX 3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO Table 17: Status Byte Summary 10.2 Register Access the status byte is sent on the SO pin each time a header byte or data byte is transmitted on The configuration registers on the CC1100 are the SI pin. When reading from registers, the located on SPI addresses from 0x00 to 0x2E. status byte is sent on the SO pin each time a Table 36 on page 61 lists all configuration header byte is transmitted on the SI pin. registers. It is highly recommended to use SmartRF® Studio [ 7] to generate optimum Registers with consecutive addresses can be register settings. The detailed description of accessed in an efficient way by setting the each register is found in Section 3 3.1 and burst bit (B) in the header byte. The address 33.2, starting on page 64. All configuration bits (A – A ) set the start address in an 5 0 registers can be both written to and read. The internal address counter. This counter is R/W¯ bit controls if the register should be incremented by one each new byte (every 8 written to or read. When writing to registers, clock pulses). The burst access is either a SWRS038C Page 26 of 96

CC1100 read or a write access and must be terminated by setting CSn high. For register addresses in the range 0x30- 0x3D, the burst bit is used to select between status registers, burst bit is one, and command Figure 8: SRES Command Strobe strobes, burst bit is zero (see 10.4 below). Because of this, burst access is not available for status registers and they must be accesses 10.5 FIFO Access one at a time. The status registers can only be The 64-byte TX FIFO and the 64-byte RX read. FIFO are accessed through the 0x3F address. When the R/W¯ bit is zero, the TX FIFO is 10.3 SPI Read accessed, and the RX FIFO is accessed when the R/W¯ bit is one. When reading register fields over the SPI interface while the register fields are updated The TX FIFO is write-only, while the RX FIFO by the radio hardware (e.g. MARCSTATE or is read-only. TXBYTES), there is a small, but finite, The burst bit is used to determine if the FIFO probability that a single read from the register access is a single byte access or a burst is being corrupt. As an example, the access. The single byte access method probability of any single read from TXBYTES expects a header byte with the burst bit set to being corrupt, assuming the maximum data zero and one data byte. After the data byte a rate is used, is approximately 80 ppm. Refer to new header byte is expected; hence, CSn can the CC1100 Errata Notes [1] for more details. remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting 10.4 Command Strobes CSn high. Command Strobes may be viewed as single The following header bytes access the FIFOs: byte instructions to CC1100. By addressing a command strobe register, internal sequences • 0x3F: Single byte access to TX FIFO will be started. These commands are used to disable the crystal oscillator, enable receive • 0x7F: Burst access to TX FIFO mode, enable wake-on-radio etc. The 13 • 0xBF: Single byte access to RX FIFO command strobes are listed in Table 35 on page 60. • 0xFF: Burst access to RX FIFO The command strobe registers are accessed When writing to the TX FIFO, the status byte by transferring a single header byte (no data is (see Section 10.1) is output for each new data being transferred). That is, only the R/W¯ bit, byte on SO, as shown in Figure 7. This status the burst access bit (set to 0), and the six byte can be used to detect TX FIFO underflow address bits (in the range 0x30 through 0x3D) while writing data to the TX FIFO. Note that are written. The R/W¯ bit can be either one or the status byte contains the number of bytes zero and will determine how the free before writing the byte in progress to the FIFO_BYTES_AVAILABLE field in the status TX FIFO. When the last byte that fits in the TX byte should be interpreted. FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that When writing command strobes, the status one byte is free in the TX FIFO. byte is sent on the SO pin. The TX FIFO may be flushed by issuing a A command strobe may be followed by any SFTX command strobe. Similarly, a SFRX other SPI access without pulling CSn high. command strobe will flush the RX FIFO. A However, if an SRES strobe is being issued, SFTX or SFRX command strobe can only be one will have to waith for SO to go low again issued in the IDLE, TXFIFO_UNDERLOW, or before the next header byte can be issued as RXFIFO_OVERFLOW states. Both FIFOs are shown in Figure 8. The command strobes are flushed when going to the SLEEP state. executed immediately, with the exception of the SPWD and the SXOFF strobes that are Figure 9 gives a brief overview of different executed when CSn goes high. register access types possible. SWRS038C Page 27 of 96

CC1100 10.6 PATABLE Access written and read from the lowest setting (0) to the highest (7), one byte at a time. An index The 0x3E address is used to access the counter is used to control the access to the PATABLE, which is used for selecting PA table. This counter is incremented each time a power control settings. The SPI expects up to byte is read or written to the table, and set to eight data bytes after receiving the address. the lowest index when CSn is high. When the By programming the PATABLE, controlled PA highest value is reached the counter restarts power ramp-up and ramp-down can be at zero. achieved, as well as ASK modulation shaping for reduced bandwidth. Note that both the ASK The access to the PATABLE is either single modulation shaping and the PA ramping is byte or burst access depending on the burst limited to output powers up to -1 dBm, and the bit. When using burst access the index counter PATABLE settings allowed are 0x00 and 0x30 will count up; when reaching 7 the counter will to 0x3F. See SmartRF® Studio [ 7] for restart at 0. The R/W¯ bit controls whether the recommended shaping / PA ramping access is a read or a write access. sequences. If one byte is written to the PATABLE and this See Section 2 4 on page 49 for details on value is to be read out then CSn must be set output power programming. high before the read access in order to set the index counter back to zero. The PATABLE is an 8-byte table that defines the PA control settings to use for each of the Note that the content of the PATABLE is lost eight PA power values (selected by the 3-bit when entering the SLEEP state, except for the value FREND0.PA_POWER). The table is first byte (index 0). Figure 9: Register Access Types 11 Microcontroller Interface and Pin Configuration In a typical system, CC1100 will interface to a (GDO1) that can output internal status microcontroller. This microcontroller must be information useful for control software. These able to: pins can be used to generate interrupts on the MCU. See Section 30 page 55 for more details • Program CC1100 into different modes on the signals that can be programmed. • Read and write buffered data GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is • Read back status information via the 4-wire 3-state output. By selecting any other of the SPI-bus configuration interface (SI, SO, programming options, the GDO1/SO pin will SCLK and CSn). become a generic pin. When CSn is low, the pin will always function as a normal SO pin. 11.1 Configuration Interface In the synchronous and asynchronous serial The microcontroller uses four I/O pins for the modes, the GDO0 pin is used as a serial TX SPI configuration interface (SI, SO, SCLK and data input pin while in transmit mode. CSn). The SPI is described in Section 10 on The GDO0 pin can also be used for an on-chip page 24. analog temperature sensor. By measuring the voltage on the GDO0 pin with an external ADC, the temperature can be calculated. 11.2 General Control and Status Pins Specifications for the temperature sensor are The CC1100 has two dedicated configurable found in Section 4.7 on page 16. pins (GDO0 and GDO2) and one shared pin SWRS038C Page 28 of 96

CC1100 With default PTEST register setting (0x7F) the latched and a command strobe is generated temperature sensor output is only available internally according to the pin configuration. It when the frequency synthesizer is enabled is only possible to change state with this (e.g. the MANCAL, FSTXON, RX, and TX functionality. That means that for instance RX states). It is necessary to write 0xBF to the will not be restarted if SI and SCLK are set to PTEST register to use the analog temperature RX and CSn toggles. When CSn is low the SI sensor in the IDLE state. Before leaving the and SCLK has normal SPI functionality. IDLE state, the PTEST register should be All pin control command strobes are executed restored to its default value (0x7F). immediately, except the SPWD strobe, which is delayed until CSn goes high. 11.3 Optional Radio Control Feature The CC1100 has an optional way of controlling CSn SCLK SI Function the radio, by reusing SI, SCLK, and CSn from the SPI interface. This feature allows for a 1 X X Chip unaffected by SCLK/SI simple three-pin control of the major states of ↓ 0 0 Generates SPWD strobe the radio: SLEEP, IDLE, RX, and TX. ↓ 0 1 Generates STX strobe This optional functionality is enabled with the ↓ 1 0 Generates SIDLE strobe MCSM0.PIN_CTRL_EN configuration bit. ↓ 1 1 Generates SRX strobe State changes are commanded as follows: When CSn is high the SI and SCLK is set to 0 SPI SPI SPI mode (wakes up into mode mode IDLE if in SLEEP/XOFF) the desired state according to Table 18. When CSn goes low the state of SI and SCLK is Table 18: Optional Pin Control Coding 12 Data Rate Programming The data rate used when transmitting, or the If DRATE_M is rounded to the nearest integer data rate expected in receive is programmed and becomes 256, increment DRATE_E and by the MDMCFG3.DRATE_M and the use DRATE_M = 0. MDMCFG4.DRATE_E configuration registers. The data rate can be set from 1.2 kBaud to The data rate is given by the formula below. 500 kBaud with the minimum step size of: As the formula shows, the programmed data rate depends on the crystal frequency. Min Data Typical Data Max Data Data rate Rate Rate Rate Step Size (256+DRATE_M)⋅2DRATE_E R = ⋅ f [kBaud] [kBaud] [kBaud] [kBaud] DATA 228 XOSC 0.8 1.2 / 2.4 3.17 0.0062 3.17 4.8 6.35 0.0124 The following approach can be used to find 6.35 9.6 12.7 0.0248 suitable values for a given data rate: 12.7 19.6 25.4 0.0496 ⎢ ⎛R ⋅220 ⎞⎥ 25.4 38.4 50.8 0.0992 DRATE_E = ⎢log ⎜ DATA ⎟⎥ ⎢⎣ 2⎜⎝ fXOSC ⎟⎠⎥⎦ 50.8 76.8 101.6 0.1984 101.6 153.6 203.1 0.3967 R ⋅228 DRATE_M = DATA −256 203.1 250 406.3 0.7935 f ⋅2DRATE_E 406.3 500 500 1.5869 XOSC Table 19: Data Rate Step Size SWRS038C Page 29 of 96

CC1100 13 Receiver Channel Filter Bandwidth In order to meet different channel width For best performance, the channel filter requirements, the receiver channel filter is bandwidth should be selected so that the programmable. The MDMCFG4.CHANBW_E and signal bandwidth occupies at most 80% of the MDMCFG4.CHANBW_M configuration registers channel filter bandwidth. The channel centre control the receiver channel filter bandwidth, tolerance due to crystal accuracy should also which scales with the crystal oscillator be subtracted from the signal bandwidth. The frequency. The following formula gives the following example illustrates this: relation between the register settings and the With the channel filter bandwidth set to channel filter bandwidth: 500 kHz, the signal should stay within 80% of f 500 kHz, which is 400 kHz. Assuming BW = XOSC 915 MHz frequency and ±20 ppm frequency channel 8⋅(4+CHANBW_M)·2CHANBW_E uncertainty for both the transmitting device and the receiving device, the total frequency The CC1100 supports the following channel uncertainty is ±40 ppm of 915MHz, which is filter bandwidths: ±37 kHz. If the whole transmitted signal MDMCFG4. MDMCFG4.CHANBW_E bandwidth is to be received within 400kHz, the transmitted signal bandwidth should be CHANBW_M 00 01 10 11 maximum 400kHz – 2·37 kHz, which is 00 812 406 203 102 326 kHz. 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58 Table 20: Channel Filter Bandwidths [kHz] (Assuming a 26MHz crystal) 14 Demodulator, Symbol Synchronizer, and Data Decision CC1100 contains an advanced and highly If the FOCCFG.FOC_BS_CS_GATE bit is set, configurable demodulator. Channel filtering the offset compensator will freeze until carrier and frequency offset compensation is sense asserts. This may be useful when the performed digitally. To generate the RSSI level radio is in RX for long periods with no traffic, (see Section 17.3 for more information) the since the algorithm may drift to the boundaries signal level in the channel is estimated. Data when trying to track noise. filtering is also included for enhanced The tracking loop has two gain factors, which performance. affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the 14.1 Frequency Offset Compensation gain before the sync word is detected, and FOCCFG.FOC_POST_K selects the gain after When using 2-FSK, GFSK, or MSK the sync word has been found. modulation, the demodulator will compensate for the offset between the transmitter and Note that frequency offset compensation is not receiver frequency, within certain limits, by supported for ASK or OOK modulation. estimating the centre of the received data. This value is available in the FREQEST status 14.2 Bit Synchronization register. Writing the value from FREQEST into FSCTRL0.FREQOFF the frequency The bit synchronization algorithm extracts the synthesizer is automatically adjusted clock from the incoming symbols. The according to the estimated frequency offset. algorithm requires that the expected data rate is programmed as described in Section 12 on The tracking range of the algorithm is page 29. Re-synchronization is performed selectable as fractions of the channel continuously to adjust for error in the incoming bandwidth with the FOCCFG.FOC_LIMIT symbol rate. configuration register. SWRS038C Page 30 of 96

CC1100 14.3 Byte Synchronization 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality Byte synchronization is achieved by a indicator mechanism described below and/or a continuous sync word search. The sync word carrier sense condition. The sync word is is a 16 bit configurable field (can be repeated configured through the SYNC1 and SYNC0 to get a 32 bit) that is automatically inserted at registers. the start of the packet by the modulator in transmit mode. The demodulator uses this In order to make false detections of sync field to find the byte boundaries in the stream words less likely, a mechanism called of bits. The sync word will also function as a preamble quality indication (PQI) can be used system identifier, since only packets with the to qualify the sync word. A threshold value for correct predefined sync word will be received if the preamble quality must be exceeded in the sync word detection in RX is enabled in order for a detected sync word to be accepted. register MDMCFG2 (see Section 17.1). The See Section 17.2 on page 37 for more details. sync word detector correlates against the user-configured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 15 Packet Handling Hardware Support The CC1100 has built-in hardware support for • Packet length check (length byte checked packet oriented radio protocols. against a programmable maximum length). In transmit mode, the packet handler can be • De-whitening configured to add the following elements to the • De-interleaving and decoding packet stored in the TX FIFO: • Optionally, two status bytes (see Table 21 • A programmable number of preamble and Table 22) with RSSI value, Link bytes Quality Indication, and CRC status can be • A two byte synchronization (sync) word. appended in the RX FIFO. Can be duplicated to give a 4-byte sync • word (recommended). It is not possible to Bit Field Name Description only insert preamble or only insert a sync 7:0 RSSI RSSI value word. • A CRC checksum computed over the Table 21: Received Packet Status Byte 1 data field. (first byte appended after the data) • • The recommended setting is 4-byte preamble and 4-byte sync word, except Bit Field Name Description for 500 kBaud data rate where the recommended preamble length is 8 bytes. 7 CRC_OK 1: CRC for received data OK (or CRC disabled) • • In addition, the following can be 0: CRC error in received data implemented on the data field and the 6:0 LQI Indicating the link quality optional 2-byte CRC checksum: • Table 22: Received Packet Status Byte 2 • Whitening of the data with a PN9 (second byte appended after the data) sequence. • • Forward error correction by the use of • Note that register fields that control the interleaving and coding of the data packet handling features should only be (convolutional coding). altered when CC1100 is in the IDLE state. • In receive mode, the packet handling support 15.1 Data Whitening will de-construct the data packet by implementing the following (if enabled): From a radio perspective, the ideal over the air data are random and DC free. This results in • Preamble detection. the smoothest power distribution over the • Sync word detection. occupied bandwidth. This also gives the • CRC computation and CRC check. regulation loops in the receiver uniform • One byte address check. operation conditions (no data dependencies). SWRS038C Page 31 of 96

CC1100 Real world data often contain long sequences XOR-ed with a 9-bit pseudo-random (PN9) of zeros and ones. Performance can then be sequence before being transmitted, as shown improved by whitening the data before in Figure 10. At the receiver end, the data are transmitting, and de-whitening the data in the XOR-ed with the same pseudo-random receiver. With CC1100, this can be done sequence. This way, the whitening is reversed, automatically by setting and the original data appear in the receiver. PKTCTRL0.WHITE_DATA=1. All data, except The PN9 sequence is initialized to all 1’s. the preamble and the sync word, are then Figure 10: Data Whitening in TX Mode 15.2 Packet Format • Optional length byte • Optional address byte The format of the data packet can be • Payload configured and consists of the following items • Optional 2 byte CRC (see Figure 11): • • Preamble • Synchronization word Optional data whitening Optionally FEC encoded/decoded Legend: Optional CRC-16 calculation Inserted automatically in TX, processed and removed in RX. P(1r0e1a0m..b.1le0 b1i0ts) Sync word Length field Address field Data field CRC-16 OpUrnpoptciroeonscasele sudss ebedur -tup nsrooetvr irddeaemtdao fv(ieaelpdda sirn tp RfrrooXcm.es FsEedC in TX, and/or whitening) 8 8 8 x n bits 16/32 bits 8 x n bits 16 bits bits bits Figure 11: Packet Format The preamble pattern is an alternating When the programmed number of preamble sequence of ones and zeros (10101010…). bytes has been transmitted, the modulator will The minimum length of the preamble is send the sync word and then data from the TX programmable. When enabling TX, the FIFO if data is available. If the TX FIFO is modulator will start transmitting the preamble. empty, the modulator will continue to send SWRS038C Page 32 of 96

CC1100 preamble bytes until the first byte is written to (PKTCTRL0.LENGTH_CONFIG=0) this opens the TX FIFO. The modulator will then send the the possibility to have a different length field sync word and then the data bytes. The configuration than supported for variable number of preamble bytes is programmed with length packets (in variable packet length mode the MDMCFG1.NUM_PREAMBLE value. the length byte is the first byte after the sync word). At the start of reception, the packet The synchronization word is a two-byte value length is set to a large value. The MCU reads set in the SYNC1 and SYNC0 registers. The out enough bytes to interpret the length field in sync word provides byte synchronization of the the packet. Then the PKTLEN value is set incoming packet. A one-byte synch word can according to this value. The end of packet will be emulated by setting the SYNC1 value to the occur when the byte counter in the packet preamble pattern. It is also possible to emulate handler is equal to the PKTLEN register. Thus, a 32 bit sync word by using the MCU must be able to program the correct MDMCFG2.SYNC_MODE set to 3 or 7. The sync length, before the internal counter reaches the word will then be repeated twice. packet length. CC1100 supports both constant packet length protocols and variable length protocols. 15.2.2 Packet Length > 255 Variable or fixed packet length mode can be Also the packet automation control register, used for packets up to 255 bytes. For longer PKTCTRL0, can be reprogrammed during TX packets, infinite packet length mode must be and RX. This opens the possibility to transmit used. and receive packets that are longer than 256 Fixed packet length mode is selected by bytes and still be able to use the packet setting PKTCTRL0.LENGTH_CONFIG=0. The handling hardware support. At the start of the desired packet length is set by the PKTLEN packet, the infinite packet length mode register. (PKTCTRL0.LENGTH_CONFIG=2) must be active. On the TX side, the PKTLEN register is In variable packet length mode, set to mod(length, 256). On the RX side the PKTCTRL0.LENGTH_CONFIG=1, the packet MCU reads out enough bytes to interpret the length is configured by the first byte after the length field in the packet and sets the PKTLEN sync word. The packet length is defined as the register to mod(length, 256). When less than payload data, excluding the length byte and 256 bytes remains of the packet the MCU the optional CRC. The PKTLEN register is disables infinite packet length mode and used to set the maximum packet length activates fixed packet length mode. When the allowed in RX. Any packet received with a internal byte counter reaches the PKTLEN length byte with a value greater than PKTLEN value, the transmission or reception ends (the will be discarded. radio enters the state determined by With PKTCTRL0.LENGTH_CONFIG=2, the TXOFF_MODE or RXOFF_MODE). Automatic packet length is set to infinite and transmission CRC appending/checking can also be used and reception will continue until turned off (by setting PKTCTRL0.CRC_EN=1). manually. As described in the next section, this When for example a 600-byte packet is to be can be used to support packet formats with transmitted, the MCU should do the following different length configuration than natively (see also Figure 12) supported by CC1100. One should make sure that TX mode is not turned off during the • Set PKTCTRL0.LENGTH_CONFIG=2. transmission of the first half of any byte. Refer to the CC1100 Errata Notes [1] for more details. • Pre-program the PKTLEN register to mod(600, 256) = 88. Note that the minimum packet length supported (excluding the optional length byte • Transmit at least 345 bytes (600 - 255), for and CRC) is one byte of payload data. example by filling the 64-byte TX FIFO six times (384 bytes transmitted). 15.2.1 Arbitrary Length Field Configuration • Set PKTCTRL0.LENGTH_CONFIG=0. The packet length register, PKTLEN, can be • The transmission ends when the packet reprogrammed during receive and transmit. In counter reaches 88. A total of 600 bytes combination with fixed packet length mode are transmitted. SWRS038C Page 33 of 96

CC1100 Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,....................... Infinite packet length enabled Fixed packet length 600 bytes transmitted and enabled when less than received 256 bytes remains of packet Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88 Figure 12: Packet Length > 255 15.3 Packet Filtering in Receive Mode CC1100 supports three different types of FIFO if the CRC check fails. After auto flushing packet-filtering; address filtering, maximum the RX FIFO, the next state depends on the length filtering, and CRC filtering. MCSM1.RXOFF_MODE setting. When using the auto flush function, the 15.3.1 Address Filtering maximum packet length is 63 bytes in variable Setting PKTCTRL1.ADR_CHK to any other packet length mode and 64 bytes in fixed value than zero enables the packet address packet length mode. Note that the maximum filter. The packet handler engine will compare allowed packet length is reduced by two bytes the destination address byte in the packet with when PKTCTRL1.APPEND_STATUS is the programmed node address in the ADDR enabled, to make room in the RX FIFO for the register and the 0x00 broadcast address when two status bytes appended at the end of the PKTCTRL1.ADR_CHK=10 or both 0x00 and packet. Since the entire RX FIFO is flushed 0xFF broadcast addresses when when the CRC check fails, the previously PKTCTRL1.ADR_CHK=11. If the received received packet must be read out of the FIFO before receiving the current packet. The MCU address matches a valid address, the packet is received and written into the RX FIFO. If the must not read from the current packet until the CRC has been checked as OK. address match fails, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODE setting). 15.4 Packet Handling in Transmit Mode If the received address matches a valid The payload that is to be transmitted must be address when using infinite packet length written into the TX FIFO. The first byte written mode and address filtering is enabled, 0xFF must be the length byte when variable packet will be written into the RX FIFO followed by the length is enabled. The length byte has a value address byte and then the payload data. equal to the payload of the packet (including the optional address byte). If address 15.3.2 Maximum Length Filtering recognition is enabled on the receiver, the second byte written to the TX FIFO must be In variable packet length mode, the address byte. If fixed packet length is PKTCTRL0.LENGTH_CONFIG=1, the enabled, then the first byte written to the TX PKTLEN.PACKET_LENGTH register value is FIFO should be the address (if the receiver used to set the maximum allowed packet uses address recognition). length. If the received length byte has a larger value than this, the packet is discarded and The modulator will first send the programmed receive mode restarted (regardless of the number of preamble bytes. If data is available MCSM1.RXOFF_MODE setting). in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word and 15.3.3 CRC Filtering then the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all The filtering of a packet when CRC check fails the data pulled from the TX FIFO and the is enabled by setting result is sent as two extra bytes following the PKTCTRL1.CRC_AUTOFLUSH=1. The CRC payload data. If the TX FIFO runs empty auto flush function will flush the entire RX before the complete packet has been SWRS038C Page 34 of 96

CC1100 transmitted, the radio will enter when a packet has been received/transmitted. TXFIFO_UNDERFLOW state. The only way to Additionally, for packets longer than 64 bytes exit this state is by issuing an SFTX strobe. the RX FIFO needs to be read while in RX and Writing to the TX FIFO after it has underflowed the TX FIFO needs to be refilled while in TX. will not restart TX mode. This means that the MCU needs to know the number of bytes that can be read from or If whitening is enabled, everything following written to the RX FIFO and TX FIFO the sync words will be whitened. This is done respectively. There are two possible solutions before the optional FEC/Interleaver stage. to get the necessary status information: Whitening is enabled by setting PKTCTRL0.WHITE_DATA=1. a) Interrupt Driven Solution If FEC/Interleaving is enabled, everything In both RX and TX one can use one of the following the sync words will be scrambled by GDO pins to give an interrupt when a sync the interleaver and FEC encoded before being word has been received/transmitted and/or modulated. FEC is enabled by setting when a complete packet has been MDMCFG1.FEC_EN=1. received/transmitted (IOCFGx.GDOx_CFG=0x06). In addition, there are 2 configurations for the 15.5 Packet Handling in Receive Mode IOCFGx.GDOx_CFG register that are In receive mode, the demodulator and packet associated with the RX FIFO handler will search for a valid preamble and (IOCFGx.GDOx_CFG=0x00 and the sync word. When found, the demodulator IOCFGx.GDOx_CFG=0x01) and two that are has obtained both bit and byte synchronism associated with the TX FIFO and will receive the first payload byte. (IOCFGx.GDOx_CFG=0x02 and IOCFGx.GDOx_CFG=0x03) that can be used If FEC/Interleaving is enabled, the FEC as interrupt sources to provide information on decoder will start to decode the first payload how many bytes are in the RX FIFO and TX byte. The interleaver will de-scramble the bits FIFO respectively. See Table 34. before any other processing is done to the data. b) SPI Polling If whitening is enabled, the data will be de- The PKTSTATUS register can be polled at a whitened at this stage. given rate to get information about the current When variable packet length mode is enabled, GDO2 and GDO0 values respectively. The the first byte is the length byte. The packet RXBYTES and TXBYTES registers can be handler stores this value as the packet length polled at a given rate to get information about and receives the number of bytes indicated by the number of bytes in the RX FIFO and TX the length byte. If fixed packet length mode is FIFO respectively. Alternatively, the number of used, the packet handler will accept the bytes in the RX FIFO and TX FIFO can be programmed number of bytes. read from the chip status byte returned on the MISO line each time a header byte, data byte, Next, the packet handler optionally checks the or command strobe is sent on the SPI bus. address and only continues the reception if the address matches. If automatic CRC check is It is recommended to employ an interrupt enabled, the packet handler computes CRC driven solution as high rate SPI polling will and matches it with the appended CRC reduce the RX sensitivity. Furthermore, as checksum. explained in Section 10.3 and the CC1100 Errata Notes [ 1], when using SPI polling there At the end of the payload, the packet handler is a small, but finite, probability that a single will optionally write two extra packet status read from registers PKTSTATUS , RXBYTES bytes (see Table 21 and Table 22) that contain and TXBYTES is being corrupt. The same is CRC status, link quality indication, and RSSI the case when reading the chip status byte. value. Refer to the TI website for SW examples ( [8] and [9]). 15.6 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know SWRS038C Page 35 of 96

CC1100 16 Modulation Formats CC1100 supports amplitude, frequency, and 16.2 Minimum Shift Keying phase shift modulation formats. The desired When using MSK1, the complete transmission modulation format is set in the (preamble, sync word, and payload) will be MDMCFG2.MOD_FORMAT register. MSK modulated. Optionally, the data stream can be Manchester Phase shifts are performed with a constant coded by the modulator and decoded by the transition time. demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN=1. Manchester The fraction of a symbol period used to encoding is not supported at the same time as change the phase can be modified with the using the FEC/Interleaver option. DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol. 16.1 Frequency Shift Keying The MSK modulation format implemented in 2-FSK can optionally be shaped by a CC1100 inverts the sync word and data Gaussian filter with BT = 1, producing a GFSK compared to e.g. signal generators. modulated signal. The frequency deviation is programmed with 16.3 Amplitude Modulation the DEVIATION_M and DEVIATION_E values in the DEVIATN register. The value has an CC1100 supports two different forms of exponent/mantissa form, and the resultant amplitude modulation: On-Off Keying (OOK) deviation is given by: and Amplitude Shift Keying (ASK). f OOK modulation simply turns on or off the PA f = xosc ⋅(8+DEVIATION _M)⋅2DEVIATION_E to modulate 1 and 0 respectively. dev 217 The ASK variant supported by the CC1100 The symbol encoding is shown in Table 23. allows programming of the modulation depth (the difference between 1 and 0), and shaping Format Symbol Coding of the pulse amplitude. Pulse shaping will 2-FSK/GFSK ‘0’ – Deviation produce a more bandwidth constrained output spectrum. Note that the pulse shaping feature ‘1’ + Deviation on the CC1100 does only support output power Table 23: Symbol Encoding for 2-FSK/GFSK up to about -1dBm. The PATABLE settings that Modulation can be used for pulse shaping are 0x00 and 0x30 to 0x3F. 1 Identical to offset QPSK with half-sine shaping (data coding may differ) SWRS038C Page 36 of 96

CC1100 17 Received Signal Qualifiers and Link Quality Information CC1100 has several qualifiers that can be used A “Preamble Quality Reached” signal can be to increase the likelihood that a valid sync observed on one of the GDO pins by setting word is detected. IOCFGx.GDOx_CFG=8. It is also possible to determine if preamble quality is reached by checking the PQT_REACHED bit in the 17.1 Sync Word Qualifier PKTSTATUS register. This signal / bit asserts If sync word detection in RX is enabled in when the received signal exceeds the PQT. register MDMCFG2 the CC1100 will not start filling the RX FIFO and perform the packet 17.3 RSSI filtering described in Section 1 5.3 before a valid sync word has been detected. The sync The RSSI value is an estimate of the signal word qualifier mode is set by power level in the chosen channel. This value MDMCFG2.SYNC_MODE and is summarized in is based on the current gain setting in the RX Table 24. Carrier sense is described in Section chain and the measured signal level in the 17.4. channel. In RX mode, the RSSI value can be read continuously from the RSSI status register until MDMCFG2. Sync Word Qualifier Mode the demodulator detects a sync word (when SYNC_MODE sync word detection is enabled). At that point the RSSI readout value is frozen until the next 000 No preamble/sync time the chip enters the RX state. The RSSI 001 15/16 sync word bits detected value is in dBm with ½dB resolution. The RSSI 010 16/16 sync word bits detected update rate, fRSSI, depends on the receiver filter bandwidth (BW defined in Section 011 30/32 sync word bits detected channel 13) and AGCCTRL0.FILTER_LENGTH. 100 No preamble/sync, carrier sense above threshold 101 15/16 + carrier sense above threshold 2⋅BW f = channel 110 16/16 + carrier sense above threshold RSSI 8⋅2FILTER_LENGTH 111 30/32 + carrier sense above threshold Table 24: Sync Word Qualifier Mode If PKTCTRL1.APPEND_STATUS is enabled the last RSSI value of the packet is automatically 17.2 Preamble Quality Threshold (PQT) added to the first byte appended after the payload. The Preamble Quality Threshold (PQT) sync- word qualifier adds the requirement that the The RSSI value read from the RSSI status received sync word must be preceded with a register is a 2’s complement number. The preamble with a quality above the following procedure can be used to convert the programmed threshold. RSSI reading to an absolute power level (RSSI_dBm). Another use of the preamble quality threshold is as a qualifier for the optional RX termination 1) Read the RSSI status register timer. See Section 19.7 on page 46 for details. 2) Convert the reading from a hexadecimal number to a decimal number (RSSI_dec) The preamble quality estimator increases an internal counter by one each time a bit is 3) If RSSI_dec ≥ 128 then RSSI_dBm = received that is different from the previous bit, (RSSI_dec - 256)/2 – RSSI_offset and decreases the counter by 8 each time a 4) Else if RSSI_dec < 128 then RSSI_dBm = bit is received that is the same as the last bit. (RSSI_dec)/2 – RSSI_offset The threshold is configured with the register field PKTCTRL1.PQT. A threshold of 4·PQT for Table 25 gives typical values for the this counter is used to gate sync word RSSI_offset. detection. By setting the value to zero, the Figure 13 and Figure 14 shows typical plots of preamble quality qualifier of the synch word is RSSI reading as a function of input power disabled. level for different data rates. SWRS038C Page 37 of 96

CC1100 Data rate [kBaud] RSSI_offset [dB], 433 MHz RSSI_offset [dB], 868 MHz 1.2 75 74 38.4 75 74 250 79 78 500 79 77 Table 25: Typical RSSI_offset Values 0 -10 -20 -30 -40 m] B d -50 dout [ -60 a Re SI -70 S R -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBuad 38.4 kBaud 250 kBaud 500 kBaud Figure 13: Typical RSSI Value vs. Input Power Level for Different Data Rates at 433 MHz 0 -10 -20 -30 m] -40 B ut [d -50 do -60 a e SI R -70 S R -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBaud 38.4 kBuad 250 kBaud 500 kBaud Figure 14: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz SWRS038C Page 38 of 96

CC1100 17.4 Carrier Sense (CS) Studio to generate the correct MAGN_TARGET setting. Carrier Sense (CS) is used as a sync word qualifier and for CCA and can be asserted Table 26 and Table 27 show the typical RSSI based on two conditions, which can be readout values at the CS threshold at 2.4 individually adjusted: kBaud and 250 kBaud data rate respectively. The default CARRIER_SENSE_ABS_THR=0 (0 • CS is asserted when the RSSI is above a dB) and MAGN_TARGET=3 (33 dB) have been programmable absolute threshold, and de- used. asserted when RSSI is below the same threshold (with hysteresis). For other data rates the user must generate similar tables to find the CS absolute • CS is asserted when the RSSI has threshold. increased with a programmable number of dB from one RSSI sample to the next, and MAX_DVGA_GAIN[1:0] de-asserted when RSSI has decreased with the same number of dB. This setting 00 01 10 11 is not dependent on the absolute signal 000 -97.5 -91.5 -85.5 -79.5 level and is thus useful to detect signals in 001 -94 -88 -82.5 -76 environments with time varying noise floor. 0] Carrier Sense can be used as a sync word N[2: 010 -90.5 -84.5 -78.5 -72.5 qualifier that requires the signal level to be GAI 011 -88 -82.5 -76.5 -70.5 _ higher than the threshold for a sync word NA 100 -85.5 -80 -73.5 -68 search to be performed. The signal can also L _ X 101 -84 -78 -72 -66 be observed on one of the GDO pins by A M setting IOCFGx.GDOx_CFG=14 and in the 110 -82 -76 -70 -64 status register bit PKTSTATUS.CS. 111 -79 -73.5 -67 -61 Other uses of Carrier Sense include the TX-if- Table 26: Typical RSSI Value in dBm at CS CCA function (see Section 17.5 on page 40) Threshold with Default MAGN_TARGET at 2.4 and the optional fast RX termination (see kBaud, 868 MHz Section 19.7 on page 46). CS can be used to avoid interference from other RF sources in the ISM bands. MAX_DVGA_GAIN[1:0] 00 01 10 11 17.4.1 CS Absolute Threshold 000 -90.5 -84.5 -78.5 -72.5 The absolute threshold related to the RSSI 001 -88 -82 -76 -70 value depends on the following register fields: 0] • AGCCTRL2.MAX_LNA_GAIN GAIN[2: 001101 --8842..55 --7786..55 --7720 --6664 • AGCCTRL2.MAX_DVGA_GAIN NA_ 100 -80.5 -74.5 -68 -62 L • AGCCTRL1.CARRIER_SENSE_ABS_THR X_ 101 -78 -72 -66 -60 A M • AGCCTRL2.MAGN_TARGET 110 -76.5 -70 -64 -58 111 -74.5 -68 -62 -56 • For a given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN setting the Table 27: Typical RSSI Value in dBm at CS absolute threshold can be adjusted ±7 dB in Threshold with Default MAGN_TARGET at 250 steps of 1 dB using kBaud, 868 MHz CARRIER_SENSE_ABS_THR. The MAGN_TARGET setting is a compromise If the threshold is set high, i.e. only strong between blocker tolerance/selectivity and signals are wanted, the threshold should be sensitivity. The value sets the desired signal adjusted upwards by first reducing the level in the channel into the demodulator. Increasing this value reduces the headroom MAX_LNA_GAIN value and then the for blockers, and therefore close-in selectivity. MAX_DVGA_GAIN value. This will reduce It is strongly recommended to use SmartRF® power consumption in the receiver front end, since the highest gain settings are avoided. SWRS038C Page 39 of 96

CC1100 17.4.2 CS Relative Threshold feature is called TX-if-CCA. Four CCA requirements can be programmed: The relative threshold detects sudden changes in the measured signal level. This setting is not • Always (CCA disabled, always goes to TX) dependent on the absolute signal level and is • If RSSI is below threshold thus useful to detect signals in environments with a time varying noise floor. The register • Unless currently receiving a packet field AGCCTRL1.CARRIER_SENSE_REL_THR • Both the above (RSSI below threshold and is used to enable/disable relative CS, and to not currently receiving a packet) select threshold of 6 dB, 10 dB, or 14 dB RSSI change. 17.6 Link Quality Indicator (LQI) 17.5 Clear Channel Assessment (CCA) The Link Quality Indicator is a metric of the current quality of the received signal. If The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or PKTCTRL1.APPEND_STATUS is enabled, the busy. The current CCA state is viewable on value is automatically added to the last byte any of the GDO pins by setting appended after the payload. The value can IOCFGx.GDOx_ CFG=0x09. also be read from the LQI status register. The LQI gives an estimate of how easily a received MCSM1.CCA_MODE selects the mode to use signal can be demodulated by accumulating when determining CCA. the magnitude of the error between ideal constellations and the received signal over the When the STX or SFSTXON command strobe is 64 symbols immediately following the sync given while CC1100 is in the RX state, the TX or word. LQI is best used as a relative FSTXON state is only entered if the clear measurement of the link quality (a high value channel requirements are fulfilled. The chip will indicates a better link than what a low value otherwise remain in RX (if the channel does), since the value is dependent on the becomes available, the radio will not enter TX modulation format. or FSTXON state before a new strobe command is sent on the SPI interface). This 18 Forward Error Correction with Interleaving 18.1 Forward Error Correction (FEC) a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, CC1100 has built in support for Forward Error transient and time-varying phenomena will Correction (FEC). To enable this option, set produce occasional errors even in otherwise MDMCFG1.FEC_EN to 1. FEC is only supported good reception conditions. FEC will mask such in fixed packet length mode errors and, combined with interleaving of the (PKTCTRL0.LENGTH_CONFIG=0). FEC is coded data, even correct relatively long employed on the data field and CRC word in periods of faulty reception (burst errors). order to reduce the gross bit error rate when operating near the sensitivity limit. The FEC scheme adopted for CC1100 is Redundancy is added to the transmitted data convolutional coding, in which n bits are in such a way that the receiver can restore the generated based on k input bits and the m original data in the presence of some bit most recent input bits, forming a code stream errors. able to withstand a certain number of bit errors between each coding state (the m-bit window). The use of FEC allows correct reception at a lower SNR, thus extending communication The convolutional coder is a rate 1/2 code with range if the receiver bandwidth remains a constraint length of m = 4. The coder codes constant. Alternatively, for a given SNR, using one input bit and produces two output bits; FEC decreases the bit error rate (BER). As the hence, the effective data rate is halved. I.e. to packet error rate (PER) is related to BER by: transmit at the same effective datarate when using FEC, it is necessary to use twice as high PER =1−(1−BER)packet_length over-the-air datarate. This will require a higher receiver bandwidth, and thus reduce a lower BER can be used to allow longer sensitivity. In other words the improved packets, or a higher percentage of packets of SWRS038C Page 40 of 96

CC1100 reception by using FEC and the degraded receiver, the received symbols are written into sensitivity from a higher receiver bandwidth the columns of the matrix, whereas the data will be counteracting factors. passed onto the convolutional decoder is read from the rows of the matrix. 18.2 Interleaving When FEC and interleaving is used at least one extra byte is required for trellis Data received through radio channels will termination. In addition, the amount of data often experience burst errors due to transmitted over the air must be a multiple of interference and time-varying signal strengths. the size of the interleaver buffer (two bytes). In order to increase the robustness to errors The packet control hardware therefore spanning multiple bits, interleaving is used automatically inserts one or two extra bytes at when FEC is enabled. After de-interleaving, a the end of the packet, so that the total length continuous span of errors in the received of the data to be interleaved is an even stream will become single errors spread apart. number. Note that these extra bytes are CC1100 employs matrix interleaving, which is invisible to the user, as they are removed illustrated in Figure 15. The on-chip before the received packet enters the RX interleaving and de-interleaving buffers are 4 x FIFO. 4 matrices. In the transmitter, the data bits When FEC and interleaving is used the from the rate ½ convolutional coder are written minimum data payload is 2 bytes. into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix. Conversely, in the Interleaver Interleaver Write buffer Read buffer Packet FEC Modulator Engine Encoder Interleaver Interleaver Write buffer Read buffer FEC Packet Demodulator Decoder Engine Figure 15: General Principle of Matrix Interleaving SWRS038C Page 41 of 96

CC1100 19 Radio Control SIDLE SPWD | SWOR SLEEP CAL_COMPLETE 0 MANCAL IDLE CSn = 0 | WOR 3,4,5 1 SXOFF SCAL CSn = 0 XOFF SRX | STX | SFSTXON | WOR 2 FS_WAKEUP 6,7 FS_AUTOCAL = 01 & SRX | STX | SFSTXON | WOR FS_AUTOCAL = 00 | 10 | 11 & CALIBRATE SRX | STX | SFSTXON | WOR 8 SETTLING CAL_COMPLETE SFSTXON 9,10,11 FSTXON 18 STX SRX | WOR STX SRX SFSTXON | RXOFF_MODE = 01 TXOFF_MODE=01 STX | RXOFF_MODE = 10 RXTX_SETTLING ( STX | SFSTXON ) & CCA 21 | TXOFF_MODE = 10 19T,X20 RXOFF_MODE = 01 | 10 13,R14X,15 RXOFF_MODE = 11 SRX | TXOFF_MODE = 11 TXRX_SETTLING 16 TXFIFO_UNDERFLOW TXOFF_M&O DE = 00 RXOFF_M&O DE = 00 RXFIFO_OVERFLOW FS_AUTOCAL = 10 | 11 FS_AUTOCAL = 10 | 11 CALIBRATE TXOFF_M&O DE = 00 12 RXOFF_M&ODE = 00 TX_UNDERFLOW FS_AUTOCAL = 00 | 01 FS_AUTOCAL = 00 | 01 RX_OVERFLOW 22 17 SFTX SFRX IDLE 1 Figure 16: Complete Radio Control State Diagram CC1100 has a built-in state machine that is 19.1 Power-On Start-Up Sequence used to switch between different operational When the power supply is turned on, the states (modes). The change of state is done system must be reset. This is achieved by one either by using command strobes or by of the two sequences described below, i.e. internal events such as TX FIFO underflow. automatic power-on reset (POR) or manual A simplified state diagram, together with reset. typical usage and current consumption, is After the automatic power-on reset or manual shown in Figure 5 on page 23. The complete reset it is also recommended to change the radio control state diagram is shown in Figure signal that is output on the GDO0 pin. The 16. The numbers refer to the state number default setting is to output a clock signal with a readable in the MARCSTATE status register. frequency of CLK_XOSC/192, but to optimize This register is primarily for test purposes. SWRS038C Page 42 of 96

CC1100 performance in TX and RX an alternative GDO XOSC and voltage regulator switched on setting should be selected from the settings found in Table 34 on page 56. 40 us CSn 19.1.1 Automatic POR A power-on reset circuit is included in the SO CC1100. The minimum requirements stated in Table 12 must be followed for the power-on XOSC Stable reset to function properly. The internal power- up sequence is completed when CHIP_RDYn SI SRES goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. See Section 10.1 Figure 18: Power-On Reset with SRES for more details on CHIP_RDYn. When the CC1100 reset is completed the chip will be in the IDLE state and the crystal Note that the above reset procedure is only oscillator will be running. If the chip has had required just after the power supply is first sufficient time for the crystal oscillator to turned on. If the user wants to reset the CC1100 stabilize after the power-on-reset the SO pin after this, it is only necessary to issue an SRES will go low immediately after taking CSn low. If command strobe. CSn is taken low before reset is completed the SO pin will first go high, indicating that the 19.2 Crystal Control crystal oscillator is not stabilized, before going low as shown in Figure 17. The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ON is set. In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released Figure 17: Power-On Reset (goes high). The XOSC will be automatically turned on again when CSn goes low. The 19.1.2 Manual Reset state machine will then go to the IDLE state. The SO pin on the SPI interface must be The other global reset possibility on CC1100 pulled low before the SPI interface is ready to uses the SRES command strobe. By issuing be used; as described in Section 10.1 on page this strobe, all internal registers and states are 26. set to the default, IDLE state. The manual power-up sequence is as follows (see Figure If the XOSC is forced on, the crystal will 18): always stay on even in the SLEEP state. • Set SCLK = 1 and SI = 0, to avoid Crystal oscillator start-up time depends on potential problems with pin control mode crystal ESR and load capacitances. The (see Section 11.3 on page 29). electrical specification for the crystal oscillator can be found in Section 4.4 on page 14. • Strobe CSn low / high. • Hold CSn high for at least 40µs relative to 19.3 Voltage Regulator Control pulling CSn low The voltage regulator to the digital core is • Pull CSn low and wait for SO to go low controlled by the radio controller. When the (CHIP_RDYn). chip enters the SLEEP state, which is the state with the lowest current consumption, the • Issue the SRES strobe on the SI line. voltage regulator is disabled. This occurs after • When SO goes low again, reset is CSn is released when a SPWD command complete and the chip is in the IDLE state. strobe has been sent on the SPI interface. The chip is now in the SLEEP state. Setting CSn SWRS038C Page 43 of 96

CC1100 low again will turn on the regulator and crystal has been successfully transmitted. Then the oscillator and make the chip enter the IDLE state will change as indicated by the state. MCSM1.TXOFF_MODE setting. The possible destinations are the same as for RX. When wake on radio is enabled, the WOR module will control the voltage regulator as The MCU can manually change the state from described in Section 19.5. RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and the SRX strobe is 19.4 Active Modes used, the current transmission will be ended CC1100 has two active modes: receive and and the transition to RX will be done. transmit. These modes are activated directly If the radio controller is in RX when the STX or by the MCU by using the SRX and STX SFSTXON command strobes are used, the TX- command strobes, or automatically by Wake if-CCA function will be used. If the channel is on Radio. not clear, the chip will remain in RX. The The frequency synthesizer must be calibrated MCSM1.CCA_MODE setting controls the regularly. CC1100 has one manual calibration conditions for clear channel assessment. See option (using the SCAL strobe), and three Section 17.5 on page 40 for details. automatic calibration options, controlled by the The SIDLE command strobe can always be MCSM0.FS_AUTOCAL setting: used to force the radio controller to go to the • Calibrate when going from IDLE to either IDLE state. RX or TX (or FSTXON) • Calibrate when going from either RX or TX 19.5 Wake On Radio (WOR) to IDLE automatically The optional Wake on Radio (WOR) • Calibrate every fourth time when going functionality enables CC1100 to periodically from either RX or TX to IDLE automatically wake up from SLEEP and listen for incoming packets without MCU interaction. If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe, calibration will not be When the WOR strobe command is sent on performed. The calibration takes a constant the SPI interface, the CC1100 will go to the number of XOSC cycles (see Table 28 for SLEEP state when CSn is released. The RC timing details). oscillator must be enabled before the WOR strobe can be used, as it is the clock source When RX is activated, the chip will remain in for the WOR timer. The on-chip timer will set receive mode until a packet is successfully CC1100 into IDLE state and then RX state. After received or the RX termination timer expires a programmable time in RX, the chip will go (see Section 19.7). Note: the probability that a back to the SLEEP state, unless a packet is false sync word is detected can be reduced by received. See Figure 19 and Section 19.7 for using PQT, CS, maximum sync word length, details on how the timeout works. and sync word qualifier mode as described in Section 17. After a packet is successfully Set the CC1100 into the IDLE state to exit WOR received the radio controller will then go to the mode. state indicated by the MCSM1.RXOFF_MODE CC1100 can be set up to signal the MCU that a setting. The possible destinations are: packet has been received by using the GDO • IDLE pins. If a packet is received, the MCSM1.RXOFF_MODE will determine the • FSTXON: Frequency synthesizer on and behaviour at the end of the received packet. ready at the TX frequency. Activate TX When the MCU has read the packet, it can put with STX . the chip back into SLEEP with the SWOR strobe from the IDLE state. The FIFO will loose its • TX: Start sending preamble contents in the SLEEP state. • RX: Start search for a new packet The WOR timer has two events, Event 0 and Event 1. In the SLEEP state with WOR activated, reaching Event 0 will turn on the Similarly, when TX is active the chip will digital regulator and start the crystal oscillator. remain in the TX state until the current packet SWRS038C Page 44 of 96

CC1100 Event 1 follows Event 0 after a programmed the RC oscillator will use the last valid timeout. calibration result. The frequency of the RC oscillator is locked to the main crystal The time between two consecutive Event 0 is frequency divided by 750. programmed with a mantissa value given by WOREVT1.EVENT0 and WOREVT0.EVENT0, In applications where the radio wakes up very and an exponent value set by often, typically several times every second, it WORCTRL.WOR_RES. The equation is: is possible to do the RC oscillator calibration once and then turn off calibration 750 t = ⋅EVENT0⋅25⋅WOR_RES (WORCTRL.RC_CAL=0) to reduce the current Event0 f consumption. This requires that RC oscillator XOSC calibration values are read from registers The Event 1 timeout is programmed with RCCTRL0_STATUS and RCCTRL1_STATUS WORCTRL.EVENT1. Figure 19 shows the and written back to RCCTRL0 and RCCTRL1 timing relationship between Event 0 timeout respectively. If the RC oscillator calibration is and Event 1 timeout. turned off it will have to be manually turned on again if temperature and supply voltage changes. Refer to Application Note AN047 [ 4] for further details. 19.6 Timing The radio controller controls most of the timing in CC1100, such as synthesizer calibration, PLL lock time, and RX/TX turnaround times. Timing from IDLE to RX and IDLE to TX is constant, Figure 19: Event 0 and Event 1 Relationship dependent on the auto calibration setting. RX/TX and TX/RX turnaround times are constant. The calibration time is constant The time from the CC1100 enters SLEEP state 18739 clock periods. Table 28 shows timing in until the next Event0 is programmed to appear crystal clock cycles for key state transitions. (t in Figure 19) should be larger than SLEEP Power on time and XOSC start-up times are 11.08 ms when using a 26 MHz crystal and variable, but within the limits stated in Table 7. 10.67 ms when a 27 MHz crystal is used. If t is less than 11.08 (10.67) ms there is a Note that in a frequency hopping spread SLEEP chance that the consecutive Event 0 will occur spectrum or a multi-channel protocol the calibration time can be reduced from 721 µs to 750 ⋅128 seconds approximately 150 µs. This is explained in f Section 3 2.2. XOSC too early. Application Note AN047 [4] explains in detail the theory of operation and the different registers involved when using WOR, as well as highlighting important aspects when using WOR mode. 19.5.1 RC Oscillator and Timing The frequency of the low-power RC oscillator used for the WOR functionality varies with temperature and supply voltage. In order to keep the frequency as accurate as possible, the RC oscillator will be calibrated whenever possible, which is when the XOSC is running and the chip is not in the SLEEP state. When the power and XOSC is enabled, the clock used by the WOR timer is a divided XOSC clock. When the chip goes to the sleep state, SWRS038C Page 45 of 96

CC1100 If the system can expect the transmission to Description XOSC 26 MHz Periods Crystal have started when enabling the receiver, the MCSM2.RX_TIME_RSSI function can be used. IDLE to RX, no calibration 2298 88.4µs The radio controller will then terminate RX if IDLE to RX, with calibration ~21037 809µs the first valid carrier sense sample indicates IDLE to TX/FSTXON, no 2298 88.4µs no carrier (RSSI below threshold). See Section calibration 17.4 on page 39 for details on Carrier Sense. IDLE to TX/FSTXON, with ~21037 809µs For ASK/OOK modulation, lack of carrier calibration sense is only considered valid after eight TX to RX switch 560 21.5µs symbol periods. Thus, the RX to TX switch 250 9.6µs MCSM2.RX_TIME_RSSI function can be used in ASK/OOK mode when the distance between RX or TX to IDLE, no calibration 2 0.1µs “1” symbols is 8 or less. RX or TX to IDLE, with calibration ~18739 721µs If RX terminates due to no carrier sense when Manual calibration ~18739 721µs the MCSM2.RX_TIME_RSSI function is used, Table 28: State Transition Timing or if no sync word was found when using the MCSM2.RX_TIME timeout function, the chip 19.7 RX Termination Timer will always go back to IDLE if WOR is disabled CC1100 has optional functions for automatic and back to SLEEP if WOR is enabled. termination of RX after a programmable time. Otherwise, the MCSM1.RXOFF_MODE setting The main use for this functionality is wake-on- determines the state to go to when RX ends. radio (WOR), but it may be useful for other This means that the chip will not automatically applications. The termination timer starts when go back to SLEEP once a sync word has been in RX state. The timeout is programmable with received. It is therefore recommended to the MCSM2.RX_TIME setting. When the timer always wake up the microcontroller on sync expires, the radio controller will check the word detection when using WOR mode. This condition for staying in RX; if the condition is can be done by selecting output signal 6 (see not met, RX will terminate. Table 34 on page 56) on one of the programmable GDO output pins, and The programmable conditions are: programming the microcontroller to wake up on an edge-triggered interrupt from this GDO • MCSM2.RX_TIME_QUAL=0: Continue pin. receive if sync word has been found • MCSM2.RX_TIME_QUAL=1: Continue receive if sync word has been found or preamble quality is above threshold (PQT) 20 Data FIFO The CC1100 contains two 64 byte FIFOs, one The chip status byte that is available on the for received data and one for data to be SO pin while transferring the SPI header transmitted. The SPI interface is used to read contains the fill grade of the RX FIFO if the from the RX FIFO and write to the TX FIFO. access is a read operation and the fill grade of Section 10.5 contains details on the SPI FIFO the TX FIFO if the access is a write operation. access. The FIFO controller will detect Section 10.1 on page 26 contains more details overflow in the RX FIFO and underflow in the on this. TX FIFO. The number of bytes in the RX FIFO and TX When writing to the TX FIFO it is the FIFO can be read from the status registers responsibility of the MCU to avoid TX FIFO RXBYTES.NUM_RXBYTES and overflow. A TX FIFO overflow will result in an TXBYTES.NUM_TXBYTES respectively. If a error in the TX FIFO content. received data byte is written to the RX FIFO at the exact same time as the last byte in the RX Likewise, when reading the RX FIFO the MCU FIFO is read over the SPI interface, the RX must avoid reading the RX FIFO past its empty FIFO pointer is not properly updated and the value, since an RX FIFO underflow will result last read byte is duplicated. To avoid this in an error in the data read out of the RX FIFO. SWRS038C Page 46 of 96

CC1100 problem one should never empty the RX FIFO NUM_RXBYTES 53 54 55 56 57 56 55 54 53 before the last byte of the packet is received. GDO For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been received before reading it out NUM_TXBYTES 6 7 8 9 10 9 8 7 6 of the RX FIFO. GDO If the packet length is larger than 64 bytes the MCU must determine how many bytes can be Figure 20: FIFO_THR=13 vs. Number of read from the RX FIFO Bytes in FIFO (GDOx_CFG=0x00 in RX and (RXBYTES.NUM_RXBYTES-1) and the following GDOx_CFG=0x02 in TX) software routine can be used: 1. Read RXBYTES.NUM_RXBYTES FIFO_THR Bytes in TX FIFO Bytes in RX FIFO repeatedly at a rate guaranteed to be at least twice that of which RF bytes are 0 (0000) 61 4 received until the same value is returned 1 (0001) 57 8 twice; store value in n. 2 (0010) 53 12 3 (0011) 49 16 2. If n < # of bytes remaining in packet, read 4 (0100) 45 20 n-1 bytes from the RX FIFO. 5 (0101) 41 24 3. Repeat steps 1 and 2 until n = # of bytes 6 (0110) 37 28 remaining in packet. 7 (0111) 33 32 8 (1000) 29 36 4. Read the remaining bytes from the RX 9 (1001) 25 40 FIFO. 10 (1010) 21 44 The 4-bit FIFOTHR.FIFO_THR setting is used 11 (1011) 17 48 to program threshold points in the FIFOs. 12 (1100) 13 52 Table 29 lists the 16 FIFO_THR settings and 13 (1101) 9 56 the corresponding thresholds for the RX and 14 (1110) 5 60 TX FIFOs. The threshold value is coded in 15 (1111) 1 64 opposite directions for the RX FIFO and TX FIFO. This gives equal margin to the overflow Table 29: FIFO_THR Settings and the and underflow conditions when the threshold Corresponding FIFO Thresholds is reached. A signal will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold. This signal can be Overflow viewed on the GDO pins (see Table 34 on margin page 56). FIFO_THR=13 Figure 21 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold signal toggles, in the case of FIFO_THR=13. Figure 20 shows the signal as the respective FIFO is filled above the threshold, and then drained below. 56 bytes FIFO_THR=13 Underflow 8 bytes margin RXFIFO TXFIFO Figure 21: Example of FIFOs at Threshold SWRS038C Page 47 of 96

CC1100 21 Frequency Programming The frequency programming in CC1100 is The base or start frequency is set by the 24 bit designed to minimize the programming frequency word located in the FREQ2, FREQ1, needed in a channel-oriented system. and FREQ0 registers. This word will typically be set to the centre of the lowest channel To set up a system with channel numbers, the frequency that is to be used. desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and The desired channel number is programmed MDMCFG1.CHANSPC_E registers. The channel with the 8-bit channel number register, spacing registers are mantissa and exponent CHANNR.CHAN, which is multiplied by the respectively. channel offset. The resultant carrier frequency is given by: f = fXOSC ⋅(FREQ +CHAN ⋅((256+CHANSPC _M)⋅2CHANSPC_E−2)) carrier 216 With a 26 MHz crystal the maximum channel Note that the SmartRF® Studio software [7] spacing is 405 kHz. To get e.g. 1 MHz channel automatically calculates the optimum spacing one solution is to use 333 kHz FSCTRL1.FREQ_IF register setting based on channel spacing and select each third channel channel spacing and channel filter bandwidth. in CHANNR.CHAN. If any frequency programming register is The preferred IF frequency is programmed altered when the frequency synthesizer is with the FSCTRL1.FREQ_IF register. The IF running, the synthesizer may give an frequency is given by: undesired response. Hence, the frequency f programming should only be updated when f = XOSC ⋅FREQ_IF the radio is in the IDLE state. IF 210 22 VCO The VCO is completely integrated on-chip. command strobe is activated in the IDLE mode. 22.1 VCO and PLL Self-Calibration Note that the calibration values are maintained in SLEEP mode, so the calibration is still valid The VCO characteristics will vary with after waking up from SLEEP mode (unless temperature and supply voltage changes, as supply voltage or temperature has changed well as the desired operating frequency. In significantly). order to ensure reliable operation, CC1100 includes frequency synthesizer self-calibration To check that the PLL is in lock the user can circuitry. This calibration should be done program register IOCFGx.GDOx_CFG to 0x0A regularly, and must be performed after turning and use the lock detector output available on on power and before using a new frequency the GDOx pin as an interrupt for the MCU (x = (or channel). The number of XOSC cycles for 0,1, or 2). A positive transition on the GDOx completing the PLL calibration is given in pin means that the PLL is in lock. As an Table 28 on page 46. alternative the user can read register FSCAL1. The PLL is in lock if the register content is The calibration can be initiated automatically different from 0x3F. Refer also to the CC1100 or manually. The synthesizer can be Errata Notes [1]. For more robust operation the automatically calibrated each time the source code could include a check so that the synthesizer is turned on, or each time the PLL is re-calibrated until PLL lock is achieved synthesizer is turned off automatically. This is if the PLL does not lock the first time. configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated when the SCAL SWRS038C Page 48 of 96

CC1100 23 Voltage Regulators CC1100 contains several on-chip linear voltage Setting the CSn pin low turns on the voltage regulators, which generate the supply voltage regulator to the digital core and starts the needed by low-voltage modules. These crystal oscillator. The SO pin on the SPI voltage regulators are invisible to the user, and interface must go low before the first positive can be viewed as integral parts of the various edge of SCLK. (setup time is given in Table modules. The user must however make sure 16). that the absolute maximum ratings and If the chip is programmed to enter power-down required pin voltages in Table 1 and Table 13 mode, (SPWD strobe issued), the power will be are not exceeded. The voltage regulator for turned off after CSn goes high. The power and the digital core requires one external crystal oscillator will be turned on again when decoupling capacitor. CSn goes low. The voltage regulator output should only be used for driving the CC1100. 24 Output Power Programming The RF output power level from the device If OOK modulation is used, the logic 0 and has two levels of programmability, as logic 1 power levels shall be programmed to illustrated in Figure 22. Firstly, the special index 0 and 1 respectively. PATABLE register can hold up to eight user Table 30 contains recommended PATABLE selected output power settings. Secondly, the settings for various output levels and 3-bit FREND0.PA_POWER value selects the frequency bands. Using PA settings from 0x61 PATABLE entry to use. This two-level to 0x6F is not recommended. See Section functionality provides flexible PA power ramp 10.6 on page 28 for PATABLE programming up and ramp down at the start and end of details. transmission, as well as ASK modulation shaping. All the PA power settings in the Table 31 contains output power and current PATABLE from index 0 up to the consumption for default PATABLE setting FREND0.PA_POWER value are used. (0xC6). PATABLE must be programmed in burst mode if you want to write to other entries The power ramping at the start and at the end than PATABLE[0]. of a packet can be turned off by setting FREND0.PA_POWER to zero and then Note that all content of the PATABLE, except program the desired output power to index 0 in for the first byte (index 0) is lost when entering the PATABLE. the SLEEP state. 315 MHz 433 MHz 868 MHz 915 MHz Output Current Current Current Current Power Setting Consumption, Setting Consumption, Setting Consumption, Setting Consumption, [dBm] Typ. [mA] Typ. [mA] Typ. [mA] Typ. [mA] -30 0x04 10.6 0x04 11.5 0x03 11.9 0x11 11.8 -20 0x17 11.1 0x17 12.1 0x0D 12.4 0x0D 12.3 -15 0x1D 11.8 0x1C 12.7 0x1C 13.0 0x1C 13.0 -10 0x26 13.0 0x26 14.0 0x34 14.5 0x26 14.3 -5 0x57 12.9 0x57 13.7 0x57 14.1 0x57 13.9 0 0x60 14.8 0x60 15.6 0x8E 16.9 0x8E 16.7 5 0x85 18.1 0x85 19.1 0x85 20.0 0x83 19.9 7 0xCB 22.1 0xC8 24.2 0xCC 25.8 0xC9 25.8 10 0xC2 27.1 0xC0 29.2 0xC3 31.1 0xC0 32.3 Table 30: Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands SWRS038C Page 49 of 96

CC1100 315 MHz 433 MHz 868 MHz 915 MHz Default Output Current Output Current Output Current Output Current Power Power Consumption, Power Consumption, Power Consumption, Power Consumption, Setting [dBm] Typ. [mA] [dBm] Typ. [mA] [dBm] Typ. [mA] [dBm] Typ. [mA] 0xC6 8.7 24.5 7.9 25.2 8.9 28.3 7.9 26.8 Table 31: Output Power and Current Consumption for Default PATABLE Setting 25 Shaping and PA Ramping With ASK modulation, up to eight power should be 7 when ASK is active. The shaping settings are used for shaping. The modulator of the ASK signal is dependent on the contains a counter that counts up when configuration of the PATABLE. transmitting a one and down when transmitting Note that the ASK shaping feature is only a zero. The counter counts at a rate equal to 8 supported for output power levels up to -1 times the symbol rate. The counter saturates dBm and only values in the range 0x30–0x3F, at FREND0.PA_POWER and 0 respectively. together with 0x00 can be used. The same is This counter value is used as an index for a the case when implementing PA ramping for lookup in the power table. Thus, in order to other modulations formats. Figure 23 shows utilize the whole table, FREND0.PA_POWER some examples of ASK shaping. PATABLE(7)[7:0] The PA uses this PATABLE(6)[7:0] setting. PATABLE(5)[7:0] PATABLE(4)[7:0] Settings 0 to PA_POWER are PATABLE(3)[7:0] used during ramp-up at start of transmission and ramp-down at PATABLE(2)[7:0] end of transmission, and for PATABLE(1)[7:0] ASK/OOK modulation. PATABLE(0)[7:0] Index into PATABLE(7:0) The SmartRF® Studio software e.g 6 should be used to obtain optimum PATABLE settings for various PA_POWER[2:0] output powers. in FREND0 register Figure 22: PA_POWER and PATABLE Output Power PATABLE[7] PATABLE[6] PATABLE[5] PATABLE[4] PATABLE[3] PATABLE[2] PATABLE[1] PATABLE[0] Time 1 0 0 1 0 1 1 0 Bit Sequence FREND0.PA_POWER = 3 FREND0.PA_POWER = 7 Figure 23: Shaping of ASK Signal SWRS038C Page 50 of 96

CC1100 Output Power [dBm] PATABLE Setting 315 MHz 433 MHz 868 MHz 915 MHz 0x00 -62.0 -62.0 -57.1 -56.0 0x30 -41.7 -39.0 -33.6 -33.1 0x31 -21.8 -21.7 -21.2 -21.0 0x32 -16.2 -16.1 -16.0 -15.8 0x33 -12.8 -12.7 -12.7 -12.5 0x34 -10.5 -10.4 -10.5 -10.3 0x35 -8.6 -8.5 -8.7 -8.5 0x36 -7.2 -7.1 -7.4 -7.2 0x37 -5.9 -5.8 -6.2 -6.0 0x38 -4.8 -4.9 -5.3 -5.1 0x39 -3.9 -4.0 -4.5 -4.3 0x3A -3.2 -3.3 -3.8 -3.7 0x3B -2.5 -2.7 -3.3 -3.1 0x3C -2.1 -2.3 -2.8 -2.7 0x3D -1.7 -1.9 -2.5 -2.3 0x3E -1.3 -1.6 -2.1 -2.0 0x3F -1.1 -1.3 -1.9 -1.7 Table 32: PATABLE Settings used together with ASK Shaping and PA Ramping Assume working in the 433 MHz and using PATABLE[7] = 0x00 PATABLE[7] = 0x00 FSK. The desired output power is -10 dBm. PATABLE[6] = 0x00 PATABLE[6] = 0x00 Figure 24 shows how the PATABLE should PATABLE[5] = 0x00 PATABLE[5] = 0x34 look like in the two cases where no ramping is PATABLE[4] = 0x00 PATABLE[4] = 0x33 used (A) and when PA ramping is being PATABLE[3] = 0x00 PATABLE[3] = 0x32 implemented (B). In case A, the PATABLE PATABLE[2] = 0x00 PATABLE[2] = 0x31 value is taken from Table 30, while in case B, PATABLE[1] = 0x00 PATABLE[1] = 0x30 the values are taken from Table 32. PATABLE[0] = 0x26 PATABLE[0] = 0x00 FREND0.PA_POWER = 0 FREND0.PA_POWER = 5 A: Output Power = -10 dBm, B: Output Power = -10 dBm, No PA Ramping PA Ramping Figure 24: PA Ramping SWRS038C Page 51 of 96

CC1100 26 Selectivity Figure 25 to Figure 27 show the typical selectivity performance (adjacent and alternate rejection). 50.0 40.0 30.0 B] d y [ vit 20.0 cti e el S 10.0 0.0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 -10.0 Frequency offset [MHz] Figure 25: Typical Selectivity at 1.2 kBaud Data Rate, 868 MHz, 2-FSK, 5.2 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 58 kHz 40.0 30.0 20.0 B] d vity [ 10.0 cti e el S 0.0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 -10.0 -20.0 Frequency offset [MHz] Figure 26: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, 2-FSK, 20 kHz Deviation. IF Frequency is 152.3 kHz and the Digital Channel Filter Bandwidth is 100 kHz SWRS038C Page 52 of 96

CC1100 50.0 40.0 30.0 B] d 20.0 vity [ cti 10.0 e el S 0.0 -2.3 1.5 -1.0 -0.8 0.0 0.8 1.0 1.5 2.3 -10.0 -20.0 Frequency offset [MHz] Figure 27: Typical Selectivity at 250 kBaud Data Rate, 868 MHz, MSK, IF Frequency is 254 kHz and the Digital Channel Filter Bandwidth is 540 kHz 27 Crystal Oscillator A crystal in the frequency range 26-27 MHz The crystal oscillator circuit is shown in Figure must be connected between the XOSC_Q1 28. Typical component values for different and XOSC_Q2 pins. The oscillator is designed values of C are given in Table 33. L for parallel mode operation of the crystal. In The crystal oscillator is amplitude regulated. addition, loading capacitors (C81 and C101) This means that a high current is used to start for the crystal are required. The loading up the oscillations. When the amplitude builds capacitor values depend on the total load up, the current is reduced to what is necessary capacitance, C , specified for the crystal. The L to maintain approximately 0.4 Vpp signal total load capacitance seen between the swing. This ensures a fast start-up, and keeps crystal terminals should equal C for the L the drive level to a minimum. The ESR of the crystal to oscillate at the specified frequency. crystal should be within the specification in 1 order to ensure a reliable start-up (see Section C = +C L 1 1 parasitic 4.4 on page 14). + C C 81 101 The initial tolerance, temperature drift, aging and load pulling should be carefully specified The parasitic capacitance is constituted by pin in order to meet the required frequency input capacitance and PCB stray capacitance. accuracy in a certain application. Total parasitic capacitance is typically 2.5 pF. XOSC_Q1 XOSC_Q2 XTAL C81 C101 Figure 28: Crystal Oscillator Circuit Component C = 10 pF C = 13 pF C = 16 pF L L L C81 15 pF 22 pF 27 pF C101 15 pF 22 pF 27 pF Table 33: Crystal Oscillator Component Values SWRS038C Page 53 of 96

CC1100 27.1 Reference Signal XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial The chip can alternatively be operated with a capacitor. When using a full-swing digital reference signal from 26 to 27 MHz instead of signal this capacitor can be omitted. The a crystal. This input clock can either be a full- XOSC_Q2 line must be left un-connected. C81 swing digital signal (0 V to VDD) or a sine and C101 can be omitted when using a wave of maximum 1 V peak-peak amplitude. reference signal. The reference signal must be connected to the 28 External RF Match The balanced RF input and output of CC1100 The passive matching/filtering network share two common pins and are designed for connected to CC1100 should have the following a simple, low-cost matching and balun network differential impedance as seen from the RF- on the printed circuit board. The receive- and port (RF_P and RF_N) towards the antenna: transmit switching at the CC1100 front-end is Z = 122 + j31 Ω controlled by a dedicated on-chip function, out 315 MHz eliminating the need for an external RX/TX- Z = 116 + j41 Ω out 433 MHz switch. Z = 86.5 + j43 Ω out 868/915 MHz A few passive external components combined To ensure optimal matching of the CC1100 with the internal RX/TX switch/termination differential output it is recommended to follow circuitry ensures match in both RX and TX the CC1100EM reference design ( [5] or [6]) as mode. closely as possible. Gerber files for the Although CC1100 has a balanced RF reference designs are available for download input/output, the chip can be connected to a from the TI website. single-ended antenna with few external low cost capacitors and inductors. 29 PCB Layout Recommendations The top layer should be used for signal best routing is from the power line (or power routing, and the open areas should be filled plane) to the decoupling capacitor and then to with metallization connected to ground using the CC1100 supply pin. Supply power filtering is several vias. very important. The area under the chip is used for grounding Each decoupling capacitor ground pad should and shall be connected to the bottom ground be connected to the ground plane using a plane with several vias. In the CC1100EM separate via. Direct connections between reference designs ( [5] and [6]) we have placed neighboring power pins will increase noise 5 vias inside the exposed die attached pad. coupling and should be avoided unless These vias should be “tented” (covered with absolutely necessary. solder mask) on the component side of the The external components should ideally be as PCB to avoid migration of solder through the small as possible (0402 is recommended) and vias during the solder reflow process. surface mount devices are highly The solder paste coverage should not be recommended. Please note that components 100%. If it is, out gassing may occur during the smaller than those specified may have reflow process, which may cause defects differing characteristics. (splattering, solder balling). Using “tented” vias Precaution should be used when placing the reduces the solder paste coverage below microcontroller in order to avoid noise 100%. interfering with the RF circuitry. See Figure 29 for top solder resist and top A CC1100/1150DK Development Kit with a paste masks. fully assembled CC1100EM Evaluation Each decoupling capacitor should be placed Module is available. It is strongly advised that as close as possible to the supply pin it is this reference layout is followed very closely in supposed to decouple. Each decoupling order to get the best performance. The capacitor should be connected to the power schematic, BOM and layout Gerber files are all line (or power plane) by separate vias. The available from the TI website ( [5] and [6]). SWRS038C Page 54 of 96

CC1100 Figure 29: Left: Top Solder Resist Mask (Negative). Right: Top Paste Mask. Circles are Vias 30 General Purpose / Test Output Control Pins The three digital output pins GDO0, GDO1, IOCFG0 register. The voltage on the GDO0 and GDO2 are general control pins configured pin is then proportional to temperature. See with IOCFG0.GDO0_CFG, Section 4 .7 on page 16 for temperature sensor IOCFG1.GDO1_CFG, and IOCFG2.GDO3_CFG specifications. respectively. Table 34 shows the different If the IOCFGx.GDOx_CFG setting is less than signals that can be monitored on the GDO 0x20 and IOCFGx_GDOx_INV is 0 (1), the pins. These signals can be used as inputs to GDO0 and GDO2 pins will be hardwired to 0 the MCU. GDO1 is the same pin as the SO pin (1) and the GDO1 pin will be hardwired to 1 on the SPI interface, thus the output (0) in the SLEEP state. These signals will be programmed on this pin will only be valid when hardwired until the CHIP_RDYn signal goes CSn is high. The default value for GDO1 is 3- low. stated, which is useful when the SPI interface is shared with other devices. If the IOCFGx.GDOx_CFG setting is 0x20 or The default value for GDO0 is a 135-141 kHz higher the GDO pins will work as programmed clock output (XOSC frequency divided by also in SLEEP state. As an example, GDO1 is 192). Since the XOSC is turned on at power- high impedance in all states if on-reset, this can be used to clock the MCU in IOCFG1.GDO1_CFG=0x2E. systems with only one crystal. When the MCU is up and running, it can change the clock frequency by writing to IOCFG0.GDO0_CFG. An on-chip analog temperature sensor is enabled by writing the value 128 (0x80) to the SWRS038C Page 55 of 96

CC1100 GDOx_CFG[5:0] Description Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO 0 (0x00) is drained below the same threshold. Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is 1 (0x01) reached. De-asserts when the RX FIFO is empty. Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold. De-asserts when the TX 2 (0x02) FIFO is below the same threshold. Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below theTX FIFO 3 (0x03) threshold. 4 (0x04) Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed. 5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed. Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert 6 (0x06) when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows. 7 (0x07) Asserts when a packet has been received with CRC OK. De-asserts when the first byte is read from the RX FIFO. 8 (0x08) Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value. 9 (0x09) Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting) Lock detector output. The PLL is in lock if the lock detector output has a positive transition or is constantly logic high. To 10 (0x0A) check for PLL lock the lock detector output should be used as an interrupt for the MCU. Serial Clock. Synchronous to the data in synchronous serial mode. 11 (0x0B) In RX mode, data is set up on the falling edge by CC1100 when GDOx_INV=0. In TX mode, data is sampled by CC1100 on the rising edge of the serial clock when GDOx_INV=0. 12 (0x0C) Serial Synchronous Data Output. Used for synchronous serial mode. 13 (0x0D) Serial Data Output. Used for asynchronous serial mode. 14 (0x0E) Carrier sense. High if RSSI level is above threshold. 15 (0x0F) CRC_OK. The last CRC comparison matched. Cleared when entering/restarting RX mode. 16 (0x10) Reserved – used for test. 17 (0x11) Reserved – used for test. 18 (0x12) Reserved – used for test. 19 (0x13) Reserved – used for test. 20 (0x14) Reserved – used for test. 21 (0x15) Reserved – used for test. 22 (0x16) RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. 23 (0x17) RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output. 24 (0x18) Reserved – used for test. 25 (0x19) Reserved – used for test. 26 (0x1A) Reserved – used for test. PA_PD. Note: PA_PD will have the same signal level in SLEEP and TX states. To control an external PA or RX/TX switch 27 (0x1B) in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead. LNA_PD. Note: LNA_PD will have the same signal level in SLEEP and RX states. To control an external LNA or RX/TX 28 (0x1C) switch in applications where the SLEEP state is used it is recommended to use GDOx_CFGx=0x2F instead. 29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output. 30 (0x1E) Reserved – used for test. 31 (0x1F) Reserved – used for test. 32 (0x20) Reserved – used for test. 33 (0x21) Reserved – used for test. 34 (0x22) Reserved – used for test. 35 (0x23) Reserved – used for test. 36 (0x24) WOR_EVNT0 37 (0x25) WOR_EVNT1 38 (0x26) Reserved – used for test. 39 (0x27) CLK_32k 40 (0x28) Reserved – used for test. 41 (0x29) CHIP_RDYn 42 (0x2A) Reserved – used for test. 43 (0x2B) XOSC_STABLE 44 (0x2C) Reserved – used for test. 45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data). 46 (0x2E) High impedance (3-state) 47 (0x2F) HW to 0 (HW1 achieved by setting GDOx_INV=1). Can be used to control an external LNA/PA or RX/TX switch. 48 (0x30) CLK_XOSC/1 49 (0x31) CLK_XOSC/1.5 50 (0x32) CLK_XOSC/2 51 (0x33) CLK_XOSC/3 52 (0x34) CLK_XOSC/4 Note: There are 3 GDO pins, but only one CLK_XOSC/n can be selected as an output at any 53 (0x35) CLK_XOSC/6 54 (0x36) CLK_XOSC/8 time. If CLK_XOSC/n is to be monitored on one of the GDO pins, the other two GDO pins must 55 (0x37) CLK_XOSC/12 be configured to values less than 0x30. The GDO0 default value is CLK_XOSC/192. 56 (0x38) CLK_XOSC/16 To optimize rf performance, these signal should not be used while the radio is in RX or TX mode. 57 (0x39) CLK_XOSC/24 58 (0x3A) CLK_XOSC/32 59 (0x3B) CLK_XOSC/48 60 (0x3C) CLK_XOSC/64 61 (0x3D) CLK_XOSC/96 62 (0x3E) CLK_XOSC/128 63 (0x3F) CLK_XOSC/192 Table 34: GDOx Signal Selection (x = 0, 1, or 2) SWRS038C Page 56 of 96

CC1100 31 Asynchronous and Synchronous Serial Operation Several features and modes of operation have 31.2 Synchronous Serial Operation been included in the CC1100 to provide Setting PKTCTRL0.PKT_FORMAT to 1 backward compatibility with previous Chipcon enables synchronous serial mode. In the products and other existing RF communication synchronous serial mode, data is transferred systems. For new systems, it is recommended on a two wire serial interface. The CC1100 to use the built-in packet handling features, as provides a clock that is used to set up new they can give more robust communication, data on the data input line or sample data on significantly offload the microcontroller, and the data output line. Data input (TX data) is the simplify software development. GDO0 pin. This pin will automatically be configured as an input when TX is active. The 31.1 Asynchronous Operation data output pin can be any of the GDO pins; this is set by the IOCFG0.GDO0_CFG, For backward compatibility with systems IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG already using the asynchronous data transfer fields. from other Chipcon products, asynchronous transfer is also included in CC1100. When Preamble and sync word insertion/detection asynchronous transfer is enabled, several of may or may not be active, dependent on the the support mechanisms for the MCU that are sync mode set by the MDMCFG2.SYNC_MODE. included in CC1100 will be disabled, such as If preamble and sync word is disabled, all packet handling hardware, buffering in the other packet handler features and FEC should FIFO, and so on. The asynchronous transfer also be disabled. The MCU must then handle mode does not allow the use of the data preamble and sync word insertion and whitener, interleaver, and FEC, and it is not detection in software. If preamble and sync possible to use Manchester encoding. word insertion/detection is left on, all packet handling features and FEC can be used. One Note that MSK is not supported for exception is that the address filtering feature is asynchronous transfer. unavailable in synchronous serial mode. Setting PKTCTRL0.PKT_FORMAT to 3 When using the packet handling features in enables asynchronous serial mode. synchronous serial mode, the CC1100 will insert In TX, the GDO0 pin is used for data input (TX and detect the preamble and sync word and data). Data output can be on GDO0, GDO1, or the MCU will only provide/get the data GDO2. This is set by the IOCFG0.GDO0_CFG, payload. This is equivalent to the IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG recommended FIFO operation mode. fields. The CC1100 modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be less than one eighth of the programmed data rate. 32 System Considerations and Guidelines 32.1 SRD Regulations MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 International regulations and national laws part 15 (USA). A summary of the most regulate the use of radio receivers and important aspects of these regulations can be transmitters. Short Range Devices (SRDs) for found in Application Note AN001 [2]. license free operation below 1 GHz are usually operated in the 433 MHz, 868 MHz or 915 Please note that compliance with regulations is MHz frequency bands. The CC1100 is dependent on complete system performance. specifically designed for such use with its 300 - It is the customer’s responsibility to ensure that 348 MHz, 400 - 464 MHz, and 800 - 928 MHz the system complies with regulations. operating ranges. The most important regulations when using the CC1100 in the 433 SWRS038C Page 57 of 96

CC1100 32.2 Frequency Hopping and Multi- time is reduced from approximately 720 µs to Channel Systems approximately 150 µs. The blanking interval between each frequency hop is then The 433 MHz, 868 MHz, or 915 MHz bands approximately 240 us. are shared by many systems both in industrial, office, and home environments. It is therefore There is a trade off between blanking time and recommended to use frequency hopping memory space needed for storing calibration spread spectrum (FHSS) or a multi-channel data in non-volatile memory. Solution 2) above protocol because the frequency diversity gives the shortest blanking interval, but makes the system more robust with respect to requires more memory space to store interference from other systems operating in calibration values. Solution 3) gives the same frequency band. FHSS also combats approximately 570 µs smaller blanking interval multipath fading. than solution 1). CC1100 is highly suited for FHSS or multi- Note that the recommended settings for channel systems due to its agile frequency TEST0.VCO_SEL_CAL_EN will change with synthesizer and effective communication frequency. This means that one should always interface. Using the packet handling support use SmartRF® Studio [ 7] to get the correct and data buffering is also beneficial in such settings for a specific frequency before doing a systems as these features will significantly calibration, regardless of which calibration offload the host controller. method is being used. Charge pump current, VCO current, and VCO It must be noted that the TESTn registers (n = capacitance array calibration data is required 0, 1, or 2) content is not retained in SLEEP for each frequency when implementing state, and thus it is necessary to re-write these frequency hopping for CC1100. There are 3 registers when returning from the SLEEP ways of obtaining the calibration data from the state. chip: 1) Frequency hopping with calibration for each 32.3 Wideband Modulation not Using hop. The PLL calibration time is approximately Spread Spectrum 720 µs. The blanking interval between each Digital modulation systems under FFC part frequency hop is then approximately 810 us. 15.247 includes 2-FSK and GFSK modulation. 2) Fast frequency hopping without calibration A maximum peak output power of 1W (+30 for each hop can be done by calibrating each dBm) is allowed if the 6 dB bandwidth of the frequency at startup and saving the resulting modulated signal exceeds 500 kHz. In FSCAL3, FSCAL2, and FSCAL1 register values addition, the peak power spectral density in MCU memory. Between each frequency conducted to the antenna shall not be greater hop, the calibration process can then be than +8 dBm in any 3 kHz band. replaced by writing the FSCAL3, FSCAL2and Operating at high data rates and frequency FSCAL1 register values corresponding to the separation, the CC1100 is suited for systems next RF frequency. The PLL turn on time is targeting compliance with digital modulation approximately 90 µs. The blanking interval system as defined by FFC part 15.247. An between each frequency hop is then external power amplifier is needed to increase approximately 90 us. The VCO current the output above +10 dBm. calibration result available in FSCAL2 is not dependent on the RF frequency. Neither is the charge pump current calibration result 32.4 Data Burst Transmissions available in FSCAL3. The same value can The high maximum data rate of CC1100 opens therefore be used for all frequencies. up for burst transmissions. A low average data 3) Run calibration on a single frequency at rate link (e.g. 10 kBaud), can be realized using startup. Next write 0 to FSCAL3[5:4] to a higher over-the-air data rate. Buffering the disable the charge pump calibration. After data and transmitting in bursts at high data writing to FSCAL3[5:4] strobe SRX (or STX) rate (e.g. 500 kBaud) will reduce the time in active mode, and hence also reduce the with MCSM0.FS_AUTOCAL=1 for each new average current consumption significantly. frequency hop. That is, VCO current and VCO Reducing the time in active mode will reduce capacitance calibration is done but not charge the likelihood of collisions with other systems pump current calibration. When charge pump in the same frequency range. current calibration is disabled the calibration SWRS038C Page 58 of 96

CC1100 32.5 Continuous Transmissions 32.8 Low Cost Systems In data streaming applications the CC1100 As the CC1100 provides 500 kBaud multi- opens up for continuous transmissions at 500 channel performance without any external kBaud effective data rate. As the modulation is filters, a very low cost system can be made. done with a closed loop PLL, there is no A differential antenna will eliminate the need limitation in the length of a transmission (open for a balun, and the DC biasing can be loop modulation used in some transceivers achieved in the antenna topology, see Figure 3 often prevents this kind of continuous data and Figure 4. streaming and reduces the effective data rate). A HC-49 type SMD crystal is used in the CC1100EM reference designs ( [5] and [6]). 32.6 Crystal Drift Compensation Note that the crystal package strongly The CC1100 has a very fine frequency influences the price. In a size constrained PCB resolution (see Table 9). This feature can be design a smaller, but more expensive, crystal used to compensate for frequency offset and may be used. drift. The frequency offset between an ‘external’ 32.9 Battery Operated Systems transmitter and the receiver is measured in the In low power applications, the SLEEP state CC1100 and can be read back from the with the crystal oscillator core switched off FREQEST status register as described in should be used when the CC1100 is not active. Section 1 4.1. The measured frequency offset It is possible to leave the crystal oscillator core can be used to calibrate the frequency using running in the SLEEP state if start-up time is the ‘external’ transmitter as the reference. That critical. is, the received signal of the device will match the receiver’s channel filter better. In the same The WOR functionality should be used in low way the centre frequency of the transmitted power applications. signal will match the ‘external’ transmitter’s signal. 32.10 Increasing Output Power In some applications it may be necessary to 32.7 Spectrum Efficient Modulation extend the link range. Adding an external CC1100 also has the possibility to use Gaussian power amplifier is the most effective way of shaped 2-FSK (GFSK). This spectrum-shaping doing this. feature improves adjacent channel power The power amplifier should be inserted (ACP) and occupied bandwidth. In ‘true’ 2-FSK between the antenna and the balun, and two systems with abrupt frequency shifting, the T/R switches are needed to disconnect the PA spectrum is inherently broad. By making the in RX mode. See Figure 30. frequency shift ‘softer’, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth using GFSK. Antenna Filter P A Balun CC1100 T/R T/R switch switch Figure 30: Block Diagram of CC1100 Usage with External Power Amplifier SWRS038C Page 59 of 96

CC1100 33 Configuration Registers The configuration of CC1100 is done by There are also 12 Status registers, which are programming 8-bit registers. The optimum listed in Table 37. These registers, which are configuration data based on selected system read-only, contain information about the status parameters are most easily found by using the of CC1100. SmartRF® Studio software [ 7]. Complete The two FIFOs are accessed through one 8-bit descriptions of the registers are given in the register. Write operations write to the TX FIFO, following tables. After chip reset, all the while read operations read from the RX FIFO. registers have default values as shown in the tables. The optimum register setting might During the header byte transfer and while differ from the default value. After a reset all writing data to a register or the TX FIFO, a registers that shall be different from the default status byte is returned on the SO line. This value therefore needs to be programmed status byte is described in Table 17 on page through the SPI interface. 26. There are 13 command strobe registers, listed Table 38 summarizes the SPI address space. in Table 35. Accessing these registers will The address to use is given by adding the initiate the change of an internal state or base address to the left and the burst and mode. There are 47 normal 8-bit configuration read/write bits on the top. Note that the burst registers, listed in Table 36. Many of these bit has different meaning for base addresses registers are for test purposes only, and need above and below 0x2F. not be written for normal operation of CC1100. Address Strobe Description Name 0x30 SRES Reset chip. 0x31 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA): Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround). 0x32 SXOFF Turn off crystal oscillator. 0x33 SCAL Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.FS_AUTOCAL=0) 0x34 SRX Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1. 0x35 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: Only go to TX if channel is clear. 0x36 SIDLE Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable. 0x38 SWOR Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5 if WORCTRL.RC_PD=0. 0x39 SPWD Enter power down mode when CSn goes high. 0x3A SFRX Flush the RX FIFO buffer. Only issue SFRX in IDLE or, RXFIFO_OVERFLOW states. 0x3B SFTX Flush the TX FIFO buffer. Only issue SFTX in IDLE or TXFIFO_UNDERFLOW states. 0x3C SWORRST Reset real time clock to Event1 value. 0x3D SNOP No operation. May be used to get access to the chip status byte. Table 35: Command Strobes SWRS038C Page 60 of 96

CC1100 Preserved in Details on Address Register Description SLEEP State Page Number 0x00 IOCFG2 GDO2 output pin configuration Yes 64 0x01 IOCFG1 GDO1 output pin configuration Yes 64 0x02 IOCFG0 GDO0 output pin configuration Yes 64 0x03 FIFOTHR RX FIFO and TX FIFO thresholds Yes 65 0x04 SYNC1 Sync word, high byte Yes 65 0x05 SYNC0 Sync word, low byte Yes 65 0x06 PKTLEN Packet length Yes 65 0x07 PKTCTRL1 Packet automation control Yes 66 0x08 PKTCTRL0 Packet automation control Yes 67 0x09 ADDR Device address Yes 67 0x0A CHANNR Channel number Yes 67 0x0B FSCTRL1 Frequency synthesizer control Yes 68 0x0C FSCTRL0 Frequency synthesizer control Yes 68 0x0D FREQ2 Frequency control word, high byte Yes 68 0x0E FREQ1 Frequency control word, middle byte Yes 68 0x0F FREQ0 Frequency control word, low byte Yes 68 0x10 MDMCFG4 Modem configuration Yes 69 0x11 MDMCFG3 Modem configuration Yes 69 0x12 MDMCFG2 Modem configuration Yes 70 0x13 MDMCFG1 Modem configuration Yes 71 0x14 MDMCFG0 Modem configuration Yes 71 0x15 DEVIATN Modem deviation setting Yes 72 0x16 MCSM2 Main Radio Control State Machine configuration Yes 73 0x17 MCSM1 Main Radio Control State Machine configuration Yes 74 0x18 MCSM0 Main Radio Control State Machine configuration Yes 75 0x19 FOCCFG Frequency Offset Compensation configuration Yes 76 0x1A BSCFG Bit Synchronization configuration Yes 77 0x1B AGCTRL2 AGC control Yes 78 0x1C AGCTRL1 AGC control Yes 79 0x1D AGCTRL0 AGC control Yes 80 0x1E WOREVT1 High byte Event 0 timeout Yes 80 0x1F WOREVT0 Low byte Event 0 timeout Yes 81 0x20 WORCTRL Wake On Radio control Yes 81 0x21 FREND1 Front end RX configuration Yes 82 0x22 FREND0 Front end TX configuration Yes 82 0x23 FSCAL3 Frequency synthesizer calibration Yes 82 0x24 FSCAL2 Frequency synthesizer calibration Yes 83 0x25 FSCAL1 Frequency synthesizer calibration Yes 83 0x26 FSCAL0 Frequency synthesizer calibration Yes 83 0x27 RCCTRL1 RC oscillator configuration Yes 83 0x28 RCCTRL0 RC oscillator configuration Yes 83 0x29 FSTEST Frequency synthesizer calibration control No 84 0x2A PTEST Production test No 84 0x2B AGCTEST AGC test No 84 0x2C TEST2 Various test settings No 84 0x2D TEST1 Various test settings No 84 0x2E TEST0 Various test settings No 84 Table 36: Configuration Registers Overview SWRS038C Page 61 of 96

CC1100 Address Register Description Details on page number 0x30 (0xF0) PARTNUM Part number for CC1100 85 0x31 (0xF1) VERSION Current version number 85 0x32 (0xF2) FREQEST Frequency Offset Estimate 85 0x33 (0xF3) LQI Demodulator estimate for Link Quality 85 0x34 (0xF4) RSSI Received signal strength indication 85 0x35 (0xF5) MARCSTATE Control state machine state 86 0x36 (0xF6) WORTIME1 High byte of WOR timer 86 0x37 (0xF7) WORTIME0 Low byte of WOR timer 86 0x38 (0xF8) PKTSTATUS Current GDOx status and packet status 87 Current setting from PLL calibration 87 0x39 (0xF9) VCO_VC_DAC module Underflow and number of bytes in the TX 87 0x3A (0xFA) TXBYTES FIFO Overflow and number of bytes in the RX 87 0x3B (0xFB) RXBYTES FIFO 0x3C (0xFC) RCCTRL1_STATUS Last RC oscillator calibration result 87 0x3D (0xFD) RCCTRL0_STATUS Last RC oscillator calibration result 88 Table 37: Status Registers Overview SWRS038C Page 62 of 96

CC1100 Write Read Single Byte Burst Single Byte Burst +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 ble 0x10 MDMCFG4 si s 0x11 MDMCFG3 po 0x12 MDMCFG2 s s 0x13 MDMCFG1 ce c 0x14 MDMCFG0 a 0x15 DEVIATN st 0x16 MCSM2 bur 0x17 MCSM1 s, 0x18 MCSM0 ster 0x19 FOCCFG gi e 0x1A BSCFG n r 0x1B AGCCTRL2 o 0x1C AGCCTRL1 urati 0x1D AGCCTRL0 g 0x1E WOREVT1 nfi o 0x1F WOREVT0 W c 0x20 WORCTRL R/ 0x21 FREND1 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 RCCTRL1 0x28 RCCTRL0 0x29 FSTEST 0x2A PTEST 0x2B AGCTEST 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F 0x30 SRES SRES PARTNUM 0x31 SFSTXON SFSTXON VERSION 000xxx333234 SSSXCROAXFL F SSSXCROAXFL F FRRELSQQSEI IS T egisters gisters 00xx3356 SSIDTLXE SSIDTLXE MWAORRCTSITMAET1E us re re atyt 00xx3378 SW OR SW OR PWKOTSRTTAIMTEU0S s, Stulti b 0x39 SPWD SPWD VCO_VC_DAC obed m 0x3A SFRX SFRX TXBYTES Stran 0x3B SFTX SFTX RXBYTES d y) 000xxx333CDE SPWASOTNAROBRPLS ET PATA BLE SPWASOTNAROBRPLS ET RRCCCCTTPRRALLT10A__BSSLTTEAA TTUUSS ommanead onl 0x3F TX FIFO TX FIFO RX FIFO RX FIFO C(r Table 38: SPI Address Space SWRS038C Page 63 of 96

CC1100 33.1 Configuration Register Details – Registers with preserved values in SLEEP state 0x00: IOCFG2 – GDO2 Output Pin Configuration Bit Field Name Reset R/W Description 7 Reserved R0 6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO2_CFG[5:0] 41 (0x29) R/W Default is CHP_RDYn (See Table 34 on page 56). 0x01: IOCFG1 – GDO1 Output Pin Configuration Bit Field Name Reset R/W Description 7 GDO_DS 0 R/W Set high (1) or low (0) output drive strength on the GDO pins. 6 GDO1_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO1_CFG[5:0] 46 (0x2E) R/W Default is 3-state (See Table 34 on page 56). 0x02: IOCFG0 – GDO0 Output Pin Configuration Bit Field Name Reset R/W Description 7 TEMP_SENSOR_ENABLE 0 R/W Enable analog temperature sensor. Write 0 in all other register bits when using temperature sensor. 6 GDO0_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO0_CFG[5:0] 63 (0x3F) R/W Default is CLK_XOSC/192 (See Table 34 on page 56). It is recommended to disable the clock output in initialization, in order to optimize RF performance. SWRS038C Page 64 of 96

CC1100 0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds Bit Field Name Reset R/W Description 7:4 Reserved 0 R/W Write 0 for compatibility with possible future extensions 3:0 FIFO_THR[3:0] 7 (0111) R/W Set the threshold for the TX FIFO and RX FIFO. The threshold is exceeded when the number of bytes in the FIFO is equal to or higher than the threshold value. Setting Bytes in TX FIFO Bytes in RX FIFO 0 (0000) 61 4 1 (0001) 57 8 2 (0010) 53 12 3 (0011) 49 16 4 (0100) 45 20 5 (0101) 41 24 6 (0110) 37 28 7 (0111) 33 32 8 (1000) 29 36 9 (1001) 25 40 10 (1010) 21 44 11 (1011) 17 48 12 (1100) 13 52 13 (1101) 9 56 14 (1110) 5 60 15 (1111) 1 64 0x04: SYNC1 – Sync Word, High Byte Bit Field Name Reset R/W Description 7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word 0x05: SYNC0 – Sync Word, Low Byte Bit Field Name Reset R/W Description 7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word 0x06: PKTLEN – Packet Length Bit Field Name Reset R/W Description 7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed packet length mode is enabled. If variable packet length mode is used, this value indicates the maximum packet length allowed. SWRS038C Page 65 of 96

CC1100 0x07: PKTCTRL1 – Packet Automation Control Bit Field Name Reset R/W Description 7:5 PQT[2:0] 0 (0x00) R/W Preamble quality estimator threshold. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. A threshold of 4·PQT for this counter is used to gate sync word detection. When PQT=0 a sync word is always accepted. 4 Reserved 0 R0 3 CRC_AUTOFLUSH 0 R/W Enable automatic flush of RX FIFO when CRC in not OK. This requires that only one packet is in the RXIFIFO and that packet length is limited to the RX FIFO size. 2 APPEND_STATUS 1 R/W When enabled, two status bytes will be appended to the payload of the packet. The status bytes contain RSSI and LQI values, as well as CRC OK. 1:0 ADR_CHK[1:0] 0 (00) R/W Controls address check configuration of received packages. Setting Address check configuration 0 (00) No address check 1 (01) Address check, no broadcast 2 (10) Address check and 0 (0x00) broadcast 3 (11) Address check and 0 (0x00) and 255 (0xFF) broadcast SWRS038C Page 66 of 96

CC1100 0x08: PKTCTRL0 – Packet Automation Control Bit Field Name Reset R/W Description 7 Reserved R0 6 WHITE_DATA 1 R/W Turn data whitening on / off 0: Whitening off 1: Whitening on 5:4 PKT_FORMAT[1:0] 0 (00) R/W Format of RX and TX data Setting Packet format 0 (00) Normal mode, use FIFOs for RX and TX Synchronous serial mode, used for backwards 1 (01) compatibility. Data in on GDO0 Random TX mode; sends random data using PN9 2 (10) generator. Used for test. Works as normal mode, setting 0 (00), in RX. Asynchronous serial mode. Data in on GDO0 and 3 (11) Data out on either of the GDO0 pins 3 Reserved 0 R0 2 CRC_EN 1 R/W 1: CRC calculation in TX and CRC check in RX enabled 0: CRC disabled for TX and RX 1:0 LENGTH_CONFIG[1:0] 1 (01) R/W Configure the packet length Setting Packet length configuration 0 (00) Fixed packet length mode. Length configured in PKTLEN register 1 (01) Variable packet length mode. Packet length configured by the first byte after sync word 2 (10) Infinite packet length mode 3 (11) Reserved 0x09: ADDR – Device Address Bit Field Name Reset R/W Description 7:0 DEVICE_ADDR[7:0] 0 (0x00) R/W Address used for packet filtration. Optional broadcast addresses are 0 (0x00) and 255 (0xFF). 0x0A: CHANNR – Channel Number Bit Field Name Reset R/W Description 7:0 CHAN[7:0] 0 (0x00) R/W The 8-bit unsigned channel number, which is multiplied by the channel spacing setting and added to the base frequency. SWRS038C Page 67 of 96

CC1100 0x0B: FSCTRL1 – Frequency Synthesizer Control Bit Field Name Reset R/W Description 7:5 Reserved R0 4:0 FREQ_IF[4:0] 15 (0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. f f = XOSC ⋅FREQ_IF IF 210 The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz crystal. 0x0C: FSCTRL0 – Frequency Synthesizer Control Bit Field Name Reset R/W Description 7:0 FREQOFF[7:0] 0 (0x00) R/W Frequency offset added to the base frequency before being used by the frequency synthesizer. (2s-complement). Resolution is F /214 (1.59kHz-1.65kHz); range is ±202 kHz to ±210 kHz, XTAL dependent of XTAL frequency. 0x0D: FREQ2 – Frequency Control Word, High Byte Bit Field Name Reset R/W Description 7:6 FREQ[23:22] 0 (00) R FREQ[23:22] is always 0 (the FREQ2 register is less than 36 with 26-27 MHz crystal) 5:0 FREQ[21:16] 30 (0x1E) R/W FREQ[23:22] is the base frequency for the frequency synthesiser in increments of F /216. XOSC f f = XOSC ⋅FREQ[23:0] carrier 216 0x0E: FREQ1 – Frequency Control Word, Middle Byte Bit Field Name Reset R/W Description 7:0 FREQ[15:8] 196 (0xC4) R/W Ref. FREQ2 register 0x0F: FREQ0 – Frequency Control Word, Low Byte Bit Field Name Reset R/W Description 7:0 FREQ[7:0] 236 (0xEC) R/W Ref. FREQ2 register SWRS038C Page 68 of 96

CC1100 0x10: MDMCFG4 – Modem Configuration Bit Field Name Reset R/W Description 7:6 CHANBW_E[1:0] 2 (0x02) R/W 5:4 CHANBW_M[1:0] 0 (0x00) R/W Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. f BW = XOSC channel 8⋅(4+CHANBW_M)·2CHANBW_E The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal. 3:0 DRATE_E[3:0] 12 (0x0C) R/W The exponent of the user specified symbol rate 0x11: MDMCFG3 – Modem Configuration Bit Field Name Reset R/W Description 7:0 DRATE_M[7:0] 34 (0x22) R/W The mantissa of the user specified symbol rate. The symbol rate is configured using an unsigned, floating-point number with 9-bit mantissa and 4-bit exponent. The 9th bit is a hidden ‘1’. The resulting data rate is: (256+DRATE_M)⋅2DRATE_E R = ⋅ f DATA 228 XOSC The default values give a data rate of 115.051 kBaud (closest setting to 115.2 kBaud), assuming a 26.0 MHz crystal. SWRS038C Page 69 of 96

CC1100 0x12: MDMCFG2 – Modem Configuration Bit Field Name Reset R/W Description 7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator. 0 = Enable (better sensitivity) 1 = Disable (current optimized). Only for data rates ≤ 250 kBaud The recommended IF frequency changes when the DC blocking is disabled. Please use SmartRF® Studio [7] to calculate correct register setting. 6:4 MOD_FORMAT[2:0] 0 (000) R/W The modulation format of the radio signal Setting Modulation format 0 (000) 2-FSK 1 (001) GFSK 2 (010) - 3 (011) ASK/OOK 4 (100) - 5 (101) - 6 (110) - 7 (111) MSK ASK is only supported for output powers up to -1 dBm MSK is only supported for datarates above 26 kBaud 3 MANCHESTER_EN 0 R/W Enables Manchester encoding/decoding. 0 = Disable 1 = Enable 2:0 SYNC_MODE[2:0] 2 (010) R/W Combined sync-word qualifier mode. The values 0 (000) and 4 (100) disables preamble and sync word transmission in TX and preamble and sync word detection in RX. The values 1 (001), 2 (010), 5 (101) and 6 (110) enables 16-bit sync word transmission in TX and 16-bits sync word detection in RX. Only 15 of 16 bits need to match in RX when using setting 1 (001) or 5 (101). The values 3 (011) and 7 (111) enables repeated sync word transmission in TX and 32-bits sync word detection in RX (only 30 of 32 bits need to match). Setting Sync-word qualifier mode 0 (000) No preamble/sync 1 (001) 15/16 sync word bits detected 2 (010) 16/16 sync word bits detected 3 (011) 30/32 sync word bits detected 4 (100) No preamble/sync, carrier-sense above threshold 5 (101) 15/16 + carrier-sense above threshold 6 (110) 16/16 + carrier-sense above threshold 7 (111) 30/32 + carrier-sense above threshold SWRS038C Page 70 of 96

CC1100 0x13: MDMCFG1– Modem Configuration Bit Field Name Reset R/W Description 7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for packet payload 0 = Disable 1 = Enable (Only supported for fixed packet length mode, i.e. PKTCTRL0.LENGTH_CONFIG=0) 6:4 NUM_PREAMBLE[2:0] 2 (010) R/W Sets the minimum number of preamble bytes to be transmitted Setting Number of preamble bytes 0 (000) 2 1 (001) 3 2 (010) 4 3 (011) 6 4 (100) 8 5 (101) 12 6 (110) 16 7 (111) 24 3:2 Reserved R0 1:0 CHANSPC_E[1:0] 2 (10) R/W 2 bit exponent of channel spacing 0x14: MDMCFG0– Modem Configuration Bit Field Name Reset R/W Description 7:0 CHANSPC_M[7:0] 248 (0xF8) R/W 8-bit mantissa of channel spacing. The channel spacing is multiplied by the channel number CHAN and added to the base frequency. It is unsigned and has the format: f ∆f = XOSC ⋅(256+CHANSPC_M)⋅2CHANSPC_E CHANNEL 218 The default values give 199.951 kHz channel spacing (the closest setting to 200 kHz), assuming 26.0 MHz crystal frequency. SWRS038C Page 71 of 96

CC1100 0x15: DEVIATN – Modem Deviation Setting Bit Field Name Reset R/W Description 7 Reserved R0 6:4 DEVIATION_E[2:0] 4 (0x04) R/W Deviation exponent 3 Reserved R0 2:0 DEVIATION_M[2:0] 7 (111) R/W When MSK modulation is enabled: Sets fraction of symbol period used for phase change. Refer to the SmartRF® Studio software [7] for correct deviation setting when using MSK. When 2-FSK/GFSK modulation is enabled: Deviation mantissa, interpreted as a 4-bit value with MSB implicit 1. The resulting frequency deviation is given by: f f = xosc ⋅(8+DEVIATION _M)⋅2DEVIATION_E dev 217 The default values give ±47.607 kHz deviation, assuming 26.0 MHz crystal frequency. SWRS038C Page 72 of 96

CC1100 0x16: MCSM2 – Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:5 Reserved R0 Reserved 4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier sense). For ASK/OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods. 3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires, the chip checks if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQI is set when RX_TIME_QUAL=1. 2:0 RX_TIME[2:0] 7 (111) R/W Timeout for sync word search in RX for both WOR mode and normal RX operation. The timeout is relative to the programmed EVENT0 timeout. The RX timeout in µs is given by EVENT0·C(RX_TIME, WOR_RES) ·26/X, where C is given by the table below and X is the crystal oscillator frequency in MHz: Setting WOR_RES = 0 WOR_RES = 1 WOR_RES = 2 WOR_RES = 3 0 (000) 3.6058 18.0288 32.4519 46.8750 1 (001) 1.8029 9.0144 16.2260 23.4375 2 (010) 0.9014 4.5072 8.1130 11.7188 3 (011) 0.4507 2.2536 4.0565 5.8594 4 (100) 0.2254 1.1268 2.0282 2.9297 5 (101) 0.1127 0.5634 1.0141 1.4648 6 (110) 0.0563 0.2817 0.5071 0.7324 7 (111) Until end of packet As an example, EVENT0=34666, WOR_RES=0 and RX_TIME=6 corresponds to 1.96 ms RX timeout, 1 s polling interval and 0.195% duty cycle. Note that WOR_RES should be 0 or 1 when using WOR because using WOR_RES > 1 will give a very low duty cycle. In applications where WOR is not used all settings of WOR_RES can be used. The duty cycle using WOR is approximated by: Setting WOR_RES=0 WOR_RES=1 0 (000) 12.50% 1.95% 1 (001) 6.250% 9765ppm 2 (010) 3.125% 4883ppm 3 (011) 1.563% 2441ppm 4 (100) 0.781% NA 5 (101) 0.391% NA 6 (110) 0.195% NA 7 (111) NA Note that the RC oscillator must be enabled in order to use setting 0-6, because the timeout counts RC oscillator periods. WOR mode does not need to be enabled. The timeout counter resolution is limited: With RX_TIME=0, the timeout count is given by the 13 MSBs of EVENT0, decreasing to the 7MSBs of EVENT0 with RX_TIME=6. SWRS038C Page 73 of 96

CC1100 0x17: MCSM1– Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:4 CCA_MODE[1:0] 3 (11) R/W Selects CCA_MODE; Reflected in CCA signal Setting Clear channel indication 0 (00) Always 1 (01) If RSSI below threshold 2 (10) Unless currently receiving a packet 3 (11) If RSSI below threshold unless currently receiving a packet 3:2 RXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been received Setting Next state after finishing packet reception 0 (00) IDLE 1 (01) FSTXON 2 (10) TX 3 (11) Stay in RX It is not possible to set RXOFF_MODE to be TX or FSTXON and at the same time use CCA. 1:0 TXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been sent (TX) Setting Next state after finishing packet transmission 0 (00) IDLE 1 (01) FSTXON 2 (10) Stay in TX (start sending preamble) 3 (11) RX SWRS038C Page 74 of 96

CC1100 0x18: MCSM0– Main Radio Control State Machine Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:4 FS_AUTOCAL[1:0] 0 (00) R/W Automatically calibrate when going to RX or TX, or back to IDLE Setting When to perform automatic calibration 0 (00) Never (manually calibrate using SCAL strobe) 1 (01) When going from IDLE to RX or TX (or FSTXON) When going from RX or TX back to IDLE 2 (10) automatically Every 4th time when going from RX or TX to IDLE 3 (11) automatically In some automatic wake-on-radio (WOR) applications, using setting 3 (11) can significantly reduce current consumption. 3:2 PO_TIMEOUT 1 (01) R/W Programs the number of times the six-bit ripple counter must expire after XOSC has stabilized before CHP_RDYn goes low. If XOSC is on (stable) during power-down, PO_TIMEOUT should be set so that the regulated digital supply voltage has time to stabilize before CHP_RDYn goes low (PO_TIMEOUT=2 recommended). Typical start-up time for the voltage regulator is 50 us. If XOSC is off during power-down and the regulated digital supply voltage has sufficient time to stabilize while waiting for the crystal to be stable, PO_TIMEOUT can be set to 0. For robust operation it is recommended to use PO_TIMEOUT=2. Setting Expire count Timeout after XOSC start 0 (00) 1 Approx. 2.3 – 2.4 µs 1 (01) 16 Approx. 37 – 39 µs 2 (10) 64 Approx. 149 – 155 µs 3 (11) 256 Approx. 597 – 620 µs Exact timeout depends on crystal frequency. 1 PIN_CTRL_EN 0 R/W Enables the pin radio control option 0 XOSC_FORCE_ON 0 R/W Force the XOSC to stay on in the SLEEP state. SWRS038C Page 75 of 96

CC1100 0x19: FOCCFG – Frequency Offset Compensation Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5 FOC_BS_CS_GATE 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CS signal goes high. 4:3 FOC_PRE_K[1:0] 2 (10) R/W The frequency compensation loop gain to be used before a sync word is detected. Setting Freq. compensation loop gain before sync word 0 (00) K 1 (01) 2K 2 (10) 3K 3 (11) 4K 2 FOC_POST_K 1 R/W The frequency compensation loop gain to be used after a sync word is detected. Setting Freq. compensation loop gain after sync word 0 Same as FOC_PRE_K 1 K/2 1:0 FOC_LIMIT[1:0] 2 (10) R/W The saturation point for the frequency offset compensation algorithm: Setting Saturation point (max compensated offset) 0 (00) ±0 (no frequency offset compensation) 1 (01) ±BW /8 CHAN 2 (10) ±BW /4 CHAN 3 (11) ±BW /2 CHAN Frequency offset compensation is not supported for ASK/OOK; Always use FOC_LIMIT=0 with these modulation formats. SWRS038C Page 76 of 96

CC1100 0x1A: BSCFG – Bit Synchronization Configuration Bit Field Name Reset R/W Description 7:6 BS_PRE_KI[1:0] 1 (01) R/W The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): Setting Clock recovery loop integral gain before sync word 0 (00) K I 1 (01) 2K I 2 (10) 3K I 3 (11) 4K I 5:4 BS_PRE_KP[1:0] 2 (10) R/W The clock recovery feedback loop proportional gain to be used before a sync word is detected. Setting Clock recovery loop proportional gain before sync word 0 (00) K P 1 (01) 2K P 2 (10) 3K P 3 (11) 4K P 3 BS_POST_KI 1 R/W The clock recovery feedback loop integral gain to be used after a sync word is detected. Setting Clock recovery loop integral gain after sync word 0 Same as BS_PRE_KI 1 K/2 I 2 BS_POST_KP 1 R/W The clock recovery feedback loop proportional gain to be used after a sync word is detected. Setting Clock recovery loop proportional gain after sync word 0 Same as BS_PRE_KP 1 K P 1:0 BS_LIMIT[1:0] 0 (00) R/W The saturation point for the data rate offset compensation algorithm: Setting Data rate offset saturation (max data rate difference) 0 (00) ±0 (No data rate offset compensation performed) 1 (01) ±3.125% data rate offset 2 (10) ±6.25% data rate offset 3 (11) ±12.5% data rate offset SWRS038C Page 77 of 96

CC1100 0x1B: AGCCTRL2 – AGC Control Bit Field Name Reset R/W Description 7:6 MAX_DVGA_GAIN[1:0] 0 (00) R/W Reduces the maximum allowable DVGA gain. Setting Allowable DVGA settings 0 (00) All gain settings can be used 1 (01) The highest gain setting can not be used 2 (10) The 2 highest gain settings can not be used 3 (11) The 3 highest gain settings can not be used 5:3 MAX_LNA_GAIN[2:0] 0 (000) R/W Sets the maximum allowable LNA + LNA 2 gain relative to the maximum possible gain. Setting Maximum allowable LNA + LNA 2 gain 0 (000) Maximum possible LNA + LNA 2 gain 1 (001) Approx. 2.6 dB below maximum possible gain 2 (010) Approx. 6.1 dB below maximum possible gain 3 (011) Approx. 7.4 dB below maximum possible gain 4 (100) Approx. 9.2 dB below maximum possible gain 5 (101) Approx. 11.5 dB below maximum possible gain 6 (110) Approx. 14.6 dB below maximum possible gain 7 (111) Approx. 17.1 dB below maximum possible gain 2:0 MAGN_TARGET[2:0] 3 (011) R/W These bits set the target value for the averaged amplitude from the digital channel filter (1 LSB = 0 dB). Setting Target amplitude from channel filter 0 (000) 24 dB 1 (001) 27 dB 2 (010) 30 dB 3 (011) 33 dB 4 (100) 36 dB 5 (101) 38 dB 6 (110) 40 dB 7 (111) 42 dB SWRS038C Page 78 of 96

CC1100 0x1C: AGCCTRL1 – AGC Control Bit Field Name Reset R/W Description 7 Reserved R0 6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA 2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA 2 gain is decreased to minimum before decreasing LNA gain. 5:4 CARRIER_SENSE_REL_THR[1:0] 0 (00) R/W Sets the relative change threshold for asserting carrier sense Setting Carrier sense relative threshold 0 (00) Relative carrier sense threshold disabled 1 (01) 6 dB increase in RSSI value 2 (10) 10 dB increase in RSSI value 3 (11) 14 dB increase in RSSI value 3:0 CARRIER_SENSE_ABS_THR[3:0] 0 R/W Sets the absolute RSSI threshold for asserting carrier sense. (0000) The 2-complement signed threshold is programmed in steps of 1 dB and is relative to the MAGN_TARGET setting. Setting Carrier sense absolute threshold (Equal to channel filter amplitude when AGC has not decreased gain) -8 (1000) Absolute carrier sense threshold disabled -7 (1001) 7 dB below MAGN_TARGET setting … … -1 (1111) 1 dB below MAGN_TARGET setting 0 (0000) At MAGN_TARGET setting 1 (0001) 1 dB above MAGN_TARGET setting … … 7 (0111) 7 dB above MAGN_TARGET setting SWRS038C Page 79 of 96

CC1100 0x1D: AGCCTRL0 – AGC Control Bit Field Name Reset R/W Description 7:6 HYST_LEVEL[1:0] 2 (10) R/W Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determine gain changes). Setting Description 0 (00) No hysteresis, small symmetric dead zone, high gain Low hysteresis, small asymmetric dead zone, medium 1 (01) gain Medium hysteresis, medium asymmetric dead zone, 2 (10) medium gain Large hysteresis, large asymmetric dead zone, low 3 (11) gain 5:4 WAIT_TIME[1:0] 1 (01) R/W Sets the number of channel filter samples from a gain adjustment has been made until the AGC algorithm starts accumulating new samples. Setting Channel filter samples 0 (00) 8 1 (01) 16 2 (10) 24 3 (11) 32 3:2 AGC_FREEZE[1:0] 0 (00) R/W Control when the AGC gain should be frozen. Setting Function 0 (00) Normal operation. Always adjust gain when required. The gain setting is frozen when a sync word has been 1 (01) found. Manually freeze the analogue gain setting and 2 (10) continue to adjust the digital gain. Manually freezes both the analogue and the digital 3 (11) gain setting. Used for manually overriding the gain. 1:0 FILTER_LENGTH[1:0] 1 (01) R/W Sets the averaging length for the amplitude from the channel filter. Sets the OOK/ASK decision boundary for OOK/ASK reception. Setting Channel filter OOK decision samples 0 (00) 8 4 dB 1 (01) 16 8 dB 2 (10) 32 12 dB 3 (11) 64 16 dB 0x1E: WOREVT1 – High Byte Event0 Timeout Bit Field Name Reset R/W Description 7:0 EVENT0[15:8] 135 (0x87) R/W High byte of EVENT0 timeout register 750 t = ⋅EVENT0⋅25⋅WOR_RES Event0 f XOSC SWRS038C Page 80 of 96

CC1100 0x1F: WOREVT0 –Low Byte Event0 Timeout Bit Field Name Reset R/W Description 7:0 EVENT0[7:0] 107 (0x6B) R/W Low byte of EVENT0 timeout register. The default EVENT0 value gives 1.0s timeout, assuming a 26.0 MHz crystal. 0x20: WORCTRL – Wake On Radio Control Bit Field Name Reset R/W Description 7 RC_PD 1 R/W Power down signal to RC oscillator. When written to 0, automatic initial calibration will be performed 6:4 EVENT1[2:0] 7 (111) R/W Timeout setting from register block. Decoded to Event 1 timeout. RC oscillator clock frequency equals F /750, which is 34.7 – 36 kHz, XOSC depending on crystal frequency. The table below lists the number of clock periods after Event 0 before Event 1 times out. Setting t Event1 0 (000) 4 (0.111 – 0.115 ms) 1 (001) 6 (0.167 – 0.173 ms) 2 (010) 8 (0.222 – 0.230 ms) 3 (011) 12 (0.333 – 0.346 ms) 4 (100) 16 (0.444 – 0.462 ms) 5 (101) 24 (0.667 – 0.692 ms) 6 (110) 32 (0.889 – 0.923 ms) 7 (111) 48 (1.333 – 1.385 ms) 3 RC_CAL 1 R/W Enables (1) or disables (0) the RC oscillator calibration. 2 Reserved R0 1:0 WOR_RES 0 (00) R/W Controls the Event 0 resolution as well as maximum timeout of the WOR module and maximum timeout under normal RX operation:: Setting Resolution (1 LSB) Max timeout 0 (00) 1 period (28µs – 29µs) 1.8 – 1.9 seconds 1 (01) 25 periods (0.89ms –0.92 ms) 58 – 61 seconds 2 (10) 210 periods (28 – 30 ms) 31 – 32 minutes 3 (11) 215 periods (0.91 – 0.94 s) 16.5 – 17.2 hours Note that WOR_RES should be 0 or 1 when using WOR because WOR_RES > 1 will give a very low duty cycle. In normal RX operation all settings of WOR_RES can be used. SWRS038C Page 81 of 96

CC1100 0x21: FREND1 – Front End RX Configuration Bit Field Name Reset R/W Description 7:6 LNA_CURRENT[1:0] 1 (01) R/W Adjusts front-end LNA PTAT current output 5:4 LNA2MIX_CURRENT[1:0] 1 (01) R/W Adjusts front-end PTAT outputs 3:2 LODIV_BUF_CURRENT_RX[1:0] 1 (01) R/W Adjusts current in RX LO buffer (LO input to mixer) 1:0 MIX_CURRENT[1:0] 2 (10) R/W Adjusts current in mixer 0x22: FREND0 – Front End TX Configuration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:4 LODIV_BUF_CURRENT_TX[1:0] 1 (0x01) R/W Adjusts current TX LO buffer (input to PA). The value to use in this field is given by the SmartRF® Studio software [7]. 3 Reserved R0 2:0 PA_POWER[2:0] 0 (0x00) R/W Selects PA power setting. This value is an index to the PATABLE, which can be programmed with up to 8 different PA settings. In OOK/ASK mode, this selects the PATABLE index to use when transmitting a ‘1’. PATABLE index zero is used in OOK/ASK when transmitting a ‘0’. The PATABLE settings from index ‘0’ to the PA_POWER value are used for ASK TX shaping, and for power ramp-up/ramp-down at the start/end of transmission in all TX modulation formats. 0x23: FSCAL3 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 FSCAL3[7:6] 2 (0x02) R/W Frequency synthesizer calibration configuration. The value to write in this field before calibration is given by the SmartRF® Studio software. 5:4 CHP_CURR_CAL_EN[1:0] 2 (0x02) R/W Enable charge pump calibration stage when 1 3:0 FSCAL3[3:0] 9 (1001) R/W Frequency synthesizer calibration result register. Digital bit vector defining the charge pump output current, on an exponential scale: IOUT = I0·2FSCAL3[3:0]/4 Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. SWRS038C Page 82 of 96

CC1100 0x24: FSCAL2 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 Reserved R0 5 VCO_CORE_H_EN 0 R/W Choose high (1) / low (0) VCO 4:0 FSCAL2[4:0] 10 (0x0A) R/W Frequency synthesizer calibration result register. VCO current calibration result and override value Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. 0x25: FSCAL1 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7:6 Reserved R0 5:0 FSCAL1[5:0] 32 (0x20) R/W Frequency synthesizer calibration result register. Capacitor array setting for VCO coarse tuning. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2 and FSCAL1 register values corresponding to the next RF frequency. 0x26: FSCAL0 – Frequency Synthesizer Calibration Bit Field Name Reset R/W Description 7 Reserved R0 6:0 FSCAL0[6:0] 13 (0x0D) R/W Frequency synthesizer calibration control. The value to use in this register is given by the SmartRF® Studio software [7]. 0x27: RCCTRL1 – RC Oscillator Configuration Bit Field Name Reset R/W Description 7 Reserved 0 R0 6:0 RCCTRL1[6:0] 65 (0x41) R/W RC oscillator configuration. 0x28: RCCTRL0 – RC Oscillator Configuration Bit Field Name Reset R/W Description 7 Reserved 0 R0 6:0 RCCTRL0[6:0] 0 (0x00) R/W RC oscillator configuration. SWRS038C Page 83 of 96

CC1100 33.2 Configuration Register Details – Registers that Lose Programming in SLEEP State 0x29: FSTEST – Frequency Synthesizer Calibration Control Bit Field Name Reset R/W Description 7:0 FSTEST[7:0] 89 (0x59) R/W For test only. Do not write to this register. 0x2A: PTEST – Production Test Bit Field Name Reset R/W Description 7:0 PTEST[7:0] 127 (0x7F) R/W Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state. The default 0x7F value should then be written back before leaving the IDLE state. Other use of this register is for test only. 0x2B: AGCTEST – AGC Test Bit Field Name Reset R/W Description 7:0 AGCTEST[7:0] 63 (0x3F) R/W For test only. Do not write to this register. 0x2C: TEST2 – Various Test Settings Bit Field Name Reset R/W Description 7:0 TEST2[7:0] 136 (0x88) R/W The value to use in this register is given by the SmartRF® Studio software [7]. 0x2D: TEST1 – Various Test Settings Bit Field Name Reset R/W Description 7:0 TEST1[7:0] 49 (0x31) R/W The value to use in this register is given by the SmartRF® Studio software [7]. 0x2E: TEST0 – Various Test Settings Bit Field Name Reset R/W Description 7:2 TEST0[7:2] 2 (0x02) R/W The value to use in this register is given by the SmartRF® Studio software [7]. 1 VCO_SEL_CAL_EN 1 R/W Enable VCO selection calibration stage when 1 0 TEST0[0] 1 R/W The value to use in this register is given by the SmartRF® Studio software [7]. SWRS038C Page 84 of 96

CC1100 33.3 Status Register Details 0x30 (0xF0): PARTNUM – Chip ID Bit Field Name Reset R/W Description 7:0 PARTNUM[7:0] 0 (0x00) R Chip part number 0x31 (0xF1): VERSION – Chip ID Bit Field Name Reset R/W Description 7:0 VERSION[7:0] 3 (0x03) R Chip version number. 0x32 (0xF2): FREQEST – Frequency Offset Estimate from Demodulator Bit Field Name Reset R/W Description 7:0 FREQOFF_EST R The estimated frequency offset (2’s complement) of the carrier. Resolution is F /214 (1.59 - 1.65 kHz); range is ±202 kHz to ±210 kHz, dependent of XTAL XTAL frequency. Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK modulation. This register will read 0 when using ASK or OOK modulation. 0x33 (0xF3): LQI – Demodulator Estimate for Link Quality Bit Field Name Reset R/W Description 7 CRC OK R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6:0 LQI_EST[6:0] R The Link Quality Indicator estimates how easily a received signal can be demodulated. Calculated over the 64 symbols following the sync word 0x34 (0xF4): RSSI – Received Signal Strength Indication Bit Field Name Reset R/W Description 7:0 RSSI R Received signal strength indicator SWRS038C Page 85 of 96

CC1100 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State Bit Field Name Reset R/W Description 7:5 Reserved R0 4:0 MARC_STATE[4:0] R Main Radio Control FSM State Value State name State (Figure 16, page 42) 0 (0x00) SLEEP SLEEP 1 (0x01) IDLE IDLE 2 (0x02) XOFF XOFF 3 (0x03) VCOON_MC MANCAL 4 (0x04) REGON_MC MANCAL 5 (0x05) MANCAL MANCAL 6 (0x06) VCOON FS_WAKEUP 7 (0x07) REGON FS_WAKEUP 8 (0x08) STARTCAL CALIBRATE 9 (0x09) BWBOOST SETTLING 10 (0x0A) FS_LOCK SETTLING 11 (0x0B) IFADCON SETTLING 12 (0x0C) ENDCAL CALIBRATE 13 (0x0D) RX RX 14 (0x0E) RX_END RX 15 (0x0F) RX_RST RX 16 (0x10) TXRX_SWITCH TXRX_SETTLING 17 (0x11) RXFIFO_OVERFLOW RXFIFO_OVERFLOW 18 (0x12) FSTXON FSTXON 19 (0x13) TX TX 20 (0x14) TX_END TX 21 (0x15) RXTX_SWITCH RXTX_SETTLING 22 (0x16) TXFIFO_UNDERFLOW TXFIFO_UNDERFLOW Note: it is not possible to read back the SLEEP or XOFF state numbers because setting CSn low will make the chip enter the IDLE mode from the SLEEP or XOFF states. 0x36 (0xF6): WORTIME1 – High Byte of WOR Time Bit Field Name Reset R/W Description 7:0 TIME[15:8] R High byte of timer value in WOR module 0x37 (0xF7): WORTIME0 – Low Byte of WOR Time Bit Field Name Reset R/W Description 7:0 TIME[7:0] R Low byte of timer value in WOR module SWRS038C Page 86 of 96

CC1100 0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status Bit Field Name Reset R/W Description 7 CRC_OK R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6 CS R Carrier sense 5 PQT_REACHED R Preamble Quality reached 4 CCA R Channel is clear 3 SFD R Sync word found 2 GDO2 R Current GDO2 value. Note: the reading gives the non-inverted value irrespective of what IOCFG2.GDO2_INV is programmed to. It is not recommended to check for PLL lock by reading PKTSTATUS[2] with GDO2_CFG=0x0A. 1 Reserved R0 0 GDO0 R Current GDO0 value. Note: the reading gives the non-inverted value irrespective of what IOCFG0.GDO0_INV is programmed to. It is not recommended to check for PLL lock by reading PKTSTATUS[0] with GDO0_CFG=0x0A. 0x39 (0xF9): VCO_VC_DAC – Current Setting from PLL Calibration Module Bit Field Name Reset R/W Description 7:0 VCO_VC_DAC[7:0] R Status register for test only. 0x3A (0xFA): TXBYTES – Underflow and Number of Bytes Bit Field Name Reset R/W Description 7 TXFIFO_UNDERFLOW R 6:0 NUM_TXBYTES R Number of bytes in TX FIFO 0x3B (0xFB): RXBYTES – Overflow and Number of Bytes Bit Field Name Reset R/W Description 7 RXFIFO_OVERFLOW R 6:0 NUM_RXBYTES R Number of bytes in RX FIFO 0x3C (0xFC): RCCTRL1_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset R/W Description 7 Reserved R0 6:0 RCCTRL1_STATUS[6:0] R Contains the value from the last run of the RC oscillator calibration routine. For usage description refer to AN047 [4] SWRS038C Page 87 of 96

CC1100 0x3D (0xFC): RCCTRL0_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset R/W Description 7 Reserved R0 6:0 RCCTRL0_STATUS[6:0] R Contains the value from the last run of the RC oscillator calibration routine. For usage description refer to Aplication Note AN047 [4]. 34 Package Description (QLP 20) All dimensions are in millimetres, angles in degrees. NOTE: The CC1100 is available in RoHS lead-free package only. Figure 31: Package Dimensions Drawing Package A A1 A2 D D1 D2 E E1 E2 L T b e Type Min 0.75 0.005 0.55 3.90 3.65 3.90 3.65 0.45 0.190 0.18 QLP 20 (4x4) Typ. 0.85 0.025 0.65 4.00 3.75 2.40 4.00 3.75 2.40 0.55 0.23 0.50 Max 0.95 0.045 0.75 4.10 3.85 4.10 3.85 0.65 0.245 0.30 Table 39: Package Dimensions SWRS038C Page 88 of 96

CC1100 34.1 Recommended PCB Layout for Package (QLP 20) Figure 32: Recommended PCB Layout for QLP 20 Package Note: Figure 32 is an illustration only and not to scale. There are five 10 mil via holes distributed symmetrically in the ground pad under the package. See also the CC1100EM reference designs ( [5] and [6]). 34.2 Package Thermal Properties Thermal Resistance Air velocity [m/s] 0 Rth,j-a [K/W] 40.4 Table 40: Thermal Properties of QLP 20 Package 34.3 Soldering Information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed. 34.4 Tray Specification CC1100 can be delivered in standard QLP 4x4 mm shipping trays. Tray Specification Package Tray Width Tray Height Tray Length Units per Tray QLP 20 135.9mm 7.62mm 322.6mm 490 Table 41: Tray Specification SWRS038C Page 89 of 96

CC1100 34.5 Carrier Tape and Reel Specification Carrier tape and reel is in accordance with EIA Specification 481. Tape and Reel Specification Package Tape Width Component Hole Reel Units per Reel Pitch Pitch Diameter QLP 20 12 mm 8 mm 4 mm 13 inches 2500 Table 42: Carrier Tape and Reel Specification 35 Ordering Information Chipcon Part TI Part Number Description Minimum Order Quantity Number (MOQ) CC1100-RTY1 CC1100RTK CC1100 QLP20 RoHS Pb-free 490/tray 490 (tray) CC1100-RTR1 CC1100RTKR CC1100 QLP20 RoHS Pb-free 2500/T&R 2,500 (tape and reel) CC1100-1150DK-433 CC1100-1150DK- CC1100/CC1150 -433 MHz Development Kit 1 433 CC1100-1150DK-868 CC1100-1150DK- CC1100/CC1150 -868/915 MHz Development 1 868 Kit CC1100EMK-433 CC1100EMK-433 CC1100 -433 MHz Evaluation Module Kit 1 CC1100EMK-868 CC1100EMK-868 CC1100 -868/915 MHz Evaluation Module Kit 1 CC1150EMK-433 CC1150EMK-433 CC1150 -433 MHz Evaluation Module Kit 1 CC1150EMK-868 CC1150EMK-868 CC1150 -868/915 MHz Evaluation Module Kit 1 Table 43: Ordering Information SWRS038C Page 90 of 96

CC1100 36 References [1] CC1100 Errata Notes (swrz012.pdf) [2] AN001 SRD Regulations for Licence Free Transceiver Operation (swra090.pdf) [3] AN039 Using the CC1100 in the European 433 and 868 MHz ISM Bands (swra054.pdf) [4] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [5] CC1100EM 315 - 433 MHz Reference Design 1.0 (swrr037.zip) [6] CC1100EM 868 – 915 MHz Reference Design 2.0 (swrr038.zip) [7] SmartRF® Studio (swrc046.zip) [8] CC1100 CC2500 Examples Libraries (swrc021.zip) [9] CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User Manual (swru109.pdf) SWRS038C Page 91 of 96

CC1100 37 General Information 37.1 Document History Revision Date Description/Changes SWRSO38C 2008-05-22 Added product information on front page SWRS038B 2007-07-09 Added info to ordering information Changes in the General Principle of Matrix Interleaving figure. Changes in Table: Bill Of Materials for the Application Circuit Changes in Figure: Typical Application and Evaluation Circuit 868/915 MHz Changed the equation for channel spacing in the MDMCFG0 register. kbps replaced by kBaud throughout the document. Some of the sections have been re-written to be easier to read without having any new info added. Absolute maximum supply voltage rating increased from 3.6 V to 3.9 V. Changed the frequency accuracy after calibration for the low power RC oscillator from ±0.3 to ±1 %. Updates to sensitivity and current consumption numbers listed under Key Features. FSK changed to 2-FSK throughout the document. Updates to the Abbreviation table. Updates to the Electrical Specifications section. Added info about RX and TX latency. Added info in the Pinout Overview table regarding GDO0 and GDO2. Changed current consumption in RX and TX in the simplified state diagram. Added info about default values after reset vs. optimum register settings in the Configuration Software section Changes to the SPI Interface Timing Requirements. Info added about t sp,pd The following figures have been changed: Configuration Registers Write and Read Operations, SRES Command Strobe, and Register Access Types. In the Register Access section, the address range is changed. In the PATABLE Access section, info is added regarding limitations on output power programming when using PA ramping. In the Packet Format section, preamble pattern is changed to 10101010 and info about bug related to turning off the transmitter in infinite packet length mode is added. Added info to the Frequency Offset Compensation section. Added info about the initial value of the PN9 sequence in the Data Whitening section. In the Packet Handling in Transmit Mode section, info about TX FIFO underflow state is added. Added section Packet Handling in Firmware. 0x00 is added as a valid PATABLE setting in addition to 0x30-0x3F when using ASK. In the PQT section a change is made as to how much the counter decreases. The RSSI value is in dBm and not dB. The whole CS Absolute Threshold section has been re-written and the equation calculating the threshold has been removed. Added info in the CCA section on what happens if the channel is not clear. Added info to the LQI section for better understanding. Removed all references to the voltage regulator in relation with the CHP_RDYn signal, as this signal is only related to the crystal. Removed references to the voltage regulator in the figures: Power-On Reset and Power-On Reset with SRES. Changes to the SI line in the Power-On Reset with SRES figure Added info on the three automatic calibration options. Removed the autosync feature from the WOR section and added info on how to exit WOR mode. Also added info about minimum sleep time and references to App. Note 047 together with info about calibration of the RC oscillator. The figure: Event 0 and Event 1 Relationship is changed for better readability. Info added to the Timing section related to reduced calibration time. The Output Power Programming section is divided into 2 new sections; Output Power Programming and Shaping and PA Ramping. Added info on programming of PATABLE when using OOK, and about PATABLE when entering SLEEP mode. 2 new figures added to the Shaping and PA Ramping section: Shaping of ASK Signal and PA Ramping, together with one new table: PATABLE Settings Used Together with ASK Shaping and PA Ramping. Changed made to current consumption in the Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands table. Added section Layout Recommendations. In section General Purpose / Test Output Control Pins: Added info on GDO pins in SLEEP state. Better explanation of some of the signals in the GDOx Signal Selection table. Also added some more signals. SWRS038C Page 92 of 96

CC1100 Revision Date Description/Changes SWRSO38C 2008-05-22 Added product information on front page Asynchronous transparent mode is called asynchronous serial mode throughout the document. Removed comments about having to use NRZ coding in synchronous serial mode. Added info that Manschester encoding cannot be used in this mode. Added a third calibration method plus additional info about the 3 methods in the Frequency Hopping and Multi-Channel Systems section. Added info about differential antenna in the Low Cost Systems section. Changes number of commands strobes from 14 to 13. Changed description of SFRX, SFTX, SWORRST, and SNOP in the Command Strobes table. Added two new registers; RCCTRL1_STATUS and RCCTRL0_STATUS Changed field name and/or description of the following registers: PKTCTRL1, MCSM2, MCSM0, WORCTRL, FSCAL3, FSCAL2, FSCAL1, and TEST0. Changed tray width in the Tray Specification table. Added references. SWRS038A 2006-06-20 Updates to Electrical Specifications due to increased amount of measurement data. Updated application circuit for 868 MHz. Updated balun component values. Updated current consumption figures in state diagrams. Added figures to table on SPI interface timing requirements. Added information about SPI read. Added table for channel filter bandwidths. Added figure showing data whitening. Updates to text and included new figure in section on arbitrary length configuration. References to SAFC strobe removed. Added additional information about support of ASK modulation. Added information about CRC filtering. Added information about sync word qualifier. Added information on RSSI offset, RSSI update rate, RSSI calculation and typical RSSI curves. Added information on CS and tables with register settings versus CS threshold. Updates to text and included new figures in section on power-on start-up sequence. Changes to wake-on-radio current consumption figures under electrical specifications. Updates to text in section on data FIFO. Corrected formula for calculation of output frequency in Frequency Programming section. Added information about how to check for PLL lock in section on VCO. Corrected table with PATABLE setting versus output power. Added typical selectivity curves for selected datarates. Added information on how to interface external clock signal. Added optimal match impedances in RF match section. Better explanation of some of the signals in table of GDO signal selection. Also added some more signals. Added information on system considerations. Added CRC_AUTOFLUSH option in PCTRL1 register. Added information on timeout for sync word search in RX in register MCSM2. Changes to wake-on-radio control register WORCTRL. WOR_RES[1:0] settings 10 b and 11b changed to NA. Added more detailed information on PO_TIMEOUT in register MCSM0. Added description of programming bits in registers FOCCFG, BSCFG, AGCCTRL2, AGCCTRL1, AGCCTRL0, FREND1, FSCAL3. 1.0 2005-04-25 First preliminary Data Sheet release Table 44: Document History SWRS038C Page 93 of 96

CC1100 37.2 Product Status Definitions Data Sheet Identification Product Status Definition Advance Information Planned or Under This data sheet contains the design specifications for product Development development. Specifications may change in any manner without notice. Preliminary Engineering Samples This data sheet contains preliminary data, and supplementary and Pre-Production data will be published at a later date. Chipcon reserves the right Prototypes to make changes at any time without notice in order to improve design and supply the best possible product. The product is not yet fully qualified at this point. No Identification Noted Full Production This data sheet contains the final specifications. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by Chipcon. The data sheet is printed for reference information only. Table 45: Product Status Definitions SWRS038C Page 94 of 96

CC1100 38 Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw 39 TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: support.ti.com TI Semiconductor KnowledgeBase Home Page: support.ti.com/sc/knowledgebase Product Information Centers Americas Phone: +1(972) 644-5580 Fax: +1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.htm Europe, Middle East and Africa Phone: Belgium (English) +32 (0) 27 45 54 32 Finland (English) +358 (0) 9 25173948 France +33 (0) 1 30 70 11 64 Germany +49 (0) 8161 80 33 11 Israel (English) 180 949 0107 Italy 800 79 11 37 Netherlands (English) +31 (0) 546 87 95 45 Russia +7 (0) 95 363 4824 Spain +34 902 35 40 28 Sweden (English) +46 (0) 8587 555 22 United Kingdom +44 (0) 1604 66 33 99 Fax: +49 (0) 8161 80 2045 Internet: support.ti.com/sc/pic/euro.htm Japan Fax International +81-3-3344-5317 Domestic 0120-81-0036 Internet/Email International support.ti.com/sc/pic/japan.htm Domestic www.tij.co.jp/pic SWRS038C Page 95 of 96

CC1100 Asia Phone International +886-2-23786800 Domestic Toll-Free Number Australia 1-800-999-084 China 800-820-8682 Hong Kong 800-96-5941 India +91-80-51381665 (Toll) Indonesia 001-803-8861-1006 Korea 080-551-2804 Malaysia 1-800-80-3973 New Zealand 0800-446-934 Philippines 1-800-765-7404 Singapore 800-886-1028 Taiwan 0800-006800 Thailand 001-800-886-0010 Fax +886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.htm SWRS038C Page 96 of 96

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) CC1100RTKR QFN RTK 20 2500 330.0 12.4 4.25 4.25 1.0 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CC1100RTKR QFN RTK 20 2500 378.0 70.0 346.0 PackMaterials-Page2

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