BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 10 December 2013 Product data sheet 1. General description Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits • Dual MOSFET • Q101 Compliant • Repetitive avalanche rated • Suitable for thermally demanding environments due to 175 °C rating • True logic level gate with V rating of greater than 0.5 V at 175 °C GS(th) 3. Applications • 12 V Automotive systems • Motors, lamps and solenoid control • Transmission control • Ultra high performance power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T ≥ 25 °C; T ≤ 175 °C - - 40 V DS j j I drain current V = 5 V; T = 25 °C; Fig. 1 - - 30 A D GS mb P total power dissipation T = 25 °C; Fig. 2 - - 53 W tot mb Static characteristics FET1 and FET2 R drain-source on-state V = 5 V; I = 10 A; T = 25 °C; Fig. 11 - 7.66 9.4 mΩ DSon GS D j resistance Dynamic characteristics FET1 and FET2 Q gate-drain charge I = 10 A; V = 32 V; V = 5 V; - 5.3 - nC GD D DS GS T = 25 °C; Fig. 13; Fig. 14 j

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S1 source1 8 7 6 5 D1D1 D2D2 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 S1 G1 S2 G2 6 D2 drain2 mbk725 1 2 3 4 7 D1 drain1 LFPAK56D (SOT1205) 8 D1 drain1 6. Ordering information Table 3. Ordering information Type number Package Name Description Version BUK9K8R7-40E LFPAK56D Plastic single ended surface mounted package (LFPAK56D); 8 SOT1205 leads 7. Marking Table 4. Marking codes Type number Marking code BUK9K8R7-40E 98E740 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V drain-source voltage T ≥ 25 °C; T ≤ 175 °C - 40 V DS j j V drain-gate voltage R = 20 kΩ - 40 V DGR GS VGS gate-source voltage Tj ≤ 175 °C; Pulsed [1][2] -15 15 V T ≤ 175 °C; DC -10 10 V j I drain current T = 25 °C; V = 5 V; Fig. 1 - 30 A D mb GS T = 100 °C; V = 5 V; Fig. 1 - 30 A mb GS I peak drain current T = 25 °C; pulsed; t ≤ 10 µs; Fig. 4 - 211 A DM mb p BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 2 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET Symbol Parameter Conditions Min Max Unit P total power dissipation T = 25 °C; Fig. 2 - 53 W tot mb T storage temperature -55 175 °C stg T junction temperature -55 175 °C j Source-drain diode FET1 and FET2 I source current T = 25 °C - 30 A S mb I peak source current pulsed; t ≤ 10 µs; T = 25 °C - 211 A SM p mb Avalanche Ruggedness FET1 and FET2 EDS(AL)S non-repetitive drain-source ID = 30 A; Vsup ≤ 40 V; VGS = 10 V; [3][4] - 84 mJ avalanche energy T = 25 °C; Fig. 3 j(init) [1] Accumulated Pulse duration up to 50 hours delivers zero defect ppm [2] Significantly longer life times are achieved by lowering Tj and or VGS. [3] Refer to application note AN10273 for further information [4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 003aal056 03aa16 60 120 IIDD ((AA)) 50 Pder (%) 40 80 30 ((11)) 20 40 10 0 0 0 25 50 75 100 125 150 175 200 0 50 100 150 200 Tj (°C) Tmb(°C) (1) Capped at 30A due to package Fig. 2. Normalized total power dissipation as a Fig. 1. Continuous drain current as a function of function of mounting base temperature mounting base temperature BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 3 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 102 003aal057 IIAALL ((AA)) 10 ((11)) ((22)) 1 ((33)) 10-1 10-3 10-2 10-1 1 10 tAL (ms) Fig. 3. Avalanche rating; avalanche current as a function of avalanche time 103 003aal058 IIDD ((AA)) LLiimmiitt RRDDSSoonn == VVDDSS // IIDD 102 ttpp == 1100 uuss 110000 uuss 10 DDCC 11 mmss 1 1100 mmss 110000 mmss 10-1 10-1 1 10 102 VDS (V) Fig. 4. Safe operating area; continuous and peak drain currents as a function of drain-source voltage 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R thermal resistance Fig. 5 - - 2.84 K/W th(j-mb) from junction to mounting base R thermal resistance Minimum footprint; mounted on a - 95 - K/W th(j-a) from junction to printed circuit board ambient BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 4 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 003aal059 10 ZZtthh((jj--mmbb)) ((KK//WW)) 1 δδ == 00..55 00..22 00..11 10-1 00..0055 P δ = tp T 00..0022 ssiinnggllee sshhoott tp t T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 tp (s) Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics FET1 and FET2 V drain-source I = 250 µA; V = 0 V; T = -55 °C 36 - - V (BR)DSS D GS j breakdown voltage I = 250 µA; V = 0 V; T = 25 °C 40 - - V D GS j V gate-source threshold I = 1 mA; V = V ; T = 25 °C; 1.4 1.7 2.1 V GS(th) D DS GS j voltage Fig. 9; Fig. 10 I = 1 mA; V = V ; T = 175 °C; 0.5 - - V D DS GS j Fig. 9; Fig. 10 I = 1 mA; V = V ; T = -55 °C; - - 2.45 V D DS GS j Fig. 9; Fig. 10 I drain leakage current V = 40 V; V = 0 V; T = 175 °C - - 500 µA DSS DS GS j V = 40 V; V = 0 V; T = 25 °C - 0.02 1 µA DS GS j I gate leakage current V = -10 V; V = 0 V; T = 25 °C - 2 100 nA GSS GS DS j V = 10 V; V = 0 V; T = 25 °C - 2 100 nA GS DS j R drain-source on-state V = 5 V; I = 10 A; T = 25 °C; Fig. 11 - 7.66 9.4 mΩ DSon GS D j resistance V = 5 V; I = 10 A; T = 175 °C; - 15.4 18.9 mΩ GS D j Fig. 11; Fig. 12 V = 10 V; I = 10 A; T = 25 °C; - 6.26 8 mΩ GS D j Fig. 11 Dynamic characteristics FET1 and FET2 Q total gate charge I = 10 A; V = 32 V; V = 5 V; - 15.7 - nC G(tot) D DS GS T = 25 °C; Fig. 13; Fig. 14 Q gate-source charge j - 3.2 - nC GS BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 5 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET Symbol Parameter Conditions Min Typ Max Unit Q gate-drain charge - 5.3 - nC GD C input capacitance V = 0 V; V = 25 V; f = 1 MHz; - 1583 2110 pF iss GS DS T = 25 °C; Fig. 15 C output capacitance j - 225 270 pF oss C reverse transfer - 114 157 pF rss capacitance t turn-on delay time V = 32 V; R = 3.3 Ω; V = 5 V; - 10.8 - ns d(on) DS L GS R = 5 Ω; T = 25 °C; I = 10 A t rise time G(ext) j D - 19.8 - ns r t turn-off delay time - 20.5 - ns d(off) t fall time - 18.2 - ns f Source-drain diode FET1 and FET2 V source-drain voltage I = 10 A; V = 0 V; T = 25 °C; Fig. 16 - 0.78 1.2 V SD S GS j t reverse recovery time I = 10 A; dI /dt = -100 A/µs; V = 0 V; - 20.5 - ns rr S S GS V = 20 V; T = 25 °C Q recovered charge DS j - 12.1 - nC r 003aal061 003aal060 30 40 RRDDSSoonn IIDD 10 V ((AA)) 4.5 V VGS = 3 V 24 32 18 24 2.8 V VGS = 3 V 12 16 2.6 V 6 8 22..46 VV 2.2 V 0 0 0 4 8 12 16 0 1 2 3 4 VGS (V) VDS (V) T = 25 °C; t = 300 μs Fig. 6. Drain-source on-state resistance as a function j p of gate-source voltage; typical values Fig. 7. Output characteristics; drain current as a function of drain-source voltage; typical values BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 6 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 80 003aal063 3 003aah025 IIDD VGS(th) ((AA)) (V) 2.5 64 max 2 48 typ 1.5 32 min 1 16 117755°°CC TTjj == 2255°°CC 0.5 0 0 0 0.8 1.6 2.4 3.2 4 -60 0 60 120 180 VGS (V) Tj(°C) Fig. 8. Transfer characteristics; drain current as a Fig. 9. Gate-source threshold voltage as a function of function of gate-source voltage; typical values junction temperature 10-1 003aah026 50 003aal064 ID RRDDSSoonn (A) 2.6 V 2.8 V 3 V 10-2 40 10-3 min typ max 30 10-4 20 3.5 V 10-5 10 4.5 V VGS(V) = 10 V 10-6 0 0 1 2 3 0 8 16 24 32 40 VGS(V) ID (A) T = 25 °C; t = 300 μs j p Fig. 10. Sub-threshold drain current as a function of gate-source voltage Fig. 11. Drain-source on-state resistance as a function of drain current; typical values BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 7 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 003aaj814 2.4 VDS a ID 1.6 VGS(pl) VGS(th) VGS 0.8 QGS1 QGS2 QGS QGD QG(tot) 003aaa508 0 -60 0 60 120 180 Fig. 13. Gate charge waveform definitions Tj(°C) Fig. 12. Normalized drain-source on-state resistance factor as a function of junction temperature 10 003aal066 104 003aal067 VVGGSS CC ((VV)) ((ppFF)) 8 6 CCiissss VVDDSS == 1144 VV 103 3322 VV 4 2 CCoossss 0 102 CCrrssss 0 5 10 15 20 25 30 10-1 1 10 102 QG (nC) VDS (V) Fig. 14. Gate-source voltage as a function of gate Fig. 15. Input, output and reverse transfer capacitances charge; typical values as a function of drain-source voltage; typical values BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 8 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 003aal068 40 IISS ((AA)) 32 24 16 8 117755°°CC TTjj == 2255°°CC 0 0 0.2 0.4 0.6 0.8 1 1.2 VSD (V) Fig. 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 9 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 11. Package outline Plastic single ended surface mounted package (LFPAK56D); 8 leads SOT1205 E A A b1 c1 L1 mounting base D1 D D2 H L 1 2 3 4 b X e w A c E1 (8x) E2 A1 C θ detail X Lp y C 0 2.5 5 mm scale Dimensions Unit A A1 b b1 c c1 D(1) D1(1) (Dre2f) E(1) E1(1) E2 e H L L1 Lp w y θ max 1.05 0.1 0.50 4.4 0.25 0.30 4.70 4.8 5.30 1.8 0.85 6.2 1.3 0.55 0.85 8° mm nom 3.5 1.27 0.25 0.1 min 0.0 0.35 4.1 0.19 0.24 4.45 4.95 1.6 5.9 0.8 0.30 0.40 0° Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. sot1205_po Outline References European Issue date version IEC JEDEC JEITA projection 13-02-19 SOT1205 13-02-21 Fig. 17. Package outline LFPAK56D (SOT1205) BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 10 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - 12. 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Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 12 / 13

Nexperia BUK9K8R7-40E Dual N-channel 40 V, 9.4 mΩ logic level MOSFET 13. Contents 1 General description ...............................................1 2 Features and benefits ............................................1 3 Applications ...........................................................1 4 Quick reference data .............................................1 5 Pinning information ...............................................2 6 Ordering information .............................................2 7 Marking ...................................................................2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics .......................................................5 11 Package outline ...................................................10 12 Legal information .................................................11 12.1 Data sheet status ...............................................11 12.2 Definitions ...........................................................11 12.3 Disclaimers .........................................................11 12.4 Trademarks ........................................................12 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 10 December 2013 BUK9K8R7-40E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 10 December 2013 13 / 13