Dual 3 MHz, 1200 mA Buck Regulators with One 300 mA LDO Data Sheet ADP5024 FEATURES a predefined threshold. When the load current falls below a pre- defined threshold, the regulator operates in power save mode Main input voltage range: 2.3 V to 5.5 V (PSM), improving the light load efficiency. Two 1200 mA buck regulators and one 300 mA LDO 24-lead, 4 mm × 4 mm LFCSP package Table 1. Family Models Regulator accuracy: ±1.8% Maximum Factory programmable or external adjustable VOUTx Model Channels Current Package 3 MHz buck operation with forced PWM and automatic ADP5023 2 Buck, 1 LDO 800 mA, LFCSP (CP-24-10) PWM/PSM modes 300 mA BUCK1/BUCK2: output voltage range from 0.8 V to 3.8 V ADP5024 2 Buck, 1 LDO 1.2 A, LFCSP (CP-24-10) 300 mA LDO: output voltage range from 0.8 V to 5.2 V ADP5034 2 Buck, 2 LDOs 1.2 A, LFCSP (CP-24-10), LDO: input supply voltage from 1.7 V to 5.5 V 300 mA TSSOP (RE-28-1) LDO: high PSRR and low output noise ADP5037 2 Buck, 2 LDOs 800 mA, LFCSP (CP-24-10) 300 mA APPLICATIONS ADP5033 2 Buck, 2 LDOs 800 mA, WLCSP (CB-16-8) Power for processors, ASICS, FPGAs, and RF chipsets with 2 EN pins 300 mA Portable instrumentation and medical devices The two bucks operate out of phase to reduce the input capacitor Space constrained devices requirement. The low quiescent current, low dropout voltage, and wide input voltage range of the LDO extends the battery life of GENERAL DESCRIPTION portable devices. The ADP5024 LDO maintains power supply The ADP5024 combines two high performance buck regula- rejection greater than 60 dB for frequencies as high as 10 kHz tors and one low dropout (LDO) regulator in a small, 24-lead, while operating with a low headroom voltage. 4 mm × 4 mm LFCSP to meet demanding performance and Regulators in the ADP5024 are activated though dedicated board space requirements. enable pins. The default output voltages can be either externally The high switching frequency of the buck regulators enables tiny set in the adjustable version or factory programmable to a wide multilayer external components and minimizes the board space. range of preset values in the fixed voltage version. When the MODE pin is set high, the buck regulators operate in forced PWM mode. When the MODE pin is set low, the buck regulators operate in PWM mode when the load current is above TYPICAL APPLICATION CIRCUIT AVIN HOUSEKEEPING C0.A1VµIFN VOUT1 2.3V TO VIN1 SW1 L1 1µH VOUT1 AT 5.5V 4.7CµF1 BUCK1 FB1 R1 1200mA C5 OFF ON EN1 EN1 MODE PGND1 R2 PWM 10µF MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH C2 SW2 VOUT2 AT 4.7µF BUCK2 FB2 R3 1200mA ON EN2 EN2 PGND2 R4 C106µF OFF 1.7V TO VEINN33 EN3(ANLADLOOG) FVBO3UT3 R5 C7 V30O0UmT3A AT 5.5V C3 R6 1µF 1µF ADP5AG02ND4 09888-001 Figure 1. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com

ADP5024 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Theory of Operation................................................................ 16 Applications...............................................................................1 Power Management Unit ..................................................... 17 General Description ..................................................................1 BUCK1 and BUCK2 ............................................................ 19 Typical Application Circuit........................................................1 LDO..................................................................................... 20 Revision History ........................................................................2 Applications Information ........................................................ 21 Specifications .............................................................................3 Buck External Component Selection ................................... 21 General Specifications............................................................3 LDO External Component Selection ................................... 23 BUCK1 and BUCK2 Specifications........................................4 Power Dissipation and Thermal Considerations ..................... 24 LDO Specifications ................................................................5 Buck Regulator Power Dissipation....................................... 24 Input and Output Capacitor, Recommended Specifications ..6 Junction Temperature .......................................................... 25 Absolute Maximum Ratings ......................................................7 PCB Layout Guidelines............................................................ 26 Thermal Resistance ................................................................7 Typical Application Schematics ............................................... 27 ESD Caution ..........................................................................7 Bill of Materials.................................................................... 27 Pin Configuration and Function Descriptions...........................8 Outline Dimensions ................................................................ 28 Typical Performance Characteristics .........................................9 Ordering Guide ................................................................... 28 REVISION HISTORY 5/13—Rev. D to Rev. E Changes to Figure 6, Figure 7 and Figure 8................................ 9 Changes to Figure 30 and Figure 31 ........................................ 13 Added Table 1; Renumbered Sequentially .................................1 Changes to Figure 34 ............................................................... 14 Changes to Figure 1 ...................................................................1 Change to Figure 38 ................................................................ 14 Changes to NC Pin Description.................................................8 Changes to Undervoltage Lockout Section .............................. 17 Changes to Figure 48 ...............................................................20 Changes to Buck Regulator Power Dissipation Section ........... 24 Changes to Figure 50 ...............................................................22 Changes to Figure 52 and Figure 53.........................................27 1/12—Rev. 0 to Rev. A 1/13—Rev. C to Rev. D Changes to Features Section and Figure 1 ................................. 1 Changes to Table 2..................................................................... 4 Changes to Figure 9 .................................................................10 Changes to Table 3..................................................................... 5 Changes to Ordering Guide .....................................................28 Changes to Table 4..................................................................... 6 12/12—Rev. B to Rev. C Changes to Table 7..................................................................... 8 Changes to Ordering Guide .....................................................28 Changes to Figure 34 ............................................................... 14 11/12—Rev. A to Rev. B Changes to LDO Section and Figure 48................................... 20 Changes to Table 9 and Figure 50 ............................................ 22 Changes to Features Section ......................................................1 Changes to Buck Regulator Power Dissipation Section ........... 24 Changes to Output Voltage Accuracy and Voltage Feedback Changes to Figure 52 and Figure 53 ........................................ 27 Parameters, Table 2 ....................................................................4 8/11—Revision 0: Initial Version Changes to Output Voltage Accuracy and Voltage Feedback Parameters, Table 3 ....................................................................5 Rev. E | Page 2 of 28

Data Sheet ADP5024 SPECIFICATIONS GENERAL SPECIFICATIONS V = V = V = 2.3 V to 5.5 V; V = 1.7 V to 5.5 V; T = −40°C to +125°C for minimum/maximum specifications, and T = 25°C for AVIN IN1 IN2 IN3 J A typical specifications, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V , V , V 2.3 5.5 V AVIN IN1 IN2 THERMAL SHUTDOWN Threshold TS T rising 150 °C SD J Hysteresis TS 20 °C SD-HYS START-UP TIME1 BUCK1, LDO t 250 µs START1 BUCK2 t 300 µs START2 EN1, EN2, EN3, MODE INPUTS Input Logic High V 1.1 V IH Input Logic Low V 0.4 V IL Input Leakage Current V 0.05 1 µA I-LEAKAGE INPUT CURRENT All Channels Enabled I No load, no buck switching 108 175 µA STBY-NOSW All Channels Disabled I T = −40°C to +85°C 0.3 1 µA SHUTDOWN J VIN1 UNDERVOLTAGE LOCKOUT High UVLO Input Voltage Rising UVLO 3.9 V VIN1RISE High UVLO Input Voltage Falling UVLO 3.1 V VIN1FALL Low UVLO Input Voltage Rising UVLO 2.275 V VIN1RISE Low UVLO Input Voltage Falling UVLO 1.95 V VIN1FALL 1 Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to VAVIN to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal levels. Start-up times are shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information. Rev. E | Page 3 of 28

ADP5024 Data Sheet BUCK1 AND BUCK2 SPECIFICATIONS V = V = V = 2.3 V to 5.5 V; T = −40°C to +125°C for minimum/maximum specifications, and T = 25°C for typical AVIN IN1 IN2 J A specifications, unless otherwise noted.1 Table 3. Parameter Symbol Test Conditions/Comments Min Typ Max Unit OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔV /V , I = I = 0 mA −1.8 +1.8 % OUT1 OUT1 LOAD1 LOAD2 ΔV /V OUT2 OUT2 Line Regulation (ΔV /V )/ΔV , PWM mode −0.05 %/V OUT1 OUT1 IN1 (ΔV /V )/ΔV OUT2 OUT2 IN2 Load Regulation (ΔV /V )/ΔI , I = 0 mA to 1200 mA, PWM mode −0.1 %/A OUT1 OUT1 OUT1 LOAD (ΔV /V )/ΔI OUT2 OUT2 OUT2 VOLTAGE FEEDBACK V , V Models with adjustable outputs 0.491 0.5 0.509 V FB1 FB2 OPERATING SUPPLY CURRENT MODE = ground BUCK1 Only I I = 0 mA, device not switching, all other 44 μA IN LOAD1 channels disabled BUCK2 Only I I = 0 mA, device not switching, all other 55 μA IN LOAD2 channels disabled BUCK1 and BUCK2 I I = I = 0 mA, device not switching, LDO 67 μA IN LOAD1 LOAD2 channels disabled PSM CURRENT THRESHOLD I PSM to PWM operation 100 mA PSM SW CHARACTERISTICS SW On Resistance R V = V = 3.6 V 155 240 mΩ NFET IN1 IN2 R V = V = 3.6 V 205 310 mΩ PFET IN1 IN2 R V = V = 5.5 V 137 204 mΩ NFET IN1 IN2 R V = V = 5.5 V 162 243 mΩ PFET IN1 IN2 Current Limit I , I PFET switch peak current limit 1600 1950 2300 mA LIMIT1 LIMIT2 ACTIVE PULL-DOWN R Channel disabled 75 Ω PDWN-B OSCILLATOR FREQUENCY f 2.5 3.0 3.5 MHz SW 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Rev. E | Page 4 of 28

Data Sheet ADP5024 LDO SPECIFICATIONS V = (V + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; C = C = 1 µF; T = −40°C to +125°C for minimum/maximum IN3 OUT3 IN OUT J specifications, and T = 25°C for typical specifications, unless otherwise noted.1 A Table 4. Parameter Symbol Test Conditions/Comments Min Typ Max Unit INPUT VOLTAGE RANGE V 1.7 5.5 V IN3 OPERATING SUPPLY CURRENT Bias Current per LDO2 I I = 0 µA 10 30 µA VIN3BIAS OUT3 I = 10 mA 60 100 µA OUT3 I = 300 mA 165 245 µA OUT3 Total System Input Current I Includes all current into AVIN, VIN1, IN VIN2, and VIN3 LDO Only I = 0 µA, all other channels 53 µA OUT3 disabled OUTPUT CHARACTERISTICS Output Voltage Accuracy ΔV /V 100 µA < I < 300 mA −1.8 +1.8 % OUT3 OUT3 OUT3 Line Regulation (ΔV /V )/ΔV I = 1 mA −0.03 +0.03 %/V OUT3 OUT3 IN3 OUT3 Load Regulation3 (ΔV /V )/ΔI I = 1 mA to 300 mA 0.001 0.003 %/mA OUT3 OUT3 OUT3 OUT3 VOLTAGE FEEDBACK V 0.491 0.5 0.509 V FB3 DROPOUT VOLTAGE4 V V = 5.2 V, I = 300 mA 50 mV DROPOUT OUT3 OUT3 V = 3.3 V, I = 300 mA 75 140 OUT3 OUT3 V = 2.5 V, I = 300 mA 100 mV OUT3 OUT3 V = 1.8 V, I = 300 mA 180 mV OUT3 OUT3 CURRENT-LIMIT THRESHOLD5 I 335 600 mA LIMIT3 ACTIVE PULL-DOWN R Channel disabled 600 Ω PDWN-L OUTPUT NOISE Regulator LDO NOISE 10 Hz to 100 kHz, V = 5 V, V = 2.8 V 100 µV rms LDO IN3 OUT3 POWER SUPPLY REJECTION PSRR RATIO Regulator LDO 10 kHz, V = 3.3 V, V = 2.8 V, 60 dB IN3 OUT3 I = 1 mA OUT3 100 kHz, V = 3.3 V, V = 2.8 V, 62 dB IN3 OUT3 I = 1 mA OUT3 1 MHz, V = 3.3 V, V = 2.8 V, 63 dB IN3 OUT3 I = 1 mA OUT3 1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). 2 This is the input current into VIN3, which is not delivered to the output load. 3 Based on an endpoint calculation using 1 mA and 300 mA loads. 4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages above 1.7 V. 5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V. Rev. E | Page 5 of 28

ADP5024 Data Sheet INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS T = −40°C to +125°C, unless otherwise specified. A Table 5. Parameter Symbol Min Typ Max Unit NOMINAL INPUT AND OUTPUT CAPACITOR RATINGS BUCK1, BUCK2 Input Capacitor Ratings C , C 4.7 40 µF MIN1 MIN2 BUCK1, BUCK2 Output Capacitor Ratings C , C 10 40 µF MIN1 MIN2 LDO1 Input and Output Capacitor Ratings C , C 1.0 µF MIN3 MIN4 CAPACITOR ESR R 0.001 1 Ω ESR 1 The minimum input and output capacitance should be greater than 0.70 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R- and X5R-type capacitors are recommended; Y5V and Z5U capacitors are not recommended for use because of their poor temperature and dc bias characteristics. Rev. E | Page 6 of 28

Data Sheet ADP5024 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter Rating θ is specified for the worst-case conditions, that is, a device JA AVIN to AGND −0.3 V to +6 V soldered in a circuit board for surface-mount packages. VIN1, VIN2 to AVIN −0.3 V to +0.3 V Table 7. Thermal Resistance PGND1, PGND2 to AGND −0.3 V to +0.3 V Package Type θ θ Unit VIN3, VOUT1, VOUT2, FB1, FB2, FB3, −0.3 V to (AVIN + 0.3 V) JA JC EN1, EN2, EN3, MODE to AGND 24-Lead, 0.5 mm pitch LFCSP 35 3 °C/W VOUT3 to AGND −0.3 V to (VIN3 + 0.3 V) SW1 to PGND1 −0.3 V to (VIN1 + 0.3 V) ESD CAUTION SW2 to PGND2 −0.3 V to (VIN2 + 0.3 V) Storage Temperature Range −65°C to +150°C Operating Junction Temperature −40°C to +125°C Range Soldering Conditions JEDEC J-STD-020 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. For detailed information on power dissipation, see the Power Dissipation and Thermal Considerations section. Rev. E | Page 7 of 28

ADP5024 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS D D 3T NGA NGA 3NE 3NIV UOV 3BF 42 32 22 12 02 91 AGND1 18AGND AGND2 17AVIN VIN23 ADP5024 16VIN1 SW24 TOP VIEW 15SW1 PGND25 14PGND1 NC6 13MODE 7 8 9 0 1 2 1 1 1 2 2 2 1 1 1 N B T T B N E F U U F E O O V V NOTES 12 .. NIBTCE I S=S ORNELODCTEO IRNMETMDEE RTNNODA ETLDHL EYT HGCAORTON TNUHENECD T EPEXLDPA.ONSEE.D PAD 09888-002 Figure 2. Pin Configuration—View from Top of the Die Table 8. Pin Function Descriptions Pin No. Mnemonic Description 1 AGND Analog Ground. 2 AGND Analog Ground. 3 VIN2 BUCK2 Input Supply (2.3 V to 5.5 V). Connect VIN2 to VIN1 and AVIN. 4 SW2 BUCK2 Switching Node. 5 PGND2 Dedicated Power Ground for BUCK2. 6 NC No Connect. Leave this pin unconnected or connect to ground. 7 EN2 BUCK2 Enable Pin. High level turns on this regulator, and low level turns it off. 8 FB2 BUCK2 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK2 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 9 VOUT2 BUCK2 Output Voltage Sensing Input. Connect VOUT2 to the top of the capacitor on VOUT2. 10 VOUT1 BUCK1 Output Voltage Sensing Input. Connect VOUT1 to the top of the capacitor on VOUT1. 11 FB1 BUCK1 Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the BUCK1 resistor divider. For device models with a fixed output voltage, leave this pin unconnected. 12 EN1 BUCK1 Enable Pin. High level turns on this regulator, and low level turns it off. 13 MODE BUCK1/BUCK2 Operating Mode. MODE = high for forced PWM operation. MODE = low for automatic PWM/PSM operation. 14 PGND1 Dedicated Power Ground for BUCK1. 15 SW1 BUCK1 Switching Node. 16 VIN1 BUCK1 Input Supply (2.3 V to 5.5 V). Connect VIN1 to VIN2 and AVIN. 17 AVIN Analog Input Supply (2.3 V to 5.5 V). Connect AVIN to VIN1 and VIN2. 18 AGND Analog Ground. 19 FB3 LDO Feedback Input. For device models with an adjustable output voltage, connect this pin to the middle of the LDO resistor divider. For device models with a fixed output voltage, connect this pin to the top of the capacitor on VOUT3. 20 VOUT3 LDO Output Voltage. 21 VIN3 LDO Input Supply (1.7 V to 5.5 V). 22 EN3 LDO Enable Pin. High level turns on this regulator, and low level turns it off. 23 AGND Analog Ground. 24 AGND Analog Ground. EPAD (EP) Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane. Rev. E | Page 8 of 28

Data Sheet ADP5024 TYPICAL PERFORMANCE CHARACTERISTICS V = V = V = 3.6 V, T = 25°C, unless otherwise noted. IN1 IN2 IN3 A 3.310 140 –40°C +25°C 3.305 +85°C 120 µA) 3.300 NT ( 100 RE 3.295 ENT CUR 6800 V (V)OUT3.290 C S 3.285 E QUI 40 3.280 20 3.275 02.3 2.8 3.3INPUT 3V.O8LTAGE4 (.V3) 4.8 5.3 09888-003 3.2700 0.1 0.2 0.3 0.4 0.5IOU0T.6 (A)0.7 0.8 0.9 1.0 1.1 1.2 09888-006 Figure 3. System Quiescent Current vs. Input Voltage, VOUT1 = 3.3 V, Figure 6. BUCK1 Load Regulation Across Temperature ,VIN = 4.2 V, VOUT2 = 1.8 V, VOUT3 = 1.2 V, All Channels Unloaded VOUT1 = 3.3 V, PWM Mode 1.812 T –40°C +25°C +85°C 1.810 SW 4 1.808 IOUT 2 V)1.806 ( UT O VOUT V1.804 1 EN 1.802 3 1.800 CCHH3125..0000VV BBWW CCHH4255.00.00VmAΩBBWW MT4101..02µ0s% ACH3 2.2V 09888-004 1.7980 0.1 0.2 0.3 0.4 0.5IOU0T.6(A)0.7 0.8 0.9 1 1.1 1.2 09888-007 Figure 4. BUCK1 Startup, VOUT1 = 1.8 V, IOUT1 = 5 mA Figure 7. BUCK2 Load Regulation Across Temperature, VIN = 3.6 V, VOUT2 = 1.8 V, PWM Mode T 0.808 –40°C +25°C +85°C SW 0.807 4 2 IOUT 0.806 V) (UT0.805 O VOUT V 1 0.804 EN 0.803 3 CCHH31 25..0000VV BBWW CCHH42 55.00.00VmA Ω BBWW MT 4101..02µ0s% A CH3 2.2V 09888-005 0.8020 0.1 0.2 0.3 0.4 0.5IOU0T.6 (A)0.7 0.8 0.9 1 1.1 1.2 09888-008 Figure 5. BUCK2 Startup, VOUT2 = 3.3 V, IOUT2 = 10 mA Figure 8. BUCK1 Load Regulation Across Temperature, VIN = 3.6 V, VOUT1 = 0.8 V, PWM Mode Rev. E | Page 9 of 28

ADP5024 Data Sheet 100 100 VIN = 3.9V 90 90 VIN = 3.6V 80 VIN = 4.2V 80 VIN = 2.3V 70 VIN = 5.5V 70 %) %) VIN = 5.5V Y ( 60 Y ( 60 C C EN 50 EN 50 VIN = 4.2V CI CI FFI 40 FFI 40 E E 30 30 20 20 10 10 0 0 0.001 0.01 IOUT (A) 0.1 1 09888-009 0.001 0.01 IOUT (A) 0.1 1 09888-012 Figure 9. BUCK1 Efficiency vs. Load Current, Across Input Voltage, Figure 12. BUCK2 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, Automatic Mode VOUT2 = 1.8 V, PWM Mode 100 100 90 90 80 80 VIN = 5.5V 70 70 %) VIN = 3.9V %) ENCY ( 5600 ENCY( 5600 VIN = 4.2V VIN = 5.5V VIN = 2.3V CI CI VIN = 3.6V FFI 40 FFI 40 E E 30 30 20 20 10 VIN = 4.2V 10 00.001 0.01 IOUT (A) 0.1 1 09888-010 00.001 0.01 IOUT (A) 0.1 1 09888-013 Figure 10. BUCK1 Efficiency vs. Load Current, Across Input Voltage, Figure 13. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT1 = 3.3 V, PWM Mode VOUT1 = 0.8 V, Automatic Mode 100 100 90 90 VIN = 3.6V 80 80 70 VIN = 2.3V 70 VIN = 2.3V %) VIN = 4.2V VIN = 5.5V %) EFFICIENCY ( 456000 VIN = 3.6V EFFICIENCY ( 456000 VIN = 4.2VVIN = 5.5V 30 30 20 20 10 10 00.001 0.01 IOUT (A) 0.1 1 09888-011 00.001 0.01 IOUT (A) 0.1 1 09888-014 Figure 11. BUCK2 Efficiency vs. Load Current, Across Input Voltage, Figure 14. BUCK1 Efficiency vs. Load Current, Across Input Voltage, VOUT2 = 1.8 V, Automatic Mode VOUT1 = 0.8 V, PWM Mode Rev. E | Page 10 of 28

Data Sheet ADP5024 100 3.3 +25°C –40°C 90 3.2 +25°C 80 +85°C –40°C Hz) 3.1 70 M CY (%) 60 ENCY ( 3.0 +85°C EN 50 QU 2.9 EFFICI 40 PE FRE 2.8 30 CO S 2.7 20 2.6 10 00.001 0.01 IOUT (A) 0.1 1 09888-015 2.50 0.2 0.4 IOU0T. 6(A) 0.8 1.0 1.2 09888-018 Figure 15. BUCK1 Efficiency vs. Load Current, Across Temperature, Figure 18. BUCK2 Switching Frequency vs. Output Current, Across VIN = 3.9 V, VOUT1 = 3.3 V, Automatic Mode Temperature, VOUT2 = 1.8 V, PWM Mode 100 T 90 +25°C +85°C VOUT 80 1 70 %) –40°C ISW Y ( 60 C EN 50 2 CI FFI 40 SW E 30 20 10 4 00.001 0.01 IOUT (A) 0.1 1 09888-016 CH1 50mV CCHH42 520.000mVA Ω MT 42.80.04µ0s% A CH2 240mA 09888-019 Figure 16. BUCK2 Efficiency vs. Load Current, Across Temperature, Figure 19. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, Automatic Mode VOUT2 = 1.8 V, Automatic Mode 100 T +25°C 90 VOUT 80 1 70 +85°C %) –40°C Y ( 60 ISW C EN 50 2 CI FFI 40 E 30 SW 20 10 4 00.001 0.01 IOUT (A) 0.1 1 09888-017 CH1 50mV BW CCHH42 520.000mVA Ω BW MT 42.80.04µ0s% A CH2 220mA 09888-020 Figure 17. BUCK1 Efficiency vs. Load Current, Across Temperature, Figure 20. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, Automatic Mode VOUT1 = 0.8 V, Automatic Mode Rev. E | Page 11 of 28

ADP5024 Data Sheet T T VOUT 1 VIN ISW VOUT 2 1 SW SW 43 4 CH1 50mV BW CCHH42 520.000mVA Ω BW MT 42080.4n0s% A CH2 220mA 09888-021 CCHH13 510.0.00mVV BBWWCH4 2.00V BW MT 13.00.04m0%s A CH3 4.80V 09888-024 Figure 21. Typical Waveforms, VOUT1 = 3.3 V, IOUT1 = 30 mA, PWM Mode Figure 24. Buck2 Response to Line Transient, VIN = 4.5 V to 5.0 V, VOUT2 = 1.8 V, PWM Mode T T SW VOUT 1 4 ISW VOUT 2 1 SW IOUT 2 4 CH1 50mV BW CCHH42 520.000mVA Ω BW MT 42080.4n0s% A CH2 220mA 09888-022 CH1 50.0mV BWCCHH42 55.00.00VmA ΩBBWW MT 2600..00µ0s0µsA CH2 356mA 09888-025 Figure 22. Typical Waveforms, VOUT2 = 1.8 V, IOUT2 = 30 mA, PWM Mode Figure 25. BUCK1 Response to Load Transient, IOUT1 from 1 mA to 50 mA, VOUT1 = 3.3 V, Automatic Mode T T SW VIN 4 VOUT VOUT 1 1 SW IOUT 3 2 CCHH13 510.0.00mVV BBWWCH4 2.00V BW MT 13.00.04m0%s A CH3 4.80V 09888-023 CH1 50.0mV BWCCHH42 55.00.00VmA ΩBBWW MT 2202..02µ0s%A CH2 379mA 09888-026 Figure 23. BUCK1 Response to Line Transient, Input Voltage from 4.5 V to Figure 26. BUCK2 Response to Load Transient, IOUT2 from 1 mA to 50 mA, 5.0 V, VOUT1 = 3.3 V, PWM Mode VOUT2 = 1.8 V, Automatic Mode Rev. E | Page 12 of 28

Data Sheet ADP5024 T SW EN 4 2 VOUT 1 VOUT IOUT 3 2 IIN 1 CH1 50.0mV BWCCHH42 52.0000mVA Ω BBWW MT 2200..04µ0s%A CH2 408mA 09888-027 CCHH13 1 10V0mA CH25V MT 4 0 µ s 159.4µs 21.M5 GPSo/isntsA CH2 4.20V 09888-030 Figure 27. BUCK1 Response to Load Transient, IOUT1 from 20 mA to 180 mA, Figure 30. LDO Startup, VOUT3 = 1.8 V VOUT1 = 3.3 V, Automatic Mode 3.304 T VIN = 3.8V SW 3.303 VVIINN == 45..25VV 3.302 4 3.301 3.300 VOUT V) 1 (UT 3.299 O V 3.298 IOUT 3.297 3.296 2 3.295 CH1 100mV BW CCHH42 250.000mVA Ω BBWW MT 2109..02µ0s%A CH2 88.0mA 09888-028 3.2940 0.1 IOUT (A) 0.2 0.3 09888-031 Figure 28. BUCK2 Response to Load Transient, IOUT2 from 20 mA to 180 mA, Figure 31. LDO Load Regulation Across Input Voltage, VOUT3 = 3.3 V VOUT2 = 1.8 V, Automatic Mode T 400 VOUT2 350 2 300 SW1 +125°C Ω) 250 +25°C m 3 (ON200 S VOUT1 RD 150 –40°C 1 SW2 100 50 4 CCHH31 55..0000VV BBWW CCHH42 55..0000VV BBWW MT 45000.0n0s% A CH4 1.90V 09888-029 02.3 2.8 3.3INPUT 3V.O8LTAGE4 (.V3) 4.8 5.3 09888-032 Figure 29. VOUTx and SW Waveforms for BUCK1 and BUCK2 in PWM Mode Figure 32. NMOS RDSON vs. Input Voltage Across Temperature Showing Out-of-Phase Operation Rev. E | Page 13 of 28

ADP5024 Data Sheet 250 50 45 200 40 +125°C +25°C A) µ 35 T ( mΩ) 150 REN 30 DS (ON –40°C D CUR 25 R 100 N 20 U O R 15 G 50 10 5 02.3 2.8 3.3 INPU3T.8 VOLTA4G.E3 (V) 4.8 5.3 09888-033 00 0.05 0.L10OAD CU0R.1R5ENT (A)0.20 0.25 09888-036 Figure 33. PMOS RDSON vs. Input Voltage Across Temperature Figure 36. LDO Ground Current vs. Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V 1.802 –40°C T +25°C 1.801 +85°C 1.800 IOUT 1.799 2 1.798 V) (UT1.797 O V1.796 1 VOUT 1.795 1.794 1.793 1.7920 0.1 IOUT (A) 0.2 0.3 09888-034 CH1 100mV BW CH2 100mA Ω BW MT 4109..02µ0s%A CH2 52.0mA 09888-037 Figure 34. LDO Load Regulation Across Temperature, VIN3 = 3.6 V, VOUT3 = 1.8 V Figure 37. LDO Response to Load Transient, IOUT3 from 1 mA to 80 mA, VOUT3 = 2.8 V 3.0 IOUT = 10mA IOUT = 100µA T 2.5 IOUT = 1mA IOUT = 100mA IOUT = 150mA VIN 2.0 IOUT = 300mA V) ( UT1.5 O VOUT V 21 1.0 0.5 3 02.4 2.6 2.8 3.0 3.2 3.4 3.6 3.V8IN4 (.0V)4.2 4.4 4.6 4.8 5.0 5.2 5.4 09888-035 CCHH13 210.0.00mVV MT 12080.4µ0s% A CH3 4.80V 09888-038 Figure 35. LDO Line Regulation Across Output Load, VOUT3 = 2.8 V Figure 38. LDO Response to Line Transient, Input Voltage from 4.5 V to 5 V, VOUT3 = 2.8 V Rev. E | Page 14 of 28

Data Sheet ADP5024 60 0 VIN = 5V 55 –20 VIN = 3.3V 50 V) –40 OISE (µ 45 R (dB) –60 S N 40 PSR M R –80 35 100µA 1mA 10mA 30 –100 50mA 100mA 150mA 205.001 0.01 0.1 ILOAD1 (mA) 10 100 09888-039 –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09888-042 Figure 39. LDO Output Noise vs. Load Current, Across Input Voltage, Figure 42. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 3.0 V VOUT3 = 2.8 V 65 0 100µA 60 VIN = 5V 11m0mAA –20 55 VIN = 3.3V 5100m0mAA 150mA µV) 50 –40 OISE ( 45 R (dB) –60 N R MS 40 PS R –80 35 –100 30 205.001 0.01 0.1 ILOAD1 (mA) 10 100 09888-040 –12010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09888-043 Figure 40. LDO Output Noise vs. Load Current, Across Input Voltage, Figure 43. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 2.8 V VOUT3 = 3.0 V 0 0 100µA 100µA –10 1mA –10 1mA 10mA 10mA –20 50mA –20 50mA 100mA 100mA –30 150mA –30 150mA B) –40 B) –40 d d R ( –50 R ( –50 R R S S P –60 P –60 –70 –70 –80 –80 –90 –90 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09888-041 –10010 100 1kFREQU1E0NkCY (Hz)100k 1M 10M 09888-044 Figure 41. LDO PSRR Across Output Load, VIN3 = 3.3 V, VOUT3 = 2.8 V Figure 44. LDO PSRR Across Output Load, VIN3 = 5.0 V, VOUT3 = 3.0 V Rev. E | Page 15 of 28

ADP5024 Data Sheet THEORY OF OPERATION VOUT1FB1FB2VOUT2 AVIN GM ERROR ENBK1 75Ω 75Ω ENBK2 GM ERROR AMP AMP PWM PWM COMP COMP VIN1 SOFT START SOFT START VIN2 ILIMIT ILIMIT PSM PSM COMP COMP PWM/ PWM/ PSM PSM LOW CONTROL CONTROL LOW CURRENT BUCK1 BUCK2 CURRENT SW1 SW2 OSCILLATOR DRIVER DRIVER AND AND ANTISHOOT SYSTEM OP ANTISHOOT THROUGH UNDERVOLTAGE MODE THROUGH LOCKOUT SEL MODE2 PGND2 PGND1 STHHUETRDMOAWLN YB A MODE EN1 ENBK1 ENABLE EN2 AND ENBK2 MODE LDO EN3 CONTROL ENLDO UNDERVOLTAGE LOCKOUT R1 LDO AVIN CONTROL R2 600Ω ENLDO ADP5024 VIN3 AGND FB3 VOUT3 09888-045 Figure 45. Functional Block Diagram Rev. E | Page 16 of 28

Data Sheet ADP5024 POWER MANAGEMENT UNIT Thermal Protection The ADP5024 is a micropower management unit (microPMU) In the event that the junction temperature rises above 150°C, combing two step-down (buck) dc-to-dc convertors and one the thermal shutdown circuit turns off all of the regulators. low dropout linear regulator (LDO). The high switching frequency Extreme junction temperatures can be the result of high current and tiny 24-lead LFCSP package allow for a small power manage- operation, poor circuit board design, or high ambient tempera- ment solution. ture. A 20°C hysteresis is included so that when thermal shutdown To combine these high performance regulators into the occurs, the regulators do not return to operation until the on-chip microPMU, there is a system controller allowing them to temperature drops below 130°C. When emerging from thermal operate together. shutdown, all regulators restart with soft start control. The buck regulators can operate in forced PWM mode if the Undervoltage Lockout MODE pin is at a logic level high. In forced PWM mode, the To protect against battery discharge, undervoltage lockout buck switching frequency is always constant and does not (UVLO) circuitry is integrated in the system. If the input change with the load current. If the MODE pin is at logic level voltage on AVIN drops below a typical 2.15 V UVLO threshold, low, the switching regulators operate in automatic PWM/PSM all channels shut down. In the buck channels, both the power mode. In this mode, the regulators operate at a fixed PWM switch and the synchronous rectifier turn off. When the voltage frequency when the load current is above the PSM current on AVIN rises above the UVLO threshold, the part is enabled threshold. When the load current falls below the PSM current once more. threshold, the regulator in question enters PSM, where the Alternatively, the user can select device models with a UVLO switching occurs in bursts. The burst repetition rate is a set at a higher level, suitable for 5 V supply applications. For function of the current load and the output capacitor value. these models, the device reaches the turn off threshold when This operating mode reduces the switching and quiescent the input supply drops to 3.65 V typical. current losses. The automatic PWM/PSM mode transition is controlled independently for each buck regulator. The two In case of a thermal or UVLO event, the active pull-downs (if bucks operate synchronized to each other. factory enabled) are enabled to discharge the output capacitors quickly. The pull-down resistors remain engaged until the thermal The ADP5024 has individual enable pins (EN1 to EN3) that fault event is no longer present or the input supply voltage falls control the activation of each regulator. The regulators are below the V voltage level. The typical value of V is approx- activated by a logic level high applied to the respective EN pin, POR POR imately 1 V. wherein EN1 controls BUCK1, EN2 controls BUCK2, and EN3 controls the LDO. Enable/Shutdown The ADP5024 has an individual control pin for each regulator. Regulator output voltages are set through external resistor dividers or can be optionally factory programmed to default A logic level high applied to the ENx pin activates a regulator whereas a logic level low turns off a regulator. values (see the Ordering Guide section). When a regulator is turned on, the output voltage ramp rate is Figure 46 shows the regulator activation timings for the ADP5024 when all enable pins are connected to AVIN. Also controlled though a soft start circuit to avoid a large inrush shown is the active pull-down activation. current due to the charging of the output capacitors. Rev. E | Page 17 of 28

ADP5024 Data Sheet AVIN VUVLO VPOR VOUT1 VOUT3 30µs 30µs (MIN) (MIN) 50µs (MIN) VOUT2 50µs (MIN) BUCK1, LDO PULL-DOWNS PULL-BDUOCWKN2 09888-046 Figure 46. Regulator Sequencing (EN1 = EN2 = EN3 = VAVIN) Rev. E | Page 18 of 28

Data Sheet ADP5024 BUCK1 AND BUCK2 mode. The output capacitor discharges until the output voltage falls to the PWM regulation voltage, at which point the device The buck uses a fixed frequency and high speed current drives the inductor to make the output voltage rise again to the mode architecture. The buck operates with an input voltage upper threshold. This process is repeated while the load current of 2.3 V to 5.5 V. is below the PSM current threshold. The buck output voltage is set through external resistor The ADP5024 has a dedicated MODE pin controlling the PSM dividers, shown in Figure 47 for BUCK1. The output voltage and PWM operation. A logic level high applied to the MODE can optionally be factory programmed to default values, as pin forces both bucks to operate in PWM mode. A logic level indicated in the Ordering Guide section. In this event, R1 and low sets the bucks to operate in automatic PSM/PWM. R2 are not needed, and FB1 can remain unconnected. In all cases, VOUT1 must be connected to the output capacitor. FB1 is 0.5 V. PSM Current Threshold The PSM current threshold is set to100 mA. The bucks employ VOUT1 VIN1 L1 a scheme that enables this current to remain accurately controlled, 1µH SW1 independent of input and output voltage levels. This scheme VOUT1 also ensures that there is very little hysteresis between the PSM BUCK current threshold for entry to and exit from the PSM. The PSM R1 FB1 C5 current threshold is optimized for excellent efficiency over all 10µF R2 load currents. AGND Oscillator/Phasing of Inductor Switching VOUT1 = VFB1 RR12+ 1 09888-047 The ADP5024 ensures that both bucks operate at the same switching frequency when both bucks are in PWM mode. Figure 47. BUCK1 External Output Voltage Setting Control Scheme Additionally, the ADP5024 ensures that when both bucks are in PWM mode, they operate out of phase, whereby the Buck2 The bucks operate with a fixed frequency, current mode PWM PFET starts conducting exactly half a clock period after the control architecture at medium to high loads for high efficiency, BUCK1 PFET starts conducting. but shift to a power save mode (PSM) control scheme at light Short-Circuit Protection loads to lower the regulation power losses. When operating in fixed frequency PWM mode, the duty cycle of the integrated The bucks include frequency foldback to prevent output current switches is adjusted and regulates the output voltage. When runaway on a hard short. When the voltage at the feedback pin operating in PSM at light loads, the output voltage is controlled falls below half the target output voltage, indicating the possi- in a hysteretic manner, with higher output voltage ripple. During bility of a hard short at the output, the switching frequency is part of this time, the converter is able to stop switching and reduced to half the internal oscillator frequency. The reduction enters an idle mode, which improves conversion efficiency. in the switching frequency allows more time for the inductor to PWM Mode discharge, preventing a runaway of output current. Soft Start In PWM mode, the bucks operate at a fixed frequency of 3 MHz, set by an internal oscillator. At the start of each oscillator cycle, The bucks have an internal soft start function that ramps the the PFET switch is turned on, sending a positive voltage across output voltage in a controlled manner upon startup, thereby the inductor. Current in the inductor increases until the current limiting the inrush current. This prevents possible input voltage sense signal crosses the peak inductor current threshold, which drops when a battery or a high impedance power source is turns off the PFET switch and turns on the nFET synchronous connected to the input of the converter. rectifier. This sends a negative voltage across the inductor, Current Limit causing the inductor current to decrease. The synchronous Each buck has protection circuitry to limit the amount of rectifier stays on for the remainder of the cycle. The buck positive current flowing through the PFET switch and the regulates the output voltage by adjusting the peak inductor amount of negative current flowing through the synchronous current threshold. rectifier. The positive current limit on the power switch limits Power Save Mode (PSM) the amount of current that can flow from the input to the The bucks smoothly transition to PSM operation when the load output. The negative current limit prevents the inductor current decreases below the PSM current threshold. When current from reversing direction and flowing out of the load. either of the bucks enters PSM, an offset is induced in the PWM 100% Duty Operation regulation level, which makes the output voltage rise. When the With a drop in input voltage, or with an increase in load output voltage reaches a level approximately 1.5% above the current, the buck may reach a limit where, even with the PFET PWM regulation level, PWM operation is turned off. At this switch on 100% of the time, the output voltage drops below the point, both power switches are off, and the buck enters an idle Rev. E | Page 19 of 28

ADP5024 Data Sheet desired output voltage. At this limit, the buck transitions to a configurations where the LDO supply voltage is provided from mode where the PFET switch stays on 100% of the time. When one of the buck regulators. the input conditions change again and the required duty cycle The LDO output voltage is set through external resistor dividers, falls, the buck immediately restarts PWM regulation without as shown in Figure 48. The output voltage can optionally be allowing overshoot on the output voltage. factory programmed to default values, as indicated in the Ordering Active Pull-Down Resistors Guide section. In this event, Ra and Rb are not needed, and FB3 All regulators have optional, factory programmable, active pull- must be connected to the top of the capacitor on VOUT3. FB3 is 0.5 V. down resistors discharging the respective output capacitors when the regulators are disabled. The pull-down resistors are VIN3 connected between VOUTx and AGND. Active pull-downs are VOUT3 VOUT3 disabled when the regulators are turned on. The typical value of C7 the pull-down resistor is 600 Ω for the LDO and 75 Ω for each LDO Ra 1µF FB3 buck. Figure 46 shows the activation timings for the active pull- Rb downs during regulator activation and deactivation. LTDheO A DP5024 contains one LDO with low quiescent current VOUT3 = VFB3 RRab+ 1 09888-048 Figure 48. LDO External Output Voltage Setting and low dropout voltage and provides up to 300 mA of output current. Drawing a low 10 μA quiescent current (typical) at no The LDO also provides high power supply rejection ratio load makes the LDO ideal for battery-operated portable (PSRR), low output noise, and excellent line and load transient equipment. response with only a small 1 µF ceramic input and output capacitor. The LDO operates with an input voltage of 1.7 V to 5.5 V. The wide operating range makes the LDO suitable for cascading Rev. E | Page 20 of 28

Data Sheet ADP5024 APPLICATIONS INFORMATION BUCK EXTERNAL COMPONENT SELECTION Ceramic capacitors are manufactured with a variety of dielec- trics, each with a different behavior over temperature and applied Trade-offs between performance parameters such as efficiency voltage. Capacitors must have a dielectric that is adequate to and transient response can be made by varying the choice of ensure the minimum capacitance over the necessary temperature external components in the applications circuit, as shown in range and dc bias conditions. X5R or X7R dielectrics with a Figure 1. voltage rating of 6.3 V or 10 V are recommended for best per- Feedback Resistors formance. Y5V and Z5U dielectrics are not recommended for For the adjustable model, shown in Figure 47, the total use with any dc-to-dc converter because of their poor temperature combined resistance for R1 and R2 is not to exceed 400 kΩ. and dc bias characteristics. Inductor The worst-case capacitance accounting for capacitor variation The high switching frequency of the ADP5024 bucks allows for over temperature, component tolerance, and voltage is calcu- the selection of small chip inductors. For best performance, use lated using the following equation: inductor values between 0.7 μH and 3 μH. Suggested inductors C = C × (1 − TEMPCO) × (1 − TOL) EFF OUT are shown in Table 9. where: The peak-to-peak inductor current ripple is calculated using C is the effective capacitance at the operating voltage. EFF the following equation: TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. V ×(V −V ) I = OUT IN OUT RIPPLE V ×f ×L In this example, the worst-case temperature coefficient IN SW (TEMPCO) over −40°C to +85°C is assumed to be 15% for an where: X5R dielectric. The tolerance of the capacitor (TOL) is assumed f is the switching frequency. SW to be 10%, and C is 9.2 μF at 1.8 V, as shown in Figure 49. OUT L is the inductor value. Substituting these values in the equation yields The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current is CEFF = 9.2 μF × (1 − 0.15) × (1 − 0.1) ≈ 7.0 μF calculated using the following equation: To guarantee the performance of the bucks, it is imperative I that the effects of dc bias, temperature, and tolerances on the IPEAK =ILOAD(MAX)+ RI2PPLE behavior of the capacitors be evaluated for each application. 12 Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc 10 resistance (DCR). Larger sized inductors have smaller DCR, which may decrease inductor conduction losses. Inductor core F) 8 losses are related to the magnetic permeability of the core material. E (µ Because the bucks are high switching frequency dc-to-dc NC A 6 converters, shielded ferrite core material is recommended for CIT A its low core losses and low EMI. P CA 4 Output Capacitor Higher output capacitor values reduce the output voltage ripple 2 and improve load transient response. When choosing this value, iotu istp aulst ov oimltapgoer dtacn bt itaos .a ccount for the loss of capacitance due to 00 1 2DC BIAS V3OLTAGE 4(V) 5 6 09888-049 Figure 49. Capacitance vs. Voltage Characteristic Table 9. Suggested 1.0 μH Inductors Vendor Model Dimensions (mm) I (mA) DCR (mΩ) SAT Murata LQM2MPN1R0NG0B 2.0 × 1.6 × 0.9 1400 85 Murata LQH32PN1R0NN0 3.2 × 2.5 × 1.6 2300 45 Taiyo Yuden CBC3225T1R0MR 3.2 × 2.5 × 2.5 2000 71 Coilcraft XFL4020-102ME 4.0 × 4.0 × 2.1 5400 11 Coilcraft XPL2010-102ML 1.9 × 2.0 × 1.0 1800 89 Toko MDT2520-CN 2.5 × 2.0 × 1.2 1350 85 Rev. E | Page 21 of 28

ADP5024 Data Sheet The peak-to-peak output voltage ripple for the selected output To minimize supply noise, place the input capacitor as close as capacitor and inductor values is calculated using the following possible to the VINx pin of the buck. As with the output capa- equation: citor, a low ESR capacitor is recommended. VRIPPLE =8×fIRIP×PLCE ≈(2π×f V)2IN×L×C Ade 4p.e7n µdFin cga opnac tihtoer a ipsp rleiccaotmionm, ean sdmeadl lfeorr o ar tlyaprgiecra lo auptppulitc caatpioanci;t or SW OUT SW OUT may be chosen. A list of suggested 4.7 µF capacitors is shown in Capacitors with lower equivalent series resistance (ESR) are preferred to guarantee low output voltage ripple, as shown in Table 11. The effective capacitance needed for stability, which the following equation: includes temperature and dc bias effects, is a minimum of 3 µF and a maximum of 10 µF. V ESR ≤ RIPPLE COUT I Table 10. Suggested 10 μF Capacitors RIPPLE Voltage The effective capacitance needed for stability, which includes Case Rating temperature and dc bias effects, is a minimum of 7 µF and a Vendor Type Model Size (V) maximum of 40 µF. Murata X5R GRM188R60J106 0603 6.3 TDK X5R C1608JB0J106K 0603 6.3 The buck regulators require 10 µF output capacitors to guarantee Panasonic X5R ECJ1VB0J106M 0603 6.3 stability and response to rapid load variations and to transition into and out of the PWM/PSM modes. A list of suggested capaci- Table 11. Suggested 4.7 μF Capacitors tors is shown in Table 10. In certain applications where one or Voltage both buck regulator powers a processor, the operating state is Case Rating known because it is controlled by software. In this condition, Vendor Type Model Size (V) the processor can drive the MODE pin according to the operating Murata X5R GRM188R60J475ME19D 0402 6.3 state; consequently, it is possible to reduce the output capacitor Taiyo Yuden X5R JMK107BJ475 0402 6.3 from 10 µF to 4.7 µF because the regulator does not expect a Panasonic X5R ECJ-0EB0J475M 0402 6.3 large load variation when working in PSM mode (see Figure 50). Table 12. Suggested 1.0 μF Capacitors Input Capacitor Voltage Case Rating Higher value input capacitors help to reduce the input voltage Vendor Type Model Size (V) ripple and improve transient response. Maximum input Murata X5R GRM155B30J105K 0402 6.3 capacitor current is calculated using the following equation: TDK X5R C1005JB0J105KT 0402 6.3 V (V −V ) Panasonic X5R ECJ0EB0J105K 0402 6.3 ICIN ≥ILOAD(MAX) OUT VIN OUT Taiyo X5R LMK105BJ105MV-F 0402 10.0 IN Yuden AVIN HOUSEKEEPING CAVIN VOUT1 0.1µF 2.3V TO VIN1 SW1 L1 1µH VOUT1 AT 5.5V 4.7Cµ1F BUCK1 FB1 R1 1200mA C5 OFFON EN1 EN1 MODE PGND1 R2PWM 10µF MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH C2 SW2 VOUT2 AT 4.7µF BUCK2 FB2 R3 1200mA ON EN2 EN2 PGND2 R4 C106µF 1.7V TO OFF VEINN33 EN3(ANLADLOOG) FVBO3UT3 R5 C7 V30O0UmT3A AT 5.5V 1CµF3 ADP502A4GND R6 1µF 09888-050 Figure 50. Processor System Power Management with PSM/PWM Control Rev. E | Page 22 of 28

Data Sheet ADP5024 1.2 LDO EXTERNAL COMPONENT SELECTION Feedback Resistors 1.0 For the adjustable model, the maximum value of Rb must not exceed 200 kΩ (see Figure 48). F)0.8 µ Output Capacitor CE ( N A0.6 The ADP5024 LDO is designed for operation with small, space- CIT A saving ceramic capacitors, but functions with most commonly P CA0.4 used capacitors as long as care is taken with the ESR value. The ESR of the output capacitor affects stability of the LDO control 0.2 loop. A minimum of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended to ensure stability of the ADP5024. Transient rceasppaocnitsaen tcoe .c Uhasningge as ilnar lgoeard v caulurere onft o ius taplsuot acfafpeaccteitda nbcye o iumtppurto ves 00 1 D2C BIAS VO3LTAGE (V4) 5 6 09888-051 Figure 51. Capacitance vs. Voltage Characteristic the transient response of the ADP5024 to large changes in load current. Use the following equation to determine the worst-case capa- citance accounting for capacitor variation over temperature, Input Bypass Capacitor component tolerance, and voltage. Connecting a 1 µF capacitor from VIN3 to ground reduces the C = C × (1 − TEMPCO) × (1 − TOL) EFF BIAS circuit sensitivity to printed circuit board (PCB) layout, especially when encountering long input traces or high source impedance. where: If greater than 1 µF of output capacitance is required, increase CBIAS is the effective capacitance at the operating voltage. the input capacitor to match it. TEMPCO is the worst-case capacitor temperature coefficient. TOL is the worst-case component tolerance. Input and Output Capacitor Properties In this example, the worst-case temperature coefficient Use any good quality ceramic capacitors with the ADP5024 (TEMPCO) over −40°C to +85°C is assumed to be 15% for an as long as they meet the minimum capacitance and maximum X5R dielectric. The tolerance of the capacitor (TOL) is assumed ESR requirements. Ceramic capacitors are manufactured with a to be 10%, and C is 0.85 μF at 1.8 V, as shown in Figure 51. variety of dielectrics, each with a different behavior over temper- BIAS ature and applied voltage. Capacitors must have a dielectric that Substituting these values into the following equation yields: is adequate to ensure the minimum capacitance over the necessary C = 0.85 μF × (1 − 0.15) × (1 − 0.1) = 0.65 μF EFF temperature range and dc bias conditions. X5R or X7R dielectrics Therefore, the capacitor chosen in this example meets the with a voltage rating of 6.3 V or 10 V are recommended for best minimum capacitance requirement of the LDO over performance. Y5V and Z5U dielectrics are not recommended temperature and tolerance at the chosen output voltage. for use with any LDO because of their poor temperature and dc bias characteristics. To guarantee the performance of the ADP5024, it is imperative that the effects of dc bias, temperature, and tolerances on the Figure 51 depicts the capacitance vs. voltage bias characteristic behavior of the capacitors be evaluated for each application. of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is about ±15% over the −40°C to +85°C tempera- ture range and is not a function of package or voltage rating. Rev. E | Page 23 of 28

ADP5024 Data Sheet POWER DISSIPATION AND THERMAL CONSIDERATIONS The ADP5024 is a highly efficient micropower management BUCK REGULATOR POWER DISSIPATION unit (microPMU), and, in most cases, the power dissipated in The power loss of the buck regulator is approximated by the device is not a concern. However, if the device operates at P = P + P (3) high ambient temperatures and maximum loading condition, LOSS DBUCK L the junction temperature can reach the maximum allowable where: operating limit (125°C). P is the power dissipation on one of the ADP5024 buck DBUCK regulators. When the temperature exceeds 150°C, the ADP5024 turns off P is the inductor power loss. all of the regulators allowing the device to cool down. When the L die temperature falls below 130°C, the ADP5024 resumes normal The inductor losses are external to the device and they do not operation. have any effect on the die temperature. This section provides guidelines to calculate the power dissi- The inductor losses are estimated (without core losses) by pated in the device and ensure that the ADP5024 operates P ≈ I 2 × DCR (4) L OUT1(RMS) L below the maximum allowable junction temperature. where: The efficiency for each regulator on the ADP5024 is given by DCR is the inductor series resistance. L P I is the rms load current of the buck regulator. η= OUT ×100% (1) OUT1(RMS) P IN r I =I × 1+ (5) where: OUT1(RMS) OUT1 12 η is the efficiency. where r is the normalized inductor ripple current. P is the input power. IN POUT is the output power. r = VOUT1 × (1 − D)/(IOUT1 × L × fSW) (6) Power loss is given by where: L is the inductance. P = P − P (2a) LOSS IN OUT f is the switching frequency. SW or D is the duty cycle. PLOSS = POUT (1− η)/η (2b) D = VOUT1/VIN1 (7) Power dissipation can be calculated in several ways. The most The buck regulator power dissipation, P , of the ADP5024 DBUCK intuitive and practical is to measure the power dissipated at the includes the power switch conductive losses, the switch losses, and input and at all of the outputs. Perform the measurements at the the transition losses of each channel. There are other sources of worst-case conditions (voltages, currents, and temperature). The loss, but these are generally less significant at high output load difference between input and output power is dissipated in the currents, where the thermal limit of the application is located. device and the inductor. Use Equation 4 to derive the power lost Equation 8 captures the calculation that must be made to in the inductor, and from this result use Equation 3 to calculate estimate the power dissipation in the buck regulator. the power dissipation in the ADP5024 buck converter. P = P + P + P (8) DBUCK COND SW TRAN A second method to estimate the power dissipation uses the effi- The power switch conductive losses are due to the output current, ciency curves provided for the buck regulator, and the power I , flowing through the P-MOSFET and the N-MOSFET OUT1 lost on the LDO can be calculated using Equation 12. When power switches that have internal resistance, RDS and the buck efficiency is known, use Equation 2b to derive the ON-P RDS . The amount of conductive power loss is found by ON-N total power lost in the buck regulator and inductor, use Equa- P = [RDS × D + RDS × (1 − D)] × I 2 (9) tion 4 to derive the power lost in the inductor, and then calculate COND ON-P ON-N OUT1(RMS) the power dissipation in the buck converter using Equation 3. where RDS is approximately 0.2 Ω, and RDS is approxi- ON-P ON-N Add the power dissipated in the buck and in the LDO to find the mately 0.16 Ω at a junction temperature of 25°C and V = V = IN1 IN2 total dissipated power. 3.6 V. At V = V = 2.3 V, these values change to 0.31 Ω and IN1 IN2 Note that the buck efficiency curves are typical values and may 0.21 Ω, respectively, and at VIN1 = VIN2 = 5.5 V, the values are not be provided for all possible combinations of V , V , and 0.16 Ω and 0.14 Ω, respectively. IN OUT I . To account for these variations, it is necessary to include a OUT safety margin when calculating the power dissipated in the buck. A third way to estimate the power dissipation is analytical and involves modeling the losses in the buck circuit provided by Equation 8 to Equation 11 and calculating the losses in the LDO provided by Equation 12. Rev. E | Page 24 of 28

Data Sheet ADP5024 Switching losses are associated with the current drawn by the JUNCTION TEMPERATURE driver to turn on and turn off the power devices at the switching In cases where the board temperature, T , is known, the A frequency. The amount of switching power loss is given by thermal resistance parameter, θ , can be used to estimate the JA PSW = (CGATE-P + CGATE-N) × VIN12 × fSW (10) junction temperature rise. TJ is calculated from TA and PD using the formula where: C is the P-MOSFET gate capacitance. T = T + (P × θ ) (14) GATE-P J A D JA C is the N-MOSFET gate capacitance. GATE-N The typical θ value for the 24-lead, 4 mm × 4 mm LFCSP is JA For the ADP5024, the total of (CGATE-P + CGATE-N) is approx- 35°C/W (see Table 7). A very important factor to consider is imately 150 pF. that θ is based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per JA JEDEC standard, and real applications may use different sizes The transition losses occur because the P-channel power and layers. To remove heat from the device, it is important to MOSFET cannot be turned on or off instantaneously, and the maximize the use of copper. Copper exposed to air dissipates SW node takes some time to slew from near ground to near heat better than copper used in the inner layers. Connect the V (and from V to ground). The amount of transition OUT1 OUT1 exposed pad to the ground plane with several vias. loss is calculated by P = V × I × (t + t ) × f (11) If the case temperature can be measured, the junction temperature TRAN IN1 OUT1 RISE FALL SW is calculated by where t and t are the rise time and the fall time of the RISE FALL T = T + (P × θ ) (15) switching node, SW. For the ADP5024, the rise and fall times of J C D JC SW are in the order of 5 ns. where T is the case temperature and θ is the junction-to-case C JC thermal resistance provided in Table 7. If the preceding equations and parameters are used for estimating the converter efficiency, it must be noted that the equations do When designing an application for a particular ambient not describe all of the converter losses, and the parameter values temperature range, calculate the expected ADP5024 power given are typical numbers. The converter performance also dissipation (P ) due to the losses of all channels by using D depends on the choice of passive components and board layout; Equation 8 to Equation 13. From this power calculation, the therefore, include a sufficient safety margin in the estimate. junction temperature, T, can be estimated using Equation 14. J LDO Regulator Power Dissipation The reliable operation of the converter and the LDO regulator The power loss of the LDO regulator is given by can be achieved only if the estimated die junction temperature of the ADP5024 (see Equation 14) is less than 125°C. Reliability P = [(V − V ) × I ] + (V × I ) (12) DLDO IN OUT LOAD IN GND and mean time between failures (MTBF) is highly affected by where: increasing the junction temperature. Additional information ILOAD is the load current of the LDO regulator. about product reliability can be found from the ADI Reliability VIN and VOUT are input and output voltages of the LDO, Handbook, which is available at the following URL: respectively. www.analog.com/reliability_handbook. I is the ground current of the LDO regulator. GND Power dissipation due to the ground current is small, and it can be ignored. The total power dissipation in the ADP5024 simplifies to P = P + P + P (13) D DBUCK1 DBUCK2 DLDO Rev. E | Page 25 of 28

ADP5024 Data Sheet PCB LAYOUT GUIDELINES Poor layout can affect ADP5024 performance, causing electro- • Maximize the size of ground metal on the component side magnetic interference (EMI) and electromagnetic compatibility to help with thermal dissipation. (EMC) problems, ground bounce, and voltage losses. Poor • Use a ground plane with several vias connected to the layout can also affect regulation and stability. A good layout is component side ground to further reduce noise implemented using the following guidelines. Also, refer to User interference on sensitive circuit nodes. Guide UG-271. • Connect VIN1, VIN2, and AVIN together close to the IC • Place the inductor, input capacitor, and output capacitor using short tracks. close to the IC using short tracks. These components carry high switching frequencies, and large tracks act as antennas. • Route the output voltage path away from the inductor and SW node to minimize noise and magnetic interference. Rev. E | Page 26 of 28

Data Sheet ADP5024 TYPICAL APPLICATION SCHEMATICS AVIN HOUSEKEEPING CAVIN VOUT1 0.1µF 2.3V TO VIN1 SW1 L1 1µH VOUT1 AT 5.5V 4.7Cµ1F BUCK1 FB1 1200mA C5 OFFON EN1 EN1 MODE PGND1 PWM 10µF MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH C2 SW2 VOUT2 AT 4.7µF BUCK2 FB2 1200mA EN2 C6 ON EN2 PGND2 10µF 1.7V TO OFF VEINN33 EN3(ANLADLOOG) FVBO3UT3 C7 3V0O0UmT3A AT 5.5V C3 1µF 1µF ADP502A4GND 09888-052 Figure 52. Fixed Output Voltages with Enable Pins AVIN HOUSEKEEPING CAVIN VOUT1 0.1µF 2.3V TO VIN1 SW1 L1 1µH VOUT1 AT 5.5V 4.7Cµ1F BUCK1 FB1 R1 1200mA C5 OFFON EN1 EN1 MODE PGND1 R2PWM 10µF MODE PSM/PWM VOUT2 VIN2 MODE L2 1µH C2 SW2 VOUT2 AT 4.7µF BUCK2 FB2 R3 1200mA ON EN2 EN2 PGND2 R4 C106µF 1.7V TO OFF VEINN33 EN3(ANLADLOOG) FVBO3UT3 R5 C7 V30O0UmT3A AT 5.5V 1CµF3 ADP502A4GND R6 1µF 09888-053 Figure 53. Adjustable Output Voltages with Enable Pins BILL OF MATERIALS Table 13. Reference Value Part Number Vendor Package or Dimension (mm) C 0.1 µF, X5R, 6.3 V JMK105BJ104MV-F Taiyo-Yuden 0402 AVIN C3, C7 1 µF, X5R, 6.3 V LMK105BJ105MV-F Taiyo-Yuden 0402 C1, C2 4.7 µF, X5R, 6.3 V ECJ-0EB0J475M Panasonic-ECG 0402 C5, C6 10 µF, X5R, 6.3 V JMK107BJ106MA-T Taiyo-Yuden 0603 L1, L2 1 µH, 0.18 Ω, 850 mA BRC1608T1R0M Taiyo-Yuden 0603 1 µH, 0.085 Ω, 1400 mA LQM2MPN1R0NG0B Murata 2.0 × 1.6 × 0.9 1 µH, 0.059 Ω, 900 mA EPL2014-102ML Coilcraft 2.0 × 2.0 × 1.4 1 µH, 0.086 Ω, 1350 mA MDT2520-CN Toko 2.5 × 2.0 × 1.2 IC1 Three-regulator microPMU ADP5024 Analog Devices 24-lead LFCSP Rev. E | Page 27 of 28

ADP5024 Data Sheet OUTLINE DIMENSIONS 4.10 0.30 4.00 SQ 0.25 PIN 1 3.90 0.20 INDICATOR PIN 1 0.50 19 24 INDICATOR BSC 18 1 EXPOSED 2.20 PAD 2.10 SQ 2.00 13 6 0.50 12 7 0.25 MIN TOP VIEW 0.40 BOTTOM VIEW 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO 0.75 0.05 MAX THE PIN CONFIGURATION AND 0.70 0.02 NOM FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COPLANARITY SEATING 0.08 PLANE COMPLIANTTOJED0E.2C0 SRTEAFNDARDS MO-220-WGGD-8. 06-11-2012-A Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-24-10) Dimensions shown in millimeters ORDERING GUIDE Temperature Output Active Model1 Range Voltage2 UVLO3 Pull-Down4 Package Description Package Option ADP5024ACPZ-R2 −40°C to +125°C Adjustable Low Enabled on buck 24-Lead Lead Frame Chip CP-24-10 channels Scale Package [LFCSP_WQ] ADP5024ACPZ-R7 −40°C to +125°C Adjustable Low Enabled on buck 24-Lead Lead Frame Chip CP-24-10 channels Scale Package [LFCSP_WQ] ADP5024ACPZ-1-R7 −40°C to +125°C VOUT1 = 1.2 V Low Enabled on buck 24-Lead Lead Frame Chip CP-24-10 VOUT2 = 3.3 V channels Scale Package [LFCSP_WQ] VOUT3 = 2.8 V ADP5024ACPZ-2-R7 −40°C to +125°C Adjustable High Enabled on all 24-Lead Lead Frame Chip CP-24-10 channels Scale Package [LFCSP_WQ] ADP5024CP-EVALZ Evaluation Board for ADP5024ACPZ-R7 1 Z = RoHS Compliant Part. 2 For additional options, contact a local sales or distribution representative. Additional options available are: BUCK1 and BUCK2: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.3 V, 2.0 V, 1.8 V, 1.6 V, 1.5 V, 1.4 V, 1.3 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V or adjustable. LDO: 3.3 V, 3.0 V, 2.8 V, 2.5 V, 2.25 V, 2 V, 1.8 V, 1.7 V, 1.6 V, 1.5 V, 1.2 V, 1.1 V, 1.0 V, 0.9 V, 0.8 V or adjustable. 3 UVLO: Low or High. 4 BUCK1, BUCK2, LDO: active pull-down resistor is programmable to be either enabled or disabled. ©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09888-0-5/13(E) Rev. E | Page 28 of 28

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: A nalog Devices Inc.: ADP5024CP-EVALZ ADP5024ACPZ-2-R7 ADP5024ACPZ-1-R7 ADP5024ACPZ-R7 ADP5024ACPZ-R2