24-Bit Capacitance-to-Digital Converter with Temperature Sensor AD7745/AD7746 FEATURES GENERAL DESCRIPTION Capacitance-to-digital converter The AD7745/AD7746 are a high resolution, Σ-Δ capacitance-to- New standard in single chip solutions digital converter (CDC). The capacitance to be measured is Interfaces to single or differential floating sensors connected directly to the device inputs. The architecture fea- Resolution down to 4 aF (that is, up to 21 ENOB) tures inherent high resolution (24-bit no missing codes, up to Accuracy: 4 fF 21-bit effective resolution), high linearity (±0.01%), and high Linearity: 0.01% accuracy (±4 fF factory calibrated). The AD7745/AD7746 Common-mode (not changing) capacitance up to 17 pF capacitance input range is ±4 pF (changing), while it can accept Full-scale (changing) capacitance range: ±4 pF Tolerant of parasitic capacitance to ground up to 60 pF up to 17 pF common-mode capacitance (not changing), which Update rate: 10 Hz to 90 Hz can be balanced by a programmable on-chip, digital-to- Simultaneous 50 Hz and 60 Hz rejection at 16 Hz capacitance converter (CAPDAC). Temperature sensor on-chip The AD7745 has one capacitance input channel, while the Resolution: 0.1°C, accuracy: ±2°C AD7746 has two channels. Each channel can be configured as Voltage input channel single-ended or differential. The AD7745/AD7746 are designed Internal clock oscillator for floating capacitive sensors. For capacitive sensors with one 2-wire serial interface (I2C®-compatible) plate connected to ground, the AD7747 is recommended. Power 2.7 V to 5.25 V single-supply operation The parts have an on-chip temperature sensor with a resolution 0.7 mA current consumption of 0.1°C and accuracy of ±2°C. The on-chip voltage reference Operating temperature: –40°C to +125°C and the on-chip clock generator eliminate the need for any 16-lead TSSOP package external components in capacitive sensor applications. The parts have a standard voltage input, which together with the APPLICATIONS differential reference input allows easy interface to an external Automotive, industrial, and medical systems for temperature sensor, such as an RTD, thermistor, or diode. Pressure measurement The AD7745/AD7746 have a 2-wire, I2C-compatible serial Position sensing interface. Both parts can operate with a single power supply Level sensing from 2.7 V to 5.25 V. They are specified over the automotive Flowmeters temperature range of –40°C to +125°C and are housed in a Humidity sensing Impurity detection 16-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAMS VDD VDD TEMP CLOCK TEMP CLOCK SENSOR GENERATOR AD7745 SENSOR GENERATOR AD7746 VIN(+) VIN(+) CVININ1((+–)) MUX 24-BITΣ-∆ DIGITAL SEIR2CIAL SDA CVININ1((+–)) MUX 24-BITΣ-∆ DIGITAL SEIR2CIAL SDA CIN1(–) MODULATOR FILTER INTERFACE CIN1(–) MODULATOR FILTER INTERFACE SCL SCL CIN2(+) CIN2(–) CONTROL LOGIC CONTROL LOGIC CAP DAC CALIBRATION RDY CAP DAC CALIBRATION RDY CAP DAC CAP DAC VOLTAGE VOLTAGE EXCA EXCITATION REFERENCE EXC1 EXCITATION REFERENCE EXCB EXC2 REFIN(+) REFIN(–) GND 05468-001 REFIN(+) REFIN(–) GND 05468-002 Figure 1. Figure 2. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.

AD7745/AD7746 TABLE OF CONTENTS Specifications.....................................................................................3 Cap Gain Calibration Register..................................................19 Timing Specifications.......................................................................5 Volt Gain Calibration Register.................................................19 Absolute Maximum Ratings............................................................6 Circuit Description.........................................................................20 Pin Configurations and Function Descriptions...........................7 Overview.....................................................................................20 Typical Performance Characteristics.............................................8 Capacitance-to-Digital Converter...........................................20 Output Noise and Resolution Specifications..............................11 Excitation Source........................................................................20 Serial Interface................................................................................12 CAPDAC.....................................................................................21 Read Operation...........................................................................12 Single-Ended Capacitive Input.................................................21 Write Operation..........................................................................12 Differential Capacitive Input....................................................21 AD7745/AD7746 Reset.............................................................13 Parasitic Capacitance to Ground..............................................22 General Call.................................................................................13 Parasitic Resistance to Ground.................................................22 Register Descriptions.....................................................................14 Parasitic Parallel Resistance......................................................22 Status Register.............................................................................15 Parasitic Serial Resistance.........................................................23 Cap Data Register.......................................................................15 Capacitive Gain Calibration.....................................................23 VT Data Register........................................................................15 Capacitive System Offset Calibration......................................23 Cap Set-Up Register...................................................................16 Internal Temperature Sensor....................................................23 VT Set-Up Register....................................................................16 External Temperature Sensor...................................................24 EXC Set-Up Register..................................................................17 Voltage Input...............................................................................24 Configuration Register..............................................................18 V Monitor................................................................................24 DD Cap DAC A Register...................................................................19 Typical Application Diagram....................................................24 Cap DAC B Register...................................................................19 Outline Dimensions.......................................................................25 Cap Offset Calibration Register................................................19 Ordering Guide..........................................................................25 REVISION HISTORY 4/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28

AD7745/AD7746 SPECIFICATIONS V = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = 32 kHz; EXC = ±V /2; –40°C to +125°C, unless otherwise noted. DD DD Table 1. Parameter Min Typ Max Unit Test Conditions/Comments CAPACITIVE INPUT Conversion Input Range ±4.096 pF1 Factory calibrated Integral Nonlinearity (INL)2 ±0.01 % of FSR No Missing Codes2 24 Bit Conversion time ≥ 62 ms Resolution, p-p 16.5 Bit Conversion time = 62 ms, see Table 5 Resolution Effective 19 Bit Conversion time = 62 ms, see Table 5 Output Noise, rms 2 aF/√Hz See Table 5 Absolute Error3 ±4 fF1 25°C, V = 5 V, after offset calibration DD Offset Error2, 4 32 aF1 After system offset calibration, Excluding effect of noise4 System Offset Calibration Range2 ±1 pF Offset Drift vs. Temperature –1 aF/°C Gain Error5 0.02 0.08 % of FS 25°C, V = 5 V DD Gain Drift vs. Temperature2 –28 –26 –24 ppm of FS/°C Allowed Capacitance to GND2 60 pF See Figure 9 and Figure 10 Power Supply Rejection 0.3 1 fF/V Normal Mode Rejection 65 dB 50 Hz ± 1%, conversion time = 62 ms 55 dB 60 Hz ± 1%, conversion time = 62 ms Channel-to-Channel Isolation 70 dB AD7746 only CAPDAC Full Range 17 21 pF Resolution6 164 fF 7-bit CAPDAC Drift vs. Temperature2 24 26 28 ppm of FS/°C EXCITATION Frequency 32 kHz Voltage Across Capacitance ±V /8 V Configurable via digital interface DD ±V /4 V DD ±V × 3/8 V DD ±V /2 V DD Average DC Voltage Across <±40 mV Capacitance Allowed Capacitance to GND2 100 pF See Figure 11 TEMPERATURE SENSOR7 V internal REF Resolution 0.1 °C Error2 ±0.5 ±2 °C Internal temperature sensor ±2 °C External sensing diode8 VOLTAGE INPUT7 V internal or V = 2.5 V REF REF Differential VIN Voltage Range ±V V REF Absolute VIN Voltage2 GND − 0.03 V + 0.03 V DD Integral Nonlinearity (INL) ±3 ±15 ppm of FS No Missing Codes2 24 Bit Conversion time = 122.1 ms Resolution, p-p 16 Bits Conversion time = 62 ms See Table 6 and Table 7 Output Noise 3 µV rms Conversion time = 62 ms See Table 6 and Table 7 Offset Error ±3 µV Offset Drift vs. Temperature 15 nV/°C Full-Scale Error2, 9 0.025 0.1 % of FS Rev. 0| Page 3 of 28

AD7745/AD7746 Parameter Min Typ Max Unit Test Conditions/Comments Full-Scale Drift vs. Temperature 5 ppm of FS/°C Internal reference 0.5 ppm of FS/°C External reference Average VIN Input Current 300 nA/V Analog VIN Input Current Drift ±50 pA/V/°C Power Supply Rejection 80 dB Internal reference, V = V /2 IN REF Power Supply Rejection 90 dB External reference, V = V /2 IN REF Normal Mode Rejection 75 dB 50 Hz ± 1%, conversion time = 122.1 ms 50 dB 60 Hz ± 1%, conversion time = 122.1 ms Common-Mode Rejection 95 dB V = 1 V IN INTERNAL VOLTAGE REFERENCE Voltage 1.169 1.17 1.171 V T = 25°C A Drift vs. Temperature 5 ppm/°C EXTERNAL VOLTAGE REFERENCE INPUT Differential REFIN Voltage2 0.1 2.5 V V DD Absolute REFIN Voltage2 GND − 0.03 V + 0.03 V DD Average REFIN Input Current 400 nA/V Average REFIN Input Current Drift ±50 pA/V/°C Common-Mode Rejection 80 dB SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) V Input High Voltage 2.1 V IH V Input Low Voltage 0.8 V IL Hysteresis 150 mV Input Leakage Current (SCL) ±0.1 ±1 µA OPEN-DRAIN OUTPUT (SDA) VOL Output Low Voltage 0.4 V ISINK = −6.0 mA I Output High Leakage Current 0.1 1 µA V = V OH OUT DD LOGIC OUTPUT (RDY) V Output Low Voltage 0.4 V I = 1.6 mA, V = 5 V OL SINK DD V Output High Voltage 4.0 V I = 200 µA, V = 5 V OH SOURCE DD V Output Low Voltage 0.4 V I = 100 µA, V = 3 V OL SINK DD V Output High Voltage V – 0.6 V I = 100 µA, V = 3 V OH DD SOURCE DD POWER REQUIREMENTS V -to-GND Voltage 4.75 5.25 V V = 5 V, nominal DD DD 2.7 3.6 V V = 3.3 V, nominal DD I Current 850 µA Digital inputs equal to V or GND DD DD 750 µA V = 5 V DD 700 µA V = 3.3 V DD I Current Power-Down Mode 0.5 2 µA Digital inputs equal to V or GND DD DD 1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F. 2 Specification is not production tested, but is supported by characterization data at initial product release. 3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At different temperatures, compensation for gain drift over temperature is required. 4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger offset can be removed using CAPDACs. 5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required. 6 The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further reduce the CIN offset or the unchanging CIN component. 7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance. 8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 41, with total serial resistance <100 Ω. 9 Full-scale error applies to both positive and negative full scale. Rev. 0 | Page 4 of 28

AD7745/AD7746 TIMING SPECIFICATIONS V = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = V ; –40°C to +125°C, unless otherwise noted. DD DD Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SERIAL INTERFACE1, 2 See Figure 3 SCL Frequency 0 400 kHz SCL High Pulse Width, t 0.6 µs HIGH SCL Low Pulse Width, t 1.3 µs LOW SCL, SDA Rise Time, t 0.3 µs R SCL, SDA Fall Time, t 0.3 µs F Hold Time (Start Condition), t 0.6 µs After this period, the first clock is generated HD;STA Set-Up Time (Start Condition), t 0.6 µs Relevant for repeated start condition SU;STA Data Set-Up Time, t 0.25 µs V ≥ 3.0 V SU;DAT DD Data Set-Up Time, t 0.35 µs V < 3.0 V SU;DAT DD Set-Up Time (Stop Condition), t 0.6 µs SU;STO Data Hold Time, t (Master) 0 µs HD;DAT Bus-Free Time (Between Stop and Start Condition, t ) 1.3 µs BUF 1 Sample tested during initial release to ensure compliance. 2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. tLOW tR tF tHD:STA SCL tHD:STA tHD:DAT tHIGH tSU:DAT tSU:STA tSU:STO SDA PtBUF S S P 05468-003 Figure 3. Serial Interface Timing Diagram Rev. 0| Page 5 of 28

AD7745/AD7746 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Positive Supply Voltage VDD to GND −0.3 V to +6.5 V rating only and functional operation of the device at these or Voltage on any Input or Output Pin to –0.3 V to V + 0.3 V DD any other conditions above those indicated in the operational GND section of this specification is not implied. Exposure to absolute ESD Rating (ESD Association Human Body 2000 V Model, S5.1) maximum rating conditions for extended periods may affect Operating Temperature Range –40°C to +125°C device reliability. Storage Temperature Range –65°C to +150°C Junction Temperature 150°C TSSOP Package θ , 128°C/W JA (Thermal Impedance-to-Air) TSSOP Package θ , 14°C/W JC (Thermal Impedance-to-Case) Lead Temperature, Soldering Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 28

AD7745/AD7746 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCL 1 16 SDA SCL 1 16 SDA RDY 2 15 NC RDY 2 15 NC EXCA 3 14 VDD EXCA 3 14 VDD AD7745 AD7746 EXCB 4 13 GND EXCB 4 13 GND TOP VIEW TOP VIEW REFIN(+) 5 (Not to Scale)12 VIN(–) REFIN(+) 5 (Not to Scale)12 VIN(–) REFIN(–) 6 11 VIN(+) REFIN(–) 6 11 VIN(+) CIN1(–) 7 10 NC CIN1(–) 7 10 CIN2(–) CIN1(+) N8C = NO CONNEC9T NC 05468-004 CIN1(+) N8C = NO CONNEC9T CIN2(+)05468-005 Figure 4. AD7745 Pin Configuration (16-Lead TSSOP) Figure 5. AD7746 Pin Configuration (16-Lead TSSOP) Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 SCL Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system. 2 RDY Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit. 3, 4 EXCA, EXCB CDC Excitation Outputs. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. 5, 6 REFIN(+), Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal REFIN(–) reference can be used for the voltage channel. These reference input pins are not used for conversion on capacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND. 7 CIN1(–) CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in single-ended CDC configuration. If not used, this pin can be left as an open circuit or connected to GND. 8 CIN1(+) CDC Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, this pin can be left as an open circuit or connected to GND. 9, 10 NC Not Connected. This pin should be left as an open circuit. (AD7745) 9 CIN2(+) CDC Second Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). If not (AD7746) used, this pin can be left open circuit or connected to GND. 10 CIN2(–) CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in a single-ended CDC (AD7746) configuration. If not used, this pin can be left as an open circuit or connected to GND. 11, 12 VIN(+), VIN(–) Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND. 13 GND Ground Pin. 14 VDD Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example in combination with a 10 µF tantalum and a 0.1 µF multilayer ceramic. 15 NC Not Connected. This pin should be left as an open circuit. 16 SDA Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system. Rev. 0| Page 7 of 28

AD7745/AD7746 TYPICAL PERFORMANCE CHARACTERISTICS 100 18 2.7V 3V 3.3V 5V 16 80 14 F) R (f 12 O m) 60 ERR 10 INL (pp 40 CITANCE 86 A P 4 A C 20 2 0 05468-014 –20 05468-017 –5 –4 –3 –2 –1 0 1 2 3 4 5 0 50 100 150 200 250 300 350 400 450 500 INPUT CAPACITANCE (pF) CAPACITANCE CIN PIN TO GND (pF) Figure 6. Capacitance Input Integral Nonlinearity, VDD = 5 V, the Same Configuration as in Figure 31 Figure 9. Capacitance Input Error vs. Capacitance between CIN and GND. CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V, the Same Configuration as in Figure 33 2000 GAIN TC≈–26ppm/°C 18 16 1000 14 pm) R (fF) 12 2.7V 3V 3.3V p 0 O AIN ERROR (–1000 TANCE ERR 1086 G CI 5V A P 4 A –2000 C 2 –3000–50 –25 0 25 50 75 100 125 15005468-015 –20 05468-018 TEMPERATURE (°C) 0 50 100 150 200 250 300 350 400 450 500 CAPACITANCE CIN PIN TO GND (pF) Figure 7. Capacitance Input Offset Drift vs. Temperature, VDD = 5 V, CIN and EXC Pins Open Circuit Figure 10. Capacitance Input Error vs. Capacitance between CIN and GND, CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V, the Same Configuration as in Figure 34 100 5 75 2.7V 3V 4 50 OFFSET ERROR (aF) –22550 ACITANCE ERROR (fF) 321 3.3V5V –50 AP C –1–7050–50 –25 0 25 50 75 100 125 15005468-016 –10 05468-019 0 50 100 150 200 250 300 350 400 450 500 TEMPERATURE (°C) CAPACITANCE EXC PIN TO GND (pF) Figure 8. Capacitance Input Gain Drift vs. Temperature, Figure 11. Capacitance Input Error vs. Capacitance between EXC and GND, VDD = 5 V, CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30 CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V, the Same Configuration as in Figure 34 Rev. 0 | Page 8 of 28

AD7745/AD7746 8 0 6 4 –2 F) F) R (f 2 R (f O O RR 0 RR –4 E E CE –2 CE AN 3V AN T –4 T –6 CI CI A A P –6 P A A C 2.7V C –8 –8 ––1120 05468-028 –10 05468-031 –250 –200 –150 –100 –50 0 50 100 150 200 250 0 1 2 3 4 5 6 7 CIN LEAKAGE TO GND (nA) SERIAL RESISTANCE (kΩ) Figure 12. Capacitance Input Error vs. Leakage Current to GND, Figure 15. Capacitance Input Error vs. Serial Resistance, CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF, CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, VDD = 5 V, VDD = 2.7 V and 3 V the Same Configuration as in Figure 34. 8 0.2 6 0 4 OR (fF) 2 OR (fF) –0.2 CAPACITANCE ERR –––2460 5V CAPACITANCE ERR ––00..46 –8 –0.8 3.3V ––1120 05468-030 –1.0 05468-032 –250 –200 –150 –100 –50 0 50 100 150 200 250 2.5 3.0 3.5 4.0 4.5 5.0 5.5 CIN LEAKAGE TO GND (nA) VDD (V) Figure 13. Capacitance Input Error vs. Leakage Current to GND, Figure 16. Capacitance Input Power Supply Rejection (PSR), CIN(+) to EXC =4 pF, CIN(−) to EXC = 0 pF, CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30 VDD=3.3 V and 5 V 10 0.20 0.15 1 ROR (pF) 0.1 NL (pF) 00..1005 R D CE E ODE 0 N C CAPACITA 0.01 CAPDAC ––00..0150 0.001 0.0001 05468-029 ––00..1250 05468-033 1 10 100 1000 10000 100000 0 16 32 48 64 80 96 112 128 PARALLEL RESISTANCE (MΩ) CAPDAC CODE Figure 14. Capacitance Input Error vs. Resistance in Parallel Figure 17. CAPDAC Differential Nonlinearity (DNL) with Measured Capacitance Rev. 0| Page 9 of 28

AD7745/AD7746 2.0 0 1.5 –20 1.0 –40 0.5 OR (°C) 0 N (dB) –60 R AI R G E –0.5 –80 –1.0 –100 ––12..50 05468-034 –120 05468-037 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 TEMPERATURE (°C) INPUT SIGNAL FREQUENCY (Hz) Figure 18. Internal Temperature Sensor Error vs. Temperature Figure 21. Capacitance Channel Frequency Response, Conversion Time = 62 ms 1.0 0 0.5 –20 0 –40 –0.5 OR (°C) –1.0 N (dB) –60 R AI R G E –1.5 –80 –2.0 –100 ––23..50 05468-035 –120 05468-038 –50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 TEMPERATURE (°C) INPUT SIGNAL FREQUENCY (Hz) Figure 19. External Temperature Sensor Error vs. Temperature Figure 22. Capacitance Channel Frequency Response, Conversion Time = 109.6 ms 0 0 –20 –20 –40 –40 B) B) d d N ( –60 N ( –60 AI AI G G –80 –80 –100 –100 –120 05468-036 –120 05468-039 0 100 200 300 400 500 600 700 800 900 1000 0 50 100 150 200 250 300 350 400 INPUT SIGNAL FREQUENCY (Hz) INPUT SIGNAL FREQUENCY (Hz) Figure 20. Capacitance Channel Frequency Response, Figure 23. Voltage Channel Frequency Response, Conversion Time = 11 ms Conversion Time = 122.1 ms Rev. 0 | Page 10 of 28

AD7745/AD7746 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS The AD7745/AD7746 resolution is limited by noise. The noise Table 6 and Table 7 show typical noise performance and performance varies with the selected conversion time. resolution for the voltage channel. These numbers were generated from 1000 data samples acquired in continuous Table 5 shows typical noise performance and resolution for the conversion mode with VIN pins shorted to ground. capacitive channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode, at an RMS noise represents the standard deviation and p-p noise excitation of 32 kHz, ±V /2, and with all CIN and EXC pins represents the difference between minimum and maximum DD connected only to the evaluation board (no external capacitors.) results in the data. Effective resolution is calculated from rms noise, and p-p resolution is calculated from p-p noise. Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time Conversion Output Data –3dB Frequency RMS Noise RMS P-P Effective Resolution P-P Resolution Time (ms) Rate (Hz) (Hz) (aF/√Hz) Noise (aF) Noise (aF) (Bits) (Bits) 11.0 90.9 87.2 4.3 40.0 212.4 17.6 15.2 11.9 83.8 79.0 3.1 27.3 137.7 18.2 15.9 20.0 50.0 43.6 1.8 12.2 82.5 19.4 16.6 38.0 26.3 21.8 1.6 7.3 50.3 20.1 17.3 62.0 16.1 13.8 1.5 5.4 33.7 20.5 17.9 77.0 13.0 10.5 1.5 4.9 28.3 20.7 18.1 92.0 10.9 8.9 1.5 4.4 27.8 20.8 18.2 109.6 9.1 8.0 1.5 4.2 27.3 20.9 18.2 Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference Conversion Output Data –3dB Frequency RMS Noise P-P Noise Effective Resolution P-P Resolution Time (ms) Rate (Hz) (Hz) (µV) (µV) (Bits) (Bits) 20.1 49.8 26.4 11.4 62 17.6 15.2 32.1 31.2 15.9 7.1 42 18.3 15.7 62.1 16.1 8.0 4.0 28 19.1 16.3 122.1 8.2 4.0 3.0 20 19.5 16.8 Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference Conversion Output Data –3dB Frequency RMS Noise P-P Noise Effective Resolution P-P Resolution Time (ms) Rate (Hz) (Hz) (µV) (µV) (Bits) (Bits) 20.1 49.8 26.4 14.9 95 18.3 15.6 32.1 31.2 15.9 6.3 42 19.6 16.8 62.1 16.1 8.0 3.3 22 20.5 17.7 122.1 8.2 4.0 2.1 15 21.1 18.3 Rev. 0| Page 11 of 28

AD7745/AD7746 SERIAL INTERFACE The AD7745/AD7746 supports an I2C-compatible 2-wire serial The address pointers’ auto-incrementer allow block data to be interface. The two wires on the I2C bus are called SCL (clock) written or read from the starting address and subsequent and SDA (data). These two wires carry all addressing, control, incremental addresses. and data information one bit at a time over the bus to all In continuous conversion mode, the address pointers’ auto- connected peripheral devices. The SDA wire carries the data, incrementer should be used for reading a conversion result. while the SCL wire synchronizes the sender and receiver during That means, the three data bytes should be read using one the data transfer. I2C devices are classified as either master or multibyte read transaction rather than three separate single byte slave devices. A device that initiates a data transfer message is transactions. The single byte data read transaction may result in called a master, while a device that responds to this message is the data bytes from two different results being mixed. The same called a slave. applies for six data bytes if both the capacitive and the To control the AD7745/AD7746 device on the bus, the voltage/temperature channel are enabled. following protocol must be followed. First, the master initiates a The user can also access any unique register (address) on a one- data transfer by establishing a start condition, defined by a to-one basis without having to update all the registers. The high-to-low transition on SDA while SCL remains high. This address pointer register contents cannot be read. indicates that the start byte follows. This 8-bit start byte is made If an incorrect address pointer location is accessed or, if the user up of a 7-bit address plus an R/W bit indicator. allows the auto-incrementer to exceed the required register All peripherals connected to the bus respond to the start address, the following applies: condition and shift in the next 8 bits (7-bit address + R/W bit). • In read mode, the AD7745/AD7746 continues to output The bits arrive MSB first. The peripheral that recognizes the various internal register contents until the master device transmitted address responds by pulling the data line low issues a no acknowledge, start, or stop condition. The during the ninth clock pulse. This is known as the acknowledge address pointers’ auto-incrementer’s contents are reset to bit. All other devices withdraw from the bus at this point and point to the status register at Address 0x00 when a stop maintain an idle condition. An exception to this is the general condition is received at the end of a read operation. This call address, which is described later in this document. The idle allows the status register to be read (polled) continually condition is where the device monitors the SDA and SCL lines without having to constantly write to the address pointer. waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 • In write mode, the data for the invalid address is not loaded LSB in the start byte means that the master writes information into the AD7745/AD7746 registers but an acknowledge is to the addressed peripheral. In this case the AD7745/AD7746 issued by the AD7745/AD7746. becomes a slave receiver. A Logic 1 LSB in the start byte means WRITE OPERATION that the master reads information from the addressed peri- pheral. In this case, the AD7745/AD7746 becomes a slave When a write is selected, the byte following the start byte is transmitter. In all instances, the AD7745/AD7746 acts as a always the register address pointer (subaddress) byte, which standard slave device on the I2C bus. points to one of the internal registers on the AD7745/ AD7746. The address pointer byte is automatically loaded into the The start byte address for the AD7745/AD7746 is 0x90 for a address pointer register and acknowledged by the AD7745/ write and 0x91 for a read. AD7746. After the address pointer byte acknowledge, a stop READ OPERATION condition, a repeated start condition, or another data byte can When a read is selected in the start byte, the register that is follow from the master. currently addressed by the address pointer is transmitted on to A stop condition is defined by a low-to-high transition on SDA the SDA line by the AD7745/AD7746. This is then clocked out while SCL remains high. If a stop condition is ever encountered by the master device and the AD7745/AD7746 awaits an by the AD7745/AD7746, it returns to its idle condition and the acknowledge from the master. address pointer is reset to Address 0x00. If an acknowledge is received from the master, the address auto- If a data byte is transmitted after the register address pointer incrementer automatically increments the address pointer byte, the AD7745/AD7746 load this byte into the register that is register and outputs the next addressed register content on to currently addressed by the address pointer register, send an the SDA line for transmission to the master. If no acknowledge acknowledge, and the address pointer auto-incrementer auto- is received, the AD7745/AD7746 return to the idle state and the matically increments the address pointer register to the next address pointer is not incremented. internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses. Rev. 0 | Page 12 of 28

AD7745/AD7746 If a repeated start condition is encountered after the address GENERAL CALL pointer byte, all peripherals connected to the bus respond When a master issues a slave address consisting of seven 0s with exactly as outlined above for a start condition, that is, a repeated the eighth bit (R/W bit) set to 0, this is known as the general call start condition is treated the same as a start condition. When a address. The general call address is for addressing every device master device issues a stop condition, it relinquishes control of connected to the I2C bus. The AD7745/AD7746 acknowledge the bus, allowing another master device to take control of the this address and read in the following data byte. bus. Hence, a master wanting to retain control of the bus issues If the second byte is 0x06, the AD7745/AD7746 are reset, successive start conditions known as repeated start conditions. completely uploading all default values. The AD7745/AD7746 AD7745/AD7746 RESET do not respond to the I2C bus commands (do not acknowledge) To reset the AD7745/AD7746 without having to reset the entire during the default values upload for approximately 150 µs (max I2C bus, an explicit reset command is provided. This uses a 200 µs). particular address pointer word as a command word to reset the The AD7745/AD7746 do not acknowledge any other general part and upload all default settings. The AD7745/AD7746 do call commands. not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately 150 µs (max 200 µs). The reset command address word is 0xBF. SDATA SCLOCKSTASRTA1D–D7R R/8W AC9K SUB1–A7DDRE8SS A9CK 1–D7ATA8 A9CK STPOP 05468-006 Figure 24. Bus Data Transfer WRITE S SLAVEADDR A(S) SUBADDR A(S) DATA A(S) DATA A(S) P SEQUENCE LSB = 0 LSB = 1 READ S SLAVEADDR A(S) SUBADDR A(S) S SLAVEADDR A(S) DATA A(M) DATA A(M) P SEQUENCE SP == SSTTAORPT B BITIT AA((SM)) == AACCKKNNOOWWLLEEDDGGEE BBYY SMLAASVTEER AA((SM)) == NNOO--AACCKKNNOOWWLLEEDDGGEE BBYY SMLAASVTEER 05468-007 Figure 25. Write and Read Sequences Rev. 0| Page 13 of 28

AD7745/AD7746 REGISTER DESCRIPTIONS The master can write to or read from all of the AD7745/ accessed over the bus and a read/write operation is selected, the AD7746 registers except the address pointer register, which is a address pointer register is set up. The address pointer register write-only register. The address pointer register determines determines from or to which register the operation takes place. which register the next read or write operation accesses. All A read/write operation is performed from/to the target address, communications with the part through the bus start with an which then increments to the next address until a stop access to the address pointer register. After the part has been command on the bus is performed. Table 8. Register Summary Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pointer Register (Dec) (Hex) Dir Default Value - - - - EXCERR RDY RDYVT RDYCAP Status 0 0x00 R 0 0 0 0 0 1 1 1 Cap Data H 1 0x01 R Capacitive channel data—high byte, 0x00 Cap Data M 2 0x02 R Capacitive channel data—middle byte, 0x00 Cap Data L 3 0x03 R Capacitive channel data—low byte, 0x00 VT Data H 4 0x04 R Voltage/temperature channel data—high byte, 0x00 VT Data M 5 0x05 R Voltage/temperature channel data—middle byte, 0x00 VT Data L 6 0x06 R Voltage/temperature channel data—low byte, 0x00 CAPEN CIN21 CAPDIFF - - - - CAPCHOP Cap Setup 7 0x07 R/W 0 0 0 0 0 0 0 0 VTEN VTMD1 VTMD0 EXTREF - - VTSHORT VTCHOP VT Setup 8 0x08 R/W 0 0 0 0 0 0 0 0 CLKCTRL EXCON EXCB EXCB EXCA EXCA EXCLVL1 EXCLVL0 EXC Setup 9 0x09 R/W 0 0 0 0 0 0 1 1 VTFS1 VTFS0 CAPFS2 CAPFS1 CAPFS0 MD2 MD1 MD0 Configuration 10 0x0A R/W 1 0 1 0 0 0 0 0 DACAENA DACA—7-Bit Value Cap DAC A 11 0x0B R/W 0 0x00 DACBENB DACB—7-Bit Value Cap DAC B 12 0x0C R/W 0 0x00 Cap Offset H 13 0x0D R/W Capacitive offset calibration—high byte, 0x80 Cap Offset L 14 0x0E R/W Capacitive offset calibration—low byte, 0x00 Cap Gain H 15 0x0F R/W Capacitive gain calibration—high byte, factory calibrated Cap Gain L 16 0x10 R/W Capacitive gain calibration—low byte, factory calibrated Volt Gain H 17 0x11 R/W Voltage gain calibration—high byte, factory calibrated Volt Gain L 18 0x12 R/W Voltage gain calibration—low byte, factory calibrated 1 The CIN2 bit is relevant only for AD7746. The CIN2 bit should always be 0 on the AD7745. Rev. 0 | Page 14 of 28

AD7745/AD7746 STATUS REGISTER The RDY pin reflects the status of the RDY bit. Therefore, the Address Pointer 0x00, Read Only, Default Value 0x07 RDY pin high-to-low transition can be used as an alternative This register indicates the status of the converter. The status indication of the finished conversion. register can be read via the 2-wire serial interface to query a finished conversion. Table 9. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic - - - - EXCERR RDY RDYVT RDYCAP Default 0 0 0 0 0 1 1 1 Table 10. Bit Mnemonic Description 7-4 - Not used, always read 0. 3 EXCERR EXCERR = 1 indicates that the excitation output cannot be driven properly. The possible reason can be a short circuit or too high capacitance between the excitation pin and ground. 2 RDY RDY = 0 indicates that conversion on the enabled channel(s) has been finished and new unread data is available. If both capacitive and voltage/temperature channels are enabled, the RDY bit is changed to 0 after conversion on both channels is finished. The RDY bit returns to 1 either when data is read or prior to finishing the next conversion. If, for example, only the capacitive channel is enabled, then the RDY bit reflects the RDYCAP bit. 1 RDYVT RDYVT = 0 indicates that a conversion on the voltage/temperature channel has been finished and new unread data is available. 0 RDYCAP RDYCAP = 0 indicates that a conversion on the capacitive channel has been finished and new unread data is available. CAP DATA REGISTER VT DATA REGISTER 24 Bits, Address Pointer 0x01, 0x02, 0x03, Read-Only, 24 Bits, Address Pointer 0x04, 0x05, 0x06, Read-Only, Default Value 0x000000 Default Value 0x000000 Capacitive channel output data. The register is updated after Voltage/temperature channel output data. The register is finished conversion on the capacitive channel, with one updated after finished conversion on the voltage channel or exception: When the serial interface read operation from the temperature channel, with one exception: When the serial CAP DATA register is in progress, the data register is not interface read operation from the VT DATA register is in updated and the new capacitance conversion result is lost. progress, the data register is not updated and the new voltage/temperature conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, The stop condition on the serial interface is considered to be the all three bytes of the data register should be read sequentially end of the read operation. Therefore, to prevent data corruption, using the register address pointer auto-increment feature of the all three bytes of the data register should be read sequentially serial interface. using the register address pointer auto-increment feature of the serial interface. To prevent losing some of the results, the CAP DATA register should be read before the next conversion on the capacitive For voltage input, Code 0 represents negative full scale (–VREF), channel is finished. the 0x800000 code represents zero scale (0 V), and the 0xFFFFFF code represents positive full scale (+V ). REF The 0x000000 code represents negative full scale (–4.096 pF), To prevent losing some of the results, the VT DATA register the 0x800000 code represents zero scale (0 pF), and the 0xFFFFFF code represents positive full scale (+4.096 pF). should be read before the next conversion on the voltage/ temperature channel is finished. For the temperature sensor, the temperature can be calculated from code using the following equation: Temperature (°C) = (Code/2048) − 4096 Rev. 0| Page 15 of 28

AD7745/AD7746 CAP SET-UP REGISTER Address Pointer 0x07, Default Value 0x00 Capacitive channel setup. Table 11. CAP Set-Up Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CAPEN CIN2 CAPDIFF - - - - CAPCHOP Default 0 0 0 0 0 0 0 0 Table 12. Bit Mnemonic Description 7 CAPEN CAPEN = 1 enables capacitive channel for single conversion, continuous conversion, or calibration. 6 CIN2 CIN2 = 1 switches the internal multiplexer to the second capacitive input on the AD7746. 5 CAPDIFF DIFF = 1 sets differential mode on the selected capacitive input. 4-1 - These bits must be 0 for proper operation. 0 CAPCHOP The CAPCHOP bit should be set to 0 for the specified capacitive channel performance. CAPCHOP = 1 approximately doubles the capacitive channel conversion times and slightly improves the capacitive channel noise performance for the longest conversion times. VT SET-UP REGISTER Address Pointer 0x08, Default Value 0x00 Voltage/Temperature channel setup. Table 13. VT Set-Up Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic VTEN VTMD1 VTMD0 EXTREF - - VTSHORT VTCHOP Default 0 0 0 0 0 0 0 0 Table 14. Bit Mnemonic Description 7 VTEN VTEN = 1 enables voltage/temperature channel for single conversion, continuous conversion, or calibration. 6 VTMD1 Voltage/temperature channel input configuration. 5 VTMD0 VTMD1 VTMD0 Channel Input 0 0 Internal temperature sensor 0 1 External temperature sensor diode 1 0 V monitor DD 1 1 External voltage input (VIN) 4 EXTREF EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(–) for the voltage input or the V monitor. DD EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal temperature sensor for proper operation. 3-2 - These bits must be 0 for proper operation. 1 VTSHORT VTSHORT = 1 internally shorts the voltage/temperature channel input for test purposes. 0 VTCHOP = 1 VTCHOP = 1 sets internal chopping on the voltage/temperature channel. The VTCHOP bit must be set to 1 for the specified voltage/temperature channel performance. Rev. 0 | Page 16 of 28

AD7745/AD7746 EXC SET-UP REGISTER Address Pointer 0x09, Default Value 0x03 Capacitive channel excitation setup. Table 15. EXC Set-Up Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic CLKCTRL EXCON EXCB EXCB EXCA EXCA EXCLVL1 EXCLVL0 Default 0 0 0 0 0 0 0 0 Table 16. Bit Mnemonic Description 7 CLKCTRL The CLKCTRL bit should be set to 0 for the specified AD7745/AD7746 performance. CLKCTRL = 1 decreases the excitation signal frequency and the modulator clock frequency by factor of 2. This also increases the conversion time on all channels (capacitive, voltage, and temperature) by a factor of 2. 6 EXCON When EXCON = 0, the excitation signal is present on the output only during capacitance channel conversion. When EXCON = 1, the excitation signal is present on the output during both capacitance and voltage/temperature conversion. 5 EXCB EXCB = 1 enables EXCB pin as the excitation output. 4 EXCB EXCB = 1 enables EXCB pin as the inverted excitation output. Only one of the EXCB or the EXCB bits should be set for proper operation. 3 EXCA EXCA = 1 enables EXCA pin as the excitation output. 2 EXCA EXCA = 1 enables EXCA pin as the inverted excitation output. Only one of the EXCA or the EXCA bits should be set for proper operation. 1 EXCLVL1, Excitation Voltage Level. 0 EXCLVL0 EXCLVL1 EXCLVL0 Voltage on Cap EXC Pin Low Level EXC Pin High Level 0 0 ±V /8 V × 3/8 V × 5/8 DD DD DD 0 1 ±V /4 V × 1/4 V × 3/4 DD DD DD 1 0 ±V × 3/8 V × 1/8 V × 7/8 DD DD DD 1 1 ±V /2 0 V DD DD Rev. 0| Page 17 of 28

AD7745/AD7746 CONFIGURATION REGISTER Address Pointer 0x0A, Default Value 0xA0 Converter update rate and mode of operation setup. Table 17. Configuration Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic VTF1 VTF0 CAPF2 CAPF1 CAPF0 MD2 MD1 MD0 Default 0 0 0 0 0 0 0 0 Table 18. Bit Mnemonic Description 7 VTF1 Voltage/temperature channel digital filter setup—conversion time/update rate setup. 6 VTF0 The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by a factor of two for the CLKCTRL = 1. VTCHOP = 1 VTF1 VTF0 Conversion Time (ms) Update Rate (Hz) –3 dB Frequency (Hz) 0 0 20.1 49.8 26.4 0 1 32.1 31.2 15.9 1 0 62.1 16.1 8.0 1 1 122.1 8.2 4.0 5 CAPF2 Capacitive channel digital filter setup—conversion time/update rate setup. 4 CAPF1 The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. 3 CAPF0 The conversion times are longer by factor of two for the CLKCTRL = 1. CAP CHOP = 0 CAPF2 CAPF1 CAPF0 Conversion Time (ms) Update Rate –3 dB Frequency (Hz) 0 0 0 11.0 90.9 87.2 0 0 1 11.9 83.8 79.0 0 1 0 20.0 50.0 43.6 0 1 1 38.0 26.3 21.8 1 0 0 62.0 16.1 13.1 1 0 1 77.0 13.0 10.5 1 1 0 92.0 10.9 8.9 1 1 1 109.6 9.1 8.0 2 MD2 Converter mode of operation setup. 1 MD1 MD2 MD1 MD0 Mode 0 MD0 0 0 0 Idle 0 0 1 Continuous conversion 0 1 0 Single conversion 0 1 1 Power-Down 1 0 0 - 1 0 1 Capacitance system offset calibration 1 1 0 Capacitance or voltage system gain calibration 1 1 1 Rev. 0 | Page 18 of 28

AD7745/AD7746 CAP DAC A REGISTER Address Pointer 0x0B, Default Value 0x00 Capacitive DAC setup. Table 19. Cap DAC A Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DACAENA DACA—7-Bit Value Default 0 0x00 Table 20. Bit Mnemonic Description 7 DACAENA DACAENA = 1 connects capacitive DACA to the positive capacitance input. 6-1 DACA DACA value, Code 0x00 ≈ 0 pF, Code 0x7F ≈ full range. CAP DAC B REGISTER Address Pointer 0x0C, Default Value 0x00 Capacitive DAC setup. Table 21. Cap DAC B Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic DACBENB DACB—7-bit value Default 0 0x00 Table 22. Bit Mnemonic Description 7 DACBENB DACBENB = 1 connects capacitive DACB to the negative capacitance input. 6-1 DACB DACB value, Code 0x00 ≈ 0 pF, Code 0x7F ≈ full range. CAP OFFSET CALIBRATION REGISTER CAP GAIN CALIBRATION REGISTER 16 Bits, Address Pointer 0x0D, 0x0E, 16 Bits, Address Pointer 0x0F, 0x10, Default Value 0x8000 Default Value 0xXXXX The capacitive offset calibration register holds the capacitive Capacitive gain calibration register. The register holds the channel zero-scale calibration coefficient. The coefficient is capacitive channel full-scale factory calibration coefficient. used to digitally remove the capacitive channel offset. The On the AD7746, the register is shared by the two capacitive register value is updated automatically following the execution channels. of a capacitance offset calibration. The capacitive offset calibra- VOLT GAIN CALIBRATION REGISTER tion resolution (cap offset register LSB) is less than 32 aF; the 16 Bits, Address Pointer 0x11,0x12, full range is 1 pF. Default Value 0xXXXX On the AD7746, the register is shared by the two capacitive Voltage gain calibration register. The register holds the voltage channels. If the capacitive channels need to be offset-calibrated channel full-scale factory calibration coefficient. individually, the host controller software should read the AD7746 capacitive offset calibration register values after performing the offset calibration on individual channels and then reload the values back to the AD7746 before executing conversion on a different channel. Rev. 0| Page 19 of 28

AD7745/AD7746 CIRCUIT DESCRIPTION VDD VDD TEMP CLOCK TEMP CLOCK SENSOR GENERATOR AD7745 SENSOR GENERATOR AD7746 VIN(+) VIN(+) CVININ1((+–)) MUX 24-BITΣ-∆ DIGITAL SEIR2CIAL SDA CVININ1((+–)) MUX 24-BITΣ-∆ DIGITAL SEIR2CIAL SDA CIN1(–) MODULATOR FILTER INTERFACE CIN1(–) MODULATOR FILTER INTERFACE SCL SCL CIN2(+) CIN2(–) CONTROL LOGIC CONTROL LOGIC CAP DAC CALIBRATION RDY CAP DAC CALIBRATION RDY CAP DAC CAP DAC VOLTAGE VOLTAGE EXCA EXCITATION REFERENCE EXC1 EXCITATION REFERENCE EXCB EXC2 REFIN(+) REFIN(–) GND 05468-001 REFIN(+) REFIN(–) GND 05468-002 Figure 26. AD7745 Block Diagram Figure 27. AD7746 Block Diagram OVERVIEW CAPACITANCE TO DIGITAL CONVERTER (CDC) The AD7745/AD7746 core is a high precision converter con- CLOCK sisting of a second order (Σ-Δ or charge balancing) modulator GENERATOR and a third order digital filter. It works as a CDC for the capa- DATA citive inputs and as a classic ADC for the voltage input or for CIN 24-BITΣ-∆ DIGITAL the voltage from a temperature sensor. MODULATOR FILTER CX In addition to the converter, the AD7745/AD7746 integrates a mcituivltei pinlepxuetrs, ,a an teexmcpiteartiaotunr seo suerncseo arn, ad vCoAltaPgDe AreCfes rfeonrc teh feo cra tphae- EXC EXCITATION 05468-027 Figure 28. CDC Simplified Block Diagram voltage and temperature inputs, a complete clock generator, a control and calibration logic, and an I2C-compatible serial EXCITATION SOURCE interface. The two excitation pins EXCA and EXCB are independently The AD7745 has one capacitive input, while the AD7746 has programmable. They are identically functional and therefore two capacitive inputs. All other features and specifications are either of them can be used for the capacitive sensor excitation. identical for both parts. On the 2-channel AD7746 using a separate excitation pin for CAPACITANCE-TO-DIGITAL CONVERTER each capacitive channel is recommended. Figure 28 shows the CDC simplified functional diagram. The measured capacitance C is connected between the excitation X source and the Σ-Δ modulator input. A square-wave excitation signal is applied on the C during the conversion and the X modulator continuously samples the charge going through the C . The digital filter processes the modulator output, which is a X stream of 0s and 1s containing the information in 0 and 1 density. The data from the digital filter is scaled, applying the calibration coefficients, and the final result can be read through the serial interface. The AD7745/AD7746 is designed for floating capacitive sensors. Therefore, both C plates have to be isolated from X ground. Rev. 0 | Page 20 of 28

AD7745/AD7746 CAPDAC The CAPDAC can be used for programmable shifting the input range. The example in Figure 31 shows how to use the full The AD7745/AD7746 CDC full-scale input range is ±4.096 pF. ±4 pF CDC span to measure capacitance between 0 pF to 8 pF. For simplicity of calculation, however, the following text and diagrams use ±4 pF. The part can accept a higher capacitance CAPDAC(+) on the input and the common-mode or offset (not-changing 4pF component) capacitance can be balanced by programmable CIN(+) 0x000000...0xFFFFFF DATA on-chip CAPDACs. CIN(–) CAPDIFF = 0 ±C4DpCF CAPDAC(+) CAPDAC(–) CX 0pF 0 ... 8pF CIN(+) CIN(–) CDC DATA EXC 05468-025 Figure 31. Using CAPDAC in Single-Ended Mode Figure 32 shows how to shift the input range further, up to CAPDAC(–) 21 pF absolute value of capacitance connected to the CIN(+). CX CY EXC 05468-010 CIN(+) C17ApPFDAC(+) 0x000000...0xFFFFFF Figure 29. Using a CAPDAC DATA CAPDIFF = 0 ±4pF The CAPDAC can be understood as a negative capacitance CIN(–) CDC connected internally to the CIN pin. There are two independent CAPDACs, one connected to the CIN(+) and the second CAPDAC(–) CX 0pF connected to the CIN(–). The relation between the capacitance 13 ... 21pF (17±4pF) input DanAdT oAu≈tp(uCt da−tCa AcaPnD bAeC e(x+p)r)e−ss(eCd a−s CAPDAC(−)) FiguErXeC 32. Using CAPDAC in Single-Ended Mode 05468-026 X Y DIFFERENTIAL CAPACITIVE INPUT The CAPDACs have a 7-bit resolution, monotonic transfer function, are well matched to each other, and have a defined When configured for a differential mode (the CAPDIFF bit in temperature coefficient. The CAPDAC full range (absolute the Cap Setup register set to 1), the AD7745/AD7746 CDC value) is not factory calibrated and can vary up to ±20% with measures the difference between positive and negative the manufacturing process. See the Specifications section and capacitance input. typical performance characteristics in Figure 17. Each of the two input capacitances C and C between the EXC X Y The CAPDACs are shared by the two capacitive channels on the and CIN pins must be less than 4 pF (without using the AD7746. If the CAPDACs need to be set individually, the host CAPDACs) or must be less than 21 pF and balanced by the controller software should reload the CAPDAC values to the CAPDACs. Balancing by the CAPDACs means that both AD7746 before executing conversion on a different channel. C –CAPDAC(+) and C –CAPDAC(–) are less than 4 pF. X Y SINGLE-ENDED CAPACITIVE INPUT If the unbalanced capacitance between the EXC and CIN pins is When configured for a single-ended mode (the CAPDIFF bit in higher than 4 pF, the CDC introduces a gain error, an offset the Cap Setup register is set to 0), the AD7745/AD7746 CIN(–) error, and nonlinearity error. pin is disconnected internally. The CDC (without using the See the examples shown in Figure 33, Figure 34, and Figure 35. CAPDACs) can measure only positive input capacitance in the range of 0 pF to 4 pF (see Figure 30). CAPDAC(+) OFF CIN(+) 0x000000...0xFFFFFF CAPDAC(+) DATA CIN(+) OFF 0x800000...0xFFFFFF CIN(–) CAPDIFF = 1 ±C4DpCF DATA CAPDIFF = 0 0 ... 4pF CIN(–) CDC CAPDAC(–) CX CY OFF 0 ... 4pF 0 ... 4pF CAPDAC(–) C0 X... 4pF FEiXgCure 30. OCFDFC Single-Ended Input Mode 05468-024 EXFCigure 33. CDC Differential Input Mode 05468-020 Rev. 0| Page 21 of 28

AD7745/AD7746 PARASITIC RESISTANCE TO GROUND CAPDAC(+) 17pF CIN(+) 0x000000...0xFFFFFF DATA ±4pF CIN(–) CAPDIFF = 1 CDC RGND1 CIN DATA CDC CAPDAC(–) CX CY 17pF 15 ... 19pF 15 ... 19pF (17±2pF) (17±2pF) FiguErXeC 34. Using CAPDAC in Differential Mode 05468-021 CX RGND2 EXC 05468-013 CAPDAC(+) 17pF Figure 37. Parasitic Resistance to Ground CIN(+) 0x000000...0xFFFFFF DATA The AD7745/AD7746 CDC result would be affected by a leak- ±4pF CIN(–) CAPDIFF = 1 CDC age current from the CX to ground, therefore the CX should be isolated from the ground. The influence of the leakage current CAPDAC(–) varies with the power supply voltage. The following limits can 17pF CX CY be used as a guideline for the allowed leakage current or the 13 ... 21pF 17pF (17±4pF) FiEgXuCre 35. Using CAPDAC in Differential Mode 05468-011 equivValDeDn ≈t r5e sVis: tIaGnNDc e< b 1e5t0w eneAn (tthhea tC iXs ,a RnGdN Dg r>o u30n dM (ΩFi)g ure 37). V ≥ 3 V: I < 60 nA (that is, R > 50 MΩ) DD GND GND PARASITIC CAPACITANCE TO GROUND V ≥ 2.7 V: I < 30 nA (that is, R > 100 MΩ) DD GND GND A higher leakage current to ground results in a gain error, an offset error, and a nonlinearity error. See the typical CGND1 CIN DATA performance characteristics shown in Figure 12 and Figure 13. CDC PARASITIC PARALLEL RESISTANCE CX CGND2 EXC 05468-012 CIN CDC DATA Figure 36. Parasitic Capacitance to Ground CX RP The CDC architecture used in the AD7745/AD7746 measures the capacitance C connected between the EXC pin and the X CafIfNec tp tihne. ICnD thCe orreysu, altn (ys ecea pFaicgiutaren c3e6 )C. P to ground should not EXC 05468-022 Figure 38. Parasitic Parallel Resistance The practical implementation of the circuitry in the chip The AD7745/AD7746 CDC measures the charge transfer implies certain limits and the result is gradually affected by between EXC pin and CIN pin. Any resistance connected in capacitance to ground. See the allowed capacitance to GND in parallel to the measured capacitance CX (see Figure 38), such as the specification table for CIN and excitation. Also see the the parasitic resistance of the sensor, also transfers charge. typical performance characteristics shown in Figure 9, Figure Therefore, the parallel resistor is seen as an additional 10, and Figure 11. capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as 1 C = P R ×F ×4 P EXC Where R is the parallel resistance and C is the excitation P EXC frequency. See the typical performance characteristics shown in Figure 14. Rev. 0 | Page 22 of 28

AD7745/AD7746 PARASITIC SERIAL RESISTANCE The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the host controller and reloaded as RS1 CIN DATA part of the AD7745/AD7746 setup. CDC On the AD7746, the register is shared by the two capacitive channels. If the capacitive channels need to be offset calibrated CX individually, the host controller software should read the AD7746 capacitive offset calibration register values after performing the offset calibration on individual channels and RS2 FiEgXuCre 39. Parasitic Serial Resistance 05468-023 tchoennv erresliooand othne a v dailfufeerse bnatc ckh taon tnheel. A D7746 before executing a The AD7745/AD7746 CDC result is affected by a resistance in INTERNAL TEMPERATURE SENSOR series with the measured capacitance. The total serial resistance, INTERNAL TEMPERATURE SENSOR which refers to RS1 + RS2 on Figure 39, should be less than 1 kΩ VDD I N×I for the specified performance. See typical performance charac- teristics shown in Figure 15. CLOCK GENERATOR CAPACITIVE GAIN CALIBRATION The AD7745/AD7746 gain is factory calibrated for the full scale DIGITAL DATA of ±4.096 pF in the production for each part individually. The ∆VBE M2O4D-BUILTAΣT-O∆R FIALNTDER factory gain coefficient is stored in a one-time programmable SCALING (OTP) memory and is copied to the capacitive gain register at VOLTAGE power-up or after reset. REFERENCE 05468-040 The gain can be changed by executing a capacitance gain Figure 40. Internal Temperature Sensor calibration mode, for which an external full-scale capacitance The temperature sensing method used in the AD7745/AD7746 needs to be connected to the capacitance input, or by writing a is to measure a difference in ∆V voltage of a transistor BE user value to the capacitive gain register. This change would be operated at two different currents (see Figure 40). The ∆V BE only temporary and the factory gain coefficient would be change with temperature is linear and can be expressed as reloaded back after power-up or reset. The part is tested and KT specified only for use with the default factory calibration ∆V =(n ) ×ln(N) BE f q coefficient. where: CAPACITIVE SYSTEM OFFSET CALIBRATION K is Boltzmann’s constant (1.38 × 10–23). The capacitive offset is dominated by the parasitic offset in the application, such as the initial capacitance of the sensor, any T is the absolute temperature in Kelvin. parasitic capacitance of tracks on the board, and the capacitance q is the charge on the electron (1.6 × 10–19 coulombs). of any other connections between the sensor and the CDC. N is the ratio of the two currents. Therefore, the AD7745/AD7746 are not factory calibrated for capacitive offset. It is the user’s responsibility to calibrate the nf is the ideality factor of the thermal diode. system capacitance offset in the application. The AD7745/AD7746 uses an on-chip transistor to measure the Any offset in the capacitance input larger than ±1 pF should temperature of the silicon chip inside the package. The Σ-Δ first be removed using the on-chip CAPDACs. The small offset ADC converts the ∆VBE to digital, the data are scaled using within ±1 pF can then be removed by using the capacitance factory calibration coefficients, thus the output code is offset calibration register. proportional to temperature: One method of adjusting the offset is to connect a zero-scale Code Temperature(°C)= −4096 capacitance to the input and execute the capacitance offset 2048 calibration mode. The calibration sets the midpoint of the The AD7745/AD7746 has a low power consumption resulting ±4.096 pF range (that is, Output Code 0x800000) to that in only a small effect due to the part self-heating (less than zero-scale input. 0.5°C at V = 5 V). DD Another method would be to calculate and write the offset cali- bration register value, the LSB is value 31.25 aF (4.096 pF/217). Rev. 0| Page 23 of 28

AD7745/AD7746 If the capacitive sensor can be considered to be at the same VOLTAGE INPUT temperature as the AD7745/AD7746 chip, the internal VDD temperature sensor can be used as a system temperature sensor. ANALOG TO DIGITAL CONVERTER That means the complete system temperature drift (ADC) compensation can be based on the AD7745/AD7746 internal temperature sensor without need for any additional external CLOCK components. See the typical performance characteristics in GENERATOR Figure 18. VIN(+) DATA EXTERNAL TEMPERATURE SENSOR RT RTD 24-BITΣ-∆ DIGITAL VIN(–) MODULATOR FILTER EXTERNAL VDD TEMPERATURE SENSOR I...N×I CLOCK REFIN(+) VOLTAGE GENERATOR RREF REFERENCE REFIN(–) 2N∆3V9B0E6 RRSS21 VVIINN((–+)) M2O4D-BUILTAΣT-O∆R DFIIAGLNTITDEARL DATA GND 05468-042 SCALING Figure 42. Resistive Temperature Sensor Connected to the Voltage Input The AD7745/AD7746 Σ-Δ core can work as a high resolution VOLTAGE REFERENCE 05468-041 (inuppu tto. T21h eE ANDOCB )c calna sbseic u AseDdC e iwthiethr wa iftuhl ltyh de ioffne-rcehnitpia hl vigohlt age Figure 41. Transistor as an External Temperature Sensor precision, low drift, 1.17 V voltage reference, or an external The AD7745/AD7746 provide the option of using an external reference connected to the fully differential reference input pins. transistor as a temperature sensor in the system. The ∆V BE method, which is similar to the internal temperature sensor The voltage and reference inputs are continuously sampled by a method, is used. However, it is modified to compensate for the Σ-Δ modulator during the conversion. Therefore, the input serial resistance of connections to the sensor. Total serial source impedance should be kept low. See the application resistance (R + R in Figure 41) up to 100 Ω is compensated. example in Figure 42. S1 S2 The VIN(–) pin must be grounded for proper external V MONITOR DD temperature sensor operation. Along with converting external voltages, the AD7745/AD7746 The AD7745/AD7746 are factory calibrated for Σ-Δ ADC can be used for monitoring the V voltage. The DD Transistor 2N3906 with the ideality factor nf = 1.008. voltage from the VDD pin is internally attenuated by 6. See the typical performance characteristics shown in Figure 19. TYPICAL APPLICATION DIAGRAM 3V/5V + POWER SUPPLY 0.1µF 10µF 10kΩ 10kΩ VDD TEMP CLOCK HOST SENSOR GENERATOR AD7745 SYSTEM VIN(+) SDA VIN(–) MUX 24-BITΣ-∆ DIGITAL I2C SERIAL CIN1(+) MODULATOR FILTER INTERFACE SCL CIN1(–) CONTROL LOGIC RDY CAP DAC CALIBRATION CAP DAC VOLTAGE EXCA EXCITATION REFERENCE EXCB REFIN(+) REFIN(–) GND 05468-008 Figure 43. Basic Application Diagram for a Differential Capacitive Sensor Rev. 0 | Page 24 of 28

AD7745/AD7746 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 6.40 4.40 BSC 4.30 1 8 PIN 1 1.20 MAX 0.15 0.20 0.05 0.09 0.75 0.30 8° 0.60 B0.S6C5 0.19 SPELAANTIENG 0° 0.45 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD7745ARUZ1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7745ARUZ-REEL1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7745ARUZ-REEL71 –40°C to +125°C 16-Lead TSSOP RU-16 AD7746ARUZ1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7746ARUZ-REEL1 –40°C to +125°C 16-Lead TSSOP RU-16 AD7746ARUZ-REEL71 –40°C to +125°C 16-Lead TSSOP RU-16 EVAL-AD7746EB Evaluation Board 1 Z = Pb-free part. Rev. 0 | Page 25 of 28

AD7745/AD7746 NOTES Rev. 0 | Page 26 of 28

AD7745/AD7746 NOTES Rev. 0 | Page 27 of 28

AD7745/AD7746 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C05468-0-4/05(0) Rev. 0 | Page 28 of 28