a +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC AD7303 FEATURES FUNCTIONAL BLOCK DIAGRAM Two 8-Bit DACs in One Package 8-Pin DIP/SOIC and microSOIC Packages AD7303 +2.7V to +5.5V Operation Internal & External Reference Capability REINGPISUTTER REGDIASCTER I DAC A I/V VOUT A Individual DAC Power-Down Function Three-Wire Serial Interface QSPI™, SPI™ and Microwire™ Compatible REINGPISUTTER REGDIASCTER I DAC B I/V VOUT B On-Chip Output Buffer Rail-to-Rail Operation DATA (8) CONTROL (8) MUX POWER ON On-Chip Control Register DIN RESET Low Power Operation: 2.3mA @ 3.3 V SCLK 16-BIT SHIFT REGISTER Full Power-Down to 1(cid:109)A max, typically 80nA SYNC ‚ 2 APPLICATIONS GND REF VDD Portable Battery Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7303 is a dual, 8-bit voltage out DAC that operates 1. Low power, single supply operation. This part operates from from a single +2.7V to +5.5V supply. Its on-chip precision out- a single +2.7 V to +5.5 V supply and consumes typically put buffers allow the DAC outputs to swing rail to rail. This de- 15 mW at 5.5 V, making it ideal for battery powered vice uses a versatile 3-wire serial interface that operates at clock applications. rates up to 30MHz, and is compatible with QSPI, SPI, microwire 2. The on-chip output buffer amplifiers allow the outputs of the and digital signal processor interface standards. The serial input DACs to swing rail to rail with a settling time of typically 1.2m s. register is sixteen bits wide; 8 bits act as data bits for the DACs, 3. Internal or external reference capability. and the remaining eight bits make up a control register. 4. High speed serial interface with clock rates up to 30 MHz. The on-chip control register is used to address the relevant DAC, to power down the complete device or an individual 5. Individual power-down of each DAC provided. When com- DAC, to select internal or external reference and to provide a pletely powered down, the DAC consumes typically 80nA. synchronous loading facility for simultaneous update of the DAC outputs with a software LDAC function. The low power consumption of this part makes it ideally suited to portable battery operated equipment. The power consump- tion is 7.5mW max at 3V, reducing to less than 3m W in full power-down mode. The AD7303 is available in an 8-pin plastic dual in-line pack- age, 8-lead SOIC and microSOIC packages. QSPI and SPI are trademarks of Motorola. Microwire is a trademark of National Semiconductor. REV.0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 617/329-4700 World Wide Web Site: http://www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 617/326-8703 © Analog Devices, Inc., 1997

AD7303–SPECIFICATIONS (V = +2.7 V to +5.5 V, Internal Reference; R = 10 k(cid:86) to V and GND; C = 100 pF DD L DD L to GND; all specifications T to T unless otherwise noted) MIN MAX Parameter B Versions1 Units Conditions/Comments STATIC PERFORMANCE Resolution 8 Bits Relative Accuracy – 1 LSB max Note 2 Differential Nonlinearity – 1 LSB max Guaranteed Monotonic Zero-Code Error @ +25(cid:176) C 3 LSB max All Zeros Loaded to DAC Register Full-Scale Error –0.5 LSB typ All Ones Loaded to DAC Register Gain Error3 +1 % FSR typ Zero-Code Temperature Coefficient 100 m V/(cid:176) C typ DAC REFERENCE INPUT REFIN Input Range 1 to V /2 V min to max DD REFIN Input Impedance 10 MW typ Internal Voltage Reference Error 4 – 1 % max OUTPUT CHARACTERISTICS Output Voltage Range 0 to V V min to max DD Output Voltage Settling Time 2 m s max Typically 1.2m s Slew Rate 7.5 V/m s typ Digital to Analog Glitch Impulse 0.5 nV-s typ 1 LSB Change Around Major Carry Digital Feedthrough 0.2 nV-s typ Digital Crosstalk 0.2 nV-s typ Analog Crosstalk – 0.2 LSB typ DC Output Impedance 40 W typ Short Circuit Current 14 mA typ Power Supply Rejection Ratio 0.0001 %/% max D V = – 10% DD LOGIC INPUTS Input Current – 10 m A max V , Input Low Voltage 0.8 V max V = +5 V INL DD 0.6 V max V = +3V DD V , Input High Voltage 2.4 V min V = +5 V INH DD 2.1 V min V = +3 V DD Pin Capacitance 5 pF max POWER REQUIREMENTS V 2.7/5.5 V min/max DD I (Normal Mode) Both DACs Active and Excluding Load Currents, DD V = 3.3 V V = V , V = GND DD IH DD IL @ +25(cid:176) C 2.1 mA max See Figure 8 T – T 2.3 mA max MIN MAX V = 5.5 V DD @ +25(cid:176) C 2.7 mA max T – T 3.5 mA max MIN MAX I (Full Power-Down) DD @ +25(cid:176) C 80 nA typ V = V , V = GND IH DD IL T – T 1 m A max See Figure 19 MIN MAX NOTES 1Temperature ranges are as follows: B Version, –40(cid:176)C to +105(cid:176)C. 2Relative Accuracy is calculated using a reduced digital code range of 15 to 245. 3Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB. 4Internal Voltage Reference Error = (Actual V – Ideal V /Ideal V ) • 100. Ideal V = V /2, actual V = voltage on reference pin when internal reference REF REF REF REF DD REF is selected. Specifications subject to change without notice. ORDERING GUIDE Temperature Package Model Range Options* AD7303BN –40(cid:176) C to +105(cid:176) C N-8 AD7303BR –40(cid:176) C to +105(cid:176) C SO-8 AD7303BRM –40(cid:176) C to +105(cid:176) C RM-8 *N = Plastic DIP; R = SOIC; RM = microSOIC. –2– REV. 0

AD7303 (V = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal V /2 Reference; all specifications TIMING CHARACTERISTICS1, 2 DD DD T to T unless otherwise noted) MIN MAX Parameter Limit at T , T (B Version) Units Conditions/Comments MIN MAX t 33 ns min SCLK Cycle Time 1 t 13 ns min SCLK High Time 2 t 13 ns min SCLK Low Time 3 t 5 ns min SYNC Setup Time 4 t 5 ns min Data Setup Time 5 t 4.5 ns min Data Hold Time 6 t 4.5 ns min SYNC Hold Time 7 t 33 ns min Minimum SYNC High Time 8 NOTES 1Sample tested at +25(cid:176)C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V ) and timed from a voltage level of (V + V )/2, DD IL IH tr and tf should not exceed 1m s on any input. 2See Figures 1 and 2. t1 SCLK (I) t2 t3 t7 t8 t4 t4 SYNC (I) t5 t6 DIN (I) DB15 DB0 Figure 1.Timing Diagram for Continuous 16-Bit Write t1 SCLK (I) t2 t3 t8 t4 t7 SYNC (I) t5 t5 t6 t6 DIN (I) DB15 DB8 DB7 DB0 Figure 2.Timing Diagram for 2 · 8-Bit Writes REV. 0 –3–

AD7303 ABSOLUTE MAXIMUM RATINGS* SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW (TA = +25(cid:176)C unless otherwise noted) q JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 157(cid:176) C/W V to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Lead Temperature, Soldering DD Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215(cid:176) C Reference Input Voltage to GND . . . . –0.3 V to V + 0.3V DD Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220(cid:176) C Digital Input Voltage to GND . . . . . . . –0.3 V to V + 0.3 V DD MicroSOIC Package, Power Dissipation . . . . . . . . . . 450 mW V A, V B to GND . . . . . . . . . . . –0.3 V to V + 0.3 V OOpUeTrating OTUeTmperature Range DD q JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206(cid:176) C/W Commercial (B Version) . . . . . . . . . . . . . –40(cid:176) C to +105(cid:176) C Lead Temperature, Soldering Storage Temperature Range . . . . . . . . . . . . –65(cid:176) C to +150(cid:176) C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215(cid:176) C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150(cid:176) C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220(cid:176) C Plastic DIP Package, Power Dissipation . . . . . . . . . . 800 mW *Stresses above those listed under “Absolute Maximum Ratings” may cause q Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 117(cid:176) C/W permanent damage to the device. This is a stress rating only; functional operation JA Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260(cid:176) C of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD7303 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE PIN CONFIGURATIONS (DIP, SOIC and microSOIC) VOUT A 1 8 VOUT B VDD 2 AD7303 7 SYNC GND 3 TOP VIEW 6 DIN (Not to Scale) REF 4 5 SCLK PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 V A Analog Output Voltage from DAC A. The output amplifier swings rail to rail on its output. OUT 2 V Power Supply Input. These parts can be operated from +2.7 V to +5.5 V and should be decoupled to GND. DD 3 GND Ground reference point for all circuitry on the part. 4 REF External Reference Input. This can be used as the reference for both DACs, and is selected by setting the INT/EXT bit in the control register to a logic one. The range on this reference input is 1 V to V /2. When DD the internal reference is selected, this voltage will appear as an output for decoupling purposes at the REF Pin. When using the internal reference, external voltages should not be connected to the REF Pin, see Figure 21. 5 SCLK Serial Clock. Logic Input. Data is clocked into the input shift register on the rising edge of the serial clock input. Data can be transferred at rates up to 30 MHz. 6 DIN Serial Data Input. This device has a 16-bit shift register, 8 bits for data and 8 bits for control. Data is clocked into the register on the rising edge of the clock input. 7 SYNC Level Triggered Control Input (active low). This is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register and data is transferred in on the rising edges of the following clocks. The rising edge of the SYNC causes the relevant registers to be updated. 8 V B Analog output voltage from DAC B. The output amplifier swings rail to rail on its output. OUT –4– REV. 0

AD7303 TERMINOLOGY DIGITAL-TO-ANALOG GLITCH IMPULSE INTEGRAL NONLINEARITY Digital-to-analog glitch impulse is the impulse injected into the For the DACs, relative accuracy or endpoint nonlinearity is a analog output when the digital inputs change state with the measure of the maximum deviation, in LSBs, from a straight DAC selected and the software LDAC used to update the DAC. line passing through the endpoints of the DAC transfer func- It is normally specified as the area of the glitch in nV-s and is tion. A graphical representation of the transfer curve is shown measured when the digital input code is changed by 1 LSB at in Figure 15. the major carry transition. DIFFERENTIAL NONLINEARITY DIGITAL FEEDTHROUGH Differential nonlinearity is the difference between the measured Digital feedthrough is a measure of the impulse injected into the change and the ideal 1 LSB change of any two adjacent codes. A analog output of a DAC from the digital inputs of the same specified differential nonlinearity of – 1 LSB maximum ensures DAC, but is measured when the DAC is not updated. It is monotonicity. specified in nV-s and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. ZERO CODE ERROR Zero code error is the measured output voltage from V of DIGITAL CROSSTALK OUT either DAC when zero code (all zeros) is loaded to the DAC Digital crosstalk is the glitch impulse transferred to the output latch. It is due to a combination of the offset errors in the DAC of one converter due to a digital code change to another DAC. and output amplifier. Zero-scale error is expressed in LSBs. It is specified in nV-s. GAIN ERROR ANALOG CROSSTALK This is a measure of the span error of the DAC. It is the devia- Analog crosstalk is a change in output of any DAC in response tion in slope of the DAC transfer characteristic from ideal to a change in the output of the other DAC. It is measured in expressed as a percent of the full-scale value. Gain error is calcu- LSBs. lated between Codes 15 and 245. POWER SUPPLY REJECTION RATIO (PSRR) FULL-SCALE ERROR This specification indicates how the output of the DAC is Full-Scale Error is a measure of the output error when the DAC affected by changes in the power supply voltage. Power supply latch is loaded with FF Hex. Full-scale error includes the offset rejection ratio is quoted in terms of % change in output per % error. of change in V for full-scale output of the DAC. V is varied DD DD – 10%. This specification applies to an external reference only because the output voltage will track the V voltage when in- DD ternal reference is selected. REV. 0 –5–

AD7303–Typical Performance Characteristics 800 5 3.5 720 VDD = +5V AND +3V 4.92 3.25 INTERNAL REFERENCE 640 TA = 25(cid:56)C 4.84 3 560 DAC LOADED WITH 00HEX 4.76 2.75 V – mVOUT434028000 – VoltsOUT 444..65.682 V– VoltsOUT 22.2.255 IVNDTDE =R N+3AVL REFERENCE 249 V4.44 1.75 DAC REGISTER LOADED WITH FFHEX 160 4.36 IVNDTDE =R N+5AVL REFERENCE 1.5 TA = 25(cid:176)C 80 4.28 DTAA C= 2R5E(cid:176)GCISTER LOADED WITH FFHEX 1.25 0 4.2 1 0 2 4 6 8 0 2 4 6 8 0 1 2 3 4 5 6 7 8 SINK CURRENT – mA SOURCE CURRENT – mA SOURCE CURRENT – mA Figure 3.Output Sink Current Capa- Figure 4.Output Source Current Figure 5.Output Source Current bility with VDD = 3 V and VDD = 5 V Capability with VDD = 5 V Capability with VDD = 3 V 0.5 5 5.5 00.4.45 TVAD D= =2 5+(cid:56)5CV 4.5 LOGIC INPUTS = VIH OR VIL 5 INTERNAL REFERENCE 4.5 TA = 25(cid:176)C 0.35 RROR – LSBs 000.2..235 INL ERROR I – mADD3.45 IVNDTDE =R N+5AVL REFERENCE I – mADD3.345 LOGIC INPUTS = VIH OR VIL E 0.15 3 DNL ERROR 2.5 0.1 2.5 LOGIC INPUTS = VDD OR GND 2 0.05 LOGIC INPUTS = VDD OR GND 0 2 1.5 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 –60–40–20 0 20 40 60 80 100120 140 2.5 3 3.5 4 4.5 5 5.5 REFERENCE VOLTAGE – Volts TEMPERATURE – (cid:56)C VDD – Volts Figure 6.Relative Accuracy vs. Figure 7.Supply Current vs. Figure 8.Supply Current vs. External Reference Temperature Supply Voltage 10 POWER UP TIME 5 VDD = +5V T INTERNAL REFERENCE 0 SYNC VDD = +3V BOTH DACS IN POWER DOWN INITIALLY 1 INTERNAL VOLTAGE REFERENCE dB –5 FULL SCALE CODE CHANGE 00H-FFH SYNC N – –10 TA = 25(cid:176)C 2 O 2 TI–15 NUA–20 EVXDTDE =R +N5AVL SINE WAVE REFERENCE VOUT ATTE–25 DTAA C= 2R5E(cid:176)GCISTER LOADED WITH FFHEX VOUT –30 VOUT 1 –35 3 –40 1 10 100 1000 10000 FREQUENCY – kHz CH1 5V, CH2 1V, CH3 20mV CH1 = 2V/div, CH2 = 5V/div, TIME BASE = 200ns/div TIME BASE = 2µs/div Figure 9.Large Scale Signal Figure 10.Full-Scale Settling Time Figure 11.Exiting Power-Down (Full Frequency Response Power-Down) –6– REV. 0

AD7303 7 VDD = +5V INTERNAL REFERENCE 6 T TA = 25(cid:56)C SYNC VDD = +5V 1 INTERNAL VOLTAGE DAC A = NORMAL OPERATION‹ 5 REFERENCE SYNC 2 DAC B INITIALLY IN POWER 10 LSB STEP CHANGE DOWN mA 4 VDD = +5V TA = 25(cid:56)C – DAC B EXITING I DD3 VOUT VOUT B POWER DOWN 2 1 VDD = +3V 1 2 0 CH1 2V, CH2 5V, M 500ns 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 CH1 5.00V, CH2 50.0mV, M 250ns Figure 12.Exiting Power-Down Figure 13.Supply Current vs. Figure 14.Small Scale Settling (Partial Power-Down) Logic Input Voltage Time 0.5 0.5 0.5 0.4 VINDTDE =R +N5AVL REFERENCE 0.4 0.4 0.3 5kW 100pF LOAD 0.3 0.3 LIMITED CODE RANGE (10-245) 0.2 TA = 25(cid:176)C B 0.2 B 0.2 OR – LSB 0.01 DAC A ROR – LS 0.01 VINDTDE =R +N5AVL REFERENCE ROR – LS 0.01 VINDTDE =R +N5AVL REFERENCE NL ERR––00..12 DAC B INL ER––00..12 DNL ER––00..12 I –0.3 –0.3 –0.3 –0.4 –0.4 –0.4 –0.5 –0.5 –0.5 0 32 64 96 128 160 192 224 255 –60–40–20 0 20 40 60 80 100120140 –60–40–20 0 20 40 60 80 100120140 Input Code (10 to 245) TEMPERATURE – (cid:56)C TEMPERATURE – (cid:56)C Figure 15.Integral Linearity Plot Figure 16.Typical INL vs. Figure 17.Typical DNL vs. Temperature Temperature 500 1.0 A (cid:54)%0.8 T – n400 VDD = +5.5V OR – VDD = +5V RREN300 VIL AND VIH = 0V OR VDD RR0.6 CU E E WN RENC0.4 R-DO200 E E F W T RE0.2 PO100 N I 0 –50 –25 0 25 50 75 100 125 150 0 –60–40–20 0 20 40 60 80 100120140 TEMPERATURE – (cid:56)C TEMPERATURE – (cid:56)C Figure 18.Typical Internal Reference Figure 19.Power-Down Current vs. Error vs. Temperature Temperature REV. 0 –7–

AD7303 GENERAL DESCRIPTION reference appears at the reference pin as an output voltage for D/A Section decoupling purposes. When using the internal reference, external The AD7303 is a dual 8-bit voltage output digital-to-analog references should not be connected to the REF pin. If external ref- converter. The architecture consists of a reference amplifier and erence is selected, both switches are open and the externally a current source DAC, followed by a current-to-voltage con- applied voltage to the REF pin is applied to the reference amplifier. verter capable of generating rail-to-rail voltages on the output of Decoupling capacitors applied to the REF pin decouple both the DAC. Figure 20 shows a block diagram of the basic DAC the internal reference and external reference. In noisy environ- architecture. ments it is recommended that a 0.1 m F capacitor be connected to the REF pin to provide added decoupling even when the in- VDD REFERENCE AD7303 11.7kW ternal reference is selected. AMPLIFIER 30kW Analog Outputs CURRENT The AD7303 contains two independent voltage output DACs REF DAC VO A/B with 8-bit resolution and rail-to-rail operation. The output buffer 11.7kW provides a gain of two at the output. Figures 3 to 5 show the sink 30kW OUTPUT AMPLIFIER and source capabilities of the output amplifier. The slew rate of the output amplifier is typically 8 V/m s and has a full-scale settling to 8 bits with a 100pF capacitive load in typically 1.2 m s. Figure 20.DAC Architecture The input coding to the DAC is straight binary. Table I shows the binary transfer function for the AD7303. Figure 22 shows Both DAC A and DAC B outputs are internally buffered and the DAC transfer function for binary coding. Any DAC output these output buffer amplifiers have rail-to-rail output character- voltage can ideally be expressed as: istics. The output amplifier is capable of driving a load of 10 kW to both V and ground and 100pF to ground. The reference VOUT = 2 · VREF (N/256) DD where: selection for the DAC can be either internally generated from V or externally applied through the REF pin. Reference N is the decimal equivalent of the binary input code. DD selection is via a bit in the control register. The range on the N ranges from 0 to 255. external reference input is from 1.0 V to VDD/2. The output VREF is the voltage applied to the external REF pin when voltage from either DAC is given by: the external reference is selected and is V /2 if the DD V A/B = 2 · V · (N/256) internal reference is used. O REF where: Table I. Binary Code Table for AD7303 DAC V is the voltage applied to the external REF pin or REF VDD/2 when the internal reference is selected. Digital Input N is the decimal equivalent of the code loaded to the DAC MSB . . . LSB Analog Output register and ranges from 0 to 255. 1111 1111 2 · 255/256 · V V REF Reference 1111 1110 2 · 254/256 · VREF V The AD7303 has the facility to use either an external reference 1000 0001 2 · 129/256 · VREF V applied through the REF pin or an internal reference generated 1000 0000 VREF V from VDD. Figure 21 shows the reference input arrangement 0111 1111 2 · 127/256 · VREF V where the internal VDD/2 has been selected. 0000 0001 2 · VREF/256V 0000 0000 0 V VDD AD7303 2.VREF 30kW INT/EXT REF E G A 0.1µF LT O REFERENCE V 30kW AMPLIFIER PUT VREF T U O C A D Figure 21.Reference Input When the internal reference is selected during the write to the 0 DAC, both switches are closed and V /2 is generated and DD applied to the reference amplifier. This internal V /2 reference DD DAC INPUT 00 01 7F 80 81 FE FF appears at the reference pin as an output voltage for decoupling CODE purposes. When using the internal reference, external references should not be connected to the REF Pin. This internal V /2 DD Figure 22.DAC Transfer Function –8– REV. 0

AD7303 SERIAL INTERFACE grammed to transfer data in 16-bit words. After clocking all six- The AD7303 contains a versatile 3-wire serial interface that is teen bits to the shift register, the rising edge of SYNC executes compatible with SPI, QSPI and Microwire interface stan- the programmed function. The DACs are double buffered dards as well as a host of digital signal processors. An active which allows their outputs to be simultaneously updated. low SYNC enables the shift register to receive data from the serial data input DIN. Data is clocked into the shift register on INPUT SHIFT REGISTER DESCRIPTION the rising edge of the serial clock. The serial clock frequency The input shift register is 16 bits wide. The first eight bits con- can be as high as 30 MHz. This shift register is 16 bits wide as sist of control bits and the last eight bits are data bits. Figure 23 shown in Figures 23 and 24. The first eight bits are control bits shows a block diagram of the logic interface on the AD7303 and the second eight bits are data bits for the DACs. Each DAC. The seven bits in the control word are taken from the in- transfer must consist of a 16-bit transfer. Data is sent MSB first put shift register to a latch sequencer that decodes this data and and can be transmitted in one 16-bit write or two 8-bit writes. provides output signals that control the data transfers to the in- SPI and Microwire interfaces output data in 8-bit bytes and put and data registers of the selected DAC, as well as output thus require two 8-bit transfers. In this case the SYNC input to updating and various power-down features associated with the the DAC should remain low until all sixteen bits have been control section. A description of all bits contained in the input transferred to the shift register. QSPI interfaces can be pro- shift register is given below. MSB INT/EXT SYNC DAC A POWER-DOWN X DAC B POWER-DOWN DAC A BIAS BANDGAP LDAC SEQLAUTECNHCER BANDGAP POWER-DOWN BIAS GEN DAC B BIAS 7 PDB REF SELECTOR PDA LATCH & CLK DRIVERS ER A/B 16 REFEINRTENCE REF GIST CR1 CSUWRIRTECNHT RSWESITISCTHOR RE CR0 CLOCK BUS T HIF DB7 BIT S DB6 8 REINGPISUTTER 8 D8E CTOOD 3E2R 30 REGDIASCTER 30 DAC A VOUT A 16- DB5 DB4 8 DB3 DB2 DB1 8 REINGPISUTTER 8 D8E CTOOD 3E2R 30 REGDIASCTER 30 DAC B VOUT B LSB DB0 SYNC SCLK DIN Figure 23.Logic Interface on the AD7303 REV. 0 –9–

AD7303 DB15 (MSB) DB0 (LSB) INT/EXT X LDAC PDB PBA A/B CR1 CR0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 |––––––––––––––––––––––––– Control Bits –––––––––––––––––––––––––|––––––––––––––––––––––––– Data Bits –––––––––––––––––––––––––| Figure 24.Input Shift Register Contents Bit Location Mnemonic Description DB15 INT/EXT Selects between internal and external reference. DB14 X Uncommitted bit. DB13 LDAC Load DAC bit for synchronous update of DAC outputs. DB12 PDB Power-down DAC B. DB11 PDA Power-down DAC A. DB10 A/B Address bit to select either DAC A or DAC B. DB9 CR1 Control Bit 1 used in conjunction with CR0 to implement the various data loading functions. DB8 CR0 Control Bit 0 used in conjunction with CR1 to implement the various data loading functions. DB7–DB0 Data These bits contain the data used to update the output of the DACs. DB7 is the MSB and DB0 the LSB of the 8-bit data word. CONTROL BITS LDAC A/B CR1 CR0 Function Implemented 0 X 0 0 Both DAC registers loaded from shift register. 0 0 0 1 Update DAC A input register from shift register. 0 1 0 1 Update DAC B input register from shift register. 0 0 1 0 Update DAC A DAC register from input register. 0 1 1 0 Update DAC B DAC register from input register. 0 0 1 1 Update DAC A DAC register from shift register. 0 1 1 1 Update DAC B DAC register from shift register. 1 0 X X Load DAC A input register from shift register and update both DAC A and DAC B DAC registers. 1 1 X X Load DAC B input register from shift register and update both DAC A and DAC B DAC registers outputs. INT/EXT Function 0 Internal V /2 reference selected. DD 1 External reference selected; this external reference is applied at the REF pin and ranges from 1 V to V /2. DD PDA PDB Function 0 0 Both DACs active. 0 1 DAC A active and DAC B in power-down mode. 1 0 DAC A in power-down mode and DAC B active. 1 1 Both DACs powered down. –10– REV. 0

AD7303 POWER-ON RESET AD7303 to 68HC11/68L11 Interface The AD7303 has a power-on reset circuit designed to allow output Figure 27 shows a serial interface between the AD7303 and the stability during power-up. This circuit holds the DACs in a reset 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 state until a write takes place to the DAC. In the reset state all zeros drives the CLKIN of the AD7303, while the MOSI output are latched into the input registers of each DAC, and the DAC reg- drives the serial data line of the DAC. The SYNC signal is isters are in transparent mode. Thus the output of both DACs are derived from a port line (PC7). The setup conditions for cor- held at ground potential until a write takes place to the DAC. rect operation of this interface are as follows: the 68HC11/ 68L11 should be configured so that its CPOL bit is a 0 and its POWER-DOWN FEATURES CPHA bit is a 0. When data is being transmitted to the DAC, Two bits in the control section of the 16-bit input word are used to the SYNC line is taken low (PC7). When the 68HC11/68L11 is put the AD7303 into low power mode. DAC A and DAC B can be configured as above, data appearing on the MOSI output is powered down separately. When both DACs are powered down, valid on the rising edge of SCK. Serial data from the 68HC11/ the current consumption of the device is reduced to less than 1 m A, 68L11 is transmitted in 8-bit bytes with only eight falling clock making the device suitable for use in portable battery powered edges occurring in the transmit cycle. Data is transmitted MSB equipment. The reference bias servo loop, the output amplifiers first. In order to load data to the AD7303, PC7 is left low after and associated linear circuitry are all shut down when the power- the first eight bits are transferred, and a second serial write op- down is activated. The output sees a load of approximately 23 kW eration is performed to the DAC and PC7 is taken high at the to GND when in power-down mode as shown in Figure 25. The end of this procedure. contents of the data registers are unaffected when in power-down mode. The time to exit power-down is determined by the nature of the power-down, if the device is fully powered down the bias gen- 68HC11/68L11* AD7303* erator is also powered down and the device takes typically 13 m s to exit power-down mode. If the device is only partially powered PC7 SYNC down, i.e., only one channel powered down, in this case the bias SCK SCLK generator is active and the time required for the power-down chan- nel to exit this mode is typically 1.6 m s. See Figures 11 and 12. MOSI DIN VDD *ADDITIONAL PINS OMITTED FOR CLARITY 11.7kW Figure 27.AD7303 to 68HC11/68L11 Interface AD7303 to 80C51/80L51 Interface IDAC VO A/B Figure 28 shows a serial interface between the AD7303 and the 11.7kW 80C51/80L51 microcontroller. The setup for the interface is as VREF follows: TXD of the 80C51/80L51 drives SCLK of the AD7303, while RXD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case port line P3.3 is used. When data is to be transmit- Figure 25.Output Stage During Power-Down ted to the AD7303, P3.3 is taken low. The 80C51/80L51 trans- mits data only in 8-bit bytes; thus only eight falling clock edges MICROPROCESSOR INTERFACING occur in the transmit cycle. To load data to the DAC, P3.3 is AD7303 to ADSP-2101/ADSP-2103 Interface left low after the first eight bits are transmitted, and a second Figure 26 shows a serial interface between the AD7303 and the write cycle is initiated to transmit the second byte of data. P3.3 ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should is taken high following the completion of this cycle. The 80C51/ be set up to operate in the SPORT Transmit Alternate Framing 80L51 outputs the serial data in a format which has the LSB Mode. The ADSP-2101/ADSP-2103 SPORT is programmed first. The AD7303 requires its data with the MSB as the first bit through the SPORT control register and should be configured received. The 80C51/80L51 transmit routine should take this as follows: Internal Clock Operation, Active Low Framing, into account. 16-Bit Word Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each falling edge of the serial clock and clocked 80C51/80L51* AD7303* into the AD7303 on the rising edge of the SCLK. P3.3 SYNC TXD SCLK ADSP-2101/ AD7303* RXD SDIN ADSP-2103* TFS SYNC *ADDITIONAL PINS OMITTED FOR CLARITY DT DIN Figure 28.AD7303 to 80C51/80L51 Interface SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY Figure 26.AD7303 to ADSP-2101/ADSP-2103 Interface REV. 0 –11–

AD7303 AD7303 to Microwire Interface Bipolar Operation Using the AD7303 Figure 29 shows an interface between the AD7303 and any The AD7303 has been designed for single supply operation, but microwire compatible device. Serial data is shifted out on the bipolar operation is achievable using the circuit shown in Figure falling edge of the serial clock and is clocked into the AD7303 31. The circuit shown has been configured to achieve an output on the rising edge of the SK. voltage range of –5V < V < +5 V. Rail-to-rail operation at the O amplifier output is achievable using an AD820 or OP295 as the output amplifier. MICROWIRE* AD7303* VDD = +5V CS SYNC R4 20kW SK SCLK 0.1µF 10µF R3 +5V SO DIN 10kW VIN – 5V *ADDITIONAL PINS OMITTED FOR CLARITY EXT VDD Figure 29.AD7303 to Microwire Interface REGFNDVOUT 0.1µF REFAD7303 R1 –5V 10kW APPLICATIONS SCLK VOUTA Typical Application Circuit AD780/ REF192 DIN R2 Figure 30 shows a typical setup for the AD7303 when using an WITH VDD = +5V SYNC 20kW OR GND external reference. The reference range for the AD7303 is from AD589 WITH VDD = +3V 1V to V /2 V. Higher values of reference can be incorporated DD SERIAL but will saturate the output at both the top and bottom end of INTERFACE the transfer function. From input to output on the AD7303 there is a gain of two. Suitable references for 5V operation are Figure 31.Bipolar Operation Using the AD7303 the AD780 and REF192. For 3 V operation, a suitable external The output voltage for any input code can be calculated as reference would be the AD589, a 1.23 V bandgap reference. follows: V = [(1+R4/R3)*(R2/(R1+R2)*(2*V *D/256)] – R4*V /R3 VDD = +3V TO +5V O REF REF where D is the decimal equivalent of the code loaded to the DAC 0.1µF 10µF and V is the reference voltage input. VIN REF ERXETF VOUT REF VDD With VREF = 2.5 V, R1 = R3 = 10kW and R2 = R4 = 20K and GND 0.1µF VOUTA VDD = 5V. AD7303 V = (10 · D/256) – 5 OUT SCLK Opto-Isolated Interface for Process Control Applications AD780/ REF192 DIN VOUTB The AD7303 has a versatile 3-wire serial interface making it WITH VODRD = +5V SYNC GND ideal for generating accurate voltages in process control and AD589 WITH VDD = +3V industrial applications. Due to noise, safety requirements or dis- SERIAL tance, it may be necessary to isolate the AD7303 from the con- INTERFACE troller. This can easily be achieved by using opto-isolators, Figure 30.AD7303 Using External Reference which will provide isolation in excess of 3kV. The serial loading structure of the AD7303 makes it ideally suited for use in opto- The AD7303 can also be used with its own internally derived isolated applications. Figure 32 shows an opto-isolated interface V /2 reference. Reference selection is through the INT/EXT DD to the AD7303 where DIN, SCLK and SYNC are driven from bit of the 16-bit input word. The internal reference, when opto-couplers. In this application the reference for the AD7303 selected, is also provided as an output at the REF pin and can is the internal V /2 reference. It is being decoupled at the REF be decoupled at this point with a 0.1m F capacitor for noise DD pin with a 0.1m F ceramic capacitor for noise reduction purposes. reduction purposes. AC references can also be applied as exter- nal references to the AD7303. The AD7303 has limited multi- plying capability, and a multiplying bandwidth of up to 10kHz is achievable. –12– REV. 0

AD7303 AD7303 as a Digitally Programmable Window Detector +5V REGULATOR A digitally programmable upper/lower limit detector using the POWER 10µF 0.1µF two DACs in the AD7303 is shown in Figure 34. The upper and lower limits for the test are loaded to DACs A and B which, VDD in turn, set the limits on the CMP04. If a signal at the V input IN 10kW is not within the programmed window, a led will indicate the fail VDD condition. SCLK SCLK REF 0.1µF +5V VDD AD7303 0.1µF 10µF VIN 1kW 1kW 10kW FAIL PASS SYNC SYNC VOUTA VDD REF 0.1µF VOUTA VDD VOUTB AD7303 1/2 10kW SYNC SYNC CMP04 PASS/FAIL DATA DIN DIN DIN AGND SCLK SCLK VOUTB 1/6 74HC05 GND Figure 32. AD7303 in Opto-Isolated Interface Figure 34. Window Detector Using AD7303 Decoding Multiple AD7303 Programmable Current Source The SYNC pin on the AD7303 can be used in applications to Figure 35 shows the AD7303 used as the control element of a decode a number of DACs. In this application, all DACs in the programmable current source. In this circuit, the full-scale cur- system receive the same serial clock and serial data, but only the rent is set to 1mA. The output voltage from the DAC is applied SYNC to one of the DACs will be active at any one time allow- across the current setting resistor of 4.7kW in series with the ing access to two channels in this eight-channel system. The full-scale setting resistor of 470W . Suitable transistors to place 74HC139 is used as a 2- to 4-line decoder to address any of the in the feedback loop of the amplifier include the BC107 and the DACs in the system. To prevent timing errors from occurring, 2N3904, which enable the current source to operate from a min the enable input should be brought to its inactive state while the V of 6 V. The operating range is determined by the oper- SOURCE coded address inputs are changing state. Figure 33 shows a dia- ating characteristics of the transistor. Suitable amplifiers in- gram of a typical setup for decoding multiple AD7303 devices in clude the AD820 and the OP295, both having rail-to-rail a system. operation on their outputs. The current for any digital input code can be calculated as follows: AD7303 I = 2 · V · D/(5E + 3 · 256) mA SCLK REF SYNC DIN DIN VDD = +5V VDD SCLK VCC 0.1µF 10µF VSOURCE ENABLE 1G 1Y0 AD7303 ADCDORDEESDS 11BA 11YY21 SDYINNC ERXETFVINVOUT REF VDDVOUTA +5V LOAD 74HC139 1Y3 SCLK GND 0.1µF AD7303 AODP822905/ DGND SCLK 4.7kW AD7303 AD780/ REF192 DIN SYNC WITH VDD = +5V SYNC DIN GND 470W SCLK SERIAL INTERFACE AD7303 SYNC Figure 35.Programmable Current Source DIN SCLK Figure 33.Decoding Multiple AD7303 Devices in a System REV. 0 –13–

AD7303 Power Supply Bypassing and Grounding Inductance (ESI), like the common ceramic types that provide a In any circuit where accuracy is important, careful consideration low impedance path to ground at high frequencies to handle of the power supply and ground return layout helps to ensure transient currents due to internal logic switching. the rated performance. The printed circuit board on which the The power supply lines of the AD7303 should use as large a AD7303 is mounted should be designed so that the analog and trace as possible to provide low impedance paths and reduce the digital sections are separated, and confined to certain areas of effects of glitches on the power supply line. Fast switching sig- the board. If the AD7303 is in a system where multiple nals such as clocks should be shielded with digital ground to devices require an AGND to DGND connection, the connec- avoid radiating noise to other parts of the board, and should tion should be made at one point only. The star ground point never be run near the reference inputs. Avoid crossover of digi- should be established as closely as possible to the AD7303. The tal and analog signals. Traces on opposite sides of the board AD7303 should have ample supply bypassing of 10 m F in paral- should run at right angles to each other. This reduces the effects of lel with 0.1m F on the supply located as closely to the package as feedthrough through the board. A microstrip technique is by far possible, ideally right up against the device. The 10 m F capaci- the best, but not always possible with a double-sided board. In tors are the tantalum bead type. The 0.1 m F capacitor should this technique, the component side of the board is dedicated to have low Effective Series Resistance (ESR) and Effective Series ground plane while signal traces are placed on the solder side. AD7303 to 68HC11 Interface Program Source Code * PORTC EQU $1003 Port C Control Register * "SYNC, 0, 0, 0, 0, 0, 0, 0" DDRC EQU $1007 Port C Data Direction PORTD EQU $1008 Port D Data Register * "0, 0, 0, SCLK, DIN, 0, 0, 0" DDRD EQU $1009 Port D Data Direction SPCR EQU $1028 SPI Control Register * "SPIE, SPE, DWOM, MSTR, CPOL, CPHA, SPR1, SPR0" SPSR EQU $1029 SPI Status Register * "SPIF, WCOL, 0, MODF, 0, 0, 0, 0" SPDR EQU $102A SPI Data Register, Read Buffer, Write Shifter * * SDI RAM Variables: DIN 1 is eight MSBs, Control BYTE DIN 2 is eight LSBs, Data BYTE DAC requires 2*8-bit Writes DIN1 EQU $00 DIN BYTE 1: " INT/EXT, X, LDAC, PDB, PBA, A/B, CR1, CR0" DIN2 EQU $01 DIN BYTE 2: " DB7, DB6, DB5, DB4, DB3, DB2, DB1, DB0" * ORG $C000 Start of users ram INIT LDS #$CFFF Top of C page Ram * LDAA #$80 1, 0, 0, 0, 0, 0, 0, 0 * SYNC is High STAA PORTC Initialize Port C Outputs LDAA #$80 1, 0, 0, 0, 0, 0, 0, 0 STAA DDRC SYNC enabled as output * LDAA #$00 0, 0, 0, 0, 0, 0, 0, 0 * SCLK is low, DIN is low STAA PORTD Initialize Port D outputs –14– REV. 0

AD7303 LDAA #$18 0, 0, 0, 1, 1, 0, 0, 0 * SCLK and DIN enabled as outputs LDAA #$53 STAA SPCR SPI on, Master mode, CPOL=0, CPHA=0, Clock rate =E/32 * BSR UPDATE Update AD7303 output. JMP #$E000 Restart. * UPDATE PSHX Save relevant registers. PSHY PSHA * LDAA #$00 Control Word "0, 0, 0, 0, 0, 0, 0, 0" STAA DIN 1 Load both DAC A and DAC B DAC registers from shift register with internal reference selected. LDAA #$AA Data Word "1, 0, 1, 0, 1, 0, 1, 0" STAA DIN 2 * LDX #DIN1 Stack pointer at first first byte to send via DIN 1. LDY #$1000 Stack pointer at on chip registers. * BCLR PORTC,Y $80 Assert SYNC. TRANSFER LDAA 0,X Get BYTE to transfer via SPI. STAA SPDR Write to DIN register to start transfer. * WAIT LDAA SPSR Wait for SPIF to be set to indicate that transfer has been completed. BPL WAIT SPIF is the MSB of the SPCR. SPIF is automatically reset if in a set state when the status register is read. * INX Increment counter for transfer of second byte. CPX #DIN 2+1 16 bits transferred? BNE TRANSFER If not, transfer second BYTE. *Execute instruction BSET PORTC,Y $80 Bring SYNC back high. PULA Restore registers. PULY PULX RTS Return to main program. REV. 0 –15–

AD7303 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Pin Plastic DIP (N-8) 0.430 (10.92) 7 0.348 (8.84) 1/9 – 8 5 12 0.280 (7.11) – 0.240 (6.10) 24 1 4 0.325 (8.25) 22 0.300 (7.62) C PIN 1 0.060 (1.52) 0.210 (5.33) 0.015 (0.38) 0.195 (4.95) MAX 0.130 0.115 (2.93) 0.160 (4.06) (3.30) 0.115 (2.93) MIN 0.015 (0.381) 00..002124 ((00..535586)) (02.1.5040) 00..007405 ((11..7175)) SPELAANTIENG 0.008 (0.204) BSC 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 0.1574 (4.00) 0.2440 (6.20) 0.1497 (3.80) 1 4 0.2284 (5.80) PIN 1 0.0688 (1.75) 0.0196 (0.50)x 45(cid:176) 0.0098 (0.25) 0.0532 (1.35) 0.0099 (0.25) 0.0040 (0.10) 8(cid:176) SEPALTAINNGE 0(B1.0.S25C70)0 00..00119328 ((00..4395)) 00..00009785 ((00..2159)) 0(cid:176) 00..00510600 ((10..2471)) 8-Lead microSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.122 (3.10) 0.199 (5.05) 0.114 (2.90) 0.187 (4.75) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.120 (3.05) A. 0.112 (2.84) 0.112 (2.84) S. 0.006 (0.15) 0.043 (1.09) U. 0.002 (0.05) 0.018 (0.46) 0.037 (0.94) 3237(cid:176)(cid:176) D IN SEATING 0.008 (0.20) 0.011 (0.28) 0.028 (0.71) E PLANE 0.003 (0.08) 0.016 (0.41) NT RI P –16– REV. 0

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