74AHC259; 74AHCT259 8-bit addressable latch Rev. 02 — 15 May 2008 Product data sheet 1. General description The74AHC259;74AHCT259isahigh-speedSi-gateCMOSdeviceandispincompatible withLow-powerSchottkyTTL(LSTTL).ItisspecifiedincompliancewithJEDECstandard No.7-A. The74AHC259;74AHCT259isahigh-speed8-bitaddressablelatchdesignedforgeneral purpose storage applications in digital systems. It is a multifunctional device capable of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer function with active HIGH outputs (Q0to Q7). It also incorporates an active LOW common reset (MR) for resetting all latches as well as an active LOW enable input (LE). The 74AHC259; 74AHCT259 has four modes of operation: • In the addressable latch mode, data on the data line (D) is written into the addressed latch. The addressed latch will follow the data input with all non-addressed latches remaining in their previous states. • Inthememorymode,alllatchesremainintheirpreviousstatesandareunaffectedby the data or address inputs. • Inthe3-to-8decodingordemultiplexingmode,theaddressedoutputfollowsthestate of the data input (D) with all other outputs in the LOW state. • In the reset mode, all outputs are LOW and unaffected by the address inputs (A0toA2) and data input (D). When operating the 74AHC259; 74AHCT259 as an address latch, changing more than one bit of the address could impose a transient-wrong address. Therefore, this should only be done while in the memory mode. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger actions n Combines demultiplexer and 8-bit latch n Serial-to-parallel capability n Output from each storage bit available n Random (addressable) data entry n Easily expandable n Common reset input n Useful as a 3-to-8 active HIGH decoder n Inputs accept voltages higher than V CC

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch n Input levels: u For 74AHC259: CMOS level u For 74AHCT259: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000V u MM EIA/JESD22-A115-A exceeds 200V u CDM EIA/JESD22-C101C exceeds 1000V n Multiple package options n Specified from- 40(cid:176) C to +85(cid:176) C and from- 40(cid:176) C to +125(cid:176) C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC259 74AHC259D - 40(cid:176) C to +125(cid:176) C SO16 plastic small outline package; 16 leads; SOT109-1 bodywidth3.9 mm 74AHC259PW - 40(cid:176) C to +125(cid:176) C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74AHCT259 74AHCT259D - 40(cid:176) C to +125(cid:176) C SO16 plastic small outline package; 16 leads; SOT109-1 bodywidth3.9 mm 74AHCT259PW - 40(cid:176) C to +125(cid:176) C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 4. Functional diagram 13 Z9 15 G8 14 G10 DX 9,10D 4 14 1 C10 0 8R 1 LE 0 5 4 2 0 Q0 G 1 13 5 3 7 6 D Q1 2 2 6 Q2 7 7 3 Q3 9 1 9 A0 Q4 4 2 10 10 A1 Q5 5 3 11 A2 Q6 11 12 6 Q7 MR 12 7 15 mna573 mna572 Fig 1. Logic symbol Fig 2. IEC logic symbol 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 2 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch Q0 4 1 A0 Q1 5 2 A1 1-of-8 Q2 6 DECODER 3 A2 Q3 7 8 LATCHES Q4 9 14 LE Q5 10 15 MR Q6 11 13 D Q7 12 mna571 Fig 3. Functional diagram 5. Pinning information 5.1 Pinning 74AHC259 74AHCT259 A0 1 16 VCC A1 2 15 MR A2 3 14 LE Q0 4 13 D Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 GND 8 9 Q4 001aai126 Fig 4. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description A0 1 address input A1 2 address input A2 3 address input Q0 4 latch output Q1 5 latch output Q2 6 latch output Q3 7 latch output GND 8 ground (0V) Q4 9 latch output Q5 10 latch output 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 3 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch Table 2. Pin description …continued Symbol Pin Description Q6 11 latch output Q7 12 latch output D 13 data input LE 14 latch enable input (active LOW) MR 15 conditional reset input (active LOW) V 16 supply voltage CC 6. Functional description Table 3. Function table[1] Operating mode Input Output MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Reset (clear) L H X X X X L L L L L L L L Demultiplexer L L d L L L Q=d L L L L L L L (activeHIGH 8-channel) d H L L L Q=d L L L L L L decoder(when D=H) d L H L L L Q=d L L L L L d H H L L L L Q=d L L L L d L L H L L L L Q=d L L L d H L H L L L L L Q=d L L d L H H L L L L L L Q=d L d H H H L L L L L L L Q=d Memory (no action) H H X X X X q q q q q q q q 0 1 2 3 4 5 6 7 Addressable latch H L d L L L Q=d q q q q q q q 1 2 3 4 5 6 7 d H L L q Q=d q q q q q q 0 2 3 4 5 6 7 d L H L q q Q=d q q q q q 0 1 3 4 5 6 7 d H H L q q q Q=d q q q q 0 1 2 4 5 6 7 d L L H q q q q Q=d q q q 0 1 2 3 5 6 7 d H L H q q q q q Q=d q q 0 1 2 3 4 6 7 d L H H q q q q q q Q=d q 0 1 2 3 4 5 7 H H H H q q q q q q q Q=d 0 1 2 3 4 5 6 [1] H=HIGH voltage level; L=LOW voltage level; X=don’t care; d=HIGH or LOW data one set-up time prior to the LOW-to-HIGHLE transition; q=lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition. 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 4 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch Table 4. Operating mode select table[1] LE MR Mode L H addressable latch H H memory L L active HIGH 8-channel demultiplexer H L reset [1] H=HIGH voltage level; L=LOW voltage level. 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0V). Symbol Parameter Conditions Min Max Unit V supply voltage - 0.5 +7.0 V CC V input voltage - 0.5 +7.0 V I I input clamping current V <- 0.5V [1] - 20 - mA IK I I output clamping current V <- 0.5V or V > V + 0.5V [1] - 20 +20 mA OK O O CC I output current V =- 0.5V to (V + 0.5V) - 25 +25 mA O O CC I supply current - +75 mA CC I ground current - 75 - mA GND T storage temperature - 65 +150 (cid:176) C stg P total power dissipation T =- 40(cid:176) Cto+125(cid:176) C [2] - 500 mW tot amb [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70(cid:176) C the value of P derates linearly at 8mW/K. tot For TSSOP16 packages: above 60(cid:176) C the value of P derates linearly at 5.5mW/K. tot 8. Recommended operating conditions Table 6. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74AHC259 V supply voltage 2.0 5.0 5.5 V CC V input voltage 0 - 5.5 V I V output voltage 0 - V V O CC T ambient temperature - 40 +25 +125 (cid:176) C amb D t/D V input transition rise and fall rate V =3.0Vto3.6V - - 100 ns/V CC V =4.5Vto5.5V - - 20 ns/V CC 74AHCT259 V supply voltage 4.5 5.0 5.5 V CC V input voltage 0 - 5.5 V I V output voltage 0 - V V O CC T ambient temperature - 40 +25 +125 (cid:176) C amb D t/D V input transition rise and fall rate V =4.5Vto5.5V - - 20 ns/V CC 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 5 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch 9. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25(cid:176) C - 40(cid:176) C to +85(cid:176) C - 40(cid:176) C to +125(cid:176) C Unit Min Typ Max Min Max Min Max 74AHC259 V HIGH-level V = 2.0 V 1.5 - - 1.5 - 1.5 - V IH CC input voltage V = 3.0 V 2.1 - - 2.1 - 2.1 - V CC V = 5.5 V 3.85 - - 3.85 - 3.85 - V CC V LOW-level V = 2.0 V - - 0.5 - 0.5 - 0.5 V IL CC input voltage V = 3.0 V - - 0.9 - 0.9 - 0.9 V CC V = 5.5 V - - 1.65 - 1.65 - 1.65 V CC V HIGH-level V = V or V OH I IH IL output voltage I =- 50m A; V =2.0 V 1.9 2.0 - 1.9 - 1.9 - V O CC I =- 50m A; V =3.0 V 2.9 3.0 - 2.9 - 2.9 - V O CC I =- 50m A; V =4.5 V 4.4 4.5 - 4.4 - 4.4 - V O CC I =- 4.0mA; V =3.0 V 2.58 - - 2.48 - 2.40 - V O CC I =- 8.0mA; V =4.5 V 3.94 - - 3.80 - 3.70 - V O CC V LOW-level V = V or V OL I IH IL output voltage I = 50m A; V =2.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50m A; V =3.0 V - 0 0.1 - 0.1 - 0.1 V O CC I = 50m A; V =4.5 V - 0 0.1 - 0.1 - 0.1 V O CC I = 4.0mA; V =3.0 V - - 0.36 - 0.44 - 0.55 V O CC I = 8.0mA; V =4.5 V - - 0.36 - 0.44 - 0.55 V O CC I input leakage V =5.5VorGND; - - 0.1 - 1.0 - 2.0 m A I I current V =0Vto5.5V CC I supply current V =V orGND; I = 0 A; - - 4.0 - 40 - 80 m A CC I CC O V =5.5V CC C input V =V orGND - 3 10 - 10 - 10 pF I I CC capacitance C output - 4 - - - - - pF O capacitance 74AHCT259 V HIGH-level V = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V IH CC input voltage V LOW-level V = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.8 V IL CC input voltage V HIGH-level V = V or V ; V =4.5 V OH I IH IL CC output voltage I =- 50m A 4.4 4.5 - 4.4 - 4.4 - V O I =- 8.0mA 3.94 - - 3.80 - 3.70 - V O V LOW-level V = V or V ; V =4.5 V OL I IH IL CC output voltage I = 50m A - 0 0.1 - 0.1 - 0.1 V O I = 8.0mA - - 0.36 - 0.44 - 0.55 V O 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 6 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 25(cid:176) C - 40(cid:176) C to +85(cid:176) C - 40(cid:176) C to +125(cid:176) C Unit Min Typ Max Min Max Min Max I input leakage V =5.5 VorGND; - - 0.1 - 1.0 - 2.0 m A I I current V =0Vto5.5V CC I supply current V =V orGND; I = 0 A; - - 4.0 - 40 - 80 m A CC I CC O V =5.5V CC D I additional perinputpin;V =V - 2.1V; - - 1.35 - 1.5 - 1.5 mA CC I CC supply current other pins at V orGND; CC I =0A; V =4.5Vto5.5V O CC C input V =V orGND - 3 10 - 10 - 10 pF I I CC capacitance C output - 4 - - - - - pF O capacitance 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure11. Symbol Parameter Conditions 25(cid:176) C - 40(cid:176) C to +85(cid:176) C - 40(cid:176) C to +125(cid:176) C Unit Min Typ[1] Max Min Max Min Max 74AHC259 t propagation D to Qn; seeFigure5 [2] pd delay V = 3.0 V to 3.6 V CC C =15pF - 5.8 11.5 1.0 13.5 1.0 15.0 ns L C =50pF - 7.3 14.5 1.0 17.0 1.0 18.5 ns L V = 4.5 V to 5.5 V CC C =15pF - 4.1 7.5 1.0 9.0 1.0 10.0 ns L C =50pF - 5.3 9.5 1.0 11.0 1.0 12.0 ns L An to Qn; seeFigure6 [2] V = 3.0 V to 3.6 V CC C =15pF - 7.5 14.5 1.0 17.0 1.0 18.5 ns L C =50pF - 9.1 18.0 1.0 21.0 1.0 23.0 ns L V = 4.5 V to 5.5 V CC C =15pF - 5.3 9.5 1.0 11.5 1.0 12.5 ns L C =50pF - 6.5 11.5 1.0 13.5 1.0 15.0 ns L LE to Qn; seeFigure7 [2] V = 3.0 V to 3.6 V CC C =15pF - 6.2 12.0 1.0 14.0 1.0 15.2 ns L C =50pF - 7.7 15.5 1.0 17.5 1.0 19.0 ns L V = 4.5 V to 5.5 V CC C =15pF - 4.3 8.0 1.0 9.5 1.0 10.5 ns L C =50pF - 5.5 10.0 1.0 11.5 1.0 12.5 ns L 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 7 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure11. Symbol Parameter Conditions 25(cid:176) C - 40(cid:176) C to +85(cid:176) C - 40(cid:176) C to +125(cid:176) C Unit Min Typ[1] Max Min Max Min Max t propagation MR to Qn; seeFigure8 [3] pd delay V = 3.0 V to 3.6 V CC C =15pF - 5.4 10.5 1.0 12.5 1.0 13.5 ns L C =50pF - 7.0 13.5 1.0 15.5 1.0 17.0 ns L V = 4.5 V to 5.5 V CC C =15pF - 3.9 7.0 1.0 8.5 1.0 9.5 ns L C =50pF - 5.1 9.0 1.0 10.5 1.0 11.5 ns L t pulse width LE HIGH or LOW; W seeFigure7 V = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns CC V = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns CC MR LOW; seeFigure8 V = 3.0 V to 3.6 V 5.0 - - 5.0 - 5.0 - ns CC V = 4.5 V to 5.5 V 5.0 - - 5.0 - 5.0 - ns CC t set-up time D, An toLE; seeFigure9 su andFigure10 V = 3.0 V to 3.6 V 4.0 - - 4.0 - 4.0 - ns CC V = 4.5 V to 5.5 V 4.0 - - 4.0 - 4.0 - ns CC t hold time D, An toLE; seeFigure9 h andFigure10 V = 3.0 V to 3.6 V 1.0 - - 1.0 - 1.0 - ns CC V = 4.5 V to 5.5 V 1.0 - - 1.0 - 1.0 - ns CC C power f =1MHz; V =GNDtoV [4] - 13 - - - - - pF PD i I CC dissipation capacitance 74AHCT259; V = 4.5 V to 5.5 V CC t propagation D to Qn; seeFigure5 [2] pd delay C =15pF - 4.1 7.5 1.0 9.0 1.0 10.0 ns L C =50pF - 5.4 9.5 1.0 11.0 1.0 12.0 ns L An to Qn; seeFigure6 [2] C =15pF - 5.5 9.5 1.0 11.5 1.0 12.5 ns L C =50pF - 6.6 12.0 1.0 14.0 1.0 15.5 ns L LE to Qn; seeFigure7 [2] C =15pF - 4.3 8.0 1.0 9.5 1.0 10.4 ns L C =50pF - 5.5 10.0 1.0 12.0 1.0 13.0 ns L MR to Qn; seeFigure8 [3] C =15pF - 3.9 7.0 1.0 8.5 1.0 9.5 ns L C =50pF - 5.1 9.0 1.0 10.5 1.0 11.5 ns L t pulse width LE HIGH or LOW; 5.0 - - 5.0 - 5.0 - ns W seeFigure7 MR LOW; seeFigure8 5.0 - - 5.0 - 5.0 - ns 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 8 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit seeFigure11. Symbol Parameter Conditions 25(cid:176) C - 40(cid:176) C to +85(cid:176) C - 40(cid:176) C to +125(cid:176) C Unit Min Typ[1] Max Min Max Min Max t set-up time D, An toLE; seeFigure9 4.0 - - 4.0 - 4.0 - ns su andFigure10 t hold time D, An toLE; seeFigure9 1.0 - - 1.0 - 1.0 - ns h andFigure10 C power f =1MHz; V =GNDtoV [4] - 17 - - - - - pF PD i I CC dissipation capacitance [1] Typical values are measured at nominal supply voltage (V =3.3V and V =5.0V). CC CC [2] t is the same as t and t . pd PLH PHL [3] t is the same as t only. pd PHL [4] C is used to determine the dynamic power dissipation (P inm W). PD D P =C · V 2· f · N+S (C · V 2· f )where: D PD CC i L CC o f =input frequency in MHz; i f =output frequency in MHz; o C =output load capacitance inpF; L V =supply voltage in V; CC N=number of inputs switching; S (C · V 2· f )=sum of the outputs. L CC o 11. Waveforms VCC D input VM GND tPHL tPLH VOH Qn output VM VOL 001aah123 Measurement points are given inTable9. V and V are typical voltage output levels that occur with the output load. OL OH Fig 5. Data input to output propagation delays 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 9 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch VCC An input VM GND tPHL tPLH VOH Qn output VM VOL 001aah122 Measurement points are given inTable9. V and V are typical voltage output levels that occur with the output load. OL OH Fig 6. Address input to output propagation delays VCC D input GND VCC LE input VM GND tW tPHL tPLH VOH Qn output VM VOL 001aah121 Measurement points are given inTable9. V and V are typical voltage output levels that occur with the output load. OL OH Fig 7. Enable input to output propagation delays and pulse width VCC MR input VM GND tW tPHL VOH Qn output VM VOL 001aah124 Measurement points are given inTable9. V and V are typical voltage output levels that occur with the output load. OL OH Fig 8. Conditional reset input to output propagation delays 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 10 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch VCC LE input VM GND tsu tsu th th VCC D input VM GND VOH Qn output Q = D VM Q = D VOL 001aah125 Measurement points are given inTable9. The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load. OL OH Fig 9. Data input to latch enable input set-up and hold times VCC An input VM ADDRESS STABLE GND tsu th VCC LE input VM GND 001aah126 Measurement points are given inTable9. The shaded areas indicate when the input is permitted to change for predictable output performance. V and V are typical voltage output levels that occur with the output load. OL OH Fig 10. Address input to latch enable input set-up and hold times Table 9. Measurement points Type Input Output V V M M 74AHC259 0.5· V 0.5· V CC CC 74AHCT259 1.5V 0.5· V CC 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 11 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch VI tW 90 % negative pulse VM VM 10 % GND tf tr tr tf VI 90 % positive pulse VM VM 10 % GND tW VCC VI VO G DUT RT CL 001aah768 Test data is given inTable10. Definitions test circuit: R = termination resistance should be equal to output impedance Z of the pulse generator. T o C = load capacitance including jig and probe capacitance. L Fig 11. Load circuitry for measuring switching times Table 10. Test data Type Input Load Test V t, t C I r f L 74AHC259 V £ 3.0ns 15pF, 50pF t , t CC PLH PHL 74AHCT259 3.0V £ 3.0ns 15pF, 50pF t , t PLH PHL 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 12 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch 12. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A1 (A 3 ) A pin 1 index q Lp 1 8 L e w M detail X bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. A1 A2 A3 bp c D(1) E(1) e HE L Lp Q v w y Z(1) q 0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7 mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8o 0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0o inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004 0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT109-1 076E07 MS-012 03-02-19 Fig 12. Package outline SOT109-1 (SO16) 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 13 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 D E A X c y HE v M A Z 16 9 Q A2 (A 3 ) A pin 1 index A1 q Lp L 1 8 detail X w M e bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mAax. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) q mm 1.1 00..1055 00..9850 0.25 00..3109 00..21 54..19 44..53 0.65 66..62 1 00..7550 00..43 0.2 0.13 0.1 00..4006 80oo Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 99-12-27 SOT403-1 MO-153 03-02-18 Fig 13. Package outline SOT403-1 (TSSOP16) 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 14 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch 13. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AHC_AHCT259_2 20080515 Product data sheet - 74AHC_AHCT259_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Table6: the conditions for input leakage current have been changed. 74AHC_AHCT259_1 20000314 Product specification - - 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 15 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatus information is available on the Internet at URLhttp://www.nxp.com. 15.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of Draft —The document is a draft version only. The content is still under NXP Semiconductors products in such equipment or applications and internal review and subject to formal approval, which may result in therefore such inclusion and/or use is at the customer’s own risk. modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of Applications —Applications that are described herein for any of these informationincludedhereinandshallhavenoliabilityfortheconsequencesof products are for illustrative purposes only. NXP Semiconductors makes no use of such information. representation or warranty that such applications will be suitable for the specified use without further testing or modification. Short data sheet —A short data sheet is an extract from a full data sheet withthesameproducttypenumber(s)andtitle.Ashortdatasheetisintended Limiting values —Stress above one or more limiting values (as defined in forquickreferenceonlyandshouldnotbereliedupontocontaindetailedand theAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanent full information. For detailed and full information see the relevant full data damagetothedevice.Limitingvaluesarestressratingsonlyandoperationof sheet, which is available on request via the local NXP Semiconductors sales the device at these or any other conditions above those given in the office. In case of any inconsistency or conflict with the short data sheet, the Characteristics sections of this document is not implied. Exposure to limiting full data sheet shall prevail. values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold 15.3 Disclaimers subjecttothegeneraltermsandconditionsofcommercialsale,aspublished athttp://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless General —Information in this document is believed to be accurate and explicitly otherwise agreed to in writing by NXP Semiconductors. In case of reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsor any inconsistency or conflict between information in this document and such warranties,expressedorimplied,astotheaccuracyorcompletenessofsuch terms and conditions, the latter will prevail. information and shall have no liability for the consequences of use of such No offer to sell or license —Nothing in this document may be interpreted information. or construed as an offer to sell products that is open for acceptance or the Right to make changes —NXPSemiconductorsreservestherighttomake grant,conveyanceorimplicationofanylicenseunderanycopyrights,patents changes to information published in this document, including without or other industrial or intellectual property rights. limitation specifications and product descriptions, at any time and without notice.Thisdocumentsupersedesandreplacesallinformationsuppliedprior to the publication hereof. 15.4 Trademarks Suitability for use —NXP Semiconductors products are not designed, Notice:Allreferencedbrands,productnames,servicenamesandtrademarks authorized or warranted to be suitable for use in medical, military, aircraft, are the property of their respective owners. space or life support equipment, nor in applications where failure or 16. Contact information For more information, please visit:http://www.nxp.com For sales office addresses, please send an email to:salesaddresses@nxp.com 74AHC_AHCT259_2 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 02 — 15 May 2008 16 of 17

74AHC259; 74AHCT259 NXP Semiconductors 8-bit addressable latch 17. Contents 1 General description. . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 4 7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Recommended operating conditions. . . . . . . . 5 9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 17 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 15 May 2008 Document identifier: 74AHC_AHCT259_2