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  • 型号: X9C104SIZT1
  • 制造商: Intersil
  • 库位|库存: xxxx|xxxx
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X9C104SIZT1产品简介:

ICGOO电子元器件商城为您提供X9C104SIZT1由Intersil设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 X9C104SIZT1价格参考¥询价-¥询价。IntersilX9C104SIZT1封装/规格:数据采集 - 数字电位器, Digital Potentiometer 100k Ohm 1 Circuit 100 Taps Up/Down (U/D, INC, CS) Interface 8-SOIC。您可以下载X9C104SIZT1参考资料、Datasheet数据手册功能说明书,资料中有X9C104SIZT1 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)

描述

IC POT DGTL CTRL 100KOHM 8SOIC

产品分类

数据采集 - 数字电位器

品牌

Intersil

数据手册

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产品图片

产品型号

X9C104SIZT1

PCN组件/产地

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rohs

无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

XDCP™

供应商器件封装

8-SOIC

其它名称

X9C104SIZT1CT

包装

剪切带 (CT)

存储器类型

非易失

安装类型

表面贴装

封装/外壳

8-SOIC(0.154",3.90mm 宽)

工作温度

-40°C ~ 85°C

抽头

100

接口

3 线串行(芯片选择,递增,增/减)

标准包装

1

温度系数

标准值 ±300 ppm/°C

电压-电源

4.5 V ~ 5.5 V

电路数

1

电阻(Ω)

100k

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PDF Datasheet 数据手册内容提取

DATASHEET X9C102, X9C103, X9C104, X9C503 FN8222 Digitally Controlled Potentiometer (XDCP™) Rev 4.00 Jan 11, 2019 The X9C102, X9C103, X9C104, X9C503 are digitally Features controlled (XDCP) potentiometers. The device consists of a • Solid-State Potentiometer resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a • Three-Wire Serial Interface three-wire interface. • 100 Wiper Tap Points The potentiometer is implemented by a resistor array - Wiper Position Stored in Non-volatile Memory and composed of 99 resistive elements and a wiper switching Recalled on Power-up network. Between each element and at either end are tap • 99 Resistive Elements points accessible to the wiper terminal. The position of the - Temperature Compensated wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in non-volatile - End-to-End Resistance, ±20% memory and then be recalled upon a subsequent power-up - Terminal Voltages, ±5V operation. • Low Power CMOS The device can be used as a three-terminal potentiometer or - V = 5V CC as a two-terminal variable resistor in a wide variety of - Active Current, 3mA max. applications ranging from control to signal processing to - Standby Current, 750µA max. parameter adjustment. • High Reliability Pinout - Endurance, 100,000 Data Changes per Bit X9C102, X9C103, X9C104, X9C503 - Register Data Retention, 100 years (8 LD SOIC, 8 LD PDIP) • X9C102 = 1k TOP VIEW • X9C103 = 10k INC 1 8 VCC • X9C503 = 50k U/D 2 7 CS • X9C104 = 100k VH/RH 3 6 VL/RL VSS 4 5 VW/RW • Packages - 8 Ld SOIC - 8 Ld PDIP • Pb-Free Available (RoHS Compliant) Block Diagram UIN/DC UP7/D-BOITWN 99 RH/VH COUNTER CS 98 VCC (SUPPLY VOLTAGE) 97 UP/DOWN (U/D) VH/RH NON-7V-OBLITATILE ONE 96 CONTROL MEMORY OF INCREMENT(INC) AND RW/VW ONE- MEMORY HUNDRED TRANSFER RESISTOR DEVICE (CS) DECODER GATES ARRAY SELECT VL/RL 2 VSS (GROUND) STORE AND RECALL 1 GENERAL VCC CONTROL GND CIRCUITRY 0 RL/VL DETAILED RW/VW FN8222 Rev 4.00 Page 1 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Ordering Information PART PART R TEMP RANGE PACKAGE PACKAGE TOTAL NUMBER MARKING (k) (°C) (RoHS Compliant) DWG. # X9C102PZ (Notes 2, 3) X9C102P Z 1 0 to +70 8 Ld PDIP MDP0031 X9C102PIZ (Notes 2, 3) X9C102P ZI -40 to +85 8 Ld PDIP MDP0031 X9C102SZ (Notes 1, 2) X9C102S Z 0 to +70 8 Ld SOIC M8.15E X9C102SIZ (Notes 1, 2) X9C102S ZI -40 to +85 8 Ld SOIC M8.15E X9C103PZ (Notes 2, 3) X9C103P Z 10 0 to +70 8 Ld PDIP MDP0031 X9C103PIZ (Notes 2, 3) X9C103P ZI -40 to +85 8 Ld PDIP MDP0031 X9C103SZ (Notes 1, 2) X9C103S Z 0 to +70 8 Ld SOIC M8.15 X9C103SIZ (Notes 1, 2) X9C103S ZI -40 to +85 8 Ld SOIC M8.15 X9C503PZ (Notes 2, 3) X9C503P Z 50 0 to +70 8 Ld PDIP MDP0031 X9C503PIZ (Notes 2, 3) X9C503P ZI -40 to +85 8 Ld PDIP MDP0031 X9C503SZ (Notes 1, 2) X9C503S Z 0 to +70 8 Ld SOIC M8.15E X9C503SIZ (Notes 1, 2) X9C503S ZI -40 to +85 8 Ld SOIC M8.15E X9C104PIZ (Notes 2, 3) X9C104P ZI 100 -40 to +85 8 Ld PDIP MDP0031 X9C104SZ (Notes 1, 2) X9C104S Z 0 to +70 8 Ld SOIC M8.15E X9C104SIZ (Notes 1, 2) X9C104S ZI -40 to +85 8 Ld SOIC M8.15E NOTES: 1. Add “T1” suffix for tape and reel. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN8222 Rev 4.00 Page 2 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1 INC INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 2 U/D UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. 3 V /R V /R The high (V /R ) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of H H H H H H a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of V /R and V /R H H L L references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. 4 V V SS SS 5 V /R V /R V /R is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The W W W W W W position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. 6 R /V R /V The low (V /R ) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a L L L L L L mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of V /R and V /R H H L L references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. 7 CS CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103, X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again. 8 V V CC CC FN8222 Rev 4.00 Page 3 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Absolute Maximum Ratings Thermal Information Voltage on CS, INC, U/D and V with Respect to V . -1V to +7V Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C CC SS Voltage on V /R and V /R Referenced to V . . . . . . . -8V to +8V Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C H H L L SS V = |V /R - V /R | Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TB493 H H L L X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V *Pb-free PDIPs can be used for through-hole wave solder X9C103, X9C104, and X9C503. . . . . . . . . . . . . . . . . . . . . . . .10V processing only. They are not intended for use in Reflow solder I (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA processing applications. W Power Rating X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW Recommended Operating Conditions X9C103 X0C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . .10mW Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C Industrial Temperature Range. . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage Range (V ). . . . . . . . . . . . . . . . . . . . . . . 5V ±10% CC CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications Over recommended operating conditions unless otherwise stated. LIMITS TYP SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) MAX UNIT POTENTIOMETER CHARACTERISTICS R End-to-End Resistance Variation -20 +20 % TOTAL V V Terminal Voltage -5 +5 V VH/RH H V V Terminal Voltage -5 +5 V VL/RL L I Wiper Current -4.4 4.4 mA W R Wiper Resistance Wiper Current = ±1mA 40 100  W Resistor Noise (Note 8) Ref 1kHz -120 dBV Charge Pump Noise (Note 8) @ 850kHz 20 mV RMS Resolution 1 % Absolute Linearity (Note 4) V - V -1 +1 MI (Note 6) W(n)(actual) W(n)(EXPECTED) Relative Linearity (Note 5) V - [V ] -0.2 +0.2 MI (Note 6) W(n + 1)(ACTUAL) W(n)+MI R Temperature Coefficient X9C103, X9C503, X9C104 ±300 (Note 8) ppm/°C TOTAL R Temperature Coefficient X9C102 ±600 (Note 8) ppm/°C TOTAL Ratiometric Temperature Coefficient ±20 ppm/°C C /C /C Potentiometer Capacitances See “Circuit #3 SPICE Macro 10/10/25 pF H L W (Note 8) Model” on page5. DC OPERATING CHARACTERISTICS ICC VCC Active Current CS = VIL, U/D = VIL or VIH and 1 3 mA INC = 0.4V to 2.4V at Max t CYC I Standby Supply Current CS = V - 0.3V, U/D and 200 750 µA SB CC INC=V orV -0.3V SS CC I CS, INC, U/D Input Leakage Current V = V to V ±10 µA LI IN SS CC V CS, INC, U/D input HIGH Voltage 2 V IH V CS, INC, U/D input LOW Voltage 0.8 V IL C CS, INC, U/D Input Capacitance (Note8) V = 5V, V = V , T =+25°C, 10 pF IN CC IN SS A f = 1MHz FN8222 Rev 4.00 Page 4 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Electrical Specifications Over recommended operating conditions unless otherwise stated. (Continued) LIMITS TYP SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) MAX UNIT AC OPERATION CHARACTERISTICS t CS to INC Setup 100 ns Cl t INC HIGH to U/D Change 100 ns lD t U/D to INC Setup 2.9 µs DI t INC LOW Period 1 µs lL t INC HIGH Period 1 µs lH t INC Inactive to CS Inactive 1 µs lC t CS Deselect Time (STORE) 20 ms CPH t CS Deselect Time (NO STORE) 100 ns CPH t (5) INC to V Change 100 µs IW W/RW t INC Cycle Time 2 µs CYC t INC Input Rise and Fall Time 500 µs CYC tR, tF Power-up to Wiper Stable (Note 8) 500 µs tPU VCC Power-up Rate (Note 8) 0.2 50 V/ms NOTES: 4. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [V - V ] = ±1 MI Maximum. W(n)(actual) W(n)(expected ) 5. Relative linearity is a measure of the error in step size between taps = V - [V ] = +0.2 MI. W(n + 1) W(n) + MI 6. 1 MI = Minimum Increment = R /99. TOT 7. Typical values are for T = +25°C and nominal supply voltage. A 8. This parameter is not 100% tested. Test Circuit #1 Test Circuit #2 Circuit #3 SPICE Macro Model VR/RH VH/RH RTOTAL TEST POINT RL RH CL CW CL VS TEST POINT 10pF Vw/RW VW/Rw FORCE 10pF 25pF CURRENT VL/RL VL/RL RW Endurance and Data Retention Power-up and Down Requirements At all times, voltages on the potentiometer pins must be less PARAMETER MIN UNIT than ±V . The recall of the wiper position from non-volatile CC Medium Endurance 100,000 Data changes per bit memory is not in effect until the V supply reaches its final per register CC value. The V ramp rate specification is always in effect. CC Data Retention 100 years AC Conditions of Test Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input Reference Levels 1.5V FN8222 Rev 4.00 Page 5 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 AC Timing Diagram CS tCYC tCI tIL tIH tIC tCPH 90% 90% INC 10% tID tDI tF tR U/D tIW VW MI(NOTE) NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION. Pin Descriptions Principles of Operation R /V and R /V There are three sections of the X9C102, X9C103, ISL9C104 H H L L and ISL9C503: the input control, counter and decode section; The high (V /R ) and low (V /R ) terminals of the ISLX9C102, H H L L the non-volatile memory; and the resistor array. The input control X9C103, X9C104, X9C503 are equivalent to the fixed section operates just like an up/down counter. The output of this terminals of a mechanical potentiometer. The minimum voltage counter is decoded to turn on a single electronic switch is -5V and the maximum is +5V. The terminology of V /R and H H connecting a point on the resistor array to the wiper output. V /R references the relative position of the terminal in relation L L Under the proper conditions, the contents of the counter can be to wiper movement direction selected by the U/D input and not stored in non-volatile memory and retained for future use. The the voltage potential on the terminal. resistor array is comprised of 99 individual resistors connected R /V in series. At either end of the array and between each resistor is W W an electronic switch that transfers the potential at that point to V /R is the wiper terminal, and is equivalent to the movable W W the wiper. terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The The wiper, when at either fixed terminal, acts like its wiper terminal series resistance is typically 40. mechanical equivalent and does not move beyond the last Up/Down (U/D) position. That is, the counter does not wrap around when clocked to either extreme. The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap Increment (INC) positions. If the wiper is moved several positions, multiple taps The INC input is negative-edge triggered. Toggling INC will are connected to the wiper for t (INC to V /R change). The IW W W move the wiper and either increment or decrement the counter R value for the device can temporarily be reduced by a TOTAL in the direction indicated by the logic level on the U/D input. significant amount if the wiper is moved several positions. Chip Select (CS) When the device is powered-down, the last wiper position The device is selected when the CS input is LOW. The current stored will be maintained in the non-volatile memory. When counter value is stored in non-volatile memory when CS is power is restored, the contents of the memory are recalled and returned HIGH while the INC input is also HIGH. After the store the wiper is reset to the value last stored. operation is complete the ISLX9C102, X9C103, X9C104, The internal charge pump allows a wide range of voltages X9C503 device will be placed in the low power standby mode (from -5V to 5V) applied to XDCP terminals yet given a until the device is selected once again. convenience of single power supply. The typical charge pump noise of 20mV at 850kHz should be taken in consideration when designing an application circuit. FN8222 Rev 4.00 Page 6 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Instructions and Programming Mode Selection The INC, U/D and CS inputs control the movement of the wiper CS INC U/D MODE along the resistor array. With CS set LOW, the device is selected L H Wiper Up and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending L L Wiper Down on the state of the U/D input) a 7-bit counter. The output of this H X Store Wiper Position counter is decoded to select one of one-hundred wiper positions along the resistive array. H X X Standby Current L X No Store, Return to Standby The value of the counter is stored in non-volatile memory whenever CS transitions HIGH while the INC input is also L H Wiper Up (not recommended) HIGH. L L Wiper Down (not recommended) The system may select the X9Cxxx, move the wiper and Symbol Table deselect the device without having to store the latest wiper position in non-volatile memory. After the wiper movement is WAVEFORM INPUTS OUTPUTS performed as previously described and once the new position is reached, the system must keep INC LOW while taking CS Must be Will be HIGH. The new wiper position will be maintained until changed steady steady by the system or until a power-down/up cycle recalled the May change Will change previously stored data. from Low to from Low to High High This procedure allows the system to always power-up to a pre- May change Will change set value stored in non-volatile memory; then during system from High to from High to Low Low operation, minor adjustments could be made. The adjustments might be based on user preference, i.e.: system parameter Don’t Care: Changing: Changes State Not changes due to temperature drift, etc. Allowed Known The state of U/D may be changed while CS remains LOW. This N/A Center Line is High allows the host system to enable the device and then move the Impedance wiper up and down until the proper trim is attained. Performance Characteristics Contact the factory for more information. Applications Information Electronic digitally controlled (XCDP) potentiometers provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer. 2. The flexibility of computer-based digital controls. 3. The retentivity of non-volatile memory used for the storage of multiple potentiometer settings or data. FN8222 Rev 4.00 Page 7 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Basic Configurations of Electronic Potentiometers VR VR VH/RH VW/RW VL/RL I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT Basic Circuits R1 +V +V +5V +V VS + LM308A +5V VO – VW OP-07 VREF + VOUT VW/RW X -5V – +V R2 -5V R1 VOUT = VW/RW VW/RW VO = (1+R2/R1)VS (a) (b) BUFFERED REFERENCE VOLTAGE CASCADING TECHNIQUES NONINVERTING AMPLIFIER R1 R2 LT311A VIN 317 VO (REG) VS VS – R1 100k – + VO VO + Iadj TL072 } } R2 10k R1 R2 10k 10k VUL = {R1/(R1 + R2)} VO(MAX) VO (REG) = 1.25V (1+R2/R1)+Iadj R2 VLL = {R1/(R1 + R2)} VO(MIN) +12V -12V (FOR ADDITIONAL CIRCUITS SEE AN1145) VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS Revision History Rev. Date Description 4.00 Jan 11, 2019 Updated Ordering Information table to remove Obsolete and Retired parts. Added Revision History. Updated PODs for X9C102, X9C104, and X9C503 SOICs from: MDP0027 to: M8.15E and X9C103 SOIC from: MDP0027 to: M8.15, to include the Land Pattern design and convert dimensions from table to graphics. Updated Intersil disclaimer to Renesas disclaimer. FN8222 Rev 4.00 Page 8 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Package Outline Drawings For the most recent package outline drawing, see M8.15. M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) AREA 5.80 (0.228) 0.50 (0.20) x 45° 4.00 (0.157) 0.25 (0.01) 3.80 (0.150) 8° 1 2 3 0° 0.25 (0.010) 0.19 (0.008) TOP VIEW SIDE VIEW “B” 2.20 (0.087) 1 8 SEATING PLANE 0.60 (0.023) 5.00 (0.197) 1.75 (0.069) 2 7 4.80 (0.189) 1.35 (0.053) 1.27 (0.050) 3 6 -C- 4 5 1.27 (0.050) 0.25(0.010) 0.10(0.004) 0.51(0.020) 5.20(0.205) 0.33(0.013) SIDE VIEW “A TYPICAL RECOMMENDED LAND PATTERN NOTES: 9. Dimensioning and tolerancing per ANSI Y14.5M-1994. 10. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 11. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 12. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 13. Terminal numbers are shown for reference only. 14. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 15. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 16. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN8222 Rev 4.00 Page 9 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 M8.15E For the most recent package outline drawing, see M8.15E. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25MC AB SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C 0.175 ± 0.075 SEATING PLANE 0.10C SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 (5.40) 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN8222 Rev 4.00 Page 10 of 12 Jan 11, 2019

X9C102, X9C103, X9C104, X9C503 Plastic Dual-In-Line Packages (PDIP) For the most recent package outline drawing, see MDP0031. D E N PIN #1 A2 A E1 INDEX SEATING PLANE c LL A1 1 2 N/2 NOTE 5 eA e b eB b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE NOTES A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 1 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 2 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference Rev. C 2/07 NOTES: 17. Plastic or metal protrusions of 0.010” maximum per side are not included. 18. Plastic interlead protrusions of 0.010” maximum per side are not included. 19. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 20. Dimension eB is measured with the lead tips unconstrained. 21. 8 and 16 lead packages have half end-leads as shown. FN8222 Rev 4.00 Page 11 of 12 Jan 11, 2019

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