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  • 型号: VN5050AJTR-E
  • 制造商: STMicroelectronics
  • 库位|库存: xxxx|xxxx
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VN5050AJTR-E产品简介:

ICGOO电子元器件商城为您提供VN5050AJTR-E由STMicroelectronics设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 VN5050AJTR-E价格参考。STMicroelectronicsVN5050AJTR-E封装/规格:PMIC - 配电开关,负载驱动器, 。您可以下载VN5050AJTR-E参考资料、Datasheet数据手册功能说明书,资料中有VN5050AJTR-E 详细功能的应用电路图电压和使用方法及教程。

产品参数 图文手册 常见问题
参数 数值
产品目录

集成电路 (IC)半导体

描述

IC DVR 1CH HISID AUTO POWERSSO12门驱动器 Sngl Ch HiSide Drivr

产品分类

PMIC - MOSFET,电桥驱动器 - 内部开关集成电路 - IC

品牌

STMicroelectronics

产品手册

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产品图片

rohs

符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求

产品系列

电源管理 IC,门驱动器,STMicroelectronics VN5050AJTR-EVIPower™

数据手册

点击此处下载产品Datasheet

产品型号

VN5050AJTR-E

产品

MOSFET Gate Drivers

产品种类

门驱动器

供应商器件封装

PowerSSO-12™

其它名称

497-11676-1

其它有关文件

http://www.st.com/web/catalog/sense_power/FM1965/CL1969/SC1037/PF151758?referrer=70071840

包装

剪切带 (CT)

商标

STMicroelectronics

安装类型

表面贴装

安装风格

SMD/SMT

导通电阻

50 毫欧

封装

Reel

封装/外壳

PowerSSO-12

封装/箱体

Power SSO-12

工作温度

-40°C ~ 150°C

工厂包装数量

2500

最大关闭延迟时间

40000 ns

最大工作温度

+ 150 C

最大开启延迟时间

20000 ns

最小工作温度

- 40 C

标准包装

1

激励器数量

1 Driver

电压-电源

4.5 V ~ 36 V

电流-峰值输出

16.5A

电流-输出/通道

12A

电源电压-最大

36 V

电源电压-最小

4.5 V

电源电流

1.5 mA

类型

高端

系列

VN5050AJ-E

输入类型

非反相

输出数

1

输出端数量

1

配置

Non-Inverting

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PDF Datasheet 数据手册内容提取

VN5050AJ-E Single channel high side driver with analog current sense for automotive applications Features Max supply voltage V 41 V CC Operating voltage range V 4.5 to 36V CC PowerSSO-12 Max On-State resistance R 50 mΩ ON – Reverse battery protection ( see Current limitation (typ) I 16.5 A Application schematic ) LIMH – Electrostatic discharge protection Off state supply current I 2 µA S ■ General features Application – Inrush current active management by ■ All types of resistive, inductive and capacitive power limitation loads – Very low stand-by current ■ Suitable as LED driver – 3.0V CMOS compatible input – Optimized electromagnetic emission Description – Very low electromagnetic susceptibility – In compliance with the 2002/95/EC The VN5050AJ-E is a monolithic device made European directive using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads ■ Diagnostic functions with one side connected to ground. Active V – Proportional load current sense CC pin voltage clamp protects the device against low – High current sense precision for wide range energy spikes (see ISO7637 transient currents compatibility table). – Current sense disable This device integrates an analog current sense – Thermal shutdown indication which delivers a current proportional to the load – Very low current sense leakage current (according to a known ratio) when CS_DIS is driven low or left open. ■ Protection When CS_DIS is driven high, the CURRENT – Undervoltage shut-down SENSE pin is in a high impedance condition. – Overvoltage clamp Output current limitation protects the device in – Load current limitation overload condition. In case of long overload duration, the device limits the dissipated power to – Self limiting of fast thermal transients safe level up to thermal shut-down intervention. – Protection against loss of ground and loss Thermal shut-down with automatic restart allows of V CC the device to recover normal operation as soon as – Thermal shut down fault condition disappears. Table 1. Device summary Order codes Package Tube Tape and Reel PowerSSO-12 VN5050AJ-E VN5050AJTR-E September 2013 Rev 7 1/31 www.st.com 31

Contents VN5050AJ-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21 3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21 3.1.2 Solution 2: diode (D ) in the ground line . . . . . . . . . . . . . . . . . . . . . . 22 GND 3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/31

VN5050AJ-E List of tables List of tables Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 4. Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 6. Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 7. Switching (V =13V, T=25°C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CC j Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 9. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 10. Current sense (8V<V <16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CC Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 13. Thermal parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3/31

List of figures VN5050AJ-E List of figures Figure 1. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Output voltage drop limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 7. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8. I /I Vs. I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 OUT SENSE OUT Figure 9. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11. Off state output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12. High level input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 14. Input low level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 17. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 18. On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 21. ILIMH Vs. Tcase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 25. CS_DIS low level voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 26. Application schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 27. Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 28. PowerSSO-12™ PC Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24 Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25 Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25 Figure 32. PowerSSO-12™ package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 33. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4/31

VN5050AJ-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram V CC V CC CLAMP UNDERVOLTAGE PwCLAMP DRIVER OUTPUT GND I LIM V LOGIC DSLIM Pwr INPUT LIM OVERTEMP. I OUT K CURRENT SENSE CS_DIS T able 2. Pin function Name Function V Battery connection. CC OUTPUT Power output. Ground connection. Must be reverse battery protected by an external GND diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output INPUT switch state. CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current. CS_DIS Active high CMOS compatible pin, to disable the current sense pin. 5/31

Block diagram and pin description VN5050AJ-E Figure 2. Configuration diagram (top view) TAB = V cc N.C. N.C. 1 12 GND 2 11 OUTPUT INPUT 3 10 OUTPUT CURRENT SENSE 4 9 OUTPUT CS_DIS 5 8 OUTPUT 6 7 N.C. N.C. Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs, these pins should be left unconnected. T able 3. Suggested connections for unused and N.C. pins Connection / Pin Current Sense N.C. Output Input CS_DIS Floating N.R. X X X X Through 10kΩ Through To ground Through 1kΩ resistor X N.R.(1) resistor 10kΩ resistor 1. Not recommended. 6/31

VN5050AJ-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions I S V CC V F I I OUT CSD CS_DIS OUTPUT V I CC IN INPUT I SENSE V V CURRENT SENSE OUT CSD V IN GND V SENSE I GND Note: V = V - V during reverse battery condition. F OUT CC 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. T able 4. Absolute maximum ratings Symbol Parameter Value Unit V DC supply voltage 41 V CC -V Reverse DC supply voltage 0.3 V CC - I DC reverse ground pin current 200 mA GND Internally I DC output current A OUT limited - I Reverse DC output current 30 A OUT I DC input current -1 to 10 mA IN I DC current sense disable input current -1 to 10 mA CSD -I DC reverse CS pin current 200 mA CSENSE V -41 V V Current sense maximum voltage CC CSENSE +V V CC Maximum switching energy (single pulse) E 104 mJ MAX (L= 3mH; R =0Ω; V =13.5V; T =150ºC; I = I (Typ.) ) L bat jstart OUT limL 7/31

Electrical specifications VN5050AJ-E Table 4. Absolute maximum ratings (continued) Symbol Parameter Value Unit Electrostatic discharge (Human Body Model: R=1.5kΩ; C=100pF) - INPUT 4000 V - CURRENT SENSE 2000 V V ESD - CS_DIS 4000 V - OUTPUT 5000 V - V 5000 V CC V Charge device model (CDM-AEC-Q100-011) 750 V ESD T Junction operating temperature -40 to 150 °C j T Storage temperature -55 to 150 °C stg 2.2 Thermal data T able 5. Thermal data Symbol Parameter Max value Unit R Thermal resistance junction-case (MAX) 2.7 °C/W thj-case R Thermal resistance junction-ambient (MAX) See Figure 29. °C/W thj-amb 8/31

VN5050AJ-E Electrical specifications 2.3 Electrical characteristics Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless otherwise specified. T able 6. Power section Symbol Parameter Test conditions Min. Typ. Max. Unit Operating supply V 4.5 13 36 V CC voltage Undervoltage V 3.5 4.5 V USD shutdown Undervoltage V 0.5 V USDhyst shutdown hysteresis I = 2A; T=25°C 50 mΩ OUT j R On state resistance I = 2A; T=150°C 100 mΩ ON OUT j I = 2A; V =5V; T=25°C 65 mΩ OUT CC j V Clamp voltage I = 20mA 41 46 52 V clamp S Off State; V =13V; T=25°C; CC j IS Supply current VIN=VOUT=VSENSE=VCSD=0V 2(1) 5(1) µA On State; VCC=13V; VIN=5V; IOUT=0A 1.5 3 mA V =V =0V; V =13V; T=25°C 0 0.01 3 I Off state output current IN OUT CC j µA L(off) V =V =0V; V =13V; T=125°C 0 5 IN OUT CC j Output - V diode V CC -I = 2A; T= 150°C 0.7 V F voltage OUT j 1. PowerMOS leakage included. T able 7. Switching (V =13V, T=25°C) CC j Symbol Parameter Test conditions Min. Typ. Max. Unit t Turn-on delay time R = 6.5Ω (see Figure 7.) 20 µs d(on) L t Turn-off delay time R = 6.5Ω (see Figure 7.) 40 µs d(off) L See (dV /dt) Turn-on voltage slope R = 6.5Ω V/µs OUT on L Figure20 See (dV /dt) Turn-off voltage slope R = 6.5Ω V/µs OUT off L Figure22 Switching energy losses W R = 6.5Ω (see Figure 7.) 0.20 mJ ON during tw L on Switching energy losses W R = 6.5Ω (see Figure 7.) 0.3 mJ OFF during tw L off 9/31

Electrical specifications VN5050AJ-E T able 8. Logic input Symbol Parameter Test conditions Min. Typ. Max. Unit V Input low level voltage 0.9 V IL I Low level input current V = 0.9V 1 µA IL IN V Input high level voltage 2.1 V IH I High level input current V = 2.1V 10 µA IH IN V Input hysteresis voltage 0.25 V I(hyst) I = 1mA 5.5 7 V V Input clamp voltage IN ICL I = -1mA -0.7 V IN V CS_DIS low level voltage 0.9 V CSDL I Low level CS_DIS current V = 0.9V 1 µA CSDL CSD V CS_DIS high level voltage 2.1 V CSDH I High level CS_DIS current V = 2.1V 10 µA CSDH CSD V CS_DIS hysteresis voltage 0.25 V CSD(hyst) I = 1mA 5.5 7 V V CS_DIS clamp voltage CSD CSCL I = -1mA -0.7 V CSD T able 9. Protection and diagnostics(1) Symbol Parameter Test conditions Min. Typ. Max. Unit I DC Short circuit VCC = 13V 12 16.5 23 A limH current 5V<V <36V 23 A CC Short circuit current I V =13V T <T<T 7 A limL during thermal cycling CC R j TSD Shutdown T 150 175 200 °C TSD temperature T Reset temperature T + 1 T + 5 °C R RS RS Thermal reset of T 135 °C RS STATUS Thermal hysteresis T 7 °C HYST (T -T ) TSD R Turn-off output voltage V I = 2A; V = 0; L= 6mH V -41 V -46 V -52 V DEMAG clamp OUT IN CC CC CC I = 0.1A; Output voltage drop OUT VON limitation Tj= -40°C...+150°C 25 mV (see Figure 5.) 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles. 10/31

VN5050AJ-E Electrical specifications T able 10. Current sense (8V<V <16V) CC Symbol Parameter Test conditions Min. Typ. Max. Unit I = 0.05A; V =0.5V; V =0V; K I /I OUT SENSE CSD 1100 2440 3480 0 OUT SENSE T= -40°C...150°C j I =1A; V =0.5V; V =0V; OUT SENSE CSD 1600 2030 2580 T= -40°C...150°C K I /I j 1 OUT SENSE I = 1A; V = 0.5V; V = 0V; OUT SENSE CSD 1630 2030 2430 T= 25°C...150°C j I =1A; V = 0.5V; OUT SENSE Current sense ratio dK /K (1) V =0V; -10 +10 % 1 1 drift CSD T =-40 °C to 150 °C J I = 2A; V = 4V; V = 0V; OUT SENSE CSD 1770 2000 2310 T= -40°C...150°C K I /I j 2 OUT SENSE I = 2A; V = 4V; V = 0V; OUT SENSE CSD 1800 2000 2200 T= 25°C...150°C j I = 2 A; V = 4 V; OUT SENSE Current sense ratio dK /K (1) V = 0V; -6 +6 % 2 2 drift CSD T = -40 °C to 150 °C J I = 4A; V = 4V; V = 0V; OUT SENSE CSD 1860 1970 2140 T= -40°C...150°C K I /I j 3 OUT SENSE I = 4A; V = 4V; V = 0V; OUT SENSE CSD 1870 1970 2120 T= 25°C...150°C j I = 4 A; V = 4 V; OUT SENSE Current sense ratio dK /K (1) V =0V; -3 +3 % 3 3 drift CSD T =-40 °C to 150 °C J I = 0A; V =0V; OUT SENSE V = 5V; V =0V; T= -40°C...150°C 0 1 µA CSD IN j I Analog sense VCSD= 0V; VIN=5V; Tj= -40°C...150°C 0 2 µA SENSE0 leakage current I = 2A; V = 0V; OUT SENSE V = 5V; V =5V; T= -40°C...150°C 0 1 µA CSD IN j Openload ON state I current detection V = 5V, I = 5 µA 4 20 mA OL IN SENSE threshold Max analog sense V I =2A; V =0V 5 V SENSE output voltage OUT CSD Analog sense output voltage in V V =13V; R =10KΩ 9 V SENSEH overtemperature CC SENSE condition Analog sense output current in I V =13V, V =5V 8 mA SENSEH overtemperature CC SENSE condition 11/31

Electrical specifications VN5050AJ-E Table 10. Current sense (8V<V <16V) (continued) CC Symbol Parameter Test conditions Min. Typ. Max. Unit Delay response VSENSE<4V, 0.5A<Iout<4A tDSENSE1H time from falling ISENSE=90% of ISENSEmax 50 100 µs edge of CS_DIS pin (see Figure 4.) Delay response VSENSE<4V, 0.5A<Iout<4A tDSENSE1L time from rising ISENSE=10% of ISENSEmax 5 20 µs edge of CS_DIS pin (see Figure 4.) Delay response VSENSE<4V, 0.5A<Iout<4A tDSENSE2H time from rising ISENSE=90% of ISENSE max 80 250 µs edge of INPUT pin (see Figure 4.) Delay response time between rising VSENSE<4V, Δt edge of output ISENSE =90% of ISENSEMAX, 65 (cid:0)(cid:0)µ DSENSE2H current and rising I =90% of I s OUT OUTMAX edge of current I =2A (see Figure6) OUTMAX sense Delay response VSENSE<4V, 0.5A<Iout<4A tDSENSE2L time from falling ISENSE=10% of ISENSE max 100 250 µs edge of INPUT pin (see Figure 4.) 1. Parameter guaranteed by design; it is not tested. Figure 4. Current sense delay characteristics INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L Figure 5. Output voltage drop limitation V -V cc out Tj=150oC T=25oC j T=-40oC j V on I out V /R on on(T) 12/31

VN5050AJ-E Electrical specifications Figure 6. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) V IN Δt DSENSE2H t I OUT I OUTMAX 90% I OUTMAX t I SENSE I SENSEMAX 90% I SENSEMAX t Figure 7. Switching characteristics V OUT tWon tWoff 90% 80% dVOUT/dt(on) dVOUT/dt(off) tr 10% tf t INPUT td(on) td(off) t 13/31

Electrical specifications VN5050AJ-E Figure 8. I /I Vs. I (see Table 10. for details) OUT SENSE OUT I / I out sense 2800 2600 max Tj = -40 °C to 150 °C 2400 2200 max Tj = 25 °C to 150 °C typical value 2000 min Tj = 25 °C to 150 °C 1800 min Tj = -40 °C to 150 °C 1600 1400 1200 1 1,5 2 2,5 3 3,5 4 4,5 5 I (A) OUT Figure 9. Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 1 2 3 4 IOUT (A) Note: Parameter guaranteed by design; it is not tested. 14/31

VN5050AJ-E Electrical specifications T able 11. Truth table Conditions Input Output Sense (V =0V)(1) CSD L L 0 Normal operation H H Nominal L L 0 Overtemperature H L V SENSEH L L 0 Undervoltage H L 0 L L 0 Short circuit to GND H L 0 if T < T (Rsc ≤ 10 mΩ) j TSD H L V if T > T SENSEH j TSD L H 0 Short circuit to V CC H H < Nominal Negative output voltage L L 0 clamp 1. If the V is high, the SENSE output is at a high impedance, its potential depends on leakage currents CSD and external circuit. 15/31

Electrical specifications VN5050AJ-E T able 12. Electrical transient requirements ISO 7637-2: Test levels Number of Burst cycle/pulse Delays and 2004(E) pulses or repetition time Impedance Test pulse III IV test times 1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω 2a +37V +50V 5000 pulses 0.2 s 5 s 50 μs, 2 Ω 3a -100V -150V 1h 90 ms 100 ms 0.1 μs, 50 Ω 3b +75V +100V 1h 90 ms 100 ms 0.1 μs, 50 Ω 100 ms, 0.01 4 -6V -7V 1 pulse Ω 5b(2) +65V +87V 1 pulse 400 ms, 2 Ω ISO 7637-2: Test level results(1) 2004(E) Test pulse III IV 1 C C 2a C C 3a C C 3b C C 4 C C 5b(2) C C 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Class Contents C All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to E disturbance and cannot be returned to proper operation without replacing the device. 16/31

VN5050AJ-E Electrical specifications Figure 10. Waveforms NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VCC VUSD INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT <Nominal <Nominal OVERLOAD OPERATION Tj TR TTSD TRS INPUT CS_DIS ILIMH LOAD CURRENT ILIML VSENSEH SENSE CURRENT current power thermal cycling limitation limitation SHORTED LOAD NORMAL LOAD 17/31

Electrical specifications VN5050AJ-E 2.4 Electrical characteristics curves Figure 11. O ff state output current Figure 12. High level input current TBD Figure 13. I n put clamp voltage Figure 14. Input low level Figure 15. I n put high level Figure 16. Input hysteresis voltage 18/31

VN5050AJ-E Electrical specifications Figure 17. O n state resistance vs. T Figure 18. On state resistance vs. V case CC Figure 19. U ndervoltage shutdown Figure 20. Turn-On voltage slope Figure 21. I Vs. T Figure 22. Turn-Off voltage slope LIMH case TBD 19/31

Electrical specifications VN5050AJ-E Figure 23. C S_DIS high level voltage Figure 24. CS_DIS clamp voltage Figure 25. CS_DIS low level voltage 20/31

VN5050AJ-E Application information 3 Application information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld μC Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE RGND Cext VGND DGND . 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: resistor in the ground line (R only) GND This can be used with any type of load. The following show how to dimension the R resistor: GND 1. R ≤ 600mV / (I ) GND S(on)max 2. R ≥ (−V ) / (-I ) GND CC GND where -I is the DC reverse ground pin current and can be found in the absolute GND maximum rating section of the device datasheet. Power dissipation in R (when V <0 during reverse battery situations) is: GND CC P = (-V )2/ R D CC GND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where I becomes the sum of the S(on)max maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the R will produce a shift (I * R ) in the input thresholds and the status output GND S(on)max GND values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same R . GND 21/31

Application information VN5050AJ-E If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: diode (D ) in the ground line GND Note that a resistor (R =1kΩ) should be inserted in parallel to D if the device drives GND GND an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection D is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the ld V maximum DC rating. The same applies if the device is subject to transients on the V CC CC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the V line, CC the control pins will be pulled negative. ST suggests to insert a resistor (R ) in line to prot prevent the µC I/O pins from latching up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os: -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Equation 1: For the following conditions: V = - 100V CCpeak I ≥ 20mA latchup VOHμC ≥ 4.5V 5kΩ ≤ R ≤ 180kΩ. prot Recommended values are: R =10kΩ, C =10nF prot EXT 22/31

VN5050AJ-E Application information 3.4 Maximum demagnetization energy (V = 13.5V) CC Figure 27. Maximum turn Off current versus inductance 100 A A B B C C 10 A) I ( 1 0,1 1 L (mH) 10 100 A: T =150°C single pulse jstart B: T =100°C repetitive pulse jstart C: T =125°C repetitive pulse jstart V , I IN L Demagnetization Demagnetization Demagnetization t Note: Values are generated with R =0 Ω.In case of repetitive pulses, T (at beginning of each L jstart demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 23/31

Package and PCB thermal data VN5050AJ-E 4 Package and PCB thermal data 4.1 PowerSSO-12™ thermal data Figure 28. PowerSSO-12™ PC Board Note: Layout condition of R and Z measurements (PCB: Double layer, Thermal Vias, FR4 th th area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. R Vs. PCB copper area in open box free air condition thj-amb RTHj_amb(°C/W) 65 60 55 50 45 40 35 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 24/31

VN5050AJ-E Package and PCB thermal data Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse ZTH (°C/W) 100 Footprint 2 cm2 8 cm2 10 1 0,1 0,001 0,01 0,1 1 10 100 1000 Time (s) Equation 2: pulse calculation formula ZTHδ = RTH⋅δ+ZTHtp(1–δ) where δ = t /T P Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ (a) a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. 25/31

Package and PCB thermal data VN5050AJ-E T able 13. Thermal parameter Area/island (cm2) Footprint 2 8 R1 (°C/W) 0.7 R2 (°C/W) 2.8 R3 (°C/W) 3 R4 (°C/W) 8 8 7 R5 (°C/W) 22 15 10 R6 (°C/W) 26 20 15 C1 (W.s/°C) 0.001 C2 (W.s/°C) 0.0025 C3 (W.s/°C) 0.0166 C4 (W.s/°C) 0.2 0.1 0.1 C5 (W.s/°C) 0.27 0.8 1 C6 (W.s/°C) 3 6 9 26/31

VN5050AJ-E Package information 5 Package information ® 5.1 ECOPACK packages In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.2 Package mechanical data Figure 32. PowerSSO-12™ package dimensions 27/31

Package information VN5050AJ-E T able 14. PowerSSO-12™ mechanical data Millimeters Symbol Min. Typ. Max. A 1.250 1.620 A1 0.000 0.100 A2 1.100 1.650 B 0.230 0.410 C 0.190 0.250 D 4.800 5.000 E 3.800 4.000 e 0.800 H 5.800 6.200 h 0.250 0.500 L 0.400 1.270 k 0° 8° X 2.200 2.800 Y 2.900 3.500 ddd 0.100 28/31

VN5050AJ-E Package information 5.3 Packing information Figure 33. PowerSSO-12™ tube shipment (no suffix) B Base Q.ty 100 C Bulk Q.ty 2000 Tube length (± 0.5) 532 A 1.85 A B 6.75 C (± 0.1) 0.6 All dimensions are in mm. Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty 2500 Bulk Q.ty 2500 A (max) 330 B (min) 1.5 C (± 0.2) 13 F 20.2 G (+ 2 / -0) 12.4 N (min) 60 T (max) 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width W 12 Tape Hole Spacing P0 (± 0.1) 4 Component Spacing P 8 Hole Diameter D (± 0.05) 1.5 Hole Diameter D1 (min) 1.5 Hole Position F (± 0.1) 5.5 Compartment Depth K (max) 4.5 Hole Spacing P1 (± 0.1) 2 All dimensions are in mm. End Start Top No components Components No components cover tape 500mm min Empty components pockets 500mm min saled with cover tape. User direction of feed 29/31

Revision history VN5050AJ-E 6 Revision history T able 15. Document revision history Date Revision Changes 24-Jan-2006 1 Initial release. Jul-2006 2 Minor updates. Document reformatted. Table14: PowerSSO-12™ mechanical data, X and Y values (slug dimensions) updated. 06-Feb-2007 3 Table10: Current sense (8V<V <16V) t entry updated. CC DSENSE2H Figure27: Maximum turn Off current versus inductance and Table13: Thermal parameter updated. Document reformatted and restructured. Contents and lists of tables and figures added. Figure2: Configuration diagram (top view) updated: pins 1-6-7-12 left unconnected (N.C). Table4: Absolute maximum ratings: updated EMAX entries. Table10 : added dk1/k1, dk2/k2, dk3/k3, Δt . DSENSE2H Added Figure6: Delay response time between rising edge of ouput 13-Sep-2007 4 current and rising edge of current sense (CS enabled). Updated Figure8: I /I Vs. I (see Table 10. for details). OUT SENSE OUT Added Figure9: Maximum current sense ratio drift vs load current. Table12: Electrical transient requirements : updated test level values III and IV for test pulse 5b and notes. Corrected Figure30: PowerSSO-12™ thermal impedance junction ambient single pulse. Figure2: Configuration diagram (top view): added note. Updated Table10: Current sense (8V<V <16V) : CC – changed t max value from 300 µs to 250µs. DSENSE2H – added I parameter. OL Updated Section4.1: PowerSSO-12™ thermal data: – changed Figure29: Rthj-amb Vs. PCB copper area in open box free air condition. 7-Dec-2007 5 – changed Figure30: PowerSSO-12™ thermal impedance junction ambient single pulse. – updated Table13: Thermal parameter: R1 value changed from 0.6 to 0.7 °C/W. R3 value changed from 6.5 to 3 °C/W R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W. C3 value changed from 0.022 to 0.0166 W.s/°C Corrected typing error in Table10: Current sense (8V<V <16V) : 12-Feb-2008 6 CC changed I test condition from V = 0V to V = 5V. OL IN IN 23-Sep-2013 7 Updated Disclaimer. 30/31

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