UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Digital PWM System Controller FEATURES APPLICATIONS 1 • FullyConfigurableMulti-OutputandMulti- • Industrial/ATE 2 PhaseNon-IsolatedDC/DCPWMController • NetworkingEquipment • ControlsUpto4VoltageRailsandUpto8 • TelecommunicationsEquipment Phases • Servers • SupportsSwitchingFrequenciesUpto2MHz • StorageSystems with250psDuty-CycleResolution • FPGA,DSPandMemoryPower • UpTo1mVClosedLoopResolution • Hardware-Accelerated,3-Pole/3-Zero DESCRIPTION CompensatorwithNon-LinearGainfor The UCD9248 is a multi-rail, multi-phase ImprovedTransientPerformance synchronousbuckdigitalPWMcontrollerdesignedfor • SupportsMultipleSoft-StartandSoft-Stop non-isolated DC/DC power applications. This device ConfigurationsIncludingPrebiasStart-up integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface • SupportsVoltageTracking,Marginingand to support configurability, monitoring and Sequencing management. • SupportsCurrentandTemperatureBalancing The UCD9248 was designed to provide a wide forMulti-PhasePowerStages variety of desirable features for non-isolated DC/DC • SupportsPhaseAdding/SheddingforMulti- converter applications while minimizing the total PhasePowerStages system component count by reducing external • SyncIn/OutPinsAlignDPWMClocksBetween circuits. The solution integrates multi-loop MultipleUCD92xxDevices management with sequencing, margining, tracking and intelligent phase management to optimize for • 12-BitDigitalMonitoringofPowerSupply total system efficiency. Additionally, loop ParametersIncluding: compensation and calibration are supported without – Input/OutputCurrentandVoltage theneedtoaddexternalcomponents. – TemperatureatEachPowerStage To facilitate configuring the device, the Texas • MultipleLevelsofOver-currentFault Instruments Fusion Digital Power™ Designer is Protection: provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool – ExternalCurrentFaultInputs allows the design engineer to configure the system – AnalogComparatorsMonitorCurrent operating parameters for the application, store the SenseVoltage configuration to on-chip non-volatile memory and – CurrentContinuallyDigitallyMonitored observe both frequency domain and time domain simulationsforeachofthepowerstageoutputs. • Over-andUnder-voltageFaultProtection • Over-temperatureFaultProtection TI has also developed multiple complementary power stage solutions – from discrete drivers in the UCD7k • EnhancedNonvolatileMemorywithError family to fully tested power train modules in the PTD CorrectionCode(ECC) family. These solutions have been developed to • DeviceOperatesFromaSingleSupplywithan complement the UCD9k family of system power InternalRegulatorControllerThatAllows controllers. OperationOveraWideSupplyVoltageRange • SupportedbyFusionDigitalPower™ Designer,aFullFeaturedPCBasedDesign TooltoSimulate,Configure,andMonitor PowerSupplyPerformance 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. FusionDigitalPower,Auto-IDaretrademarksofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2010–2012,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) OPERATINGTEMPERATURE ORDERABLEPART PINCOUNT SUPPLY PACKAGE TOPSIDE RANGE,T NUMBER MARKING A UCD9248PFCR 80-pin Reelof1000 QFP UCD9248 –40°Cto125°C UCD9248PFC 80-pin Trayof119 QFP UCD9248 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT VoltageappliedatV toDGND –0.3to3.8 V 33D VoltageappliedatV toAGND –0.3to3.8 V 33A Voltageappliedtoanypin(2) –0.3to3.8 V Storagetemperature(T ) –40to150 °C STG (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoGND. RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Supplyvoltageduringoperation,V ,V ,V 3 3.3 3.6 V 33D 33DIO 33A T Operatingfree-airtemperaturerange(1) –40 125 °C A T Junctiontemperature (1) 125 °C J (1) Whenoperating,theUCD9248’stypicalpowerconsumptioncausesa15°Ctemperaturerisefromambient. ELECTRICAL CHARACTERISTICS PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT IV33A V33A=3.3V 8 15 IV33DIO V33DIO=3.3V 2 10 IV33D Supplycurrent V33D=3.3V 40 45 mA IV33D Vin33flDas=h3m.3eVmosrtoyringconfigurationparameters 50 55 INTERNALREGULATORCONTROLLERINPUTS/OUTPUTS V33 3.3-Vlinearregulator EmitterofNPNtransistor 3.25 3.3 3.6 V V33FB 3.3-Vlinearregulatorfeedback 4 4.6 IV33FB Seriespassbasedrive VVIN=12V 10 mA Beta SeriesNPNpassdevice 40 EXTERNALLYSUPPLIED3.3VPOWER V33D Digital3.3-Vpower TA=25°C 3.0 3.6 V V33A Analog3.3-Vpower TA=25°C 3.0 3.6 V 2 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 ELECTRICAL CHARACTERISTICS (continued) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ERRORAMPLIFIERINPUTSEAPn,EANn VCM Commonmodevoltageeachpin –0.15 1.848 V VERROR Internalerrorvoltagerange AFE_GAINfieldofCLA_GAINS=0(1) –256 248 mV EAP-EAN Errorvoltagedigitalresolution AFE_GAINfieldofCLA_GAINS=3 1 mV REA InputImpedance Groundreference 0.5 1.5 3 MΩ IOFFSET Inputoffsetcurrent 1kΩsourceimpedence –5 5 µA Vref10-bitDAC Vref Referencevoltagesetpoint 0 1.6 V Vrefres Referencevoltageresolution 1.56 mV ANALOGINPUTSCS-1A,CS-1B,CS-2A,CS-2B,CS-3A,CS-3B,CS-4A,CS-4B,Vin/Iin,TEMP,ADDR-0,ADDR-1,Vtrack,ADCref VADDR_OPEN Voltageindicatingopenpin ADDR-0,ADDR-1open 2.37 V VADDR_SHORT Voltageindicatingshortedpin ADDR-0,ADDR-1shorttoground 0.36 V VADC_RANGE Measurementrangeforvoltagemonitoring ICnSp-u2tsA:,VCinS/-I2inB,VCtrSa-c3kA,,TCeSm-p3,BC,SC-S1-A4,AC,SC-S1-B4,B 0 2.5 V Over-currentcomparatorthresholdvoltage VOC_THRS range(2) Inputs:CS-1A,CS-2A,CS-3A,CS-4A 0.032 2 V Over-currentcomparatorthresholdvoltage VOC_RES range Inputs:CS-1A,CS-2A,CS-3A,CS-4A 31.25 mV ADCref Externalreferenceinput 1.8 V33A V Tempinternal Int.temperaturesenseaccuracy Overrangefrom0°Cto125°C –5 5 °C INL ADCintegralnonlinearity –2.5 2.5 mV Ilkg Inputleakagecurrent 3Vappliedtopin 100 nA RIN Inputimpedance Groundreference 8 MΩ CIN CurrentSenseInputcapacitance 10 pF DIGITALINPUTS/OUTPUTS VOL Low-leveloutputvoltage IOL=6mA(3),V33DIO=3V +D0g.2n5d V VOH High-leveloutputvoltage IOH=-6mA(4),V33DIO=3V V–303.D6IVO V VIH High-levelinputvoltage V33DIO=3V 2.1 3.6 V VIL Low-levelinputvoltage V33DIO=3.5V 1.4 V SYSTEMPERFORMANCE VRESET Voltagewheredevicecomesoutofreset V33DPin 2.3 2.4 V tRESET Pulsewidthneededforreset nRESETpin 2 µs Vrefcommandedtobe1V,at25°C, VRefAcc Setpointreferenceaccuracy AFEgain=4,1VinputtoEAP/Nmeasuredat –10 10 mV outputoftheEADC(5) Setpointreferenceaccuracyovertemperature –40°Cto125°C –20 20 mV VDiffOffset Differentialoffsetbetweengainsettings AFEgain=4comparedtoAFEgain=1,2,or8 –4 4 mV 240+1 tDelay Digitalcompensatordelay 240 switching ns cycle FSW Switchingfrequency 15.260 2000 kHz Duty MaxandMindutycycle 0% 100% V33Slew MinimumV33slewrateduringpoweron V33slewratebetween2.3Vand2.9V 0.25 V/ms tretention Retentionofconfigurationparameters TJ=25°C 100 Years Write_Cycles Numberofnonvolatileerase/writecycles TJ=25°C 20 Kcycles (1) SeetheUCD92xxPMBusCommandReferenceforthedescriptionoftheAFE_GAINfieldofCLA_GAINScommand. (2) Canbedisabledbysettingto'0' (3) ThemaximumI ,foralloutputscombined,shouldnotexceed12mAtoholdthemaximumvoltagedropspecified. OL (4) ThemaximumI ,foralloutputscombined,shouldnotexceed48mAtoholdthemaximumvoltagedropspecified. OH (5) Withdefaultdevicecalibration.PMBuscalibrationcanbeusedtoimprovetheregulationtolerance Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com ADC MONITORING INTERVALS AND RESPONSE TIMES The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power stage's output current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage). The length of the sequence is determined by the number of output rails (NumRails) and total output power stages (NumPhases) configured for use. The time to complete the monitoring samplingsequenceisgivebytheformula: t =t ×(NumRAILS+NumPHASE+4) ADC_SEQ ADC PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t ADCsingle-sampletime 3.84 µs ADC Min=1Rail+1Phase+4=6samplesMax=4 t ADCsequencerinterval 23.04 61.44 µs ADC_SEQ Rails+8Phases+4=16samples The most recent ADC conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The monitoringoperatesasynchronouslytotheADC,atintervalsshowninthetablebelow. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT t Outputvoltagemonitoringinterval 200 µs Vout t Outputcurrentmonitoringinterval 200×NRails µs Iout t Inputvoltagemonitoringinterval 2 ms Vin t Inputcurrentmonitoringinterval 2 ms Iin t Temperaturemonitoringinterval 100 ms TEMP t Outputcurrentbalancinginterval 2 ms Ibal Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC sequence interval. Once a fault condition is detected, some additional time is required to determine the correct action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following tableliststheworse-casefaultresponsetimes. PARAMETER TESTCONDITIONS MAXTIME UNIT Over-/under-voltagefaultresponsetimeduring Normalregulation,noPMBusactivity,8 300 µs normaloperation stagesenabled t ,t Over-/under-voltagefaultresponsetime,during Duringdataloggingtononvolatilememory(1) 800 µs OVF UVF datalogging Over-/under-voltagefaultresponsetime,when Duringtrackingandsoft-startramp. 400 µs trackingorsequencingenable Over-/under-currentfaultresponsetimeduring Normalregulation,noPMBusactivity,8 100+(600×NRails) µs normaloperation stagesenabled75%to125%currentstep Over-/under-currentfaultresponsetime,during Duringdataloggingtononvolatilememory t ,t 600+(600×NRails) µs OCF UCF datalogging 75%to125%currentstep Over-/under-currentfaultresponsetime,when Duringtrackingandsoftstartramp75%to 300+(600×NRails) µs trackingorsequencingenable 125%currentstep Temperatureriseof10°C/sec, t Over-temperaturefaultresponsetime 2.5 S OTF OTthreshold=100°C (1) DuringaSTORE_DEFAULT_ALLcommand,whichstorestheentireconfigurationtononvolatilememory,thefaultdetectionlatencycan beupto10ms. 4 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 HARDWARE FAULT DETECTION LATENCY ThecontrollercontainshardwarefaultdetectioncircuitsthatareindependentoftheADCmonitoringsequencer. PARAMETER TESTCONDITIONS MAX UNIT t TimetodisableDPWMoutputbasedoncorresponding 15+3× FAULT HighlevelonFAULTpin µs activeFLTpin NumPhases TimetodisablethefirstDPWMoutputbasedon StepchangeinCSvoltagefrom0Vto Switch 4 internalanalogcomparatorfault 2.5V Cycles tCLF TimetodisableallremainingDPWMandSREoutputs StepchangeinCSvoltagefrom0Vto 10+3× configuredforthevoltagerailafteraninternalanalog µs 2.5V NumPhases comparatorfault PMBUS/SMBUS/I2C The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBusareshownbelow. I2C/SMBus/PMBus TIMING CHARACTERISTICS T =–40°Cto125°C,3V<V33<3.6V,typicalvaluesatT =25°C A A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f SMBus/PMBusoperatingfrequency Slavemode;SMBC50%dutycycle 10 1000 kHz SMB f I2Coperatingfrequency Slavemode;SCL50%dutycycle 10 1000 kHz I2C t Busfreetimebetweenstartandstop 4.7 µs (BUF) t Holdtimeafter(repeated)start 0.26 µs (HD:STA) t Repeatedstartsetuptime 0.26 µs (SU:STA) t Stopsetuptime 0.26 µs (SU:STO) t Dataholdtime Receivemode 0 ns (HD:DAT) t Datasetuptime 50 ns (SU:DAT) t Errorsignal/detect See (1) 35 ms (TIMEOUT) t Clocklowperiod 0.5 µs (LOW) t Clockhighperiod See (2) 0.26 50 µs (HIGH) t Cumulativeclocklowslaveextendtime See (3) 25 ms (LOW:SEXT) t Clock/datafalltime See (4) 120 ns FALL t Clock/datarisetime See (5) 120 ns RISE (1) TheUCD9248timesoutwhenanyclocklowexceedst(TIMEOUT). (2) t ,max,istheminimumbusidletime.SMBC=SMBD=1fort>50mscausesresetofanytransactioninvolvingUCD9248thatis (HIGH) inprogress. (3) t isthecumulativetimeaslavedeviceisallowedtoextendtheclockcyclesinonemessagefrominitialstarttothestop. (LOW:SEXT) (4) Risetimet =V –0.15)to(V +0.15) RISE ILMAX IHMIN (5) Falltimet =0.9V to(V –0.15) FALL 33 ILMAX Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com Figure1. I2C/SMBus/PMBusTiminginExtendedModeDiagram 6 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Fusion Power Peripheral4 Digital DPWM-4A EAp4 Analog front end Compensator DPWM-4B High Res (AFE) 3P/3Z IIR EAn4 PWM FAULT-4A FAULT-4B Fusion Power Peripheral3 Digital DPWM-3A EAp3 Analog front end Compensator DPWM-3B High Res (AFE) 3P/3Z IIR EAn3 PWM FAULT-3A FAULT-3B Fusion Power Peripheral2 Digital DPWM-2A EAp2 Analog front end Compensator DPWM-2B High Res (AFE) 3P/3Z IIR EAn2 PWM FAULT-2A FAULT-2B Fusion Power Peripheral1 Aalog front end Compensator EAp1 DPWM-1A Diff Digital EAn1 Amp Ref AEmrrp A6DbCit 3PII/R3Z HiPghW RMes FFDAAPUUWLLMTT---111BAB Coeff. Regs SYNC-IN SYNC-OUT 5 V33x 3.3V reg. SRE-4B 6 controller Analog Comparators SRE-4A xGnd &1.8V SRE-3B BPCap regulator SRE SRE-3A Trip1 control SRE-2B Ref1 ARM-7core SRE-2A SRE-1B ADDR-0 Trip2 SRE-1A ADDR-1 Ref2 CS-1A Flash Mux TMUX0 CCCSSS---122BAB 1A2D-bCit Ref3 Trip3 memEoCryC with control TTMMUUXX12 CS-3A 260ksps Seq. SEQ_1 SEQ_2 CS-3B control SEQ_3 CCSS--44AB Ref4 Trip4 Osc PMBus-Clk Vin/Iin PMBus-Data Vtrack POR/BOR PMBus PMBus-Alert Temperature PMBus-Cntl internal PGood Temp sense ADCref nRESET Figure2. FunctionalBlockDiagram Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com TheUCD9248isavailableinan80-pinTQFPpackage(PFC). 4) 3) 1 1 D D GND3 S-1B S-2B DDR-0 DDR-1 S-1A S-3B S-4B ux-in(A ux-in(A 33FB An4 Ap4 An3 Ap3 An2 Ap2 An1 Ap1 GND2 A C C A A C C C A A V E E E E E E E E A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 ADCref 1 60 AGND1 CS-4A 2 59 BPCap CS-3A 3 58 V33A CS-2A 4 57 V33D Vin/Iin 5 56 V33DIO Vtrack 6 55 DGND3 Temperature 7 54 TMUX-2 V33DIO 8 53 SEQ-2 DGND1 9 52 SRE-3B UCD9248 SEQ-3 10 51 SRE-2A SRE-1B 11 50 SRE-4B SRE-1A 12 49 PGood nRESET 13 48 nTRST TRCK 14 47 TMS FLT-1A 15 46 TDI FLT-1B 16 45 TDO FLT-2A 17 44 TCK FLT-2B 18 43 FLT-4B PMBus_Clk 19 42 FLT-4A PMBus_Data 20 41 FLT-3B 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-3B DPWM-4A DPWM-4B FLT-3A Sync-Out Sync-In SEQ-1 SRE-4A DGND2 MBus_Alert us_Control SRE-2B SRE-3A TMUX-0 TMUX-1 P MB P Figure3. PinAssignmentDiagram TYPICAL APPLICATION SCHEMATIC Figure 4 shows the UCD9248 power supply controller as part of a system that provides the regulation of one eight-phase power supply. The loop for the power supply is created by the voltage output feeding into the differential voltage error ADC (EADC) input, and completed by DPWM outputs feeding into the gate drivers for eachpowerstage. The ±V rail signal must be routed to the EAp/EAn input that matches the number of the lowest DPWM sense configuredaspartoftherail.(SeemoredetailinFlexibleRail/PowerStageConfiguration.) 8 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 UCD7231Power Stage Vin Vin +3.3V Temp_1A Vin HS_SNS TemSpeenrsaotrure FF BST PWM HS_Gate +Vs SRE SW IOUT VGG -Vs UCD7231 BP3 SRE_Mode LS_Gate ILIM PGND RDLY Vin/Iin Vin/Iin V33FB V33A V33D V33DIO V33DIO BPCAP FLT-1A VGG_DISAGND PwPd CCSSNP Vtrack DPWM-1A Temperature Temperature SRE-1A +Vs1 CS-1A EAP1 EAN1 -Vs1 FLT-1B FF Temp Temp_1B EAP2 EAN2 DPSWRME--11BB PSWREM UCD7231Power Stage +Vs CS-1B IOUT -Vs EAP3 EAN3 FLT-2A FF Temp Temp_2A +Vs1 EAP4 EAN4 DPSWRME--22AA PSWREM UCD7231Power Stage +Vs CS-2A IOUT -Vs Sync_In Sync_Out -Vs1 FLT-2B FF Temp Temp_2B ADCref DPWM-2B PWM UCD7231Power Stage Aux-in(AD13) SRE-2B SRE +Vs Aux-in(AD14) CS-2B IOUT -Vs SEQ-1 UCD9248 SEQ-2 FLT-3A FF Temp Temp_3A SEQ-3 DPWM-3A PWM UCD7231Power Stage SRE-3A SRE +Vs TMUX-0 TMUX-0 CS-3A IOUT -Vs TMUX-1 TMUX-1 TMUX-2 TMUX-2 +3.3V FLT-3B FF Temp Temp_3B TRCK TMS DPSWRME--33BB PSWREM UCD7231Power Stage +Vs TDI CS-3B IOUT -Vs TDO TCK nTRST FLT-4A FF Temp Temp_4A ADDR-0 DPSWRME--44AA PSWREM UCD7231Power Stage +Vs ADDR-1 CS-4A IOUT -Vs PMBus_Clock PMBus_Data +3.3V PMBus_Alert FLT-4B FF Temp Temp_4B PMBus_Cntl DPWM-4B PWM UCD7231Power Stage PGood SRE-4B SRE +Vs nRESET AGND1 AGND2 AGND3 DGND1 DGND2 DGND3 PowerPad CS-4B IOUT -Vs +3.3V +3.3V Vcc Temp_1A A0 A Temperature Temp_1B A1 Temp_2A A2 Temp_2B A3 Vcc Iin B2 A Vin/Iin CD74HC4051 Vin SN74LVC1G3157 Temp_3A A7 B1 S TMUX-0 Temp_3B A5 S2 TMUX-2 Temp_4A A6 S1 TMUX-1 Gnd Temp_4B A7 S0 TMUX-0 VeeGnd E Figure4. TypicalApplicationSchematic Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com PIN DESCRIPTIONS PINNO. PINNAME DESCRIPTION 1 ADCref ADCDecouplingcapacitor–tie0.1µFcapacitortoground 2 CS-4A Powerstage4Acurrentsenseinputandinputtoanalogcomparator4 3 CS-3A Powerstage3Acurrentsenseinputandinputtoanalogcomparator3 4 CS-2A Powerstage2Acurrentsenseinputandinputtoanalogcomparator2 5 V /I Inputsupplysense,alternatesbetweenV andI in in in in 6 Vtrack Voltagetrackinput 7 Temperature Temperaturesenseinput 8 V33DIO DigitalI/O3.3Vsupply 9 DGND1 DigitalGround 10 SEQ-3 SequencingInput/Output 11 SRE-1B Synchronousrectifierenableoutput1B,activehigh 12 SRE-1A Synchronousrectifierenableoutput1A,activehigh 13 nRESET Activelowdeviceresetinput,pullupto3.3Vwith10kΩresistor 14 TRCK JTAGTestreturnclock 15 FLT-1A Externalfaultinput1A,activehigh 16 FLT-1B Externalfaultinput1B,activehigh 17 FLT-2A Externalfaultinput2A,activehigh 18 FLT-2B Externalfaultinput2B,activehigh 19 PMBus_Clock PMBusClock,pullupto3.3Vwith2kΩresistor 20 PMBus_Data PMBusData,pullupto3.3Vwith2kΩresistor 21 DPWM-1A DigitalPulseWidthModulatoroutput1A 22 DPWM-1B DigitalPulseWidthModulatoroutput1B 23 DPWM-2A DigitalPulseWidthModulatoroutput2A 24 DPWM-2B DigitalPulseWidthModulatoroutput2B 25 DPWM-3A DigitalPulseWidthModulatoroutput3A 26 DPWM-3B DigitalPulseWidthModulatoroutput3B 27 DPWM-4A DigitalPulseWidthModulatoroutput4A 28 DPWM-4B DigitalPulseWidthModulatoroutput4B 29 FLT-3A Externalfaultinput3A,activehigh 30 Sync-Out SynchronizationoutputfromDPWM 31 Sync-In SynchronizationinputtoDPWM 32 SEQ-1 SequencingInput/Output 33 SRE-4A Synchronousrectifierenableoutput4A,activehigh 34 DGND2 DigitalGround 35 PMBus_Alert PMBusAlert,pullupto3.3Vwith2kΩresistor 36 PMBus_Cntl PMBusControl,pullupto3.3Vwith2kΩresistor 37 SRE-2B Synchronousrectifierenableoutput2B,activehigh 38 SRE-3A Synchronousrectifierenableoutput3A,activehigh 39 TMUX-0 TemperaturemultiplexerselectoutputSO,Vin/Iinselect 40 TMUX-1 TemperaturemultiplexerselectoutputS1 41 FLT-3B Externalfaultinput3B,activehigh 42 FLT-4A Externalfaultinput4A,activehigh 43 FLT-4B Externalfaultinput4B,activehigh 44 TCK JTAGTestclock 45 TDO JTAGTestdataout 46 TDI JTAGTestdataintietoV33Dwith10kΩresistor 47 TMS JTAGTestmodeselect–tietoV33Dwith10kΩresistor 10 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 PINNO. PINNAME DESCRIPTION 48 nTRST JTAGTestreset–tietogroundwith10kOhmresistor 49 PGood PowerGoodindication,Activehighopen-drainoutput.Pull-upto3.3Vwith10kΩresistor. 50 SRE-4B Synchronousrectifierenableoutput4B,activehigh 51 SRE-2A Synchronousrectifierenableoutput2A,activehigh 52 SRE-3B Synchronousrectifierenableoutput3B,activehigh 53 SEQ-2 SequencingInput/Output 54 TMUX-2 TemperaturemultiplexerselectoutputS2 55 DGND3 DigitalGround 56 V33DIO DigitalI/O3.3Vsupply 57 V33D Digitalcore3.3Vsupply 58 V33A Analog3.3Vsupply 59 BPCap 1.8Vbypasscapacitorconnection 60 AGND1 AnalogGround 61 AGND2 AnalogGround 62 EAP1 Erroranalog,differentialvoltage.Positivechannel#1input 63 EAN1 Erroranalog,differentialvoltage.Negativechannel#1input 64 EAP2 Erroranalog,differentialvoltage.Positivechannel#2input 65 EAN2 Erroranalog,differentialvoltage.Negativechannel#2input 66 EAP3 Erroranalog,differentialvoltage.Positivechannel#3input 67 EAN3 Erroranalog,differentialvoltage.Negativechannel#3input 68 EAP4 Erroranalog,differentialvoltage.Positivechannel#4input 69 EAN4 Erroranalog,differentialvoltage.Negativechannel#4input 70 V33FB Connectiontothebaseofthe3.3Vlinearregulatortransistor.(noconnectifnotusinganexternal transistor) 71 Aux-In(AD13) UnusedAnalogInput–Tietogroundwitha10KOhmresistor 72 Aux-In(AD14) UnusedAnalogInput–Tietogroundwitha10KOhmresistor 73 CS-4B Powerstage4Bcurrentsenseinput 74 CS-3B Powerstage3Bcurrentsenseinput 75 CS-1A Powerstage1Acurrentsenseinputandinputtoanalogcomparator1 76 ADDR-1 Addresssenseinput.Channel1 77 ADDR-0 Addresssenseinput.Channel0 78 CS-2B Powerstage2Bcurrentsenseinput 79 CS-1B Powerstage1Bcurrentsenseinput 80 AGND3 AnalogGround Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com FUNCTIONAL OVERVIEW The UCD9248 contains four fusion power peripherals (FPP). Each FPP can be configured to regulated up to four DC/DC converter outputs. There are eight PWM outputs that can be assigned to drive the converter outputs. EachFPPconsistsof: • Adifferentialinputerrorvoltageamplifier • A10-bitDACusedtosettheoutputregulationreferencevoltage. • AfastADCwithprogrammableinputgaintodigitallymeasuretheerrorvoltage. • Adedicated3-pole/3-zerodigitalfiltertocompensatetheerrorvoltage. • AdigitalPWM(DPWM)enginethatgeneratesthePWMpulsewidthbasedonthecompensatoroutput. EachcontrollerisconfiguredthroughaPMBusserialinterface. PMBus Interface The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus interface that is built on the I2C physical specification. The UCD9248 supports revision 1.1 of the PMBus standard. Wherever possible, standard PMBus commands are used to support the function of the device. For uniquefeaturesoftheUCD9248,MFR_SPECIFICcommandsaredefinedtoconfigureoractivatethosefeatures. ThesecommandsaredefinedintheUCD92xxPMBUSCommandReference. The UCD9248 is PMBus compliant, in accordance with the Compliance section of the PMBus specification. The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function. Thehardwarecansupport100kHz,400kHz,or1MHzPMBusoperation. Resistor Programmed PMBus Address Decode Two pins are allocated to decode the PMBus address. At power-up, the device applies a bias current to each address detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is calculatedasfollows: PMBusAddress=12× PMBusAddress1+PMBusAddress0 WherePMBusAddress1and0areselectedfromTable1. V33 UCD9248 ADDR - 0, ADDR - 1 pins 10mA I BIAS Resistor to set PMBus To 12-bitADC Address Figure5. PMBusAddressDetectionMethod Table1.PMBusAddressBins R PMBusRESISTANCE PMBusADDRESS PMBus (kΩ) open – 11 205 10 178 9 154 8 133 7 115 6 100 12 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Table1.PMBusAddressBins(continued) R PMBusRESISTANCE PMBusADDRESS PMBus (kΩ) 5 86.6 4 75 3 64.9 2 56.2 1 48.7 0 42.2 short – A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the PMBus address to default to address 126. A high impedance (open) on either address pin that produces a voltageabovethemaximumvoltagealsocausesthePMBusaddresstodefaulttoaddress126. Someaddressesshouldbeavoid,seeTable2. Table2.PMBusAddressAssignmentRules ADDRESS STATUS REASON 0 Prohibited SMBusgeneralladdresscall 1-10 Avaliable 11 Avoid Causesconfilctswithotherdevicesduringprogramflashupdates. 12 Prohibited PMBusalertresponseprotocol 13–125 Avaliable 126 Avoid Defaultvalue;maycauseconflictswithotherdevices. 127 Prohibited UsedbyTImanufacturingfordevicetests. JTAG Interface TheJTAGinterfacecanprovideanalternateinterfaceforprogrammingthedevice.Itisenabledbydefaultonthe UCD9248. Bias Supply Generator (Shunt Regulator Controller) Internally, the circuits in the UCD9248 require 3.3V to operate. This can be provided directly on the V33x pins, or it can be generated from the power supply input voltage using an internal shunt regulator and an external transistor. The requirements for the external transistor are that it be an NPN device with a beta of at least 40. Figure 6 shows the typical application using the external series pass transistor. The base of the transistor is driven by a 10kΩ resistor to Vin and a transconduction amplifier whose output is on the VD33FB pin. The NPN emitterbecomesthe3.3Vsupplyforthechipandrequiresbypasscapacitorsof0.1µFand4.7µF. The transconductance amplifier sinks current into the V33FB pin, in order to regulate the amount of current allowedintothebaseofthetransistor,whichregulatesthecollectorcurrent,whichdeterminestheemittervoltage (3.3V). The resistor value should be sized low enough to give sufficient base drive at minimum input voltage, yet large enough to not exceed the maximum current sink capability of the V33FB pin at maximum input voltage. Higher beta transistors help in increasing the minimum resistance value, as less base current is needed to sufficiently drive the higher beta transistor. A resistor value of 10 kΩ works well for most applications that use the FCX491ABJT. Some circuits in the device require 1.8V that is generated internally from the 3.3V supply. This voltage requires a 0.1µFto1µFbypasscapacitorfromBPCaptoground. Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com Vin To Power Stage FCX491A +3.3V 4.7mF 10 kW +1.8V 0.1mF 0.1mF B ADp 33F V33V33PCa V B UC9248 Figure6. Series-Pass3.3VRegulatorControllerI/O Power On Reset The UCD9248 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the POR circuit detects the V33D rise. When V33D is greater than V , the device initiates an internal startup RESET sequence. At the end of the delay sequence, the device begins normal operation, as defined by the downloaded devicePMBusconfiguration. External Reset The device can be forced into the reset state by an external circuit connected to the nRESET pin. A logic low voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a 10 kΩ pull up resistorto3.3Visrecommended. Output Voltage Adjustment The nominal output voltage is programmed by a combination of PMBus commands: VOUT_COMMAND, VOUT_CAL_OFFSET, VOUT_SCALE_LOOP, and VOUT_MAX. Their relationship is shown in Figure 7. These PMBus parameters need to be set such that the resulting Vref DAC value does not exceed the maximum value ofV . ref Output voltage margining is configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands. The OPERATION command selects between the nominal output voltage and either of the margin voltages. The OPERATION command also includes an option to suppress certain voltage faults and warnings while operating atthemarginsettings. 14 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 OPERATION Command VOUT_MAX VOUT_MARGIN_HIGH + VOUT_ 3:1 VOUT_COMMAND Limiter SCALE_ Vref DAC Mux LOOP VOUT_MARGIN_LOW VOUT_CAL_OFFSET Figure7. PMBusVoltageAdjustmentMethods For a complete description of the commands supported by the UCD9248 see the UCD92xx PMBUS Command Reference. Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™ Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands to configuretheUCD9248device. Calibration To optimize the operation of the UCD9248, PMBus commands are supplied to enable fine calibration of output voltage, output current, and temperature measurements. The supported commands and related calibration formulasmaybefoundintheUCD92xxPMBUSCommandReference. Analog Front End (AFE) VEAP V GAFE=1,2,4,or8 6-bit EA VEAN Vead EADC result G =8mV/LSB eADC Vref DAC CPU Vref=1.563mV/LSB PMBus Figure8. AnalogFrontEndBlockDiagram The UCD9248 senses the power supply output voltage differentially through the EAP and EAN pins. The error amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage sensesignals.Thefullydifferentialnatureoftheerroramplifieralsoensureslowoffsetperformance. The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by the 10-bit Vref DAC as shown in Figure 8. The resulting error voltage is then amplified by a programmable gain circuit before the error voltage is converted to a digital value by the error ADC (EADC). This programmable gain is configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as showninTable3. Table3.AnalogFrontEndResolution AFE_GAINfor EFFECTIVEADCRESOLUTION DIGITALERRORVOLTAGE AFEGAIN PMBusCOMMAND (mV) DYNAMICRANGE(mV) 0 1 8 –256to248 Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com Table3.AnalogFrontEndResolution(continued) AFE_GAINfor EFFECTIVEADCRESOLUTION DIGITALERRORVOLTAGE AFEGAIN PMBusCOMMAND (mV) DYNAMICRANGE(mV) 1 2 4 –128to124 2 4 2 –64to62 3 8 1 –32to31 The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This allowstheusertotrade-offresolutionanddynamicrangeforeachoperationalmode. The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time. However, its range is limited as shown in Table 3. If the output voltage is different from the reference by more than this, the EADC reports a saturated value at –32 LSBs or 31 LSBs. The UCD9248 overcomes this limitation by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156 V/ms,referredtotheEAdifferentialinputs. The differential feedback error voltage is defined as V = V – V . An attenuator network using resistors R1 EA EAP EAN and R2 (see Figure 9) should be used to ensure that V does not exceed the maximum value of V when EA ref operating at the commanded voltage level. The commanded voltage level is determined by the PMBus settings describedintheOutputVoltageAdjustmentsection. R1 EAP +Vout R2 C2 Rin -Vout Ioff EAN Figure9. InputOffsetEquivalentCircuit Voltage Sense Filtering Conditioning should be provided on the EAP and EAN signals. Figure 9 a divider network between the output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the signal conditionedbythelow-passfilterformedbyR1andC2. As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly across an output capacitor as close to the load as possible. Route the positive and negative differential sense signalsasabalancedpairoftracesorasatwistedpaircablebacktothecontroller.Putthedividernetworkclose to the controller. This ensures that there is low impedance driving the differential voltage sense signal from the voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss and minimizing interference susceptibility. A parallel resistance (R ) of 1kΩ to 4kΩ is a good compromise. Once P R ischosen,R andR canbedeterminedfromthefollowingformulas. P 1 2 R R = P 1 K (1) R p R = 2 1 - K (2) 16 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Where V K= EA @ VOUT_SCALE_LOOP V OUT (3) It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter, thecornerfrequencyshouldbe35%to40%oftheswitchingfrequency.Thenthecapacitoriscalculatedas: 1 C = 2 2p ´ 0.35 ´ FSW ´ RP (4) To obtain the best possible accuracy, the input resistance and offset current on the device should be considered when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the UCD9224. The input resistance and input offset current are specified in the parametric tables in this datasheet. V =V –V intheequationbelow. EA EAP EAN R R R V = 2 V + 1 2 I EA OUT OFFSET æR R ö æR R ö R +R + 1 2 R +R + 1 2 1 2 ç R ÷ 1 2 ç R ÷ è EA ø è EA ø (5) Theeffectoftheoffsetcurrentcanbereducedbymakingtheresistanceofthedividernetworklow. Digital Compensator Each voltage rail controller in the UCD9248 includes a digital compensator. The compensator consists of a nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter sectioncascadedwithafirstorderIIRfiltersection. The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the compensator coefficients. The design tool allows the compensator to be described in terms of the pole frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™ Designercanbeusedtocharacterizethepowerstagesothatthecompensatorcoefficientscanbechosenbased on the total loop gain for each feedback system. The coefficients of the filter sections are generated through modelingthepowerstageandload. Additionally, the UCD9248 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is belowtheconfiguredlightloadthreshold. Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com Figure10. DigitalCompensation The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to be symmetric. For example, the four limit registers could all be set to positive values causing the Gain 0 value to setthegainforallnegativeerrorsandanonlineargainprofilewouldbeappliedtoonlypositiveerrorvoltages. Thecascaded1storderfiltersectionisusedtogeneratethethirdzeroandthirdpole. DPWM Engine The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty cycle as a digital number representing a value from 0 to 100%. This duty cycle value is multiplied by the configured period to generate a comparator threshold value. This threshold is compared against the high speed switchingperiodcountertogeneratethedesiredDPWMpulsewidth.ThisisshowninFigure11. Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SYNC_INandSYNC_OUTpins.ConfigurationofthesynchronizationfunctionisdonethroughaMFR_SPECIFIC PMBuscommand.SeetheDPWMSynchronizationsectionformoredetails. 18 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 DPWM Engine (1 of 4) high res Clk SysClk ramp counter reset SyncIn S PWM gate drive Switch period output R Current balance adj Compensator output EADC trigger (Calculated duty cycle) EADC trigger SyncOut threshold Figure11. DPWMEngine Flexible Rail/Power Stage Configuration TheUCD9248cancontroluptofourrails,eachofwhichcancompriseaprogrammablenumberofpowerstages. Constraints on the mapping of power stages to rails are described in detail in the UCD92xx PMBus Command ReferenceunderthePHASE_INFOcommand. While there is significant flexibility in terms of mapping power stages to output rails, the differential voltage feedback signals (EAP/EAN) cannot be re-mapped through any commands, and therefore, must be connected to the proper input on the circuit board. Because the EADC sample trigger for a given front end stage is derived from the ramp timer of the first (lowest numbered) DPWM on the rail, the system must ensure that the number of the EADC and the number of the first DPWM match. For example, consider a two rail configuration in which 4 power stages (1A, 2A, 1B and 2B) are assigned to the first rail and 2 power stages (3A and 4A) to the second. The first DPWM on the first rail is 1; its voltage feedback must be through EAP1/EAN1. The first DPWM on the second rail is 3; its voltage feedback must be through EAP3/EAN3. (In this configuration EAP2/EAN2 and EAP4/EAN4areunusedandaredisabledtoreduceunnecessarypowerconsumption.) DPWM Phase Distribution The number of voltage rails is configured using the PHASE_INFO PMBus command. The UCD9248 automaticallysynchronizesthefirstpowerstageofeachvoltagerail.Thephase(intime)ofeach1stpowerstage is shifted by an amount in order to minimize input current ripple. The amount that each 1st power stage is shifted is: 3t t = sw rail-railspread 13 (6) Wheret istheperiodoftherailwiththefastestswitchingfrequency. SW The ratio 3/13 is chosen because it is close to 1/4, but it is a prime ratio. This should ensure that any configurationofrailsandpowerstagesshouldnothavetheleadingedgeoftheDPWMsignalaligned. Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com The PHASE_INFO PMBus command is also used to configure the number of power stages driving each voltage rail. When multiple power stages are configured to drive a voltage rail, the UCD9248 automatically distributes the phase of each DPWM output to minimize ripple. This is accomplished by setting the rising edge of each DPWM pulsetobeseparatedby: t t = sw phase-phasespread N phases (7) Wheret istheswitchingperiodandN isthenumberofpowerstagesdrivingavoltagerail. SW Phases DPWM Synchronization DPWMsynchronizationprovidesamethodtolinkthetimingbetweenrailsontwodistinctdevicesattheswitching rate; i.e., two rails on different devices can be configured to run at the same frequency and sync forcing them not to drift from each other. (Note that within a single device, because all rails are driven off a common clock there is noneedforaninternalsyncbecauserailswon’tdrift.) The PMBus SYNC_IN_OUT command sets which rails (if any) should follow the sync input, and which rail (if any)shoulddrivethesyncoutput. Forrailsthatarefollowingthesyncinput,theDPWMramptimerforthatoutputisresetwhenthesyncinputgoes high. This allows the slave device to sync to inputs that are faster. On the fast side, there is no limit to how much faster the input is compared to the defined frequency of the rail; when the pulse comes in, the timer is reset and the frequencies are locked. This is the standard mode of operation -setting the slave to run slower, and letting thesyncspeeditup. The Sync Input and Output Configuration Word set by the PMBus command consists of two bytes. The upper byte (sync_out) controls which rail drives the sync output signal (0=DPWM1, 1=DPWM2, 2=DPWM3, 3=DPWM4. Any other value disables sync_out). The lower byte (sync_in) determines which rail(s) respond to the sync input signal (each bit represents one rail -note that multiple rails can be synchronized to the input). The DPWM period isalignedtothesyncinput.Formoreinformation,seetheUCD92xxPMBUSCommandReference. Note that once a rail is synchronized to an external source, the rail-to-rail spacing that attempts to minimize input current ripple is lost. Rail-to-rail spacing can only be restored by power cycling or issuing a SOFT_RESET command. Phase Shedding at Light Current Load ByissuingLIGHT_LOAD_LIMIT_LOW,LIGHT_LOAD_LIMIT_HIGH,andLIGHT_LOAD_CONFIGcommands,the UCD9248 can be configured to shed (disable) power stages when at light load. When this feature is enabled, the device disables the configured number of power stages when the average current drops below the specified LIGHT_LOAD_LIMIT_LOW. In addition, a separate set of compensation coefficients can be loaded into the digitalcompensatorwhenenteringalightloadcondition. Phase Adding at Normal Current Load After shedding phases, if the current load is increased past the LIGHT_LOAD_LIMIT_HIGH threshold, all phases are re-enabled. If the compensator was configured for light load, the normal load coefficients are restored as well.SeetheUCD92xxPMBUSCommandReferenceformoreinformation. Output Current Measurement Pins CS-1A, CS-1B, CS-2A, CS-2B, CS-3A, CS-3B, CS-4A, and CS-4B are used to measure either output current or inductor current in each of the controlled power stages. PMBus commands IOUT_CAL_GAIN and IOUT_CAL_OFFSET are used to calibrate each measurement. See the UCD92xx PMBus Command Reference forspecificsonconfiguringthisvoltagetocurrentconversion. When the measured current is outside the range of either the over-current or undercurrent threshold, a FAULT is declared and the UCD9248 performs the PMBus configured fault recovery. ADC current measurements are digitally averaged before they are compared against the FAULT threshold. The output current is measured at a rate of one output rail per 200 microseconds. The current measurements are then passed through a smoothing filter to reduce noise on the signal and prevent false errors. The output of the smoothing filter asymptotically approachestheinputvaluewithatimeconstantthatisapproximately3.5timesthesamplinginterval. 20 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Table4.OutputCurrentFilterTimeConstants OUTPUTCURRENTSAMPLING FILTERTIMECONSTANTS NUMBEROFOUTPUTRAILS INTERVALS(µs) (ms) 1 200 0.7 2 400 1.4 3 600 2.1 4 800 2.8 For example, with a single rail, the filter has the transfer function characteristics that shows the signal magnitude at the output of the averaging filter due to a sine wave input for a range of frequencies. This plot includes an RC analoglowpassnetwork,withacornerfrequencyof3kHz,onthecurrentsenseinputs. This averaged current measurement is used for output current fault detection; see “Over-Current Detection” section. In response to a PMBus request for a current reading, the device returns an average current value. When the UCD9248 is configured to drive a multi-phase power converter, the device adds the average current measurementforeachofthepowerstagestiedtoapowerrail. Current Sense Input Filtering Each power stage current is monitored by the device at the CS pins. There are 4 "A" channel pins and 4 "B" channel pins. The B channel monitors the current with a 12-bit ADC and samples each current sense voltage in turn. The A channels monitor the current with the same12-bit ADC and also monitor the current with a digitally programmable analog comparator. The comparator can be disabled by writing a zero to the FAST_OC_FAULT_LIMIT. Because the current sense signal is both digitally sampled and compared to the programmable over-current threshold, it should be conditioned with an RC network acting as an anti-alias filter. If the comparator is disabled, the CS input should be filtered at 35% of the sampling rate. An RC network with this characteristic can be calculatedas N T R=0.45 rails Iout C (8) Where N is the number of rails configured and T is the sample period for the current sense inputs. rails Iout Therefore,whenthecomparatorisnotused,therecommendedcomponentvaluesfortheRCnetworkareC=10 nFandR=35.7kΩ. When the fast over-current comparator is used, the filter corner frequency based on the ADC sample rate may betooslowandacornerfrequencythatisacompromisebetweentherequirementsoffastover-currentdetection and attenuating aliased content in the sampled current must be sought. In this case, the filter corner frequency canbecalculatedbasedonthetimetocrosstheover-currentthreshold. V =V +DV (1-e-tt ) OC_thres CS_nom Imon (9) Where V is the programmed OC comparator threshold, V is the nominal CS voltage, ΔV is the OC_thres CS_nom Imon change in CS voltage due to an over-current fault and is the filter time constant. Using the equation for the comparatorvoltageabove,theRCnetworkvaluescanbecalculatedas T 1 R = det C ln(DV ) - ln(ΔV - V +V ) Imon Imon OC_thres CS_nom (10) WhereT isthetimetocrosstheover-currentcomparatorthreshold.ForT =10µsec,ΔV =1.5V,V det det Imon OC_thres = 2.0V and V = 1.5V, the corner frequency is 6.4 kHz and the recommended RC network component CS_nom valuesareC=10nFandR=2.49kΩ. Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com Output Current Balancing When the UCD9248 is configured to drive multiple power stage circuits from one compensator, current balancing is implemented by adjusting each gate drive output pulse width to correct for current imbalance between the connected power stage sections. The UCD9248 balances the current by monitoring the current at the CS analog input for each power stage and then adding a current balance adjustment value to the DPWM ramp threshold valueforeachpowerstage. When there is more than one power stage connected to the voltage rail, the device continually determines which stage has the highest measured current and which stage has the lowest measured current. To balance the currents while maintaining a constant total current, the adjustment value for the power stage with the lowest current is increased by the same amount as the adjustment value for the power stage with the highest current is decreased. A slight modification to this algorithm is made to keep the adjustment values positive in order to ensurethatapositiveDPWMdutycycleiscommandedunderallconditions. Over-Current Detection Several mechanisms are provided to sense output current fault conditions. This allows for the design of power systemswithmultiplelayersofprotection. 1. An integrated gate driver, such as the UCD72xx of integrated gate drivers, can be used to generate the FAULT signal. The driver monitors the voltage drop across the high side FET and if it exceeds a resistor/voltage programmed threshold, the driver activates its fault output. The FAULT input can be disabled by reconfiguring the FAULT pin to be a sequencing pin. A logic high signal on the FAULT input causes a hardware interrupt to the internal CPU. The CPU then determines which DPWM outputs are configured to be associated with the voltage rail that contained the fault and disables those DPWM and SRE outputs. This processtakesabout14microseconds. 2. Inputs CS-1A, CS-2A, CS-3A and CS-4A each drive an internal analog comparator. These comparators can be used to detect the voltage output of a current sense circuit. Each comparator has a separate PMBus configurable threshold. This threshold is set by issuing the FAST_OC_FAULT_LIMIT command. Though the command is specified in amperes, the hardware threshold is programmed with a value between 31mV and 2V in 64 steps. The conversion from amperes to volts is accomplished by issuing the IOUT_CAL_GAIN command. When the current sense voltage exceeds the configured threshold the corresponding DPWM and SREoutputsaredrivenlowonthevoltagerailwiththefault. 3. Each Current Sense input to the UCD9248 is also monitored by the 12-bit ADC. Each measured value is scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands. The currents for each power stage configured as part of a voltage rail are summed and compared to the OC limit set by the IOUT_OC_FAULT_LIMIT command. The action taken when a fault is detected is defined by the IOUT_OC_FAULT_RESPONSEcommand. Because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a combination of the time constant (τ) from Table 4, the recent measurement history, and how much the measured value exceeds the over-current limit. When the current steps from a current (I ) that is 1 lessthanthelimittoahighercurrent(I )thatisgreaterthanthelimit,theoutputofthesmoothingfilteris: 2 I (t) =I +(I - I )(1 - e-t/t ) smoothed 1 2 1 (11) AtthepointwhenIsmoothedexceedsthelimit,thesmoothingfilterlagstime,t is: lag æ I - I ö tlag =tlnç 2 1 ÷ èI2 - Ilimit ø (12) The worst case response time to an over-current condition is the sum of the sampling interval (see Table 4) and thesmoothingfilterlag,t fromtheequationabove. lag 22 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Current Foldback Mode When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the UCD9248 attempts to continue to operate by reducing the output voltage in order to maintain the output current at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT. If the output voltage is pulled down to less than that value, the device shuts down, if programmed to do so by the IOUT_OC_LV_FAULT_RESPONSE command. Input Voltage and Current Monitoring The Vin/Iin pin on the UCD9248 monitors the input voltage and current. To measure both input voltage and input current, an external multiplexer is required, see Figure 4. If measurement of only the input voltage, and not input current, is desired, then a multiplexer is not needed. The multiplexer is switched between voltage and current using the TMUX-0 signal. (This signal is the LSB of the temperature mux select signals, so the TMUX-0 signal is connected both to the temperature multiplexer as well as the voltage/current multiplexer). When TMUX-0 is low the V /I pin will be sampled for V . When TMUX-0 is high the V /I pin will be sampled for I . The V /I pin is in in in in in in in in monitoredusingtheinternal12-bitADCandsohasadynamicrangeof0toVADC_RANGE.Thefaultthresholds for the input voltage are set using the VIN_OV_FAULT_LIMIT and VIN_UV_FAULT_LIMIT commands. The scaling for V is set using the VIN_SCALE_MONITOR command, and the scaling for I is set using the in in IIN_SCALE_MONITORcommand. Input UV Lockout The input supply lock-out voltage thresholds are configured with the VIN_ON and VIN_OFF commands. When input supply voltage drops below the value set by VIN_OFF, the device starts a normal soft stop ramp. When the input supply voltage drops below the voltage set by VIN_UV_FAULT_LIMIT, the device performs per the configuration using the VIN_UV_FAULT_RESPONSE command. For example, when the bias supply for the controller is derived from another source, the response code can be set to "Continue" or "Continue with delay," and the controller attempts to finish the soft stop ramp. If the bias voltages for the controller and gate driver are uncertain below some voltage, the user can set the UV fault limit to that voltage and specify the response code to be "shut down immediately" disabling all DPWM and SRE outputs. If VIN_OFF sets the voltage at which the outputvoltagesoft-stoprampisinitiated,andVIN_UV_FAULT_LIMITsetsthevoltagewherepowerconversionis stopped. Temperature Monitoring Both the internal device temperature and up to eight external temperatures are monitored by the UCD9248. The controller supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1, which reads the internal temperature, READ_TEMPERATURE_2, which reads the external power stage temperatures, OT_FAULT_LIMIT, which sets the over temperature fault limit, and OT_FAULT_RESPONSE, whichdefinestheactiontotakewhentheconfiguredlimitisexceeded. If more than one external temperature is to be measured, the UCD9248 provides analog multiplexer select pins (TMUX0-2) to allow up to 8 external temperatures to be measured. The output of the multiplexer is routed to the Temperature pin. The controller cycles through each of the power stage temperature measurement signals. The signal from the external temperature sensor is expected to be a linear voltage proportional to temperature. The PMBus commands TEMPERATURE_CAL_GAIN and TEMPERATURE_CAL_OFFSET are used to scale the measuredtemperature-dependentvoltageto°C. The inputs to the multiplexer are mapped in the order that the outputs are assigned using the PHASE_INFO PMBus command. For example, if only one power stage is wired to each DPWM, the four temperature signals shouldbewiredtothefirstfourmultiplexerinputs. The UCD9248 monitors temperature using the 12-bit monitor ADC, sampling each temperature in turn with an 100 ms sample period. These measurements are smoothed by a digital filter, similar to that used to smooth the output current measurements. The filter has a time constant 15.5 times the sample interval, or 1.55 s (15.5 × 0 ms=1.55seconds).Thisfilteringreducestheprobabilityoffalsefaultdetections. Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com +3.3V Vcc Temp_1A A0 A Temperature Temp_1B A1 Temp_2A A2 Temp_2B A3 CD74HC4051 Temp_3A A7 Temp_3B A5 S2 TMUX-2 Temp_4A A6 S1 TMUX-1 Temp_4B A7 S0 TMUX-0 VeeGnd E Figure12. TemperatureMux(1rail,8phases) Below is an example of a system with two output voltage rails driven by 3 power stages each. The first output voltage rail is driven with DPWM-1A, DPWM-1B and DPWM-3A. The second output voltage rail is driven with DPWM-2A, DPWM-2B and DPWM-4A. The order in which the temperature multiplexer inputs are assigned is showninTable5. 24 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Table5.TemperatureSensorMapping TEMPERATUREMUXINPUT POWERSTAGE A0 DPWM-1A A1 DPWM-1B A2 DPWM-3A A3 DPWM-2A A4 DPWM-2B A5 DPWM-4A A6 n/c A7 n/c Temperature Balancing Temperature balancing between phases is performed by adjusting the current such that cooler phases draw a larger share of the current. Temperature balancing occurs slowly (the loop runs at a 10 Hz rate), and only when the phase currents exceeds the PMBus settable TEMP_BALANCE_IMIN. This minimum current threshold prevents the controller from "winding up" and forcing one phase to carry all the current under a low-load condition,whenthetotalcurrentmaybeinsufficienttosignificantlyaffectphasetemperatures. Soft Start, Soft Stop Ramp Sequence TheUCD9248performssoftstartandsoftstoprampsunderclosedloopcontrol. Performing a start or stop ramp or tracking is considered a separate operational mode. The other operational modes are normal regulation and light load regulation. Each operational mode can be configured to have an independent loop gain and compensation. Each set of loop gain coefficients is called a "bank" and is configured usingtheCLA_GAINSPMBuscommand. Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramp the internal reference toward the commanded reference voltage at the rate specified by the TON_RISE time and VOUT_COMMAND. The DPWM and SRE outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is completedatthesametimeitwouldbeiftherewerenotapre-biascondition. Figure13showstheoperationofsoft-startrampsandsoft-stopramps. Figure13. StartandStopRamps Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on the EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to minimize the error voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is required to match the measured voltage on the rail. Nominally this is calculated as Vout / Vin. If the pre-bias voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage hasincreasedtothepointwheretherequireddutycycleexceedsthespecifiedminimumduty. Once a soft start/stop ramp has begun, the output is controlled by adjusting the Vref DAC at a fixed rate and allowing the digital compensator control engine to generate a duty cycle based on the error. The Vref DAC adjustmentsaremadeatarateof10kHzandarebasedontheTON_RISEorTOFF_FALLPMBusconfiguration parameters. Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when the DPWM and SRE signals become active, the time from when the controller starts processing the turn-on command to the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or minimumdutycycle. During a normal ramp (i.e., no tracking, no current limiting events and no EADC saturation), the set point slews at a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the compensatorfollowsthisrampuptotheregulationpoint. Because the EADC in the controller has a limited range, it may saturate due to a large transient during a start/stop ramp. If this occurs, the controller overrides the calculated set point ramp value, and adjusts the reference DAC in the direction to minimize the error. It continues to step the reference DAC in this direction until the EADC comes out of saturation. Once it is out of saturation, the start ramp continues, but from this new set pointvoltage;andtherefore,hasanimpactontheramptime. Voltage Tracking Each voltage rail can be configured to operate in a tracking mode. When a voltage rail is configured to track another voltage rail, it adjusts the set point to follow the master, which can be either another internal rail or the external Vtrack pin. As in standard non-tracking mode, a target Vout is still specified for the voltage rail. If the tracking input exceeds this target, the tracking voltage rail stops following the master signal, switches to regulation gains, and regulates at the target voltage. When the tracking input drops below the target with 20 mV of hysteresis, tracking gains are re-loaded and the voltage rail follows the tracking reference. Note that the target can be set above the range of the tracking input, forcing the voltage rail to always remain in tracking mode with thestart-stopgains. During tracking, the Vref DAC is permitted to change only as fast as is possible without inducing the EADC to saturate. This limit may be reached if the master ramps at an extremely fast rate, or if the master is at a significantly different voltage when the rail is turned on. A current limit (current foldback) or the detection of the EADCsaturatingwillforcetherailtotemporarilydeviatefromthetrackingreference.Thisbehavioristhesamein normalregulationmode. ThePMBuscommandTRACKING_SOURCEisavailabletoenabletrackingmodeandselectthemastertotrack. The tracking mode is set individually for each rail, allowing each rail to have a different master, multiple rails to share a master, or some rails to track while others remain independent. Additionally, TRACKING_SCALE_MONITOR permits tracking at voltage with a fixed ratio to a master voltage. For example, a ratioof0.5causestherailtoregulateatonehalfofthemaster’svoltage. Sequencing There are three methods to sequence voltage rails controlled by the UCD9248 that allow for a variety of system sequencingconfigurations.EachoftheseoptionsisconfigurableintheGUI.Thesemethodsinclude: 1. Use the PMBus to set the soft start/stop parameters for each rail. Multiple start/stop sequences may be triggered simultaneously. Each voltage rail performs its sequencing in an open-loop manner. If any rail fails tocompleteitssequence,allotherrailsareunaffected. 2. Daisy-chainthePowerGoodoutputsignalfromonecontrollertothePMBus_CTRLinputonanother. 3. Use the GPIO_SEQ_CONFIG command to assign dependencies between rails, or to configure unused pins assequencingcontrolinputsorsequencingstatusoutputs. 26 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 Method 1: Each rail has programmable delay times, TON_DELAY and TOFF_DELAY, before beginning a soft start ramp or a soft stop ramp, and programmable ramp times, TON_RISE and TOFF_FALL determine how long the ramp takes. These PMBus commands are defined in the UCD92xx PMBUS Command Reference. The parameterscanalsobeconfiguredusingtheFusionDigitalPower™DesignerGUI (seehttp://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html). The configurable times can be used to program a time based sequence for each voltage rail. Using this method eachrailrampsindependentlyandcompletestherampregardlessofthesuccessoftheotherrails. The start/stop sequence is initiated for a single rail by the PMBus_CTRL pin or via the PMBus using the OPERATIONorON_OFF_CONTROLcommands. The start/stop sequence may be initiated simultaneously for multiple rails within the same controller by configuringeachrailtorespondtothePMBus_CTRLpin.Alternatively,aftersettingthePMBusPAGEvariableto 255,subsequentOPERATIONorON_OFF_CONTROLcommandsappliestoallrailsatthesametime. To simultaneously initiate start/stop sequences in multiple controllers, a common PMBus_CTRL signal can be fed into each controller. Alternatively, the PMBus Group Command Protocol may be used to send separate commands to multiple controllers. All the commands are sent in one continuous transmission and wait for the finalSTOPsignalinordertostartexecutingtheircommandssimultaneously. Method 2: The PGood pin can be used to coordinate multiple controllers by running the PGood pin output from one controller to the PMBus_CTRL input pin of another. This imposes a master/slave relationship between multiple devices. During startup, the slave controllers initiate their start sequences after the master completes its start sequence and reaches its regulation voltage. During shut-down, as soon as the master starts its shut-down sequence,theshut-downsignalstoitsslaves. Unlike Method 1, a shut-down on one or more rails on the master can initiate shut-downs of the slave devices. Themastershut-downscaninitiateintentionallyorbyafaultcondition. The PMBus specification implies that the Power Good signal is active when ALL the rails in a controller are above their power-good “on” threshold setting. The UCD9248 allows the Power Good pin to be reprogrammed usingtheGPIO_SEQ_CONFIGcommandsothatthepinrespondstoadesiredsubsetofrails. This method works to coordinate multiple controllers, but it does not enforce interdependency between rails withinasinglecontroller. Method 3: Using the GPIO_SEQ_CONFIG command, several sequencing options can be configured using undedicated pins for input/output. As many as four pins can be configured as inputs, and as many as six as outputs.Theoutputscanbeopen-drainoractivelydrivenwithselectablepolarity. Each rail can be configured to respond to a combination of the power-good status of other internal rails and/or the state of sequencing input pins. The output pins can be configured to reflect the power-good status of a combination of rails, or to one of several status indicators including power-good, an over-current warning, or the “open-drainoutputsvalid” signal. When using the output signals for sequencing, they may be routed to sequencing control inputs or to the PMBus_CTRLinputsonothercontrollers. Once each rail’s input dependencies are configured, the rail responds to those input pins or internal rails. Like method 2, shut-downs on one rail or controller can initiate shut-downs of other rails or controllers. Unlike method 2, GPIO_SEQ_CONFIG offers much more flexibility in assigning relationships between multiple rails within a single controller or between multiple controllers. It is possible for each controller to be both a master and a slave toanothercontroller. GPIO_SEQ_CONFIG allows the configuration of fault relationships such that a fault on one rail can result in the shut down of any selection of rails in addition to the rail at fault. These fault interactions are not constrained to a single master/slave relationship; for example, a system can be configured such that a fault on any rail shuts down all rails. If the fault response of the failing rail is to shut down immediately, all dependent rails follow suit and shuts down immediately regardless of their programmed response code. The fault slaves can be configured toshutdownwhenthemasterfirstreportsafaultorafterthemasterhasexhausteditsretries. Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com Each rail can be optionally configured to monitor a sequencing input pin for a specified period of time after it turns on and reaches its power good threshold. If the programmable timeout is reached before the input pin state matches its defined logic level, the rail is shut down, and a status error posted. This feature could be used, for example, to ensure that an LDO on the board did turn on when the main system voltage came up. Each rail is enabled independently of the other rails and has a unique timeout value; a single input pin is used as the timeout source. The setup of the GPIO_SEQ_CONFIG command is aided by the use of the Fusion Digital Power™ Designer, which graphically displays relationships between rails and provides intuitive controls to allocate and configure availableresources. The following pins are available for use as sequencing control, provided they are not being used for their primary purpose: PINNAME 80-PIN DPWM-1A IN/OUT DPWM-1B IN/OUT DPWM-2A IN/OUT DPWM-2B IN/OUT DPWM-3A IN/OUT DPWM-3B IN/OUT DPWM-4A IN/OUT DPWM-4B IN/OUT FAULT-1A IN/OUT FAULT-1B IN/OUT FAULT-2A IN/OUT FAULT-2B IN/OUT FAULT-3A IN/OUT FAULT-3B IN/OUT FAULT-4A IN/OUT FAULT-4B IN/OUT SRE-1A IN/OUT SRE-1B IN/OUT SRE-2A IN/OUT SRE-2B IN/OUT SRE-3A IN/OUT SRE-3B IN/OUT SRE-4A IN/OUT SRE-4B IN/OUT PGOOD IN/OUT SEQ-1 IN/OUT SEQ-2 IN SEQ-3 IN Non-volatile Memory Error Correction Coding The UCD9248 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array. These extra check bits, along with the hardware ECC algorithm, allow for any single bit error to be detected and correctedwhentheDataFlashisread. ADCRef Pin The ADCRef pin is the decoupling pin for the ADC12. Connect this pin to ground through a 0.1µF to 1µF capacitor. 28 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

UCD9248 www.ti.com SLVSA33A–JANUARY2010–REVISEDAUGUST2012 APPLICATION INFORMATION Automatic System Identification ( Auto-ID™) By using digital circuits to create the control function for a switch-mode power supply, additional features can be implemented. One of those features is the measurement of the open loop gain and stability margin of the power supply without the use of external test equipment. This capability is called automatic system identification or Auto-ID™. To identify the frequency response, the UCD9248 internally synthesizes a sine wave signal and injects it into the loop at the set point DAC. This signal excites the system, and the closed-loop response to that excitation can be measured at another point in the loop. The UCD9248 measures the response to the excitation at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is calculated.Theopen-looptransferfunctionmaybecalculatedfromtheclosed-loopresponse. Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be divided out of the measured open-loop gain. In this way the UCD9248 can accurately measure the power stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and send the measurement data back to a host through the PMBus interface without the need for external test equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus CommandReference. Data Logging The UCD9248 maintains a data log in non-volatile memory. This log tracks the peak internal and external temperature sensor measurements, peak current measurements and fault history. The PMBus commands and dataformatfortheDataLoggingcanbefoundintheUCD92xxPMBusCommandReference(SLUU337). Copyright©2010–2012,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29

UCD9248 SLVSA33A–JANUARY2010–REVISEDAUGUST2012 www.ti.com REVISION HISTORY ChangesfromOriginal(January2010)toRevisionA Page • ChangedinthePinDescriptionstableforpins30and31. ................................................................................................ 10 • DeletedPowerPadfromthePinDescriptionstable............................................................................................................ 11 30 SubmitDocumentationFeedback Copyright©2010–2012,TexasInstrumentsIncorporated

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCD9248PFC ACTIVE TQFP PFC 80 96 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD & no Sb/Br) 9248 UCD9248PFCR ACTIVE TQFP PFC 80 1000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 UCD & no Sb/Br) 9248 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 15-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCD9248PFCR TQFP PFC 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 15-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCD9248PFCR TQFP PFC 80 1000 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE PFC0080A TQFP - 1.2 mm max height SCALE 1.250 PPLLAASSTTIICC QQUUAADD FFLLAATTPPAACCKK 12.2 PIN 1 ID 11.8 B 80 61 A 1 60 12.2 14.2 TYP 11.8 13.8 20 41 21 40 76X 0.5 0.27 80X 4X 9.5 0.17 0.08 C A B 1.2 MAX C (0.13) TYP SEATING PLANE SEE DETAIL A 0.08 0.25 GAGE PLANE (1) 0.75 0.05 MIN 0 -7 0.45 DETSDCEATLAEIL: 1A4AIL A TYPICAL 4215165/B 06/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Reference JEDEC registration MS-026. www.ti.com

EXAMPLE BOARD LAYOUT PFC0080A TQFP - 1.2 mm max height PLASTIC QUAD FLATPACK SYMM 80 61 80X (1.5) 1 60 80X (0.3) 76X (0.5) SYMM (13.4) (R0.05) TYP 20 41 21 40 (13.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:6X 0.05 MAX EXPOSED METAL ALL AROUND EXPOSED METAL 0.05 MIN ALL AROUND METAL SOLDER MASK SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4215165/B 06/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 6. For more information, see Texas Instruments literature number SLMA004 (www.ti.com/lit/slma004). www.ti.com

EXAMPLE STENCIL DESIGN PFC0080A TQFP - 1.2 mm max height PLASTIC QUAD FLATPACK SYMM 80 61 80X (1.5) 1 60 80X (0.3) 76X (0.5) SYMM (13.4) (R0.05) TYP 20 41 21 40 (13.4) SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE:6X 4215165/B 06/2017 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

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