UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 8-CHANNEL POWER-SUPPLY SEQUENCER AND MONITOR FEATURES APPLICATIONS 1 • SingleSupplyVoltage:3.3V • TelecommunicationsSwitches 234 • LowPowerConsumption • Servers • SequencesandMonitorsuptoEightVoltage • NetworkingEquipment Rails • TestEquipment • RailVoltagesSampledEvery50m sWith • AnySystemRequiringSequencingofMultiple VoltageRails 3.2-mVResolution • FourConfigurableDigitalOutputsfor DESCRIPTION Power-OnResetandOtherFunctions • ConfigurableRail-EnableOutputPolarity The UCD9080 power-supply sequencer controls the enable sequence of up to eight independent voltage • FlexibleRailSequencing:Timeline(ms), rails and provides four general-purpose digital ParentRailRegulationWindow,ParentRail outputs. The device operates from a 3.3-V supply, AchievingDefinedThreshold provides 3.2-mV resolution of voltage rails, and • Under-andOvervoltageThresholds:Settable requires no external memory or clock. The UCD9080 Per-Rail monitors the voltage rails independently at more than a 20-kHz rate and has a high degree of rail sequence • RegulationExpirationTime:SettablePer-Rail and rail error-response configurability. The • FlexibleRailShutdown:ParentRailShutdown sequencing of rails can be based on time or on time CanShutDownChildRails,IndependentRail in conjunction with other rails achieving regulation or Configuration a voltage threshold. In addition, each rail is monitored • Per-RailAlarmConditions,WithTimestamp: for undervoltage and overvoltage glitches and thresholds. Each rail the UCD9080 monitors can be Under-andOvervoltageGlitch,Sustained configured to shut down a user-defined set of other Under-and/orOvervoltage,RailDidNotStart rails, and alarm conditions are monitored on a per-rail • I2CInterfaceforConfigurationandMonitoring basis. • Microsoft®Windows®GUIforConfiguration Figure 1 shows the UCD9080 power-supply andMonitoring sequencerinatypicalapplication. MON[1:8] 10 kW VOUT1 3.3V RST EN[1:7] Power Supply 0.01mF 3.3V XIN EN 1 TEST VOUT2 Power 100 kW UCD9080 ENSuppl2y 3.3V ROSC VCC 3.3V 10 kW 3.3V SCL 1mF 10 kW 3.3V SDA VSS To I2C AGDEPNDOR8/11/ AGDPDOR22/ AGDPDOR33/ AGDPDOR44/ Power VOUTX Master Device Supply 3.3V EN X A1 SAladvder eI2sCs AAA234 DOiugtiptaults Figure1.TypicalApplicationDiagram 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. TMS320isatrademarkofTexasInstruments. 2 Microsoft,WindowsareregisteredtrademarksofMicrosoftCorporation. 3 Allothertrademarksarethepropertyoftheirrespectiveowners. 4 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document,orseetheTIWebsiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) VALUE UNIT VoltageappliedfromVCCtoVSS –0.3to4.1 V Voltageappliedtoanypin(2) –0.3toV +0.3 V CC Diodecurrentatanydeviceterminal ±2 mA T Storagetemperature –40to85 (cid:176) C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoVSS. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supplyvoltageduringoperation 3 3.3 3.6 V V CC Supplyvoltageduringconfigurationchanges 3 3.3 3.6 T Operatingfree-airtemperaturerange –40 85 (cid:176) C A ELECTRICAL CHARACTERISTICS Thesespecificationsareoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature,unlessotherwise noted PARAMETER TESTCONDITIONS MIN NOM MAX UNIT SUPPLYCURRENT IS ScuurprepnlytcurrentintoVCC,excludingexternal TA=25(cid:176)C 3 4 mA IC Supplycurrentduringconfiguration 3.6V 3 7 mA STANDARDINPUTS(RST,TEST) VIL Low-levelinputvoltage VCC=3V VSS VSS+0.6 V VIH High-levelinputvoltage VCC=3V 0.8VCC VCC V SCHMITTTRIGGERINPUTS(SDA,SCL,EN1,EN2,EN3,EN4,EN5,EN6,EN7,EN8/ADDR1,ADDR2,ADDR3,ADDR4) VIT+ Positive-goinginputthresholdvoltage VCC=3V 1.5 1.9 V VIT– Negative-goinginputthresholdvoltage VCC=3V 0.9 1.3 V Vhys Input-voltagehysteresis,(VIT+–VIT–) VCC=3V 0.5 1 V Ilkg High-impedanceleakagecurrent ±50 nA 2 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 ELECTRICAL CHARACTERISTICS (continued) Thesespecificationsareoverrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature,unlessotherwise noted PARAMETER TESTCONDITIONS MIN NOM MAX UNIT ANALOGINPUTS(MON1,MON2,MON3,MON4,MON5,MON6,MON7,MON8,ROSC) VCC Analogsupplyvoltage VSS=0V 3 3.6 V Internalvoltagereference 0 2.5 V(R<1..8>) Analoginputvoltage Externalvoltagereference V (VCC=3.3Vusedasreference) 0 VCC CI(1) Inputcapacitance O(MnOlyNo1n–eMtOerNm8in)alcanbeselectedatatime 27 pF RI(1) InputMUXONresistance 0V≤V(MONx)≤VCC,VCC=3V 2000 Ω Ilkg High-impedanceleakagecurrent MON1–MON8 ±50 nA VREF+ Positiveinternalreferencevoltageoutput REF2_5V=1for2.5VI(VREF+)≤ 2.35 2.5 2.65 V I(VREF+)max,VCC=3V VCCminimumvoltage,positivebuilt-in REF2_5V=1,I(VREF+)≤0.5mA 3 V VCC(min) referenceactive REF2_5V=1,I(VREF+)≤1mA 3 V Internalreference(2.5V) ±6.8 ±12 ±17.4 V(acc) Accuracyofvoltagesamplingfromrails mV Externalreference(3.3V/VCC) ±0.2 ±1.6 ±6.8 TREF+(1) Treefmerpeenrcaeturecoefficientofbuilt-in I0(VmREAF+≤)iIs(VaREcFo+n)≤sta1nmtiAn,tVheCCran=g3eVof ±100 ppm/(cid:176)C MISCELLANEOUS tretention Retentionofconfigurationparameters TJ=25(cid:176)C 100 Years POR,Brownout,Reset(2)(3) td(BOR) 2000 m s VCC(start) 0.7· V(B_IT–) V V(B_IT–) Brownout VCC/dt≤3V/s 1.71 V Vhys(B_IT–) 70 130 180 mV t(reset) Preuslesetinletnegrnthallnye,eVdCeCd=a3tRVSTpintoaccept 2 m s DIGITALOUTPUTS(EN8/GPO1,GPO2,GPO3,GPO4,EN1,EN2,EN3,EN4,EN5,EN6,EN7,SDA,SCL) IOH(max)=–1.5mA,(4)VCC=3V VCC–0.25 VCC VOH High-leveloutputvoltage IOH(max)=–6mA,(5)VCC=3V VCC–0.6 VCC V IOH(max)=–1.5mA,(4)VCC=3V VSS VSS+0.25 VOL Low-leveloutputvoltage IOH(max)=–6mA,(5)VCC=3V VSS VSS+0.6 V Ilkg High-impedanceleakagecurrent VCC=3V ±50 nA (1) Notproductiontested.Limitsverifiedbydesign. (2) ThecurrentconsumptionofthebrownoutmoduleisalreadyincludedintheI current-consumptiondata. CC (3) Duringpowerup,deviceinitializationstartssubsequenttoaperiodoft afterV =V +V . d(BOR) CC (B_IT–) hys(B_IT–) (4) Themaximumtotalcurrent,I maxandI max,foralloutputscombined,shouldnotexceed±12mAtoholdthemaximumvoltagedrop OH OL specified. (5) Themaximumtotalcurrent,I maxandI max,foralloutputscombined,shouldnotexceed±48mAtoholdthemaximumvoltagedrop OH OL specified. The UCD9080 is compatible with 3.3-V IO ports of microcontrollers, TMS320™ DSP family as well as ASICs. TheUCD9080isavailableinaplastic32-pinQFNpackage(RHB). Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com DIGITAL OUTPUTS (Only One Output Loaded at a Time) TYPICALLOW-LEVELOUTPUTCURRENT TYPICALHIGH-LEVELOUTPUTCURRENT vs vs LOW-LEVELOUTPUTVOLTAGE HIGH-LEVELOUTPUTVOLTAGE 50 0 A m VCC= 3 V mA VCC= 3 V rent− 40 P1.0 TA= 25oC ent− −10 P1.0 ur T = 85oC rr C A u put ut C −20 Out 30 utp vel el O −30 e v L e cal Low- 20 al High-L −40 TA= 85oC pi c Ty 10 ypi − T −50 OL −H TA= 25oC I O I 0 −60 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 2.5 3 3.5 VOL−Low-Level Output Voltage−V VOH−High-Level Output Voltage −V Figure2. Figure3. V CC V hys(B_IT–) V (B_IT–) V CC(start) 1 Set signal for POR circuitry 0 t d(BOR) Figure4.POR/BrownoutReset(BOR)vsSupplyVoltage 4 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 V CC t pw 2 V = 3 V 3 V CC Typical Conditions 1.5 V - n) mi 1 C( V C CC(min) V 0.5 0 0.001 1 1000 1 ns 1 ns t -Pulse Width-mS pw t -Pulse Width-mS pw Figure5.V LevelWithaSquareVoltageDroptoGenerateaPOR/BrownoutSignal CC(min) V CC t pw 2 3 V V = 3 V CC Typical Conditions V 1.5 - n) mi 1 C( C VCC(min) V 0.5 t =t fall rise 0 0.001 1 1000 tfall trise t -Pulse Width-mS pw t -Pulse Width-ms pw Figure6.V LevelWithaTriangleVoltageDroptoGenerateaPOR/BrownoutSignal CC(min) I2C TIMING The UCD9080 supports the same timing parameters as standard-mode I2C. See the following timing diagram andtimingparametersformoreinformation. SDA tf tLOW tr tSU;DAT tHD;STA tr tBUF t of SCL tHD;STA tHIGH tHD;DAT tSU;STA tSU;STO S Sr P S Figure7.TimingDiagramforI2CInterface Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com TIMING PARAMETERS FOR I2C INTERFACE PARAMETER MIN MAX UNIT t OutputfalltimefromV toV (1)withabuscapacitancefrom10pFto400pF 250(2) ns of OH OL C Capacitanceforeachpin. 10 pF I f SCLclockfrequency 10 100 kHz SCL t Holdtime(repeated)STARTcondition.Afterthisperiod,thefirstclockpulseisgenerated. 4 m s HD;STA t Dataholdtime 0(3) 3.45(4) m s HD;DAT t LOWperiodoftheSCLclock 4.7 m s LOW t HIGHperiodoftheSCLclock 4 m s HIGH t Set-uptimeforrepeatedstartcondition 4.7 m s SU;STA t Datasetuptime 250 ns SU;DAT t RisetimeofbothSDAandSCLsignals 1000 ns r t FalltimeofbothSDAandSCLsignals 300 ns f t SetuptimeforSTOPcondition 4 m s SU;STO t BusfreetimebetweenaSTOPandSTARTcondition 4.7 m s BUF C Capacitiveloadforeachbusline 400 pF (b) V NoisemarginattheLOWlevelforeachconnecteddevice(includinghysteresis) 0.1VDD V nL V NoisemarginattheHIGHlevelforeachconnecteddevice(includinghysteresis) 0.2VDD V nH (1) SeetheElectricalCharacteristicssectionofthisdatasheet. (2) Themaximumt fortheSDAandSCLbuslines(300ns)islongerthanthespecifiedmaximumt fortheoutputstages(250ns).This f of allowsseriesprotectionresistors(R)tobeconnectedbetweentheSDA/SCLpinsandtheSDA/SCLbuslineswithoutexceedingthe s maximumspecifiedt. f (3) Adevicemustinternallyprovideaholdtimeofatleast300nsfortheSDAsignaltobridgetheundefinedregionofthefallingedgeof SCL. (4) Themaximumt mustonlybemetifthedevicedoesnotstretchtheLOWperiod(t )oftheSCLsignal. HD;DAT LOW RHBPACKAGE (TOPVIEW) 1 O P 4 3 2 G O O O 1/ P P P R G G G D 4/ 3/ 2/ D SC C ST DR DR DR 8/A O C C E D D D N R N V T A A A E VSS 132 31 30 29 28 27 26 2524 EN2 NC 2 23 EN1 XIN 3 22 SCL NC 4 21 SDA RST 5 20 NC MON1 6 19 MON5 MON2 7 18 MON4 MON3 8 9 10 11 12 13 14 15 1617 NC 6 4 3 5 6 7 7 8 N N N N N N N N O E E E E E O O M M M 6 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 Table1. TERMINALFUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. ADDR2/GPO2 26 I/O I2Caddressselect2,general-purposedigitaloutput2 ADDR3/GPO3 27 I/O I2Caddressselect3,general-purposedigitaloutput3 ADDR4/GPO4 28 I/O I2Caddressselect4,general-purposedigitaloutput4 EN1 23 I/O Voltagerail1enable(digitaloutput) EN2 24 I/O Voltagerail2enable(digitaloutput) EN3 11 I/O Voltagerail3enable(digitaloutput) EN4 10 I/O Voltagerail4enable(digitaloutput) EN5 12 I/O Voltagerail5enable(digitaloutput) EN6 13 I/O Voltagerail6enable(digitaloutput) EN7 14 I/O Voltagerail7enable(digitaloutput) EN8/ADDR1/ 25 I/O Voltagerail8enable(digitaloutput),I2Caddressselect1,general-purposedigitaloutput1 GPO1 MON1 6 I Analoginputforvoltagerail1 MON2 7 I Analoginputforvoltagerail2 MON3 8 I Analoginputforvoltagerail3 MON4 18 I Analoginputforvoltagerail4 MON5 19 I Analoginputforvoltagerail5 MON6 9 I Analoginputforvoltagerail6 MON7 15 I Analoginputforvoltagerail7 MON8 16 I Analoginputforvoltagerail8 NC 2 Donotconnect. 4,17, NC Notconnectedinternally.ConnecttoVSS. 20,31 Internaloscillatorfrequencyadjust.Mustuse100-kΩpulluptoVCCforminimumdriftandmaximum ROSC 32 frequencywhensamplingvoltagerails. RST 5 I Resetinput SCL 22 I/O I2Cclock.Apulluprwesistorto3.3Visrequired. SDA 21 I/O I2Cdata(bidirectional).Apullupresistorto3.3Visrequired. TEST 29 I ConnecttoVSS VCC 30 Supplyvoltage VSS 1 Groundreference XIN 3 ConnecttoVCC Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com FUNCTIONALBLOCKDIAGRAM MON1 EN1 Oscillator MON2 EN2 MON3 EN3 MON4 Analog Power EN4 MON5 Inputs Enables EN5 Sequencing MON6 EN6 Engine MON7 EN7 MON8 EN8/GPO1 General- GPO2 Purpose GPO3 10-bit Outputs GPO4 SARADC Config Memory Status Registers 2 I C Engine SCL SDA 8 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 FUNCTIONAL DESCRIPTION POWER-SUPPLY SEQUENCING The UCD9080 can be configured to sequence the power rails using the enable signals or the general-purpose outputsinoneofthreeways. The first way is to specify a delay time after a UCD9080 RESET. The enable/GPO is asserted after the UCD9080RESETplusaspecifieddelay. The second way is to specify a delay time after another (parent) rail has achieved regulation (that is, V is RAIL within the specified under- and overvoltage settings). The enable/GPO is asserted after the (parent) rail is in regulationplusspecifieddelay. The third way is to specify a (parent) rail voltage. The enable/GPO is asserted after the (parent) rail voltage is greaterthanorequaltothespecifiedvoltage. Of course, a rail does not have to be sequenced, as in the case of a backplane voltage that is not under the controloftheUCD9080,butisbeingmonitored. POWER-SUPPLY ENABLES The UCD9080 can sequence up to eight power supplies using the ENx (EN1 to EN8) signals. These signals can beconfiguredasactive-highoractive-low,supportingpowersupplieswitheitherpolarity. EN8 can also be configured as a GPO (GPO1). EN8/ADDR1/GPO1 is also used for I2C address selection (ADDR1). GENERAL-PURPOSE OUTPUTS The UCD9080 can control up to four general-purpose digital outputs using the same sequencing mechanisms as described in the Power-Supply Enables section. These general-purpose outputs (referred to as GPO1–GPO4) can be used for digital signals such as RESET or status. Note that these signals are multiplexed with other functions (primarily I2C address selection). See the Terminal Functions table to ensure that these signals are usedproperlybytheapplication.AlsonotethattheGPO1signalismultiplexedwithEN8,sobothofthese cannot beusedatthesametime. EXTERNAL CONSIDERATIONS FOR EN AND GPO PINS During the UCD9080 RESET interval, all ENx and GPOx pins become Schmitt-trigger Inputs. A UCD9080 RESEToccursunderthefollowingconditions: • ExternalRSTpinisdrivenlow. • Powerisappliedtothedevice(power-onreset)orpoweriscycled. • Asequenceeventoccursasaresultofaconfiguredrail-alarmevent. • TheRESTARTregisteriswrittenwithavalueof0overtheI2Cbus. All ENx and GPOx pins must be externally terminated to one of the following Schmitt-trigger input-logic states for propersequenceroperation. • EN or GPO pin configured for ACTIVE-LOW polarity: the external resistor network must default the corresponding EN or GPO pin to a voltage greater than or equal to 1.9 V (V , MAX, positive-going input IT+ thresholdvoltage)duringdevicereset. • EN or GPO pin configured for ACTIVE-HIGH polarity: the external resistor network must default the corresponding EN or GPO pin to a voltage less than or equal to 0.9 V (V , MIN, negative-going input IT– thresholdvoltage)duringdevicereset. NOTE: The external resistor networks should not derive their voltage from a sequenced power supply, as this may cause the voltage level presented to the ENx or GPOx pin to be at the wrong level during device reset. It is best to use the UCD9080 VCC supplyfortheexternalresistornetworks. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com The user must consider GPO polarity usage when programming the UCD9080 I2C address using the external GPOx (ADDRx) resistor networks. Acceptable ADDRx bit voltage levels are set according to Schmitt-trigger input specifications.ThefollowingGPOx/ADDRxcombinationsareacceptable: • GPOx=Active-lowpolarity:CorrespondingADDRxbitsettoSchmitt-triggerinputlogiclevel=1 • GPOx=Active-highpolarity:CorrespondingADDRxbitsettoSchmitt-triggerinputlogiclevel=0 VOLTAGE REFERENCE The UCD9080 has a voltage reference that is selectable via the I2C interface and parameter configuration section. The voltage reference can either be an internally generated 2.5-V reference or an external 3.3-V reference. If the external voltage reference is selected, then the 3.3-V reference is from the V supply to the CC UCD9080. Depending on the voltage reference that is being used, the accuracy of reading voltages is affected. The internal reference is not as accurate as the external reference and affects the accuracy of the sampled voltages of the monitored rails. See the Electrical Characteristics for information on voltage reading accuracy for use with each ofthereferences. TheConfiguringtheUCD9080sectiondetailshowtoselecttheinternalorexternalvoltagereference. VOLTAGE MONITORING The UCD9080 can monitor eight voltage rails through the MONx terminals of the device (MON1–MON8). The UCD9080 samples these eight input channels using either the internal 2.5-V reference or V (3.3 V) as a CC voltage reference to convert the voltage to digital values. The eight digitally monitored voltage values are accessibleviatheI2Cinterface. Whenmonitoring a voltage rail that has a nominal voltage larger than 2.5 V (internal reference) or 3.3 V (external reference),aresistordividernetworkistypically used. The design must ensure that the source impedance of that resistor network is not too high, because it causes the UCD9080 analog-to-digital converter (ADC) to take longer to perform the sample-and-hold conversion. The extended conversion time causes the frequency of the sampling ofvoltagerailstoslowbelow20kHz. Using a higher-valued resistor network lowers the overall power dissipation of the solution, which is desirable. In order to keep the source impedance low, a buffer circuit is typically used. The UCD9080 analog inputs require thatasourceimpedanceoflessthan20kΩbeusedinordertomaintainthehighsamplingrateofthevoltages. The UCD9080 allows specification of overvoltage threshold, undervoltage threshold, and out-of-regulation or glitchdurationforeachmonitoredrail. Each voltage rail can also be marked so that it is not monitored, in which case all checks and alarm conditions aredisabled. RAIL SHUTDOWN Rail shutdown is the act of setting the ENx pin associated with that rail to a state which disables the power supply output. Each UCD9080 rail can be configured to shut down based on a monitored alarm event (sustained overvoltage,sustainedundervoltage,orraildidnotstart)andinaconfigurablemanner. Theoptionsforrailshutdownareasfollows: • Ignore • Logonly • Sequence • Retry1time • Retry0times If the system does not care whether a monitored rail enters a sustained error condition, the UCD9080 can be configuredtoeitherignoreorlogtheerroreventandtakenosubsequentaction. 10 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 The UCD9080 can also be configured to sequence the entire system in response to a sustained error condition. When the UCD9080 monitors an alarm event on the configured rail, UCD9080 RESET occurs (all ENx and GPOx outputs go to the high-impedance state for ~4–5 ms). Next, a sequence of all configured enables and GPOs occurs, as defined by the current sequencer configuration. Note that for this configuration, a shutdown accordingtothevaluesintheUnsequenceTimeregisterdoesnotoccurpriortoUCD9080RESET. The UCD9080 can also be configured to attempt to restart a rail once in response to a sustained error condition. When the UCD9080 monitors an alarm event on a configured rail, the rail is momentarily disabled and then re-enabled. The rail remains enabled according to the RampTime register setting (time), and if the rail does not properly achieve regulation, the system (rail and dependent rails) is shut down as defined by the current sequencerconfiguration(UnsequenceTimeregister). The last option that the UCD9080 supports is to shut down (if specified as a dependency) and disable (Retry 0 times) a configured rail in response to a sustained error condition. When the UCD9080 monitors an alarm event on the configured rail, the system (dependent rails and GPOs) is shut down as defined by the current sequencer configuration (UnsequenceTime register). Only rails and GPOs marked as dependencies of the configured rail are shut down. If there are no rails or GPO dependencies marked, the configured rail is just disabled in response tothesustainederrorcondition. Each UCD9080 ENx and GPOx output can be marked to sequence after shutdown (as defined by the current sequencer configuration) if specified as a dependency in the DependencyMasks register. For example, if rail 1 is configured to sequence after shutdown (RESEQ bit set), and rail 2 has rail 1 set in its dependency mask, then if/whenrail2isshutdown,rail1shutsdownandthesystemresequences. BROWNOUT The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and poweroff. I2C INTERFACE The UCD9080 power-supply sequencer has a 100-kHz, slave-mode I2C interface for communication with an I2C master.TheI2CmasterusesthisinterfacetoconfigureandmonitortheUCD9080. I2CAddressSelection The UCD9080 supports 7-bit I2C addressing. The UCD9080 selects an I2C address by sampling the logic level of the four digital inputs to the device (ADDR1–ADDR4) during the UCD9080 RESET interval. When the UCD9080 is released from RESET, the ADDRx logic levels are latched and the I2C address is assigned as shown in Figure8. A A A7=1 A6=1 A5=0 A4=ADDR4/GPO4 A3=ADDR3/GPO3 A2=ADDR2/GPO2 A1=EN8/ADDR1/GPO1 Figure8.I2CADDRESS=0x60–0x6F Externalpullup/pulldownresistorsarerequiredto configure the I2C address; the UCD9080 does not have internal bias resistors. Note that the 7-bit I2C address refers to the address bits only, not the read/write (8th) bit in the first byteoftheI2Cprotocol.ThebaseI2Caddressis0x60andtheI2Cgeneral-calladdress(0x00)isnotsupported. After the initialization process of the UCD9080 is complete, these four pins can be used as general-purpose outputs (GPOs). They can be programmed and sequenced as described in the Configuring the UDC9080 section. GPO polarity must consider the external I2C address resistors as described in the External ConsiderationsforENandGPOPinssection. I2CTransactions The UCD9080 can be configured and monitored via I2C memory-mapped registers. Registers that are configurable (can be written) via an I2C write operation are implemented using an I2C unidirectional data transfer, fromthemastertoslave,withastopbitbetweentransactions. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com I2CUnidirectionalTransfer 1 7 1 1 8 1 8 1 1 SLAVE REGISTER S R/W A A DATA A/A P ADDRESS ADDRESS 0 (write) From master to slave A= acknowledge (SDAlow) A= Not acknowledge (SDAhigh) S = STARTcondition From slave to master P= STOPcondition Figure9.I2CRegisterAccessWithSTART/STOP Registers that can be read are implemented using an I2C read operation, which uses the I2C combined format that changes data direction during the transaction. This transaction uses an I2C repeated START during the directionchange. I2CCombinedFormat 1 7 1 1 8 1 1 7 1 1 8 1 1 SLAVE REGISTER SLAVE S R/W A A Sr R/W A DATA A/A P ADDRESS A ADDRESS A ADDRESS A DATA (n bytes + acknowledge) 0 (write) 1 (read) A= acknowledge (SDAlow) From master to slave A= Not acknowledge (SDAhigh) S = STARTcondition From slave to master P= STOPcondition Sr = Repeated START Figure10.I2CRegisterAccessWithRepeatedSTART The UCD9080 also supports a feature that auto-increments the register address pointer for increased efficiency whenaccessingsequentialblocksofdata.ItisnotnecessarytoissueseparateI2Ctransactions. CONFIGURING AND MONITORING THE UCD9080 The UCD9080 supports both configuration and monitoring using its I2C slave interface. A Microsoft Windows GUI is available for configuring and monitoring the UCD9080. See the UCD9080 Power Supply Sequencer and MonitorEVMuser'sguide(SLVU184). 12 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 For monitoring the sequencer, an I2C memory map allows an I2C host to perform memory-mapped reads (and in some cases writes) to obtain status information from the UCD9080. For instance, all rails can report their voltage through the I2C memory map. For information on which parameters are available via the I2C memory map, see theMonitoringtheUCD9080section. To change configuration parameters of the sequencer, a different mechanism is used. The entire set of configurationparametersmustbewrittentothedeviceatone time as one large transaction over the I2C interface to ensure that the configuration of the device is consistent at any given time. The process for configuring the UCD9080isdescribedintheConfiguringtheUDC9080section. MONITORING THE UCD9080 RegisterMap The UCD9080 allows all monitoring of the system through the I2C interface on the device. The following is the memory map of the supported registers in the system. The detail of each of these registers is given in the next sectionaswell. Note that the UCD9080 supports functionality to increment the I2C register address value automatically when a register is being accessed, to access blocks of like registers more efficiently. The following table also shows the amountthattheregisteraddressisincrementedforeachregisteraccess. REGISTERNAME ADDRESS ACCESS ADJUSTMENTAFTERACCESS RAIL1H 0x00 r +1(0x01) RAIL1L 0x01 r +1(0x02) RAIL2H 0x02 r +1(0x03) RAIL2L 0x03 r +1(0x04) RAIL3H 0x04 r +1(0x05) RAIL3L 0x05 r +1(0x06) RAIL4H 0x06 r +1(0x07) RAIL4L 0x07 r +1(0x08) RAIL5H 0x08 r +1(0x09) RAIL5L 0x09 r +1(0x0A) RAIL6H 0x0A r +1(0x0B) RAIL6L 0x0B r +1(0x0C) RAIL7H 0x0C r +1(0x0D) RAIL7L 0x0D r +1(0x0E) RAIL8H 0x0E r +1(0x0F) RAIL8L 0x0F r –15(0x00) ERROR1 0x20 r +1(0x21) ERROR2 0x21 r +1(0x22) ERROR3 0x22 r +1(0x23) ERROR4 0x23 r +1(0x24) ERROR5 0x24 r +1(0x25) ERROR6 0x25 r –5(0x20) STATUS 0x26 r 0(0x26) VERSION 0x27 r 0(0x27) RAILSTATUS1 0x28 r +1(0x29) RAILSTATUS2 0x29 r –1(0x28) FLASHLOCK 0x2E rw 0(0x2E) RESTART 0x2F w 0(0x2F) WADDR1 0x30 rw +1(0x31) WADDR2 0x31 rw –1(0x30) Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com REGISTERNAME ADDRESS ACCESS ADJUSTMENTAFTERACCESS WDATA1 0x32 rw +1(0x33) WDATA2 0x33 rw –1(0x32) RegisterDescriptions ThefollowingarethedetaileddescriptionsofeachoftheUCD9080I2Cregisters. The following register bit conventions are used. Each register is shown with a key indicating the accessibility of eachbit,andtheinitialconditionafterdeviceinitialization. KEY ACCESS rw Read/write r Read-only r0 Readas0 r1 Readas1 w Write-only w0 Writeas0 w1 Writeas1 rc Readclearsbitafterread rs Readsetsbitafterread -0,-1 Conditionafterinitialization RAIL For each of eight voltage rails, the UCD9080 has two registers that contain the rolling average voltage for the associated rail as measured by the device. This average voltage is maintained in real-time by the UCD9080 and is calculated as the output of a 4-TAP FIR filter. There are two registers for each voltage rail. One holds the least-significant 8 bits of the voltage and the other the most-significant 2 bits of the voltage. This is shown in the followingtable. RegisterName Address RegisterContents RAIL1H 0x00 RAIL1voltage,bits9:8 RAIL1L 0x01 RAIL1voltage,bits7:0 RAIL2H 0x02 RAIL2voltage,bits9:8 RAIL2L 0x03 RAIL2voltage,bits7:0 RAIL3H 0x04 RAIL3voltage,bits9:8 RAIL3L 0x05 RAIL3voltage,bits7:0 RAIL4H 0x06 RAIL4voltage,bits9:8 RAIL4L 0x07 RAIL4voltage,bits7:0 RAIL5H 0x08 RAIL5voltage,bits9:8 RAIL5L 0x09 RAIL5voltage,bits7:0 RAIL6H 0x0A RAIL6voltage,bits9:8 RAIL6L 0x0B RAIL6voltage,bits7:0 RAIL7H 0x0C RAIL7voltage,bits9:8 RAIL7L 0x0D RAIL7voltage,bits7:0 RAIL8H 0x0E RAIL8voltage,bits9:8 RAIL8L 0x0F RAIL8voltage,bits7:0 14 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 A rail voltage is read with a 16-bit access. The auto-increment feature of the UCD9080 allows multiple rail voltagestobereadwithasingleaccess. Arailvoltageisprovidedasa10-bitvalueinanunsignedformat: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAILVn r0 r0 r0 r0 r0 r0 r r r r r r r r r r Thefollowingformulascanbeusedtocalculatetheactualmeasuredrailvoltage: Withoutexternalvoltagedivider: V (cid:2)RAILVn(cid:1)V RAILn 1024 REF (1) Withexternalvoltagedivider: R (cid:2)R V (cid:3)RAILVn(cid:1)V (cid:1) PULLDOWN PULLUP RAILn 1024 REF R PULLDOWN (2) Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com ERROR Error conditions are logged by the UCD9080 and are accessible to the user via reading the ERROR register. Thisisa6-byteregisterwiththefollowingformat: 0x20 0x21 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Error Code RAIL Data (dependent on error code) RAIL Meaning Rail #(n)–1, RAIL= 0 through 7 Error Codes Meaning Data 0 0 0 Null alarm 0x0000 0 0 1 Supply did not start Average voltage on rail 0 1 0 Sustained overvoltage detected Average voltage on rail 0 1 1 Sustained undervoltage detected Average voltage on rail 1 0 0 Overvoltage glitch detected Glitch voltage level on rail 1 0 1 Undervoltage glitch detected Glitch voltage level on rail 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved NOTE:When error code =NullAlarm, then the Hours, Minutes, Seconds, and Milliseconds fields are zero. 0x23 0x22 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Hour Minutes 0x25 0x24 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Seconds Milliseconds Error conditions encountered during processing post error logs to this register with some exceptions. This register is internally managed as a FIFO (with a depth of 8). Errors are posted to the FIFO as they occur, and read out of the FIFO via I2C access. Due to the unknown latency of host extraction of the FIFO data, the UCD9080 only posts to the FIFO if there is room to write. There is no real-time impact to processing in the UCD9080ifthisFIFOisfullandcannotbepostedto. Thevaluesinregisters0x22through0x25areresettoavalueof0duringUCD9080RESET. 16 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 STATUS STATUS is an 8-bit read-only register. This register provides real-time status information about the state of the UCD9080.Thefollowingbitsaredefined. 7 6 5 4 3 2 1 0 IICERROR RAIL NVERRLOG Register Status rc-0 rc-0 r r-0 r-0 r-0 rc-0 Register IICERRORMeaning Status Meaning 2 0 No I C PHYlayer error 00 No error 1 I2C PHYlayer error 01 Invalid address 10 Read access error RAIL Meaning 11 Write access error 0 No RAILerror pending 1 RAILerror pending NVERRLOG:Reserved Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the deviceisreset.Descriptionsofthedifferenterrorsfollow. The IICERROR bit is set when an I2C access fails. This is most often a case where the user has accessed an invalid address or performed an illegal number of operations for a given register (for example, reading 3 bytes from a 2-byte register). In the event of an I2C error when IICERROR is set, bits 1:0 of the STATUS register furtherdefinethenatureoftheerrorasshownintheprecedingfigure. The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is advised to query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The user may thenquerytheERRORregisterstogetfurtherinformationaboutthenatureoftheerrorcondition. TheNVERRLOGbitisreservedforfutureuse. When the IICERROR bit is set, the register status bits provide further information about the type of I2C error that hasbeendetected,asindicatedpreviously. RAILSTATUS The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit mask to represent the error status of the rails as indicated in the following diagram. The RAILSTATUS1 register is reserved. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 RAILn Meaning 0 No alarm pending for RAILn 1 Alarm pending for RAILn Bits15:8areRAILSTATUS1andbits7:0are RAILSTATUS2. These are read as two 8-bit registers or as a single 16-bitregister. If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the RAILSTATUS1andRAILSTATUS2registersareclearedwhenread. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com FLASHLOCK The FLASHLOCK register is used to lock and unlock the configuration memory on the UCD9080 when updating theconfiguration.TheConfiguringtheUDC9080sectiondetailsthisprocess. TheformatfortheFLASHLOCKregisterisasfollows: 7 6 5 4 3 2 1 0 FLASHLOCK rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 FLASHLOCK 0x00 Lock flash (default) 0x01 Flash is being updated 0x02 Unlock flash (before configuration) RESTART The RESTART register provides the capability for the I2C host to force a re-initialization and restart of the UCD9080.Thisisan8-bitregister,andwhena value of 0 is written to the register, the UCD9080 is restarted and therailsareresequenced. Note that in order to respond to this I2C request properly, there is a 50-m s delay before the system is restarted, sothattheI2CACKcantakeplace. WADDRandWDATA In order to update the configuration on the UCD9080, four registers are provided: WADDR2 (address bits 8–15), WADDR1 (address bits 0–7), WDATA2 (data bits 8–15), and WDATA1 (data bits 0–7). WADDR2 and WADDR1 specify the 16-bit memory address and WDATA2 and WDATA1 specify the 16-bit data written to or read from thatmemoryaddress. TheformatfortheWADDRregisterisasfollows: 15 8 7 0 Address rw-0x00 rw-0x00 WADDR2 WADDR1 (0x31) (0x30) To set the address of the memory that will be accessed, write the LSB of the address to the WADDR1 register and the MSB of the address to the WADDR2 register. For example, to write the address 0x1234 to the device, set WADDR1 = 0x34 and WADDR2 = 0x12. Note that because these addresses support the auto-increment feature,theusercanperformasingle16-bitwritetoWADDR1towritetheentireaddress. 18 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 TheformatfortheWDATAregisterisasfollows: 15 8 7 0 Data rw rw WDATA2 WDATA1 (0x33) (0x32) Tosetthevalueofthedatathatwillbewritten,writetheLSBofthedatatotheWDATA1registerandtheMSB of thedatatotheWDATA2register.Forexample,towritethedata0xBEEFto the device, set WDATA1 = 0xEF and WDATA2 = 0xBE. Note that because these addresses support the auto-increment feature, the user can perform a single 16-bit write to WDATA1 to write the entire data. To read the value of the data at the specified address, readtheLSBfromWDATA1andtheMSBfromWDATA2. These registers are used for updating the UCD9080 configuration as explained in the Configuring the UDC9080 section. CONFIGURING THE UCD9080 The UCD9080 has many different configurable parameters, such as sequencing policies, shutdown policies and dependency masks. The UCD9080 can configure all of its parameters via the I2C interface while the device is operational.Sequencing,shutdown,andrailmonitoringarenotperformedduringdeviceconfigurationtime. NOTE: During runtime, if the UCD9080 is configured, there is a delay in voltage monitoring whilethenewconfigurationparametersareappliedtothedevice. To configure the UCD9080, a large block of configuration information is sent to the device via the I2C interface. This block is 512 bytes and contains all the configuration information that the device requires for any function of theUCD9080. This 512-byte block of configuration information is sent to the device in multiple segments. The segment size can range from 2 to 32 bytes at one time, and must be a power of 2 bytes. That is, a master can send 256 2-byte segments or 32 16-byte segments, and so on. All the segments must be sent back-to-back in the proper sequence, and this operation must be completed by sending the last segment so that the last byte of the 512-byte block is written. If this is not done, the UCD9080 is in an unknown state and does not function as designed. TheprocessforsendingtheconfigurationinformationtotheUCD9080isasshowninFigure11: . . . I2CWrite: I2CWrite: I2CWrite: I2CWrite: I2CWrite: I2CWrite: I2CWrite: FLASHSTATE= WADDR= WDATA= WADDR= WDATA= WDATA= FLASHSTATE= UNLOCK(0x02) 0xE000 0xBADC 0xE000 Data(16b) Data(16b) LOCK(0x00) 16 times(32 bytes) -OR - Repeat asnecessarywith WADDR updated to write 512 bytes Figure11.ConfigurationInformation AsshowninFigure11,theprocessforupdatingtheconfigurationoftheUCD9080isasfollows: 1. UnlockflashmemorybywritingtheFLASHLOCKregisterwithavalueof0x02. 2. Writetheaddressoftheconfigurationsectionofmemory(WADDR=0xE000). 3. Writetheconstant0xBADCtoupdatememory(WDATA=0xBADC). 4. Writetheaddressoftheconfigurationsectionofmemoryagain(WADDR=0xE000). Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com 5. Write the data (WDATA = <varies>). Repeat steps 4 and 5 as necessary, depending on the data segment sizeused,towrite512bytes.Incrementtheaddressasnecessary. 6. Lock flash memory after the last byte of the last segment is written by writing the FLASHLOCK register with avalueof0x00. Attheconclusionofthisprocess,theconfigurationoftheUCD9080isupdatedwiththeconfigurationchanges,as represented by the values from the data segments. The UCD9080 can then be reset by writing the RESTART registerwithavalueof0.Thenewsequencerconfigurationthenstarts. The memory map for the 512-byte configuration segment is defined in the Configuration Parameters Detail section. User Data User data (128 bytes) can be stored in the UCD9080 user-data area at memory location 0x1080 to 0x10FF. Accesstotheuser-dataareaoccursbyfollowingtheprocedureoutlinedintheConfiguringtheUCD9080section. Configuration Parameters Memory Map Table 2 shows the 512-byte configuration parameters memory map. User-configurable bytes in bold are described in the Configuration Parameters Detail section; adjacent groups of user-configurable bytes are distinguishedinthetablebyalternatinguseofitalics.OtherbytesmustremainexactlyasshowninTable2. Table2.ConfigurationParametersMemoryMap ADDRESS +0 +1 +2 +3 +4 +5 +6 +7 0xE000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE008 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE010 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE018 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE020 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE028 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE030 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE038 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE040 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE048 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0xE050 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE058 0xFF 0x00 0x00 0x00 0x00 0x00 0xC0 0x02 0xE060 0x00 0x00 0x00 0x0F 0x00 0x02 0x00 0x02 0xE068 0xFF 0x0F 0x00 0x50 0x00 0x00 0x00 0x00 0xE070 0x00 0x00 0xC0 0x20 0x00 0x00 0x00 0x00 0xE078 0x00 0x00 0x00 0x00 0x00 0xA8 0xDC 0xBA 0xE080 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0xE088 0x00 0x49 0x4A 0x4B 0x01 0x00 0x01 0x04 0xE090 0x01 0x04 0x05 0x06 0x00 0x00 0x00 0x00 0xE098 0x05 0xE0 0x05 0xA0 0x32 0xE0 0x33 0xE0 0xE0A0 0x33 0xE0 0x35 0xE0 0x35 0xE0 0x00 0x00 0xE0A8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0B0 0xFF 0x7F 0xFF 0x7F 0xFF 0x7F 0xFF 0x7F 0xE0B8 0xFF 0x7F 0xFF 0x7F 0xFF 0x7F 0xFF 0x7F 0xE0C0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0C8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0D0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0D8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0E0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 20 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 Table2.ConfigurationParametersMemoryMap (continued) ADDRESS +0 +1 +2 +3 +4 +5 +6 +7 0xE0E8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0F0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE0F8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE100 0x7F 0x00 0x01 0x00 0x02 0x00 0x04 0x00 0xE108 0x08 0x00 0x10 0x00 0x20 0x00 0x40 0x00 0xE110 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE118 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE120 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0xE128 0x00 0x04 0x00 0x04 0x00 0x04 0x00 0x04 0xE130 0xA0 0x0F 0xA0 0x0F 0xA0 0x0F 0xA0 0x0F 0xE138 0xA0 0x0F 0xA0 0x0F 0xA0 0x0F 0xA0 0x0F 0xE140 0x10 0x00 0x10 0x00 0x10 0x00 0x10 0x00 0xE148 0x10 0x00 0x10 0x00 0x10 0x00 0x10 0x00 0xE150 0xFF 0xC0 0xFF 0xC1 0xFF 0xC2 0xFF 0xC3 0xE158 0xFF 0xC4 0xFF 0xC5 0xFF 0xC6 0xFF 0xC7 0xE160 0x00 0x00 0x00 0xC0 0x00 0xC0 0x00 0xC0 0xE168 0x04 0x20 0x08 0x20 0x04 0x18 0x02 0x18 0xE170 0x08 0x18 0x10 0x18 0x20 0x18 0x10 0x20 0xE178 0x00 0x20 0x20 0x20 0x40 0x20 0x80 0x20 0xE180 0x00 0x00 0x00 0x04 0x94 0x02 0xF2 0x08 0xE188 0x10 0x03 0x05 0xC0 0x40 0x00 0xFF 0x08 0xE190 0x05 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE198 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1A0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1A8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1B0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1B8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1C0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1C8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1D0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1D8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1E0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1E8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1F0 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xE1F8 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com CONFIGURATION PARAMETERS DETAIL The following sections detail the format and meaning of the configuration parameters from the Configuration ParametersMemoryMap,Table2. SequenceEventParameters The SequenceEventParameters field in the configuration parameters specifies the rail identification, monitoring status,andsequencingoptionsforeachrail.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE080 1 0x50 Rail1identification,monitoringstatusandsequencingoptions 0xE081 1 0x51 Rail2identification,monitoringstatus,andsequencingoptions 0xE082 1 0x52 Rail3identification,monitoringstatus,andsequencingoptions 0xE083 1 0x53 Rail4identification,monitoringstatus,andsequencingoptions 0xE084 1 0x54 Rail5identification,monitoringstatus,andsequencingoptions 0xE085 1 0x55 Rail6identification,monitoringstatus,andsequencingoptions 0xE086 1 0x56 Rail7identification,monitoringstatus,andsequencingoptions 0xE087 1 0x57 Rail8identification,monitoringstatus,andsequencingoptions 0xE088 1 0x00 GPO1identification,sequencingoptions 0xE089 1 0x49 GPO2identification,sequencingoptions 0xE08A 1 0x4A GPO3identification,sequencingoptions 0xE08B 1 0x4B GPO4identification,sequencingoptions Theformatofeachregisterisasfollows: 7 6 5 4 3 2 1 0 ENABLE 0 MON RAIL/GPO RAIL Rail #(n)–1, RAIL= 0 through 7 GPO GPO #(n) + 7, GPO = 8, 9, 0xA, 0xB MON Meaning 0 Do not monitor rail status (for event sequencing of GPOs) Monitor rail status ENABLE Meaning 00 Sequence is disabled 01 Sequenceistriggeredafterdelayaftersequenceevent 10 Sequenceistriggeredafterparentrailachievesvoltagelevel 11 Sequenceistriggeredafterdelayafterparentrailachievesvoltageregulation 22 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 SequenceEventLink The SequenceEventLink field allows a parent rail (monitored input) to be specified for each ENx and GPOx output. The RESEQ bit (sequence after shutdown) allows an enable or GPO to be marked to sequence the system (as defined by the current sequencer configuration) after it has been shut down. The address map for theseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE08C 1 0x01 Rail1parentrailidentifierandresequenceindicator 0xE08D 1 0x00 Rail2parentrailidentifierandresequenceindicator 0xE08E 1 0x01 Rail3parentrailidentifierandresequenceindicator 0xE08F 1 0x04 Rail4parentrailidentifierandresequenceindicator 0xE090 1 0x01 Rail5parentrailidentifierandresequenceindicator 0xE091 1 0x04 Rail6parentrailidentifierandresequenceindicator 0xE092 1 0x05 Rail7parentrailidentifierandresequenceindicator 0xE093 1 0x06 Rail8parentrailidentifierandresequenceindicator 0xE094 1 0x00 GPO1parentrailidentifierandresequenceindicator 0xE095 1 0x00 GPO2parentrailidentifierandresequenceindicator 0xE096 1 0x00 GPO3parentrailidentifierandresequenceindicator 0xE097 1 0x00 GPO4parentrailidentifierandresequenceindicator Theformatofeachregisterisasfollows: 7 6 5 4 3 2 1 0 0 RESEQ 0 0 PARENTRAIL RESEQ Meaning 0 Do not sequence after shutdown. 1 Sequence after shutdown. PARENTRAIL Meaning 0x0000 Sequence is dependent on RAIL1 achieving the specified event. 0x0001 Sequence is dependent on RAIL2 achieving the specified event. 0x0010 Sequence is dependent on RAIL3 achieving the specified event. 0x0011 Sequence is dependent on RAIL4 achieving the specified event. 0x0100 Sequence is dependent on RAIL5 achieving the specified event. 0x0101 Sequence is dependent on RAIL6 achieving the specified event. 0x0110 Sequence is dependent on RAIL7 achieving the specified event. 0x0111 Sequence is dependent on RAIL8 achieving the specified event. Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com SequenceEventData The SequenceEventData field in the configuration parameters specifies the rail and GPO sequencing and shutdownparameters.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE098 2 0xE005 Rail1sequencingandshutdownparameters 0xE09A 2 0xA005 Rail2sequencingandshutdownparameters 0xE09C 2 0xE032 Rail3sequencingandshutdownparameters 0xE09E 2 0xE033 Rail4sequencingandshutdownparameters 0xE0A0 2 0xE033 Rail5sequencingandshutdownparameters 0xE0A2 2 0xE035 Rail6sequencingandshutdownparameters 0xE0A4 2 0xE035 Rail7sequencingandshutdownparameters 0xE0A6 2 0x0000 Rail8sequencingandshutdownparameters 0xE0A8 2 0x0000 GPO1sequencingandshutdownparameters 0xE0AA 2 0x0000 GPO2sequencingandshutdownparameters 0xE0AC 2 0x0000 GPO3sequencingandshutdownparameters 0xE0AE 2 0x0000 GPO4sequencingandshutdownparameters The format for each register is as follows. The value in the ENABLE field of the SequenceEventParameters register determines the measure represented by the value in the RAILDATA field of the SequenceEventData register. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEQPARAM 0 RAILDATA SEQPARAM Meaning ENABLE RAILDATAMeaning (SequenceEventParameters) 000 Log only 001 Sequence 01 Delay (in units of ms) 010 Reserved 10 Voltage (in units of Vref/1024 volts) 011 Reserved 11 Delay (in units ofms) 100 Reserved 101 Retry 1 times 110 Retry 0 times 111 Reserved 24 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 DependencyMasks The DependencyMasks field in the configuration parameters defines the rail dependency masks used for rail and GPO shutdown. This mask represents the set of other rails and GPOs that should be shut down when this rail shuts down. Note that because only rails are monitored, the table only has entries for the shutdown of rails. In thedependencymaskitself,therearebitsthatallowforGPOshutdown. Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE100 2 0x007F Dependencymaskforrail1 0xE102 2 0x0001 Dependencymaskforrail2 0xE104 2 0x0002 Dependencymaskforrail3 0xE106 2 0x0004 Dependencymaskforrail4 0xE108 2 0x0008 Dependencymaskforrail5 0xE10A 2 0x0010 Dependencymaskforrail6 0xE10C 2 0x0020 Dependencymaskforrail7 0xE10E 2 0x0040 Dependencymaskforrail8 Theformatforeachregisterisasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 GPO4 GPO3 GPO2 GPO1 RAIL8 RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1 RAILn or GPOn Meaning 0 Shutdown of this rail does not shut down RAILn or GPOn. 1 Shutdown of this rail shuts down RAILn or GPOn. UnderVoltageThresholds The UnderVoltageThresholds field in the configuration parameters specifies each rail undervoltage threshold that isusedwhenmonitoringthisrail.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE110 2 0x0000 Undervoltagethresholdforrail8 0xE112 2 0x0000 Undervoltagethresholdforrail7 0xE114 2 0x0000 Undervoltagethresholdforrail6 0xE116 2 0x0000 Undervoltagethresholdforrail5 0xE118 2 0x0000 Undervoltagethresholdforrail4 0xE11A 2 0x0000 Undervoltagethresholdforrail3 0xE11C 2 0x0000 Undervoltagethresholdforrail2 0xE11E 2 0x0000 Undervoltagethresholdforrail1 Theformatforeachregisterisasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 Vraw The voltage conversion is dependent upon the configured voltage reference, and the pullup/pulldown resistors used on the board for each rail. The voltage reference is selected as either 2.5 V (internal) or V (external). The CC formulatoconvertthedesiredrailUnderVoltageThresholdtoVrawfollows: Withoutexternalrailvoltagedivider: 1024´V Vraw = RAILUV V REF (3) Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com Withexternalrailvoltagedivider: 1024´V R Vraw = RAILUV ´ PULLDOWN V R +R REF PULLDOWN PULLUP (4) OverVoltageThresholds The OverVoltageThreholds field in the configuration parameters specifies each rail overvoltage threshold that is usedwhenmonitoringthisrail.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE120 2 0x0400 Overvoltagethresholdforrail8 0xE122 2 0x0400 Overvoltagethresholdforrail7 0xE124 2 0x0400 Overvoltagethresholdforrail6 0xE126 2 0x0400 Overvoltagethresholdforrail5 0xE128 2 0x0400 Overvoltagethresholdforrail4 0xE12A 2 0x0400 Overvoltagethresholdforrail3 0xE12C 2 0x0400 Overvoltagethresholdforrail2 0xE12E 2 0x0400 Overvoltagethresholdforrail1 Theformatforeachregisterisasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 Vraw The voltage conversion is dependent upon the configured voltage reference, and the pullup/pulldown resistors used on the board for each rail. The voltage reference is selected as either 2.5 V (internal) or V (external). The CC formulatoconvertthedesiredrailOverVoltageThresholdtoVrawfollows: Withoutexternalrailvoltagedivider: 1024´V Vraw = RAILOV V REF (5) Withexternalvoltagedivider: 1024´V R Vraw = RAILOV ´ PULLDOWN V R +R REF PULLDOWN PULLUP (6) RampTime The RampTime field in the configuration parameters specifies the maximum amount of time for each rail to achieveregulation.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE130 2 0x0FA0 Maximumvoltageramptimeforrail1 0xE132 2 0x0FA0 Maximumvoltageramptimeforrail2 0xE134 2 0x0FA0 Maximumvoltageramptimeforrail3 0xE136 2 0x0FA0 Maximumvoltageramptimeforrail4 0xE138 2 0x0FA0 Maximumvoltageramptimeforrail5 0xE13A 2 0x0FA0 Maximumvoltageramptimeforrail6 0xE13C 2 0x0FA0 Maximumvoltageramptimeforrail7 0xE13E 2 0x0FA0 Maximumvoltageramptimeforrail8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 RAMPTIME RAMPTIME = RAILn RailTime (in unitsof ms). 26 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 OutOfRegulationWidth The OutOfRegulationWidth field in the configuration parameters specifies the maximum amount of time that the rail is allowed to be out of regulation before an error is declared (glitch duration). The address map for these registersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE140 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail1 0xE142 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail2 0xE144 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail3 0xE146 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail4 0xE148 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail5 0xE14A 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail6 0xE14C 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail7 0xE14E 2 0x0010 Theout-of-regulationdurationpermissiblewithoutflaggingerrorforrail8 Thecontentsofthisregisterareasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 OORW OORW = RAILn out-of-regulation glitchwidth(in unitsof 1/10 ms). UnsequenceTime The UnsequenceTime field in the configuration parameters specifies the amount of time that each rail should delaybeforeunsequencing.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE150 2 0xC0FF Unsequencedelayforrail1 0xE152 2 0xC1FF Unsequencedelayforrail2 0xE154 2 0xC2FF Unsequencedelayforrail3 0xE156 2 0xC3FF Unsequencedelayforrail4 0xE158 2 0xC4FF Unsequencedelayforrail5 0xE15A 2 0xC5FF Unsequencedelayforrail6 0xE15C 2 0xC6FF Unsequencedelayforrail7 0xE15E 2 0xC7FF Unsequencedelayforrail8 0xE160 2 0x0000 UnsequencedelayforGPO1 0xE162 2 0xC000 UnsequencedelayforGPO2 0xE164 2 0xC000 UnsequencedelayforGPO3 0xE166 2 0xC000 UnsequencedelayforGPO4 Thecontentsofthisregisterareasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COPYSEQPARAM 0 USTIME COPYSEQPARAM = CopySEQPARAM bit value USTIME = RAILn UnsequenceTime (in unitsof ms). (bits15:13) in SequenceEvent Data register Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com EnablePolarity The EnablePolarity field in the configuration parameters specifies whether each power-supply enable or GPO is tobeconfiguredactive-highoractive-low.Theaddressmapfortheseregistersisasfollows: ADDRESS SIZE DEFAULTVALUE DESCRIPTION 0xE168 2 0x2004 Polarityforrail1enable 0xE16A 2 0x2008 Polarityforrail2enable 0xE16C 2 0x1804 Polarityforrail3enable 0xE16E 2 0x1802 Polarityforrail4enable 0xE170 2 0x1808 Polarityforrail5enable 0xE172 2 0x1810 Polarityforrail6enable 0xE174 2 0x1820 Polarityforrail7enable 0xE176 2 0x2010 Polarityforrail8enable 0xE178 2 0x2000 PolarityforGPO1 0xE17A 2 0x2020 PolarityforGPO2 0xE17C 2 0x2040 PolarityforGPO3 0xE17E 2 0x2080 PolarityforGPO4 Thecontentsofthisregisterareasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POL DEFAULTVALUES as specified previously POL Meaning 0 Rail enable or GPO is active-low. 1 Rail enable or GPO is active-high. ReferenceSelect The ReferenceSelect field in the configuration parameters specifies which voltage reference is used on the UCD9080. The selected reference can be internal (2.5-V), or external via V (3.3 V). The register address is CC 0xE186andcontentsareasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SELREF 0 0x8F2 SELREF Meaning 000 External reference selected (VCC) 001 Internal reference selected (2.5 V) Thedefaultvalueforthisregisteris0x08F2,whichselectstheexternalreference. LastUnusedSeq The LastUnusedSeq field in the configuration parameters specifies the amount of time for the last rail to be shut downwithoutcreatinganerror.Theregisteraddressis0xE18Eandcontentsareasfollows: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LUTIME LUTIME = Maximum value USTIME + 255 (in units of ms) Thedefaultvalueforthisregisteris0x08FF. 28 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

UCD9080 www.ti.com................................................................................................................................................... SLVS692E–SEPTEMBER2006–REVISEDMAY2008 APPLICATION INFORMATION Typical Application Diagram Figure 12 illustrates a typical power-supply sequencing configuration. Power Supply 1 and Power Supply X require active-low enables, whereas Power Supply 2 and Power Supply 3 require active-high enables. V and OUT1 V exceed the selected A/D reference voltage, so these outputs are divided before being sampled by the OUT3 MON1 and MON3 inputs. V and V are within the selected A/D reference voltage, so theser outputs can OUT2 OUTX be sampled directly by the MON2 and MON7 inputs. Figure 12 illustrates the use of the GPO digital output pins toprovidestatusandpower-onresettoothersystemdevices. SystemDeviceResets VOUT1 VOUT2 VOUT3 VOUTX R1 R2 R3 R4 O O O O PowerSupply1 PowerSupply2 PowerSupply3 * * * PowerSupplyX P P P P N N N N E E E E V V 3.3 3.3 W 330 V 3.3 1Fm StatusLEDs 23 24 11 10 12 13 14 2 17 20 31 30 1 EN1 EN2 EN3 EN4 EN5 EN6 EN7 NC NC NC NC VCC VSS EN8/ADDR1/GPO1 25 UCD9080 ADDR3/ADDR2/GPO3GPO2 2726 MON1 MON2 MON3 MON4 MON5 MON6 MON7 MON8 RST XIN TEST NC ROSC SCL SDA ADDR4/GPO4 28 6 7 8 18 19 9 15 16 5 3 29 4 32 22 21 V 3.3 10kW 0.01Fm 100kW 10kW 10kW V 3.3 V V V V 3.3 3.3 3.3 3.3 VBUS VBUSRTN 3.3VRegulator 2ICMaster 3.3V3.3V3.3V3.3V 10k10k10k10kWWWW DNP1kDNP1kWW 2EX: Slave ICAddress = 0x65(InternalADDR[7:5] = 0b110) Figure12. TypicalPower-SupplySequencingApplication Copyright©2006–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):UCD9080

UCD9080 SLVS692E–SEPTEMBER2006–REVISEDMAY2008................................................................................................................................................... www.ti.com ChangesfromRevisionD(December2007)toRevisionE ........................................................................................... Page • Deletedorderinginformationtable......................................................................................................................................... 2 • ChangedNOMandMAXsupplycurrentspecifications......................................................................................................... 2 • UpdatedSchmitt-triggerinputsignallisttoaddtheENxpins(inputsduringreset).............................................................. 2 • Removedsignallistfromhigh-impedanceleakagecurrentspecification.............................................................................. 2 • UpdatedthedigitaloutputsignallisttoincludetheSCLpin(forclockstretching)................................................................ 3 • UpdatedthedirectionalityfortheENxandSCLpins............................................................................................................ 7 • Clarifiedwording.................................................................................................................................................................... 9 • Clarifiedwordinginseveralsentencesandremovednoteatendofparagraph................................................................... 9 • MovedthissectiontofollowthePower-SupplyEnablessection.Minorwordingchange..................................................... 9 • AddednewsectiontodescribeENxandGPOxbehaviorduringdevicereset,andtodescribeI2Caddressand GPOxpolarityrelationship..................................................................................................................................................... 9 • Clarifiedwordinginsequenceparagraph............................................................................................................................ 10 • Clarifiedwordinginseveralparagraphs.............................................................................................................................. 11 • Clarifieddevicetimecounterreset...................................................................................................................................... 16 • ClarifiedFLASHLOCKwording............................................................................................................................................ 18 • ClarifiedRESTARTwording................................................................................................................................................ 18 • ClarifiedWDATA/WADDRwording...................................................................................................................................... 18 • Clarifiedwordinginseveralsteps........................................................................................................................................ 19 • ChangedpinnamesfromNICtoNCforpins2,4,17,20,31............................................................................................. 29 ChangesfromRevisionC(January2007)toRevisionD ............................................................................................... Page • Changedminimumanalogsupplyandpositivebuilt-inreferenceactiveV (min)voltage.Removedminimum CC samplingvoltage,1.5-Vinternalreference,andDCOOPERATINGPERIODspecifications............................................... 3 • Addedspecificationfordataholdtime,t andnotes3and4......................................................................................... 6 HD;DAT • Changedpin#2from"connecttoVSS"to"donotconnect"................................................................................................. 7 • Removedcritica-rail-specificationsentencefromparagraph4............................................................................................ 10 • AddedIgnoreoptionandupdatedavailableretryoptions.Updateddescriptionsofoptions.............................................. 10 • AddedversionregisterandchangedWDATAaccesstypefromwtorw........................................................................... 13 • Removedreferencetoflashandnon-volatileerrorlogfeatureinNVERRLOGbitdescription........................................... 17 • ChangeWDATAaccesstypefromwtorw......................................................................................................................... 19 • RemovedResettingtheFlashErrorLogssection............................................................................................................... 19 • AddedtheUserDatasection................................................................................................................................................ 20 • Updatedfactorybytevalues................................................................................................................................................ 20 • Updatedfactorybytevalues................................................................................................................................................ 21 • Removedretry2,retry3,retry4,andretrycontinuouslyoptions........................................................................................ 24 • RemovedSaveRailLogregisterdescription......................................................................................................................... 28 • Removedpin-2connectiontoground.................................................................................................................................. 29 30 SubmitDocumentationFeedback Copyright©2006–2008,TexasInstrumentsIncorporated ProductFolderLink(s):UCD9080

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) UCD9080RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCD & no Sb/Br) 9080 UCD9080RHBRG4 ACTIVE VQFN RHB 32 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCD & no Sb/Br) 9080 UCD9080RHBT ACTIVE VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCD & no Sb/Br) 9080 UCD9080RHBTG4 ACTIVE VQFN RHB 32 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 UCD & no Sb/Br) 9080 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) UCD9080RHBR VQFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 UCD9080RHBT VQFN RHB 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) UCD9080RHBR VQFN RHB 32 3000 367.0 367.0 35.0 UCD9080RHBT VQFN RHB 32 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height 5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com

PACKAGE OUTLINE RHB0032E VQFN - 1 mm max height SCALE 3.000 PLASTIC QUAD FLATPACK - NO LEAD A 5.1 B 4.9 PIN 1 INDEX AREA 5.1 (0.1) 4.9 SIDE WALL DETAIL OPTIONAL ME20.000TAL THICKNESS C 1 MAX SEATING PLANE 0.05 0.00 0.08 C 2X 3.5 3.45 0.1 (0.2) TYP 9 16 EXPOSED THERMAL PAD 28X 0.5 8 17 SEE SIDE WALL DETAIL 2X 33 SYMM 3.5 0.3 32X 0.2 24 0.1 C A B 1 0.05 C 32 25 PIN 1 ID SYMM (OPTIONAL) 0.5 32X 0.3 4223442/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 3.45) SYMM 32 25 32X (0.6) 1 24 32X (0.25) (1.475) 28X (0.5) 33 SYMM (4.8) ( 0.2) TYP VIA 8 17 (R0.05) TYP 9 16 (1.475) (4.8) LAND PATTERN EXAMPLE SCALE:18X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4223442/B 08/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RHB0032E VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4X ( 1.49) (R0.05) TYP (0.845) 32 25 32X (0.6) 1 24 32X (0.25) 28X (0.5) (0.845) SYMM 33 (4.8) 8 17 METAL TYP 9 16 SYMM (4.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X 4223442/B 08/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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