Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 TPS54328 4.5-V to 18-V Input, 3-A Synchronous Step-Down Converter With Eco-Mode™ 1 Features 3 Description • D-CAP2™ModeEnablesFastTransient The TPS54328 is an adaptive on-time D-CAP2™ 1 mode synchronous buck converter. The TPS54328 Response enables system designers to complete the suite of • LowOutputRippleandAllowsCeramicOutput various end-equipment power bus regulators with a Capacitor cost effective, low component count, low standby • WideInputVoltageRange:4.5Vto18V current solution. The main control loop for the TPS54328 uses the D-CAP2 mode control that • OutputVoltageRange:0.76Vto7V provides a fast transient response with no external • HighlyEfficientIntegratedFETsOptimizedfor compensationcomponents. LowerDutyCycleApplications The adaptive on-time control supports seamless – 100mΩ (High-Side)and70mΩ (Low-Side) transition between PWM mode at higher load • HighEfficiency,LessThan10µAatShutdown conditions and Eco-mode operation at light loads. • HighInitialBandgapReferenceAccuracy Eco-mode allows the TPS54328 to maintain high efficiency during lighter load conditions. The • AdjustableSoftStart TPS54328 also has a proprietary circuit that enables • Pre-BiasedSoftStart the device to adopt to both low equivalent series • 700-kHzSwitchingFrequency(f ) resistance (ESR) output capacitors, such as SW • Cycle-By-CycleOvercurrentLimit POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors. The device operates from 4.5-V to 18-V • Auto-SkipEco-Mode™forHighEfficiencyatLight input(V ). Load IN The output voltage can be programmed from 0.76 V 2 Applications to 7 V. The device also features an adjustable soft start time. The TPS54328 is available in 8-pin DDA • WideRangeofApplicationsforLowVoltage and 10-pin DRC packages, and is designed to Systems operateovertheambienttemperaturerangeof –40°C – DigitalTVPowerSupplies to85°C. – HighDefinitionBlu-rayDisc™Players DeviceInformation(1) – NetworkingHomeTerminals PARTNUMBER PACKAGE BODYSIZE(NOM) – DigitalSetTopBoxes(STB) HSOP(8) 4.89mm×3.90mm TPS54328 VSON(10) 3.00mm×3.00mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic TPS54320TransientResponse V = 50 mV / div (-950 mV dc offset) O I = 1A/ div (0.75 to 2.25Aload step, O slew rate = 1A/ µsec) Copyright © 2016,Texas Instruments Incorporated Time = 50 µsec / div 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com Table of Contents 1 Features.................................................................. 1 8 ApplicationandImplementation........................ 11 2 Applications........................................................... 1 8.1 ApplicationInformation............................................11 3 Description............................................................. 1 8.2 TypicalApplication..................................................11 4 RevisionHistory..................................................... 2 9 PowerSupplyRecommendations...................... 15 5 PinConfigurationandFunctions......................... 3 10 Layout................................................................... 15 6 Specifications......................................................... 4 10.1 LayoutGuidelines.................................................15 6.1 AbsoluteMaximumRatings......................................4 10.2 LayoutExample....................................................16 6.2 ESDRatings..............................................................4 10.3 ThermalConsiderations........................................17 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 18 6.4 ThermalInformation..................................................5 11.1 DeviceSupport......................................................18 6.5 ElectricalCharacteristics...........................................5 11.2 DocumentationSupport........................................18 6.6 TypicalCharacteristics..............................................6 11.3 ReceivingNotificationofDocumentationUpdates18 7 DetailedDescription.............................................. 8 11.4 CommunityResources..........................................18 7.1 Overview...................................................................8 11.5 Trademarks...........................................................18 7.2 FunctionalBlockDiagram.........................................8 11.6 ElectrostaticDischargeCaution............................18 7.3 FeatureDescription...................................................8 11.7 Glossary................................................................18 7.4 DeviceFunctionalModes........................................10 12 Mechanical,Packaging,andOrderable Information........................................................... 18 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionC(November2012)toRevisionD Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • DeletedOrderingInformationtable;seePOAattheendofthedatasheet........................................................................... 1 • ChangedheartsicktoheatsinkinThermalConsiderationssection...................................................................................... 17 ChangesfromRevisionB(April2012)toRevisionC Page • ChangedtheDescriptiontexttoincludetheDRCpackage................................................................................................... 1 • AddedtheDRC-10pinPackagetotheORDERINGINFORMATIONtable........................................................................... 1 • AddedFigure17................................................................................................................................................................... 16 ChangesfromRevisionA(January2012)toRevisionB Page • DeletedSwift™fromthedatasheettitle................................................................................................................................ 1 • ChangedFigure9andFigure10......................................................................................................................................... 13 ChangesfromOriginal(November2010)toRevisionA Page • AddedconditiontotheTYPICALCHARACTERISTICStitleline,allpages........................................................................... 6 • ChangedtheFunctionalBlockDiagram................................................................................................................................. 8 2 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 5 Pin Configuration and Functions DDAPackage DRCPackage 8-PinHSOP 10-PinVSON TopView TopView EN 1 8 VIN EN 1 10 VIN VFB 2 7 VBST Thermal Pad VFB 2 9 VIN VREG5 3 6 SW VREG5 3 Thermal Pad 8 VBST SS 4 5 GND SS 4 7 SW GND 5 6 SW Not to scale Not to scale PinFunctions PIN I/O DESCRIPTION NAME HSOP VSON EN 1 1 I Enableinputcontrol.Activehigh. Groundpin.Powergroundreturnforswitchingcircuit.ConnectsensitiveSSandVFB 5 — — GND returnstoGNDatasinglepoint. — 5 — Groundpin.ConnectsensitiveSSandVFBreturnstoGNDatasinglepoint. SS 4 4 I Soft-startcontrol.AnexternalcapacitormustbeconnectedtoGND. SW 6 6,7 O Switchnodeconnectionbetweenhigh-sideNFETandlow-sideNFET. Supplyinputforthehigh-sideFETgatedrivecircuit.Connect0.1-µFcapacitorbetween VBST 7 8 I VBSTandSWpins.AninternaldiodeisconnectedbetweenVREG5andVBST. VFB 2 2 I Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider. VIN 8 9,10 I Inputvoltagesupplypin. 5.5-Vpower-supplyoutput.Acapacitor(typically1µF)mustbeconnectedtoGND.VREG5 VREG5 3 3 O isnotactivewhenENislow. Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Mustbe Exposed Backside — — connectedtoGND. Thermal Pad — Backside — Thermalpadofthepackage.PGNDpowergroundreturnofinternallow-sideFET.Mustbe solderedtoachieveappropriatedissipation. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT VIN,EN –0.3 20 VBST –0.3 26 VBST(10nstransient) –0.3 28 Inputvoltage VBST(vsSW) –0.3 6.5 V VFB,SS –0.3 6.5 SW –2 20 SW(10-nstransient) –3 22 VREG5 –0.3 6.5 Outputvoltage V GND –0.3 0.3 VoltagefromGNDtothermalpad,V –0.2 0.2 V diff Operatingjunctiontemperature,T –40 150 °C J Storagetemperature,T –55 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyinputvoltage 4.5 18 V IN VBST –0.1 24 VBST(10-nstransient) –0.1 27 VBST(vsSW) –0.1 5.7 SS –0.1 5.7 Inputvoltage EN –0.1 18 V VFB –0.1 5.5 SW –1.8 18 SW(10-nstransient) –3 21 GND –0.1 0.1 V Outputvoltage VREG5 –0.1 5.7 V OUT I Outputcurrent I 0 10 mA OUT VREG5 T Operatingfree-airtemperature –40 85 °C A T Operatingjunctiontemperature –40 150 °C J 4 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 6.4 Thermal Information TPS54328 THERMALMETRIC(1) DDA(HSOP) DRC(VSON) UNIT 8PINS 10PINS R Junction-to-ambientthermalresistance 42.1 43.9 °C/W θJA R Junction-to-case(top)thermalresistance 50.9 55.4 °C/W θJC(top) R Junction-to-boardthermalresistance 31.8 18.9 °C/W θJB ψ Junction-to-topcharacterizationparameter 5 0.7 °C/W JT ψ Junction-to-boardcharacterizationparameter 13.5 19.1 °C/W JB R Junction-to-case(bottom)thermalresistance 7.1 5.3 °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT I Operatingnon-switchingsupplycurrent VINcurrent,T =25°C,EN=5V,V =0.8V 800 1200 µA VIN A FB I Shutdownsupplycurrent VINcurrent,T =25°C,EN=0V 1.8 10 µA VINSDN A LOGICTHRESHOLD V ENhigh-levelinputvoltage EN 1.6 V ENH V ENlow-levelinputvoltage EN 0.45 V ENL V VOLTAGEANDDISCHARGERESISTANCE FB T =25°C,V =1.05V,I =10mA, A OUT OUT 772 mV Eco-modeoperation V VFBthresholdvoltage FBTH T =25°C,V =1.05V,continuousmode A OUT 749 765 781 mV operation I VFBinputcurrent V =0.8V,T =25°C 0 ±0.1 µA VFB FB A VREG5OUTPUT V VREG5outputvoltage T =25°C,6V<V <18V,0<I <5mA 5.2 5.5 5.7 V VREG5 A IN VREG5 V Lineregulation 6V<V <18V,I =5mA 25 mV LN5 IN VREG5 V Loadregulation 0mA<I <5mA 100 mV LD5 VREG5 I Outputcurrent V =6V,V =4V,T =25°C 60 mA VREG5 IN VREG5 A MOSFET R High-sideswitchresistance T =25°C,V –SW=5.5V 100 mΩ DS(ON)H A BST R Low-sideswitchresistance T =25°C 70 mΩ DS(ON)L A CURRENTLIMIT I Currentlimit L =1.5µH(1),T =–20ºCto85ºC 3.5 4.2 5.7 A OCL OUT A THERMALSHUTDOWN Shutdowntemperature (1) 165 T Thermalshutdownthreshold °C SDN Hysteresis (1) 30 ON-TIMETIMERCONTROL t ONtime V =12V,V =1.05V 150 ns ON IN OUT t Minimumofftime T =25°C,V =0.7V 260 310 ns OFF(MIN) A FB SOFTSTART I SSchargecurrent V =0V 1.4 2 2.6 µA SSC SS I SSdischargecurrent V =0.5V 0.05 0.1 mA SSD SS (1) Notproductiontested. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com Electrical Characteristics (continued) overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT UVLO WakeupVREG5voltage 3.45 3.75 4.05 UVLO UVLOthreshold V HysteresisVREG5voltage 0.17 0.32 0.45 6.6 Typical Characteristics V =12V,T =25°C(unlessotherwisenoted). IN A 1200 10.0 1000 8.0 A A µ urrent - µ 800 Current - 6.0 ply C 600 pply up Su 4.0 I- SVIN 400 I- VINSDN 2.0 200 0 0 -50 0 50 100 150 -50 0 50 100 150 T- Junction Temperature - °C T- Junction Temperature - °C j j Figure1.VINCurrentvsJunctionTemperature Figure2.VINShutdownCurrentvsJunctionTemperature 100 1.08 90 VIN= 18 V 80 V1.07 Am 70 e - EN - Input Current - 34560000 V- Output VoltagO11..0056 VIN= 5.5V V=V 1IN2= V18 V IN 20 10 0 1.04 0 2 4 6 8 10 12 14 16 18 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 EN - Input Voltage - V I - Output Current -A O Figure3.ENCurrentvsENVoltage Figure4.1.05-VOutputVoltagevsOutputCurrent 6 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 Typical Characteristics (continued) V =12V,T =25°C(unlessotherwisenoted). IN A 1.08 I = 10 mA O V1.07 e - g a olt ut V1.06 IO= 1A p ut O - VO1.05 1.04 0 5 10 15 20 V - Input Voltage - V IN Figure5.1.05-VOutputVoltagevsInputVoltage Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com 7 Detailed Description 7.1 Overview The TPS54328 is a 3-A, synchronous, step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2 mode control. The fast transient response of D-CAP2 control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low- ESRoutputcapacitorsincludingceramicandspecialpolymertypes. 7.2 Functional Block Diagram EN 1 EN VIN Logic VIN 8 VREG5 VBST Control Logic 7 Ref + SS +PWM VFB 1 shot SW VO 2 - 6 XCON ON VREG5 VREG5 Ceramic 3 Capacitor SGND SS SS 5 4 Softstart + SW GND PGND ZC - PGND SGND + SW OCP - PGND VIN VREG5 UVLO Protection TSD Logic UVLO REF Ref Copyright © 2016,Texas Instruments Incorporated 7.3 Feature Description 7.3.1 PWMOperation The main control loop of the TPS54328 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2 mode control. D-CAP2 mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. 8 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 Feature Description (continued) At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage (V ) and the output voltage (V ) to IN OUT maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2modecontrol. 7.3.2 PWMFrequencyandAdaptiveOn-TimeControl TPS54328 uses an adaptive on-time control scheme and does not have a dedicated onboard oscillator. The TPS54328 runs with a pseudo-constant frequency of 700 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the outputvoltage,therefore,whenthedutyratioisV /V ,thefrequencyisconstant. OUT IN 7.3.3 Auto-SkipEco-ModeControl The TPS54328 is designed with Auto-Skip Eco-Mode to increase light load efficiency. As the output current decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor with smaller load current to the level of the reference voltage. The transition point to the light load operation I currentcanbecalculatedinEquation1. OUT(LL) 1 (V -V )×V IN OUT OUT I = = OUT(LL) 2×L× fsw V IN (1) 7.3.4 SoftStartandPre-BiasedSoftStart The soft start function is adjustable. When the EN pin becomes high, 2-µA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is 2µA. C6(nF)xVREF x1.1 C6(nF)x0.765x1.1 t (ms)= = SS I (mA) 2 SS (2) The TPS54328 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage V ), the controller slowly activates synchronous rectification by starting FB the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by- cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that V starts and ramps up smoothly OUT intoregulationandthecontrolloopisgiventimetotransitionfrompre-biasedstart-uptonormalmodeoperation. 7.3.5 CurrentProtection The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by V , IN V , the on-time, and the output inductor value. During the on time of the low-side FET switch, this current OUT decreases linearly. The average value of the switch current is the load current I . The TPS54328 constantly OUT monitorsthelow-sideFETswitchvoltage,whichisproportionaltotheswitchcurrent,duringthelow-sideon-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com Feature Description (continued) cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the highervalue. There are some important considerations for this type of over-current protection. The load current one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the over current condition is removed, the output voltagereturnstotheregulatedvalue.Thisprotectionisnon-latching. 7.3.6 UVLOProtection Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lowerthanUVLOthresholdvoltage,theTPS54328isshutoff.Thisprotectionisnon-latching. 7.3.7 ThermalShutdown TPS54328 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), thedeviceisshutoff.Thisisnon-latchprotection. 7.4 Device Functional Modes 7.4.1 NormalOperation When the input voltage is above the UVLO threshold and the EN voltage is above the enable threshold, the TPS54328 can operate in the normal switching modes. Normal continuous conduction mode (CCM) occurs when the minimum switch current is above 0 A. In CCM, the TPS54328 operates at a quasi-fixed frequency of 700kHz. 7.4.2 StandbyOperation When the device is operating in either normal CCM or forced CCM, it may be placed in standby operation mode byassertingtheENpinlow. 10 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54328 is typically used as step down converters, which convert a voltage from 4.5 V to 18 V to a lower voltage.WEBENCH®softwareisavailabletoaidinthedesignandanalysisofcircuits. 8.2 Typical Application Copyright © 2016,Texas Instruments Incorporated Figure6. SchematicDiagram 8.2.1 DesignRequirements Forthisdesignexample,usetheparameterslistedinTable1astheinputparameters. Table1.DesignParameters PARAMETER EXAMPLEVALUE Inputvoltage 4.5Vto18V Outputvoltage 1.05V Outputcurrent 3A Outputvoltageripple 50mV PP 8.2.2 DetailedDesignProcedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent • Outputvoltageripple Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com • Inputvoltageripple 8.2.2.1 OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends using 1% toleranceorbetterdividerresistors.StartbyusingEquation3tocalculateV . OUT To improve efficiency at very light loads consider using larger value resistors, too high of resistance is more susceptibletonoiseandvoltageerrorsfromtheVFBinputcurrentismorenoticeable. æ R1ö VOUT =0.765x çççè1+ R2÷÷÷÷ø (3) 8.2.2.2 OutputFilterSelection TheoutputfilterusedwiththeTPS54328isanLCcircuit.ThisLCfilterhasadoublepoleat: 1 F = P 2p L xC OUT OUT (4) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54328. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2 introduces a high-frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesinTable2. Table2.RecommendedComponentValues OUTPUTVOLTAGE R1(kΩ) R2(kΩ) C4(pF) L1(µH) C8+C9(µF) (V) 1 6.81 22.1 — 1.5 22–68 1.05 8.25 22.1 — 1.5 22–68 1.2 12.7 22.1 — 1.5 22–68 1.8 30.1 22.1 5-22 2.2 22–68 2.5 49.9 22.1 5-22 2.2 22–68 3.3 73.2 22.1 5-22 2.2 22–68 5 124 22.1 5-22 3.3 22–68 6.5 165 22.1 5-22 3.3 22–68 Because the DC gain is dependent on the output voltage, the required inductor value increases as the output voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by addingafeedforwardcapacitor(C4)inparallelwithR1 The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5, Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 700 kHz for f . SW Use 700 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 6 and the RMS SW currentofEquation7. I = VOUT x VIN(max) -VOUT IPP V L x f IN(max) O SW (5) I lpp I =I + Ipeak O 2 (6) 1 I = I 2 + I 2 Lo(RMS) O 12 IPP (7) 12 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 For this design example, the calculated peak current is 3.49 A and the calculated RMS current is 3.01 A. The inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54328 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 22 µF to 68 µF. Use Equation 8 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V x(V -V ) I = OUT IN OUT Co(RMS) 12 xV xL x f IN O SW (8) For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.271Aandeachoutputcapacitorisratedfor4A. 8.2.2.3 InputCapacitorSelection The TPS54328 requires an input decoupling capacitor and a bulk capacitor is required depending on the application. TI recommends a ceramic capacitor over 10 µF for the decoupling capacitor. TI recommends an additional 0.1-µF capacitor from VIN to ground to improve the stability of the over-current limit function. The capacitorvoltageratingrequirestobegreaterthanthemaximuminputvoltage. 8.2.2.4 BootstrapCapacitorSelection A 0.1-µF ceramic capacitor must be connected between the VBST and SW pin for proper operation. TI recommendsusingaceramiccapacitor. 8.2.2.5 VREG5CapacitorSelection A 1-µF ceramic capacitor must be connected between the VREG5 and GND pins for proper operation. TI recommendsusingaceramiccapacitor. 8.2.3 ApplicationCurves V = 50 mV / div (-950 mV dc offset) O EN = 10 V / div SS = 5 V / div I = 1A/ div (0.75 to 2.25Aload step, O slew rate = 1A/ µsec) V = 500 mV / div O Time = 50 µsec / div Time = 2 msec / div Figure7.1.05V,LoadTransientResponse Figure8.Start-upWaveform Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com 100 100 90 90 80 70 %) 80 %) Efficiency ( 6700 Efficiency ( 456000 VVVOOO === 321...358 VVV 30 VO = 3.3V 50 VO = 2.5 V 20 VO = 1.8 V 10 40 0 0 0.5 1 1.5 2 2.5 3 0.001 0.01 0.1 1 10 Iout−Output Current (A) Iout−Output Current (A) G008 G009 Figure9.EfficiencyvsOutputCurrent Figure10.LightLoadEfficiencyvsOutputCurrent 900 900 V = 12 V IN 850 850 Switching Frequency - kHz566778505050000000 VO= 1.8 V VO= 1V.0O5= V 3.3 V Switching Frequency - kHz 566778505050000000 VVOO== 1 1.0.85 VV VO= 3.3 V F- S500 F- S 500 450 450 400 400 0 5 10 15 20 0 0.5 1 1.5 2 2.5 3 VIN- Input Voltage - V IO- Output Current -A Figure11.SwitchingFrequencyvsInputVoltage Figure12.SwitchingFrequencyvsOutputCurrent VO= 50 mV / div (-950 mV dc offset) VO= 50 mV / div (-950 mV dc offset) SW = 10 V / div SW = 10 V / div Time = 1 µsec / div Time = 1 µsec / div I =3A I =30mA OUT OUT Figure13.VoltageRippleatOutput Figure14.DCMVoltageRippleatOutput 14 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 V = 50 mV / div IN SW = 5 V / div Time = 1 µsec / div I =3A OUT Figure15.VoltageRippleatInput 9 Power Supply Recommendations The TPS54328 is designed to operate from input supply voltage of 4.5 V to 18 V. Buck converters require the input voltage to be higher than the output voltage for proper operation. The maximum recommended operating dutycycleis65%.Usingthatcriteria,theminimumrecommendedinputvoltageisV /0.65. OUT 10 Layout 10.1 Layout Guidelines • Keeptheinputswitchingcurrentloopassmallaspossible. • Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections must be brought from the output to the feedbackpinofthedevice. • Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. • Makeasinglepointconnectionfromthesignalgroundtopowerground. • Donotallowswitchingcurrenttoflowunderthedevice. • KeepthepatternlinesforVINandPGNDbroad. • ExposedpadofdevicemustbeconnectedtoPGNDwithsolder. • VREG5capacitormustbeplacednearthedevice,andconnectedPGND. • OutputcapacitormustbeconnectedtoabroadpatternofthePGND. • Voltagefeedbackloopmustbeasshortaspossible,andpreferablywithgroundshield. • LowerresistorofthevoltagedividerwhichisconnectedtotheVFBpinmustbetiedtoSGND. • ProvidingsufficientviasispreferableforVIN,SWandPGNDconnection. • PCBpatternforVIN,SW,andPGNDmustbeasbroadaspossible. • VINcapacitormustbeplacedasnearaspossibletothedevice. Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com 10.2 Layout Example VIN VIN INPUT BYPASS CAPACITOR VIN HIGH FREQENCY BYPASS FEEDBACK CAPACITOR RESISTORS TO ENABLE CONTROL EN VIN BOOST VFB VBST CAPACITOR VREG5 SW OUTPUT VOUT BCIAAPS SS GND INDUCTOR SLOW START CAP EXPOSED THERMALPAD AREA OUTPUT Connection to POWER GROUND FILTER on internal or CAPACITOR bottom layer ANALOG GROUND TRACE POWER GROUND VIAto Ground Plane Figure16. PCBLayout VIN VIN INPUT BYPASS CAPACITOR VIN HIGH FREQUENCY FEEDBACK BYPASS RESISTORS TO ENABLE CAPACITOR CONTROL EN VIN VFB VIN BOOST VREG5 VBST CAPACITOR BIAS VOUT CAP SS SW SLOW START GND SW OUTPUT CAP INDUCTOR EXPOSED OUTPUT THERMALPAD FILTER ANALOG AREA CAPACITOR GROUND Connection to TRACE PonO iWntEerRn aGl RorOUND POWER GROUND bottom layer VIAto Ground Plane Figure17. PCBLayoutfortheDRCPackage 16 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

TPS54328 www.ti.com SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 10.3 Thermal Considerations This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heat sink.Thethermalpadmustbesoldereddirectlytotheprintedboard(PCB).Aftersoldering,thePCBcanbeused as a heat sink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heat sink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities,seePowerPAD™ThermallyEnhancedPackageandPowerPAD™MadeEasy. TheexposedthermalpaddimensionsforthispackageareshowninFigure18. Figure18. ThermalPadDimensions Copyright©2010–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54328

TPS54328 SLVSAN2D–NOVEMBER2010–REVISEDAUGUST2016 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 DevelopmentSupport FortheWEBENCHTools,gotohttp://www.ti.com/lsds/ti/analog/webench/overview.page 11.2 Documentation Support 11.2.1 RelatedDocumentation Forrelateddocumentationseethefollowing: • PowerPAD™ThermallyEnhancedPackage(SLMA002) • PowerPAD™MadeEasy(SLMA004) 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.5 Trademarks D-CAP2,Eco-Mode,E2EaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Blu-rayDiscisatrademarkofBlu-rayDiscAssociation. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 11.7 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 18 SubmitDocumentationFeedback Copyright©2010–2016,TexasInstrumentsIncorporated ProductFolderLinks:TPS54328

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54328DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS SN Level-2-260C-1 YEAR -40 to 85 54328 & no Sb/Br) TPS54328DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS SN Level-2-260C-1 YEAR -40 to 85 54328 & no Sb/Br) TPS54328DRCR ACTIVE VSON DRC 10 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54328 & no Sb/Br) TPS54328DRCT ACTIVE VSON DRC 10 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 54328 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54328DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD TPS54328DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54328DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54328DDAR SOPowerPAD DDA 8 2500 366.0 364.0 50.0 TPS54328DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS54328DRCT VSON DRC 10 250 210.0 185.0 35.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4202561/G

None

None

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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