Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 TPS54240 3.5-V to 42-V Step-Down DC - DC Converter With Eco-Mode™ 1 Features 3 Description • 3.5-Vto42-VInputVoltageRange The TPS54240 device is a 42-V, 2.5-A, step-down 1 regulator with an integrated high-side MOSFET. • 200-mΩ High-SideMOSFET Current mode control provides simple external • HighEfficiencyatLightLoadsWithaPulse compensation and flexible component selection. A SkippingEco-Mode™ low-ripple, pulse skip mode reduces the no load, • 138-μAOperatingQuiescentCurrent regulated output supply current to 138 μA. Using the enable pin, shutdown supply current is reduced to 1.3 • 1.3-μAShutdownCurrent μA,whentheenablepinislow. • 100-kHzto2.5-MHzSwitchingFrequency Undervoltage lockout is internally set at 2.5 V, but it • SynchronizestoExternalClock can be increased using the enable pin. The output • AdjustableSlowStartandSequencing voltage startup ramp is controlled by the slow-start • UVandOVPowerGoodOutput pin that can also be configured for sequencing and tracking. An open-drain power good signal indicates • AdjustableUVLOVoltageandHysteresis the output is within 94% to 107% of its nominal • 0.8-VInternalVoltageReference voltage. • 10-PinHVSSOPand10-Pin3-mmx3-mmVSON A wide switching frequency range allows efficiency PackageswithPowerPAD™ and optimization of external component size. • Supportedby WEBENCH®SoftwareTool Frequency foldback and thermal shutdown protects thepartduringanoverloadcondition. 2 Applications The TPS54240 is available in 10-pin, thermally- • 12-Vand24-VIndustrialandCommercialLow- enhanced HVSSOP and 10-pin 3-mm x 3-mm PowerSystems PowerPADpackage. • GSM,GPRSModulesinFleetManagement, DeviceInformation(1) eMeters,andSecuritySystems PARTNUMBER PACKAGE BODYSIZE(NOM) HVSSOP(10) TPS54240 3.00mmx3.00mm VSON(10) (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic EfficiencyvsLoadCurrent 100 V VVIINN PWRGD IN 90 TPS54240 80 70 BOOT EN % 60 y - SS/TR PH VOUT cienc 50 RT/CLK Effi 40 30 COMP 20 VIN=12V VSENSE VOUT=3.3V fsw=300kHz 10 0 GND 0 0.5 1.0 1.5 2.0 2.5 3.0 IO- Output Current -A 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes.......................................30 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 30 3 Description............................................................. 1 8.1 ApplicationInformation ..........................................30 4 RevisionHistory..................................................... 2 8.2 TypicalApplication..................................................31 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 42 6 Specifications......................................................... 4 10 Layout................................................................... 42 6.1 AbsoluteMaximumRatings .....................................4 10.1 LayoutGuidelines.................................................42 6.2 HandlingRatings.......................................................4 10.2 LayoutExample....................................................42 6.3 RecommendedOperatingConditions.......................4 10.3 EstimatedCircuitArea..........................................43 6.4 ThermalInformation..................................................5 11 DeviceandDocumentationSupport................. 43 6.5 ElectricalCharacteristics...........................................6 11.1 DeviceSupport ....................................................43 6.6 TypicalCharacteristics..............................................8 11.2 DocumentationSupport........................................43 7 DetailedDescription............................................ 12 11.3 Trademarks...........................................................43 7.1 Overview.................................................................12 11.4 ElectrostaticDischargeCaution............................43 7.2 FunctionalBlockDiagram.......................................13 11.5 Glossary................................................................43 7.3 FeatureDescription.................................................13 12 Mechanical,Packaging,andOrderable Information........................................................... 43 4 Revision History NOTE:Pagenumbersofcurrentversionmaydifferfrompreviousversions. ChangesfromRevisionA(April2010)toRevisionB Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 • ChangedtheStartInputVoltagevalueinDesignRequirementsfrom6.0Vto6.25V....................................................... 31 • ChangedtheStopInputVoltagevalueinDesignRequirementsfrom5.5Vto5.9V ........................................................ 31 • Changedthevalue6.0Vto6.25V...................................................................................................................................... 36 • Changedthevalue5.5Vto5.9V........................................................................................................................................ 36 • Changedthevalue6.0Vto6.25V...................................................................................................................................... 36 • Changedthevalue5.5Vto5.9V........................................................................................................................................ 36 ChangesfromOriginal(April2010)toRevisionA Page • Added10-Pin3mmx3mmSONtoFeatures......................................................................................................................... 1 • AddedThermalInformationtableanddeletedPackageDissipationRatingstable............................................................... 4 2 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 5 Pin Configuration and Functions DGQ PACKAGE DRC PACKAGE (TOPVIEW) (TOPVIEW) BOOT 1 10 PH BOOT 1 10 PH VIN 2 9 GND VIN 2 9 GND Thermal Thermal EN 3 Pad 8 COMP EN 3 Pad 8 COMP (11) (11) SS/TR 44 7 VSENSE SS/TR 44 7 VSENSE RT/CLK 5 6 PWRGD RT/CLK 5 6 PWRGD PinFunctions PIN I/O DESCRIPTION NAME NO. AbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitorisbelowthe BOOT 1 O minimumrequiredbytheoutputdevice,theoutputisforcedtoswitchoffuntilthecapacitorisrefreshed. Erroramplifieroutput,andinputtotheoutputswitchcurrentcomparator.Connectfrequencycompensation COMP 8 O componentstothispin. Enablepin,internalpullupcurrentsource.Pullbelow1.2Vtodisable.Floattoenable.Adjusttheinput EN 3 I undervoltagelockoutwithtworesistors. GND 9 – Ground PH 10 I Thesourceoftheinternalhigh-sidepowerMOSFET. POWERPAD 11 – GNDpinmustbeelectricallyconnectedtotheexposedpadontheprintedcircuitboardforproperoperation. Anopen-drainoutput,assertslowifoutputvoltageislowduetothermalshutdown,dropout,overvoltageor PWRGD 6 O ENshutdown. ResistorTimingandExternalClock.Aninternalamplifierholdsthispinatafixedvoltagewhenusingan externalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLLupperthreshold, RT/CLK 5 I amodechangeoccursandthepinbecomesasynchronizationinput.Theinternalamplifierisdisabledand thepinisahighimpedanceclockinputtotheinternalPLL.Ifclockingedgesstop,theinternalamplifierisre- enabledandthemodereturnstoaresistorsetfunction. Slow-StartandTracking.Anexternalcapacitorconnectedtothispinsetstheoutputrisetime.Sincethe SS/TR 4 I voltageonthispinoverridestheinternalreference,itcanbeusedfortrackingandsequencing. VIN 2 I Inputsupplyvoltage,3.5Vto42V. VSENSE 7 I Invertingnodeofthetransconductance(gm)erroramplifier. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VIN –0.3 47 EN –0.3 5 VSENSE –0.3 3 Inputvoltage COMP –0.3 3 V PWRGD –0.3 6 SS/TR –0.3 3 RT/CLK –0.3 3.6 BOOT-PH 8 Outputvoltage PH –0.6 47 V PH,10-nsTransient –2 47 Voltagedifference PADtoGND ±200 mV EN 100 μA BOOT 100 mA Sourcecurrent VSENSE 10 μA PH CurrentLimit A RT/CLK 100 μA VIN CurrentLimit A COMP 100 μA Sinkcurrent PWRGD 10 mA SS/TR 200 μA Operatingjunctiontemperature –40 150 °C (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings onlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 Handling Ratings MIN MAX UNIT T Storagetemperaturerange –65 150 °C stg Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,all -2 2 pins(1) kV V Electrostaticdischarge (ESD) Chargeddevicemodel(CDM),perJEDECspecification -500 500 JESD22-C101,allpins(2) V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT OperatingInputVoltageon(VINpin) 3.5 42 V Operatingjunctiontemperature,T -40 150 °C J 4 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 6.4 Thermal Information TPS54240 THERMALMETRIC(1)(2)(2) DGQ DRC UNIT 10PINS 10PINS θ Junction-to-ambientthermalresistance(standardboard) 62.5 40 JA ψ Junction-to-topcharacterizationparameter 1.7 0.6 JT ψ Junction-to-boardcharacterizationparameter 20.1 7.5 JB °C/W θ Junction-to-case(top)thermalresistance 83 65 JCtop θ Junction-to-case(bottom)thermalresistance 21 7.8 JCbot θ Junction-to-boardthermalresistance 28 8 JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) PowerratingataspecificambienttemperatureTAshouldbedeterminedwithajunctiontemperatureof150°C.Thisisthepointwhere distortionstartstosubstantiallyincrease.Seepowerdissipationestimateinapplicationsectionofthisdatasheetformoreinformation. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 6.5 Electrical Characteristics T =–40°Cto150°C,VIN=3.5to42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage 3.5 42 V Internalundervoltagelockoutthreshold Novoltagehysteresis,risingandfalling 2.5 V Shutdownsupplycurrent EN=0V,25°C,3.5V≤VIN≤42V 1.3 4 μA Operating:nonswitchingsupplycurrent VSENSE=0.83V,VIN=12V,25°C 138 200 ENABLEANDUVLO(ENPIN) Enablethresholdvoltage Novoltagehysteresis,risingandfalling,25°C 1.15 1.25 1.36 V Enablethreshold+50mV –3.8 Inputcurrent μA Enablethreshold–50mV –0.9 Hysteresiscurrent –2.9 μA VOLTAGEREFERENCE T =25°C 0.792 0.8 0.808 J Voltagereference V 0.784 0.8 0.816 HIGH-SIDEMOSFET VIN=3.5V,BOOT-PH=3V 300 On-resistance mΩ VIN=12V,BOOT-PH=6V 200 410 ERRORAMPLIFIER(EA) Inputcurrent 50 nA Erroramplifiertransconductance(g ) –2μA<I <2μA,V =1V 310 μS M COMP COMP Erroramplifiertransconductance(gM) –2μA<ICOMP<2μA,VCOMP=1V, 70 μS duringslowstart V =0.4V VSENSE Erroramplifierdcgain V =0.8V 10,000 V/V VSENSE Erroramplifierbandwidth 2700 kHz Erroramplifiersource/sink V =1V,100mVoverdrive ±27 μA (COMP) COMPtoswitchcurrent 10.5 A/V transconductance 6 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Electrical Characteristics (continued) T =–40°Cto150°C,VIN=3.5to42V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT Currentlimitthreshold VIN=12V,T =25°C 3.5 6.1 A J THERMALSHUTDOWN Thermalshutdown 182 °C TIMINGRESISTORANDEXTERNALCLOCK (RT/CLKPIN) SwitchingFrequencyRangeusingRT 100 2500 kHz mode f Switchingfrequency R =200kΩ 450 581 720 kHz SW T SwitchingFrequencyRangeusingCLK 300 2200 kHz mode MinimumCLKinputpulsewidth 40 ns RT/CLKhighthreshold 1.9 2.2 V RT/CLKlowthreshold 0.5 0.7 V RT/CLKfallingedgetoPHrisingedge Measuredat500kHzwithRTresistorinseries 60 ns delay PLLlockintime Measuredat500kHz 100 μs SLOW-STARTANDTRACKING(SS/TR) Chargecurrent V =0.4V 2 μA SS/TR SS/TR-to-VSENSEmatching V =0.4V 45 mV SS/TR SS/TR-to-referencecrossover 98%nominal 1.15 V SS/TRdischargecurrent(overload) VSENSE=0V,V(SS/TR)=0.4V 382 μA SS/TRdischargevoltage VSENSE=0V 54 mV POWERGOOD(PWRGDPIN) VSENSEfalling 92% V VSENSErising 94% VSEN VSENSEthreshold SE VSENSErising 109% VSENSEfalling 107% Hysteresis VSENSEfalling 2% Outputhighleakage VSENSE=VREF,V(PWRGD)=5.5V,25°C 10 nA Onresistance I(PWRGD)=3mA,VSENSE<0.79V 50 Ω MinimumVINfordefinedoutput V(PWRGD)<0.5V,I(PWRGD)=100μA 0.95 1.5 V Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 6.6 Typical Characteristics W)500 0.816 m e ( c n a sist375 BOOT-PH = 3 V V) 0.808 Re e ( ate enc n-St250 efer 0.800 O BOOT-PH = 6 V R e e c g our olta n-S125 V 0.792 ai Dr c ati St 0 0.784 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C001 C002 V =12V I Figure1.OnResistancevsJunctionTemperature Figure2.VoltageReferencevsJunctionTemperature 7.0 610 V= 12 V I 600 z) 6.5 H k y (590 A nc urrent -6.0 Freque580 Switch C witching 570 S 5.5 560 550 –50 –25 0 25 50 75 100 125 150 5.0 JunctionTemperature (°C) -50 -25 0 25 50 75 100 125 150 C004 V =12V RT=200kΩ I T - Junction Temperature - °C J Figure3.SwitchCurrentLimitvsJunctionTemperature Figure4.SwitchingFrequencyvsJunctionTemperature 2500 500 2000 400 Hz) Hz) witching Frequency (k11050000 witching Frequency (k 230000 S 500 S 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK Resistance (kW) RT/CLK Resistance (kW) C005 C006 VI=12V TJ=25°C VI=12V TJ=25°C Figure5.SwitchingFrequencyvsRT/CLKResistanceHigh Figure6.SwitchingFrequencyvsRT/CLKResistanceLow FrequencyRange FrequencyRange 8 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Typical Characteristics (continued) 120 500 VI= 12 V VI= 12 V 450 100 400 80 V V A/ A/ m m350 m - m - g 60 g 300 40 250 20 200 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure7.EATransconductanceduringSlowStartvs Figure8.EATransconductancevsJunctionTemperature JunctionTemperature 1.40 –3.25 –3.5 V) 1.30 hreshold ( μI(A)(EN)–3.75 T N E 1.20 –4 –4.25 1.10 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C010 C009 VI=12V VI(EN)=Threshold VI=12V +50mV Figure9.ENPinVoltagevsJunctionTemperature Figure10.ENPinCurrentvsJunctionTemperature –0.8 –1 –0.85 –1.5 A) A) μI((EN) –0.9 μI((SS/TR) –2 –0.95 –2.5 –1 –50 –25 0 25 50 75 100 125 150 –3 JunctionTemperature (°C) –50 –25 0 25 50 75 100 125 150 C011 JunctionTemperature (°C) VI=12V VI(EN)=Threshold C012 +50mV VI=12V Figure11.ENPinCurrentvsJunctionTemperature Figure12.SS/TRChargeCurrentvsJunctionTemperature Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Typical Characteristics (continued) 575 100 V= 12 V I 500 80 -Am 425 minal fsw 60 II(SS/TR) 350 % of No 40 275 20 200 0 -50 0 50 100 150 0 0.2 0.4 0.6 0.8 TJ- Junction Temperature - °C VSENSE(V) C014 V =12V T =25°C I J Figure13.SS/TRDischargeCurrentvsJunction Figure14.SwitchingFrequencyvsVSENSE Temperature 2 2 T = 25°C J 1.5 1.5 A) A μ m ( 1 - 1 I(VIN) I(VIN) 0.5 0.5 0 0 –50 –25 0 25 50 75 100 125 150 0 10 20 30 40 JunctionTemperature (°C) C015 VI- Input Voltage - V V =12V I Figure15.ShutdownSupplyCurrentvsJunction Figure16.ShutdownSupplyCurrentvsInputVoltage(VIN) Temperature 210 170 VI= 12 V, T = 25oC, V = 0.83 V J 190 I(VSENSE) VI(VSENSE)= 0.83 V 170 150 Am 150 Am I-(VIN) 130 I-(VIN) 130 110 90 70 110 -50 0 50 100 150 0 10 20 30 40 TJ- Junction Temperature - °C VI- Input Voltage - V Figure17.VINSupplyCurrentvsJunctionTemperature Figure18.VINSupplyCurrentvsInputVoltage 10 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Typical Characteristics (continued) 100 115 VSENSE Rising 80 V)ref110 % of 105 VSENSE Falling W) 60 d ( ON ( shol100 RDS 40 DThre 95 VSENSE Rising G R W 20 P 90 VSENSE Falling 0 85 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C019 C020 V =12V V =12V I I Figure19.PWRGDonResistancevsJunctionTemperature Figure20.PWRGDThresholdvsJunctionTemperature 2.5 3 2.3 2.75 V) ( V) VI(BOOT-PH) 2 V(I(VIN) 2.50 1.8 2.25 1.5 2 –50 –25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 JunctionTemperature (°C) JunctionTemperature (°C) C021 C022 Figure21.BOOT-PHUVLOvsJunctionTemperature Figure22.InputVoltageUVLOvsJunctionTemperature 600 60 V = 0.4 V V= 12 V, (SS/TR) 500 TI= 25oC 50 VI= 12 V J 400 40 V V m m Offset - 300 Offset - 30 200 20 100 10 0 0 0 100 200 300 400 500 600 700 800 -50 -25 0 25 50 75 100 125 150 VSENSE - mV TJ- Junction Temperature - °C Figure23.SS/TRtoVSENSEOffsetvsVsense Figure24.SS/TRtoVSENSEOffsetvsTemperature Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 7 Detailed Description 7.1 Overview The TPS54240 device is a 42-V, 2.5-A, step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant-frequency, current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide-switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switchturnontoafallingedgeofanexternalsystemclock. The TPS54240 has a default startup voltage of approximately 2.5 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating, the device will operate. The operating current is 138 μA when not switching and under no load. When the device is disabled, thesupplycurrentis1.3μA. The integrated 200-mΩ high-side MOSFET allows for high-efficiency power supply designs capable of delivering 2.5 amperes of continuous current to a load. The TPS54240 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54240 can operate at high duty cycles because of the boot UVLO. The output voltage can be stepped down to as low as the 0.8-V reference. The TPS54240 has a power good comparator (PWRGD) which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open drain output which deasserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage allowing the pintotransitionhighwhenapullupresistorisused. The TPS54240 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV powergood comparator. When the OV comparator is activated, the high-side MOSFET is turned off and masked fromturningonuntiltheoutputvoltageislowerthan107%. The SS/TR (slow-start / tracking) pin is used to minimize inrush currents or provide power supply sequencing during power-up. A small value capacitor should be coupled to the pin to adjust the slow-start time. A resistor dividercanbecoupledtothepinforcriticalpowersupplysequencingrequirements.TheSS/TRpinisdischarged before the output powers up. This discharging ensures a repeatable restart after an over-temperature fault, UVLOfaultoradisabledcondition. The TPS54240, also, discharges the slow-start capacitor during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startupandovercurrentfaultconditionstohelpcontroltheinductorcurrent. 12 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 7.2 Functional Block Diagram PWRGD EN VIN 6 3 2 Shutdown Thermal Shutdown UVLO Enable UV Logic Comparator Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Minimum Boot Reference Clamp UVLO Current Pulse Sense ERROR Skip AMPLIFIER PWM VSENSE 7 Comparator 1 BOOT SS/TR 4 Logic And PWM Latch Shutdown Slope Compensation COMP 8 10PH 11 POWERPAD Frequency Shift Overload Maximum Recovery Clamp Oscillator TPS54240Block Diagram 9 GND with PLL 5 RT/CLK 7.3 Feature Description 7.3.1 FixedFrequencyPWMControl The TPS54240 uses an adjustable fixed frequency, peak current mode control. The output voltage is compared through external resistors on the VSENSE pin to an internal voltage reference by an error amplifier which drives the COMP pin. An internal oscillator initiates the turn on of the high-side power switch. The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximumlevel.TheEco-ModeisimplementedwithaminimumclampontheCOMPpin. 7.3.2 SlopeCompensationOutputCurrent The TPS54240 adds a compensating ramp to the switch current signal. This slope compensation prevents sub- harmonicoscillations.Theavailablepeakinductorcurrentremainsconstantoverthefulldutycyclerange. 7.3.3 PulseSkipEco-Mode The TPS54240 operates in a pulse skip Eco-Mode at light load currents to improve efficiency by reducing switching and gate drive losses. The TPS54240 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-Mode. This current threshold is the current level corresponding to a nominal COMP voltage or 500mV. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) WheninEco-Mode,theCOMPpinvoltageisclampedat500mVandthehigh-sideMOSFETisinhibited.Further decreasesinloadcurrentorinoutputvoltagecannotdrivetheCOMPpinbelowthisclampvoltagelevel. Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates forthefallingoutputvoltage,theCOMPpinvoltagebeginstorise.Atthistime,thehigh-sideMOSFETisenabled andaswitchingpulseinitiatesonthenextswitchingcycle.ThepeakcurrentissetbytheCOMPpinvoltage.The output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually fallsbelowtheEco-ModethresholdatwhichtimethedeviceagainentersEco-Mode. For Eco-Mode operation, the TPS54240 senses peak current, not average or load current, so the load current where the device enters Eco-Mode is dependent on the output inductor value. For example, the circuit in Figure 49 enters Eco-Mode at about 5 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 138-μA input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse skip mode, the switchingtransitionsoccursynchronouslywiththeexternalclocksignal. 7.3.4 LowDropoutOperationandBootstrapVoltage(BOOT) The TPS54240 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 10 V or higher is recommended becauseofthestablecharacteristicsovertemperatureandvoltage. To improve drop out, the TPS54240 is designed to operate at 100% duty cycle as long as the BOOT to PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V, the high-side MOSFET is turnedoffusinganUVLOcircuitwhichallowsthelow-sidediodetoconductandrefreshthechargeontheBOOT capacitor. Since the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor, thus the effective duty cycle of the switchingregulatorishigh. The effective duty cycle during dropout of the regulator is mainly influenced by the voltage drops across the power MOSFET, inductor resistance, low-side diode and printed circuit board resistance. During operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT to PH voltagefallsbelow2.1V. Take care of maximum duty cycle applications which experience extended time periods with light loads or no load.WhenthevoltageacrosstheBOOTcapacitorfallsbelowthe2.1-VUVLOthreshold,thehigh-sideMOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1 V. The output capacitor then decays until the difference in the input voltage and output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the BOOTUVLOtriggerconditionattheminimumloadoftheapplicationusingtheadjustableVINUVLOfeaturewith resistorsontheENpin. The start and stop voltages for typical 3.3-V and 5-V output applications are shown in Figure 25 and Figure 26. The voltages are plotted versus load current. The start voltage is defined as the input voltage needed to regulate the output within 1%. The stop voltage is defined as the input voltage at which the output drops by 5% or stops switching. During high-duty cycle conditions, the inductor current ripple increases while the BOOT capacitor is being recharged resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot capacitorbeinglongerthanthetypicalhigh-sideoff-timewhenswitchingoccurseverycycle. 14 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) 4 5.6 3.8 5.4 V) V) ge ( 3.6 Start ge ( 5.2 Start a a olt olt V V ut 3.4 Stop ut 5 p p n n I I Stop 3.2 4.8 3 4.6 0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20 Output Current (A) Output Current (A) C025 C026 V =3.3V V =5V O O Figure25.3.3VStart/StopVoltage Figure26.5.0VStart/StopVoltage 7.3.5 ErrorAmplifier The TPS54240 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (g ) of the error amplifier is 310 μA/V during normal operation. During the slow-start operation, M thetransconductanceisafractionofthenormaloperatinggm.WhenthevoltageoftheVSENSEpinisbelow0.8 VandthedeviceisregulatingusingtheSS/TRvoltage,thegmis70 μA/V. The frequency compensation components (capacitor, series resistor and capacitor) are added to the COMP pin toground. 7.3.6 VoltageReference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output ofatemperaturestablebandgapcircuit. 7.3.7 AdjustingTheOutputVoltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using 1%toleranceorbetterdividerresistors.Startwitha10-kΩ fortheR2resistorandusetheEquation1tocalculate R1. To improve efficiency at light loads, consider using larger value resistors. If the values are too high, the regulatorwillbemoresusceptibletonoiseandvoltageerrorsfromtheVSENSEinputcurrentwillbenoticeable. æVout - 0.8Vö R1=R2 ´ ç ÷ è 0.8V ø (1) 7.3.8 EnableAndAdjustingUndervoltageLockout The TPS54240 is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 27 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation it is highly recommended to provide consistent power-up behavior. The EN pin has an internal pullup current source, I1, of 0.9 μA that provides the default condition of the TPS54240 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the inputstartvoltage. spacer Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) TPS54240 VIN Ihys I1 R1 0.9mA 2.9mA + R2 EN 1.25 V - Figure27. AdjustableUndervoltageLockout(UVLO) V -V R1= START STOP I HYS (2) V R2= ENA V -V START ENA +I R1 1 (3) Another technique to add input voltage hysteresis is shown in Figure 28. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sourcesadditionalhysteresiscurrentintotheENpin. spacer TPS54240 VIN Ihys R1 I1 2.9mA 0.9mA + R2 EN 1.25 V - VOUT R3 Figure28. AddingAdditionalHysteresis V -V R1= START STOP V I + OUT HYS R3 (4) V R2= ENA V -V V START ENA +I - ENA R1 1 R3 (5) 16 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) 7.3.9 Slow-Start/TrackingPin(SS/TR) The TPS54240 effectively uses the lower voltage of the internal voltage reference, or the SS/TR pin voltage as the power supply's reference voltage, and regulates the output accordingly. A capacitor on the SS/TR pin-to- ground implements a slow start time. The TPS54240 has an internal pullup current source of 2 μA that charges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6. The voltage reference (V ) is 0.8 V and the slow start current (I ) is 2 μA. The slow-start capacitor should REF SS remainlowerthan0.47μFandgreaterthan0.47nF. Tss(ms) ´ Iss(mA) Css(nF)= Vref(V) ´ 0.8 (6) At power-up, the TPS54240 will not start switching until the slow-start pin is discharged to less than 40 mV. To ensureaproperpowerup,seeFigure29. Also, during normal operation, the TPS54240 will stop switching and the SS/TR must be discharged to 40 mV. WhentheVINUVLOisexceeded,theENpinmustbepulledbelow1.25V,orathermalshutdowneventoccurs. The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure23).TheSS/TRvoltagewillramplinearlyuntilclampedat1.7V. spacer EN SS/TR V SENSE VOUT Figure29. OperationofSS/TRPinWhenStarting 7.3.10 OverloadRecoveryCircuit The TPS54240 has an overload recovery (OLR) circuit. The OLR circuit will slow start the output from the overload voltage to the nominal regulation voltage once the fault condition is removed. The OLR circuit will discharge the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of 382 μA when the error amplifier is changed to a high voltage from a fault condition. When the fault condition is removed,theoutputwillslowstartfromthefaultvoltagetonominaloutputvoltage. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) 7.3.11 Sequencing Many of the common power supply sequencing methods can be implemented using the SS/TR, EN and PWRGD pins. The sequential method can be implemented using an open-drain output of a power on reset pin of another device. The sequential method is illustrated in Figure 30 using two TPS54240 devices. The powergood is coupled to the EN pin on the TPS54240, which will enable the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supply will provide a 1-msstartupdelay.Figure31showstheresultsofFigure30. TPS54240 PWRGD EN EN SS/TR SS/TR PWRGD Figure30. SchematicforSequentialStartupSequence EN1 PWRGD1 VOUT1 VOUT2 Figure31. SequentialStartupUsingENandPWRGD 18 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) TTPPSS5544126400 3 EN 4 SS/TR 6 PWRGD TTPPSS5544126400 3 EN 4 SS/TR 6 PWRGD Figure32. SchematicforRatio-metricStartupSequence EN1, EN2 VOUT1 VOUT2 Figure33. Ratio-metricStartupUsingCoupledSS/TRPins Figure 32 shows a method for ratio-metric start up sequence by connecting the SS/TR pins together. The regulator outputs will ramp up and reach regulation at the same time. When calculating the slow-start time, the pullupcurrentsourcemustbedoubledinEquation6.Figure33showstheresultsofFigure32. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) TPS54240 EN VOUT1 SS/TR PWRGD TPS54240 EN VOUT2 R1 SS/TR R2 PWRGD R3 R4 Figure34. SchematicforRatio-metricandSimultaneousStartupSequence Ratio-metric and simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in Figure 34 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 7 and Equation 8, the tracking resistors can be calculated to initiate the Vout2 slightly before, after, or at the same time as Vout1. Equation 9 is the voltage difference between Vout1 and Vout2atthe95%ofnominaloutputregulation. The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE, offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (ISS) and trackingresistors,theVssoffsetandIssareincludedasvariablesintheequations. To design a ratio-metric startup in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reachesregulation,useanegativenumberinEquation7throughEquation9fordeltaV.Equation9 willresultina positivenumberforapplicationswhichtheVout2isslightlylowerthanVout1whenVout2regulationisachieved. Since the SS/TR pin must be pulled below 40 mV before starting after an EN, UVLO or thermal shutdown fault, careful selection of the tracking resistors is needed to ensure the device will restart after a fault. Make sure the calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the device can recoverfromafault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage the Vssoffset becomes larger as the slow-start circuits gradually hands off the regulation reference to the internal voltage reference. The SS/TR pin voltage needs to be greater than 1.3 V for a complete handoff to the internal voltage reference as showninFigure23. Vout2+deltaV Vssoffset R1= ´ VREF Iss (7) VREF ´ R1 R2= Vout2+deltaV - VREF (8) deltaV=Vout1 - Vout2 (9) R1>2800 ´ Vout1 - 180 ´ deltaV (10) 20 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) EN EN VOUT1 VOUT1 VOUT2 VOUT2 Figure35.Ratio-metricStartupWithTrackingResistors Figure36.Ratio-metricStartupWithTrackingResistors EN VOUT1 VOUT2 Figure37.SimultaneousStartupWithTrackingResistor Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) 7.3.12 ConstantSwitchingFrequencyandTimingResistor(RT/CLKPin) The switching frequency of the TPS54240 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor- to-ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 11 or the curves in Figure 38 or Figure 39. To reduce the solution size, one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimumcontrollableontimeshouldbeconsidered. Theminimumcontrollableontimeistypically135nsandlimitsthemaximumoperatinginputvoltage. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of themaximumswitchingfrequencyislocatedbelow. 206033 RT (kOhm)= ¦sw (kHz)1.0888 (11) 2500 500 V= 12 V, I T = 25°C J Hz 2000 z) 400 k H ency - 1500 ncy (k 300 u e q u e q hing Fr 1000 ng Fre 200 Switc witchi f- s 500 S 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK - Clock Resistance - kW RT/CLK Resistance (kW) C006 V =12V T =25°C I J Figure38.HighRangeRT Figure39.LowRangeRT 7.3.13 OvercurrentProtectionandFrequencyShift The TPS54240 implements current mode control which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To increase the maximum operating switching frequency at high-input voltages, the TPS54240 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSEpin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Since the device can only divide the switching frequency by 8, there is a maximum inputvoltagelimitinwhichthedeviceoperatesandstillhavefrequencyshiftprotection. Duringshort-circuitevents(particularlywithhigh-inputvoltageapplications),thecontrolloophasafiniteminimum controllable on time and the output has a low voltage. During the switch-on time, the inductor current ramps to the peak current limit because of the high-input voltage and minimum on time. During the switch-off time, the inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the ramp- upamount.Thefrequencyshifteffectivelyincreasestheoff-timeallowingthecurrenttorampdown. 22 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) 7.3.14 SelectingtheSwitchingFrequency The switching frequency that is selected should be the lower value of the two equations, Equation 12 and Equation13.Equation12isthemaximumswitchingfrequencylimitationsetbytheminimumcontrollableon-time. Settingtheswitchingfrequencyabovethisvaluewillcausetheregulatortoskip-switchingpulses. Equation 13 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high-input voltages, the switching frequency should be set to be less than the f frequency. In Equation 13, to calculate the maximum switching frequency one must take into account SW(maxshift) that the output voltage decreases from the nominal voltage to 0 volts, the fdiv integer increases from 1 to 8, correspondingtothefrequencyshift. In Figure 40, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.130-Ω, MOSFET on resistance of 0.2 Ω and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet, or use the WEBENCH design software to determine the switching frequency. fSW(maxskip)=æçt1 ö÷´æçç(I(LV´ -RIdc´+VROhUsT++VVdd))ö÷÷ è ONø è IN L ø (12) fdiv æ(I ´Rdc+V +Vd)ö fSW(shift)= t ´çç L(V -I xORUhTsSC+Vd) ÷÷ ON è IN L ø (13) I inductorcurrent L Rdc inductorresistance V maximuminputvoltage IN V outputvoltage OUT V outputvoltageduringshort OUTSC Vd diodevoltagedrop R switchonresistance DS(on) t controllableontime ON ƒ frequencydivideequals(1,2,4,or8) DIV 2500 V = 3.3 V O Hz 2000 y - k Shift c n ue 1500 q Fre Skip g n hi 1000 c wit S - fs 500 0 10 20 30 40 VI- Input Voltage - V Figure40. MaximumSwitchingFrequencyvs.InputVoltage Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) 7.3.15 HowtoInterfacetoRT/CLKPin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 41. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 nS and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal.Theexternalsynchronizationcircuitshouldbedesignedinsuchawaythatthedevicewillhavethedefault frequency set resistor connected from the RT/CLK pin-to-ground should the synchronization signal turn-off. It is recommended to use a frequency set resistor connected as shown in Figure 41 through a 50-Ω resistor-to- ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends AC-coupling the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold, the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decreasetheswitchingfrequencyuntilthePLLlocksontotheCLKfrequencywithin100microseconds. When the device transitions from the PLL to resistor mode, the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 42, Figure 43 and Figure 44 show the device synchronized to an external system clockincontinuousconductionmode(CCM)discontinuousconduction(DCM)andpulseskipmode(PSM). TPS54240 10 pF 4 kW PLL R fset EXT RT/CLK Clock 50W Source Figure41. SynchronizingtoaSystemClock 24 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) PH PH EXT EXT IL IL Figure42.PlotofSynchronizinginCCM Figure43.PlotofSynchronizinginDCM PH EXT IL Figure44.PlotofSynchronizinginPSM 7.3.16 Powergood(PWRGDPin) The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference, the PWRGD pin is de-asserted and the pin floats. TI recommends using a pullup resistor between the values of 10 and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V but with reduced current sinking capability. The PWRGD will achievefullcurrentsinkingcapabilityasVINinputvoltageapproaches3V. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) ThePWRGDpinispulledlowwhentheVSENSEislowerthan92%orgreaterthan109%ofthenominalinternal reference voltage. Also, the PWRGD is pulled low, if the UVLO or thermal shutdown are asserted or the EN pin pulledlow. 7.3.17 OvervoltageTransientProtection The TPS54240 incorporates an overvoltage transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low-value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage, thus requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond, this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low-value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVTP threshold,thehigh-sideMOSFETisdisabled,preventingcurrentfromflowingtotheoutputandminimizingoutput overshoot. When the VSENSE voltage drops lower than the OVTP threshold, the high-side MOSFET is allowed toturnonatthenextclockcycle. 7.3.18 ThermalShutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power-up sequence bydischargingtheSS/TRpin. 7.3.19 SmallSignalModelforLoopResponse Figure45showsanequivalentmodelfortheTPS54240controlloopwhichcanbemodeledinacircuitsimulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 310 μA/V. The error amplifier can be modeled using an ideal voltage controlled current EA source. The resistor R and capacitor C model the open-loop gain and frequency response of the amplifier. The o o 1-mV AC voltage source between the nodes A and B effectively breaks the control loop for the frequency response measurements. Plotting C/A shows the small signal response of the frequency compensation. Plotting A/B shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing R with a current source with the appropriate load step amplitude and ste- rate in a time domain L analysis.Thisequivalentmodelisonlyvalidforcontinuousconductionmodedesigns. 26 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) PH V Power Stage O gm 10.5A/V ps a b R1 RESR COMP RL c VSENSE C 0.8 V OUT CO RO R3 gm ea C2 350mA/V R2 C1 Figure45. SmallSignalModelforLoopResponse 7.3.20 SimpleSmallSignalModelforPeakCurrentModeControl Figure 46 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54240 power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 14 and consists of a DC gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node C in Figure 45) is the power stage transconductance. The gm for the TPS54240 is 10.5 A/V. The low-frequency gain of the power stage PS frequencyresponseistheproductofthetransconductanceandtheloadresistanceasshowninEquation15. Astheloadcurrentincreasesanddecreases,thelow-frequencygaindecreasesandincreases,respectively.This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 16). The combined effect is highlighted by the dashed line in the right half of Figure 46. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases fromtheESRzeroatthelowerfrequencies(seeEquation17). Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) V O VC Adc R ESR fp R L gm ps C OUT fz Figure46. SimpleSmallSignalModelandFrequencyResponseforPeakCurrentModeControl æ s ö ç1+ ÷ VOUT = Adc´è 2p´fZ ø V æ s ö C ç1+ ÷ è 2p´fP ø (14) Adc=gm ´ R ps L (15) 1 f = P C ´R ´2p OUT L (16) 1 f = Z C ´R ´2p OUT ESR (17) 7.3.21 SmallSignalModelforFrequencyCompensation The TPS54240 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 47. Type 2 circuits most likely implemented in high-bandwidth, power supply designs using low- ESR output capacitors. The Type 1 circuit is used with power supply designs with high-ESR aluminum electrolytic or tantalum capacitors.. Equation 18 and Equation 19 show how to relate the frequency response of theamplifiertothesmallsignalmodelinFigure47.Theopen-loopgainandbandwidtharemodeledusingtheR O and C shown in Figure 47. See Application Information for a design example using a Type 2A network with a O low-ESRoutputcapacitor. Equation 18 through Equation 27 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the Application InformationandImplementationsectionoruseswitchedinformation. 28 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 Feature Description (continued) V O R1 VSENSE gm Type 2A Type 2B Type 1 ea COMP Vref R3 C2 R3 R2 RO CO C2 C1 C1 Figure47. TypesofFrequencyCompensation Aol P1 A0 Z1 P2 A1 BW Figure48. FrequencyResponseoftheType2AandType2BFrequencyCompensation Aol(V/V) Ro= gm ea (18) gm C = ea O 2p ´ BW (Hz) (19) æ s ö ç1+ ÷ è 2p´fZ1ø EA = A0´ æ s ö æ s ö ç1+ ÷´ç1+ ÷ è 2p´fP1ø è 2p´fP2 ø (20) R2 A0=gm ´ Ro ´ ea R1+R2 (21) R2 A1=gm ´ Ro||R3 ´ ea R1+R2 (22) 1 P1= 2p´Ro´C1 (23) Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com Feature Description (continued) 1 Z1= 2p´R3´C1 (24) 1 P2= type2a 2p ´ R3||R ´ (C2+C ) O O (25) 1 P2= type2b 2p ´ R3||R ´ C O O (26) 1 P2 = type 1 2p ´ R ´ (C2 + C ) O O (27) 7.4 Device Functional Modes 7.4.1 OperationNearMinimumVIN(V =<3.5V) (VIN) The TPS54240 is designed to operate with input voltage above 3.5 V. The typical VIN UVLO threshold is 2.5 V and the device may operate at input voltages down to the UVLO voltage. At input voltages below the UVLO voltage, the device does not switch. If an external resistor divider pulls the EN pin up to VIN or the EN pin is floating, when VIN passes the UVLO threshold the device becomes active. When the device is active, switching begins and the soft-start sequence initiates. The TPS54240 ramps up the output voltage at the soft-start time determinedbytheexternalcapacitanceontheSS/TRpin. 7.4.2 OperationWithENControl The enabled threshold voltage is 1.2 V typical. With EN held below the threshold voltage the device is shut down and switching is inhibited even if the VIN voltage is above its UVLO threshold. The IC quiescent current decreases to a minimum in this state. If the EN pin voltage is increased above its threshold while the VIN voltage is also above its UVLO threshold, the device becomes active. When the device is active, switching begins and the soft-start sequence initiates. The TPS54240 ramps up the output voltage at the soft-start time determined by theexternalcapacitanceontheSS/TRpin. 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54240 device is a 42-V, 2.5-A, step-down regulator with an integrated high-side MOSFET. This device typically converts a higher DC voltage to a lower DC voltage with a maximum available output current of 2.5 A. Example applications are 12-V and 24-V industrial, automotive and communication power systems. Use the following design procedure to select component values for the TPS54240 device. This procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. The Excel™ spreadsheet (SLVC432) located on the product page can help on all calculations. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensivedatabaseofcomponentswhengeneratingadesign. 30 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 8.2 Typical Application 8.2.1 TPS542403.3-VOutputDesign TPS54240DGQ Figure49. 3.3-VOutputTPS54240DesignExample 8.2.1.1 DesignRequirements This example details the design of a high-frequency switching regulator design using ceramic output capacitors. Afewparametersmustbeknowninordertostartthedesignprocess.Theseparametersaretypicallydetermined atthesystemlevel.Forthisexample,wewillstartwiththefollowingknownparameters: DESIGNPARAMETERS VALUE OutputVoltage 3.3V TransientResponse0to1.5-Aloadstep ΔVout=3% MaximumOutputCurrent 2.5A InputVoltage 12Vnom.10.8Vto13.2V OutputVoltageRipple 1%ofVout StartInputVoltage(risingVIN) 6.25V StopInputVoltage(fallingVIN) 5.9V 8.2.1.2 DetailedDesignProcedure 8.2.1.2.1 SelectingtheSwitchingFrequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high-switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switchesatalowerfrequency.Theswitchingfrequencythatcanbeselectedislimitedbytheminimumon-timeof theinternalpowerswitch,theinputvoltageandtheoutputvoltageandthefrequencyshiftlimitation. Equation 12 and Equation 13 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping orthelackofovercurrentprotectionduringashortcircuit. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com The typical minimum on time, t , is 135 ns for the TPS54240. For this example, the output voltage is 3.3 V onmin and the maximum input voltage is 13.2 V, which allows for a maximum switch frequency up to 2247 kHz when including the inductor resistance, on resistance output current and diode voltage in Equation 12. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 13 or the solid curve in Figure 40 to determine the maximum switching frequency. With a maximum input voltage of 13.2 V, assuming a diode voltage of 0.7 V, inductor resistance of 26 mΩ, switch resistance of 200 mΩ, a current limit value of 3.5 A andashortcircuitoutputvoltageof0.2V.Themaximumswitchingfrequencyisapproximately4449kHz. For this design, a much lower switching frequency of 300 kHz is used. To determine the timing resistance for a givenswitchingfrequency,useEquation11orthecurveinFigure39. The switching frequency is set by resistor R3 shown in Figure 49 For 300-kHz operation a 412-kΩ resistor is required. 8.2.1.2.2 OutputInductorSelection(L ) O Tocalculatetheminimumvalueoftheoutputinductor,useEquation28. K isacoefficientthatrepresentstheamountofinductorripplecurrentrelativetothemaximumoutputcurrent. IND The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high-inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion ofthedesigner;however,thefollowingguidelinesmaybeused. For designs using low ESR output capacitors such as ceramics, a value as high as K = 0.3 may be used. IND When using higher ESR output capacitors, K = 0.2 yields better results. Since the inductor ripple current is IND part of the PWM control system, the inductor ripple current should always be greater than 150 mA for dependable operation. In a wide-input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use K = 0.3 and the minimum inductor value is calculated to be 11 μH. For this IND design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation30andEquation31. For this design, the RMS inductor current is 2.51 A and the peak inductor current is 2.913 A. The chosen inductor is a Coilcraft MSS1038-103NLB . It has a saturation current rating of 4.52 A and an RMS current rating of4.05A. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of theregulatorbutallowforalowerinductancevalue. The current flowing through the inductor is the inductor ripple current plus the output current. During power-up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitchcurrentlimitratherthanthepeakinductorcurrent. Vinmax - Vout Vout Lomin= ´ Io ´ K Vinmax ´ ƒsw IND (28) IRIPPLE = VOUVTin´ma(xVin´mLaOx ´-fSVWOUT) (29) 2 I = (I )2 + 1 ´æçVOUT ´ (Vinmax - VOUT)ö÷ L(rms) O 12 ç Vinmax ´ L ´ f ÷ è O SW ø (30) Iripple ILpeak = Iout+ 2 (31) 32 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 8.2.1.2.3 OutputCapacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in loadcurrent.Theoutputcapacitanceneedstobeselectedbasedonthemorestringentofthesethreecriteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance necessarytoaccomplishthis. Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 3% changeinVoutforaloadstepfrom1.5Ato2.5A(fullload).Forthisexample, ΔIout=2.5-1.5=1.0Aand ΔVout = 0.03 × 3.3 = 0.099 V. Using these numbers gives a minimum capacitance of 67 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESRthatshouldbetakenintoaccount. The catch diode of the regulator cannot sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 50. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 33 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, I is the output current under heavy load, I is the output under light load, Vf is the OH OL final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 2.5 A to 1.5 A. The output voltage will increase during this load transition and the stated maximum in our specification is 3 % of the output voltage. This will make Vf = 1.03 × 3.3 = 3.399 V. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 33 yields a minimum capacitanceof60μF. Equation 34 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, V is the maximum allowable output voltage ripple, and I is the oripple ripple inductorripplecurrent.Equation34yields12 μF. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification.Equation35indicatestheESRshouldbelessthan36mΩ. The most stringent criteria for the output capacitor is 67 μF of capacitance to keep the output voltage in regulationduringanloadtransient. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which will increase this minimum value. For this example, 2 x 47-μF, 10-V ceramic capacitors with 3 mΩ of ESR will be used. The deratedcapacitanceis72.4µF,abovetheminimumrequiredcapacitanceof67µF. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRootMeanSquare(RMS)valueofthemaximumripplecurrent.Equation36 canbeused to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 36 yields 238mA. 2 ´ DIout Cout> ¦sw ´ DVout (32) Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com (Ioh2 - Iol2) Cout>Lo ´ (V¦2 -Vi2) (33) 1 1 Cout> ´ 8 ´¦sw VORIPPLE I RIPPLE (34) V R < ORIPPLE ESR I RIPPLE (35) Vout ´ (Vinmax - Vout) Icorms= 12 ´ Vinmax ´ Lo ´ ¦sw (36) 8.2.1.2.4 CatchDiode The TPS54240 requires an external catch diode between the PH pin and GND. The selected diode must have a reversevoltageratingequaltoorgreaterthanVinmax.Thepeakcurrentratingofthediodemustbegreaterthan the maximum inductor current. The diode should also have a low-forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low-forward voltage. The lower the forward voltage of the diode, the highertheefficiencyoftheregulator. Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Although the design example has an input voltage up to 13.2 V, a diode with a minimum of 60-V reverse voltage isselected. For the example design, the B360B-13-F Schottky diode is selected for its lower-forward voltage and it comes in a larger package size which has good thermal characteristics over small devices. The typical forward voltage of theB360B-13-Fis0.70volts. The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the AC losses of the diode need to be taken into account. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 37 is used to calculate the total powerdissipation,conductionlossesplusSClosses,ofthediode. The B360B-13-F has a junction capacitance of 200 pF. Using Equation 37, the selected diode will dissipate 1.32 Watts. If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diodewhichhasalowleakagecurrentandslightlyhigher-forwardvoltagedrop. 2 (Vinmax - Vout) ´ Iout ´ Vƒd Cj ´ ƒsw ´ (Vin+ Vƒd) Pd= + Vinmax 2 (37) 8.2.1.2.5 InputCapacitor The TPS54240 requires a high-quality ceramic, type X5R or X7R, input-decoupling capacitor of at least 3 μF of effective capacitance, and in some applications, a bulk capacitance. The effective capacitance includes any DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54240. TheinputripplecurrentcanbecalculatedusingEquation38. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power-regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias taken into account. The capacitance value of a capacitor decreasesastheDCbiasacrossacapacitorincreases. 34 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V or 100 V, so a 100-V capacitor should be selected. For this example, two 2.2-μF, 100-V capacitors in parallel have been selected. Table 1 shows a selection of high voltage capacitors. The input capacitance value determinestheinputripplevoltageoftheregulator.TheinputvoltageripplecanbecalculatedusingEquation39. Usingthedesignexamplevalues,Ioutmax=2.5A,Cin=4.4 μF, ƒsw=300kHz,yieldsaninputvoltagerippleof 206mVandarmsinputripplecurrentof1.15A. Vout (Vinmin - Vout) Icirms=Iout ´ ´ Vinmin Vinmin (38) Ioutmax ´ 0.25 ΔVin= Cin ´ ¦sw (39) Table1.CapacitorTypes VENDOR VALUE(μF) EIASize VOLTAGE DIALECTRIC COMMENTS 1.0to2.2 100V 1210 GRM32series 1.0to4.7 50V Murata 1.0 100V 1206 GRM31series 1.0to2.2 50V 1.0101.8 50V 2220 1.0to1.2 100V Vishay VJX7Rseries 1.0to3.9 50V 2225 1.0to1.8 100V X7R 1.0to2.2 100V 1812 CseriesC4532 1.5to6.8 50V TDK 1.0.to2.2 100V 1210 CseriesC3225 1.0to3.3 50V 1.0to4.7 50V 1210 1.0 100V AVX X7Rdielectricseries 1.0to4.7 50V 1812 1.0to2.2 100V 8.2.1.2.6 Slow-StartCapacitor The slow-start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power-up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54240 reach the current limit or excessive current draw from the input power supply may cause the input voltagerailtosag.Limitingtheoutputvoltageslewratesolvesbothoftheseproblems. The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 40 can be used to find the minimum slow-start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow-start current of Issavg. In the example, to charge the effective output capacitance of 72.4 µF up to 3.3 V whileonlyallowingtheaverageoutputcurrenttobe1Awouldrequirea0.19-msslow-starttime. Once the slow-start time is known, the slow-start capacitor value can be calculated using Equation 6. For the example circuit, the slow-start time is not too critical since the output capacitor value is 2 x 47 μF which does not require much current to charge to 3.3 V. The example circuit has the slow start-time set to an arbitrary value of 3.5 ms which requires a 8.75 nF slow-start capacitor. For this design, the next larger standard value of 10 nF is used. Cout ´ Vout ´ 0.8 tss> Issavg (40) Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 8.2.1.2.7 BootstrapCapacitorSelection A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or highervoltagerating. 8.2.1.2.8 UndervoltageLockOutSetPoint The Undervoltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54240. The UVLO has two thresholds, one for power-up when the input voltage is rising, and one for power- downorbrownoutswhentheinputvoltageisfalling.Fortheexampledesign,thesupplyshouldturnonandstart switching once the input voltage increases above 6.25 V (enabled). After the regulator starts switching, it should continuetodosountiltheinputvoltagefallsbelow5.9V (UVLOstop). The programmable UVLO and enable voltages are set using the resistor divider of R1 and R2 between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 124 kΩ between Vin and EN (R1) and a 30.1 kΩ between EN and ground (R2) arerequiredtoproducethe6.25and5.9voltstartandstopvoltages. 8.2.1.2.9 OutputVoltageAndFeedbackResistorsSelection The voltage divider of R5 and R6 is used to set the output voltage. For the example design, 10.0 kΩ was selected for R6. Using Equation 1, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease quiescent current and improve efficiency at low-output currentsbutmayintroducenoiseimmunityproblems. 8.2.1.2.10 Compensation There are several methods used to compensate DC - DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. This method assumes the cross-over frequency is between the modulator pole and the ESRzeroandtheESRzeroisatleast10timesgreaterthemodulatorpole.UseSwitcherProsoftwareforamore accuratedesign. To get started, the modulator pole, fpmod, and the ESR zero, fz1 must be calculated using Equation 41 and Equation 42. For Cout, use a derated value of 40 μF. Use equations Equation 43 and Equation 44, to estimate a starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is 1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and Equation44gives13.4kHz.UsethelowervalueofEquation43 orEquation44foraninitialcrossoverfrequency. For this example, a higher fco is desired to improve transient response. the target fco is 35.0 kHz. Next, the compensation components are calculated. A resistor-in-series with a capacitor is used to create a compensating zero.Acapacitorinparalleltothesetwocomponentsformsthecompensatingpole. Ioutmax ¦pmod= 2×p ×Vout×Cout (41) 1 ¦zmod= 2 ´ p ´ Resr×Cout (42) f = f mod´ f mod co p z (43) f f = f mod´ sw co p 2 (44) To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance, gmps, is 10.5 A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 310 μA/V, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20.0 kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 4740 pF forcompensatingcapacitorC5,a4700pFisusedforthisdesign. 36 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 æ2´p´ f ´C ö æ V ö R4=ç co out ÷´ç out ÷ è gmps ø èVref´gmeaø (45) 1 C5= 2´p´R4´ f mod p (46) A compensation pole can be implemented if desired using an additional capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value of Equation 47 and Equation 48 to calculate the C8, to set the compensationpole.C8isnotusedforthisdesignexample. C ´Resr C8= o R4 (47) 1 C8= R4´ f ´p sw (48) 8.2.1.2.11 DiscontinuousModeAndEco-ModeBoundary With an input voltage of 12 V, the power supply enters discontinuous mode when the output current is less than 337mA.ThepowersupplyentersEco-Modewhentheoutputcurrentislowerthan5mA. Theinputcurrentdrawatnoloadis392μA. 8.2.1.2.12 PowerDissipationEstimate The following formulas show how to estimate the IC power dissipation under continuous conduction mode (CCM) operation.Theseequationsshouldnotbeusedifthedeviceisworkingindiscontinuousconductionmode(DCM). The power dissipation of the IC includes conduction loss (Pcon), switching loss (Psw), gate drive loss (Pgd) and supplycurrent(Pq). Vout Pcon=Io2 ´ R ´ DS(on) Vin (49) Psw=Vin2 ´ ¦sw ´ lo ´ 0.25 ´ 10-9 (50) Pgd=Vin ´ 3 ´ 10-9´¦sw (51) Pq=116 ´ 10-6 ´Vin (52) Where: Ioutistheoutputcurrent(A). R istheon-resistanceofthehigh-sideMOSFET(Ω). DS(on) Voutistheoutputvoltage(V). Vinistheinputvoltage(V). fswistheswitchingfrequency(Hz). So Ptot=Pcon+Psw +Pgd+Pq (53) ForgivenT , A TJ=TA+Rth ´ Ptot (54) ForgivenT =150°C JMAX TAmax=TJmax - Rth ´ Ptot (55) Where: Ptotisthetotaldevicepowerdissipation(W). T istheambienttemperature(°C). A T isthejunctiontemperature(°C). J Rthisthethermalresistanceofthepackage(°C/W). T ismaximumjunctiontemperature(°C). JMAX T ismaximumambienttemperature(°C). AMAX Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com There will be additional power losses in the regulator circuit due to the inductor AC and DC losses, the catch diodeandtraceresistancethatwillimpacttheoverallefficiencyoftheregulator. 8.2.1.3 ApplicationCurves Vout = 50 mv / div (ac coupled) Vin = 10 V / div Vout = 2 V / div Output Current = 1A/ div (Load Step 1.5Ato 2.5A) EN = 2 V / div SS/TR = 2 V / div Time = 200 usec / div Time = 5 msec / div Figure50.LoadTransient Figure51.StartupWithVIN Vout = 20 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 2 usec / div Time = 2 usec / div Figure52.OutputRipple,CCM Figure53.OutputRipple,DCM Vin = 200 mV / div (ac coupled) Vout = 20 mV / div (ac coupled) PH = 5 V / div PH = 5 V / div Time = 10 usec / div Time = 2 usec / div Figure54.OutputRipple,PSM Figure55.InputRipple,CCM 100 90 Vin = 50 mV / div (ac coupled) 80 70 %60 PH = 5 V / div Efficiency - 4500 30 20 VVIONU=T1=23V.3V fsw=300kHz 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 Time = 2 usec / div IO- Output Current -A Figure56.InputRipple,DCM Figure57.EfficiencyvsLoadCurrent 38 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 100 60 180 90 80 40 120 Phase 70 20 60 % 60 Gain Efficiency - 4500 Gain - dB 0 0 oPhase - -20 -60 30 VIN=12V 20 VOUT=3.3V VIN=12 V fsw=300kHz -40 VOUT=3.3V -120 10 IOUT=2.5A 0 -60 -180 0.001 0.01 0.1 10 100 1-103 1-104 1-105 1-106 IO- Output Current -A f - Frequency - Hz Figure58.LightLoadEfficiency Figure59.OverallLoopFrequencyResponse 3.4 3.4 3.38 3.38 - Output Voltage - VO33..3346 -Output Voltage - V33..3346 V O V VIN=12V 3.32 3.32 VOUT=3.3V VIN=12V fsw=300kHz VOUT=3.3V IOUT=1.5A fsw=300kHz 3.3 3.3 0 0.5 1.0 1.5 2.0 2.5 3.0 10.8 11.2 11.6 12 12.4 12.8 13.2 IO- Output Current -A IO- Output Current -A Figure60.RegulationvsLoadCurrent Figure61.RegulationvsInputVoltage 8.2.2 TPS54240InvertingPowerSupply This application circuit shows how to use the TPS54240 to convert a positive-input voltage to a negative-output voltage. Ideal applications are amplifiers requiring a negative power supply. For a more-detailed example, see CreateanInvertingPowerSupplyFromaStep-DownRegulator,applicationreportSLVA317. VIN + Cin Cboot Lo VIN BOOT PH GND Cd R1 GND + TPS54240 R2 Co VOUT VSENSE EN SS/TR COMP RT/CLK Rcomp Czero Cpole Css RT Figure62. TPS54240InvertingPowerSupply Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 8.2.3 TPS54240SplitRailPowerSupply This application circuit shows how to use the TPS54240 to convert a positive-input voltage to a split-rail positive- and negative-output voltage by using a coupled inductor. Ideal applications are amplifiers requiring a split-rail positive- and negative-voltage power supply. For a more-detailed example, see Creating a Split-Rail Power SupplyWithaWideInputVoltageBuckRegulator, applicationreportSLVA369. VOPOS + VIN Copos + Cin Cboot GND VIN BOOT PH Lo Cd R1 + GND Coneg TPS54240 R2 VONEG VSENSE EN SS/TR COMP RT/CLK Rcomp Czero Cpole Css RT Figure63. TPS54240SplitRailPowerSupply 8.2.4 12-VTo3.8-VGSMPowerSupply This application circuit is designed with TPS54240 device to power GSM-GPRS modules. GSM-GPRS modules typically require a power supply that can support large output current transients. For a more-detailed example, seeCreatingGSM-GPRSPowerSupply, applicationreportSLVA412. TPS54240DGQ Figure64. 12-Vto3.8-VGSMPowerSupply 40 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 8.2.5 24-Vto4.2-VGSMPowerSupply This application circuit is also designed to power GSM-GPRS modules. For a more-detailed example, see CreatingGSM-GPRSPowerSupply, applicationreportSLVA412. TPS54240DGQ Figure65. 24-Vto4.2-VGSMPowerSupply Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TPS54240

TPS54240 SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 www.ti.com 9 Power Supply Recommendations The design of the device is for operation from an input voltage supply range between 3.5 V and 42 V. Good regulation of this input supply is essential. If the input supply is more distant than a few inches from the TPS54240 converter, the circuit may require additional bulk capacitance in addition to the ceramic bypass capacitors.Anelectrolyticcapacitorwithavalueof100 µFisatypicalchoice. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signal paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch diode. See Figure 66 for a PCB layout example. The GND pin should be tied directly to the power pad under the IC and the power pad. The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC. The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH connection is the switching node, the catch diode and output inductor should be located close to the PH pins, andtheareaofthePCBconductorminimizedtopreventexcessivecapacitivecoupling.Foroperationatfullrated load,thetop-sidegroundareamustprovideadequateheatdissipatingarea.TheRT/CLKpinissensitivetonoise so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meantasaguideline. 10.2 Layout Example Vout Output Capacitor Output Topside Inductor Ground Route Boot Capacitor Catch Area Trace on another layer to provide wide path for Diode topside ground Input Bypass Capacitor BOOT PH Vin VIN GND EN COMP UVLO Adjust SS/TR VSENSE Compensation Resistor Resistors Network RT/CLK PWRGD Divider Slow Start Frequency Thermal VIA Capacitor Set Resistor Signal VIA Figure66. PCBLayoutExample 42 SubmitDocumentationFeedback Copyright©2010–2014,TexasInstrumentsIncorporated ProductFolderLinks:TPS54240

TPS54240 www.ti.com SLVSAA6B–APRIL2010–REVISEDNOVEMBER2014 10.3 Estimated Circuit Area TheestimatedprintedcircuitboardareaforthecomponentsusedinthedesignofFigure49 is0.55in2.Thisarea doesnotincludetestpointsorconnectors. 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-PartyProductsDisclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONEORINCOMBINATIONWITHANYTIPRODUCTORSERVICE. 11.2 Documentation Support 11.2.1 RelatedDocumentation CreateanInvertingPowerSupplyFromaStep-DownRegulator,applicationreportSLVA317 CreatingaSplit-RailPowerSupplyWithaWideInputVoltageBuckRegulator, applicationreportSLVA369 CreatingGSM-GPRSPowerSupply, applicationreportSLVA412 11.3 Trademarks Eco-Mode,PowerPADaretrademarksofTexasInstruments. WEBENCHisaregisteredtrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.4 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.5 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2010–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:TPS54240

PACKAGE OPTION ADDENDUM www.ti.com 2-Aug-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54240DGQ ACTIVE MSOP- DGQ 10 80 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 54240 PowerPAD & no Sb/Br) TPS54240DGQR ACTIVE MSOP- DGQ 10 2500 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 54240 PowerPAD & no Sb/Br) TPS54240DRCR ACTIVE VSON DRC 10 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 54240 & no Sb/Br) TPS54240DRCT ACTIVE VSON DRC 10 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 54240 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 2-Aug-2016 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS54240 : •Automotive: TPS54240-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54240DGQR MSOP- DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Power PAD TPS54240DGQR MSOP- DGQ 10 2500 330.0 12.4 5.3 3.3 1.3 8.0 12.0 Q1 Power PAD TPS54240DRCR VSON DRC 10 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 TPS54240DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54240DGQR MSOP-PowerPAD DGQ 10 2500 364.0 364.0 27.0 TPS54240DGQR MSOP-PowerPAD DGQ 10 2500 346.0 346.0 35.0 TPS54240DRCR VSON DRC 10 3000 346.0 346.0 35.0 TPS54240DRCT VSON DRC 10 250 203.0 203.0 35.0 PackMaterials-Page2

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GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M

PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 1.0 C 0.8 SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) (0.2) TYP EXPOSED 4X (0.25) THERMAL PAD 5 6 2X 11 SYMM 2 2.4 0.1 10 1 8X 0.5 0.30 10X 0.18 PIN 1 ID SYMM 0.1 C A B (OPTIONAL) 0.5 0.05 C 10X 0.3 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 SYMM (2.4) (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MIN 0.07 MAX EXPOSED METAL ALL AROUND ALL AROUND EXPOSED METAL SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL 11 TYP 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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