TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 4.5V to 18V INPUT, 2-A SYNCHRONOUS STEP DOWN CONVERTER WITH INTEGRATED FET CheckforSamples:TPS54229 FEATURES DESCRIPTION 1 • D-CAP2™ModeEnablesFastTransient The TPS54229 is an adaptive on-time D-CAP2™ 23 Response mode synchronous buck converter. TheTPS54229 enables system designers to complete the suite of • LowOutputRippleandAllowsCeramicOutput various end equipment’s power bus regulators with a Capacitor cost effective, low component count, low standby • WideV InputVoltageRange:4.5Vto18V current solution. The main control loop for the IN • OutputVoltageRange:0.76Vto7.0V TPS54229 uses the D-CAP2™ mode control which provides a fast transient response with no external • HighlyEfficientIntegratedFETsOptimized compensation components. The TPS54229 also has forLowerDutyCycleApplications a proprietary circuit that enables the device to adopt –160mΩ (HighSide)and110mΩ (LowSide) to both low equivalent series resistance (ESR) output • HighEfficiency,LessThan10μAatShutdown capacitors, such as POSCAP or SP-CAP, and ultra- low ESR ceramic capacitors. The device operates • HighInitialBandgapReferenceAccuracy from 4.5-V to 18-V VIN input. The output voltage can • AdjustableSoftStart be programmed between 0.76 V and 7 V. The device • Pre-BiasedSoftStart also features an adjustable soft start time. The TPS54229 is available in the 8-pin DDA package, • 650-kHzSwitchingFrequency(f ) SW anddesignedtooperatefrom–40°Cto85°C. • CycleByCycleOverCurrentLimit APPLICATIONS • WideRangeofApplicationsforLowVoltage System – DigitalTVPowerSupply – HighDefinitionBlu-rayDisc™Players – NetworkingHomeTerminal – DigitalSetTopBox(STB) Vout = 50 mV/div TPS54229DDA Iout = 1A/div t - Time - 100ms 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. D-CAP2isatrademarkofTexasInstruments. 2 Blu-rayDiscisatrademarkofBlu-rayDiscAssociation. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2011–2012,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) TRANSPORT T PACKAGE ORDERABLEPARTNUMBER PIN A MEDIA TPS54229DDA Tube –40°Cto85°C DDA 8 TPS54229DDAR TapeandReel (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1) VALUE UNIT MIN MAX VIN,EN –0.3 20 V VBST –0.3 26 V VBST(10nstransient) –0.3 28 V Inputvoltagerange VBST(vsSW) –0.3 6.5 V VFB,SS –0.3 6.5 V SW –2 20 V SW(10nstransient) –3 22 V VREG5 –0.3 6.5 V Outputvoltagerange GND –0.3 0.3 V VoltagefromGNDtothermalpad,Vdiff –0.2 0.2 V HumanBodyModel(HBM) 2 kV Electrostaticdischarge ChargedDeviceModel(CDM) 500 V Operatingjunctiontemperature,TJ –40 150 °C Storagetemperature,Tstg –55 150 °C (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. THERMAL INFORMATION TPS54229 THERMALMETRIC UNITS DDA(8PINS) θJA Junction-to-ambientthermalresistance 45.3 θJCtop Junction-to-case(top)thermalresistance 54.8 θJB Junction-to-boardthermalresistance 16.2 °C/W ψJT Junction-to-topcharacterizationparameter 6.6 ψJB Junction-to-boardcharacterizationparameter 16.0 θJCbot Junction-to-case(bottom)thermalresistance 8.5 2 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VIN Supplyinputvoltagerange 4.5 18 V VBST –0.1 24 VBST(10nstransient) -0.1 27 VBST(vsSW) –0.1 5.7 SS –0.1 5.7 VI Inputvoltagerange EN –0.1 18 V VFB –0.1 5.5 SW –1.8 18 SW(10nstransient) –3 21 GND –0.1 0.1 VO Outputvoltagerange VREG5 –0.1 5.7 V IO OutputCurrentrange IVREG5 0 10 mA TA Operatingfree-airtemperature –40 85 °C TJ Operatingjunctiontemperature –40 150 °C ELECTRICAL CHARACTERISTICS overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYCURRENT IVIN Operating-non-switchingsupplycurrent VVIFNBc=ur0r.e8nVt,TA=25°C,EN=5V, 840 1200 μA IVINSDN Shutdownsupplycurrent VINcurrent,TA=25°C,EN=0V 5.8 10 μA LOGICTHRESHOLD VENH ENhigh-levelinputvoltage EN 1.6 V VENL ENlow-levelinputvoltage EN 0.6 V REN ENpinresistancetoGND VEN=12V 220 440 880 kΩ V VOLTAGEANDDISCHARGERESISTANCE FB VFBTH VFBthresholdvoltage TA=25°C,VO=1.05V,continuousmode 749 765 781 mV IVFB VFBinputcurrent VFB=0.8V,TA=25°C 0 ±0.1 μA V OUTPUT REG5 VVREG5 VREG5outputvoltage T0A<=IV2R5E°GC5,<6.50mVA<VIN<18V, 5.5 V IVREG5 Outputcurrent VIN=6V,VREG5=4.0V,TA=25°C(1) 60 mA MOSFET RDS(on)h Highsideswitchresistance 25°C,VBST-SW=5.5V(1) 160 mΩ RDS(on)l Lowsideswitchresistance 25°C(1) 110 mΩ CURRENTLIMIT Iocl Currentlimit Lout=2.2μH(1) 2.5 3.3 4.7 A (1) Notproductiontested. Copyright©2011–2012,TexasInstrumentsIncorporated 3 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) overoperatingfree-airtemperaturerange,V =12V(unlessotherwisenoted) IN PARAMETER TESTCONDITIONS MIN TYP MAX UNIT THERMALSHUTDOWN Shutdowntemperature (2) 165 TSDN Thermalshutdownthreshold Hysteresis (2) 35 °C ON-TIMETIMERCONTROL tON Ontime VIN=12V,VO=1.05V 155 ns tOFF(MIN) Minimumofftime TA=25°C,VFB=0.7V(2) 260 ns SOFTSTART ISSC SSchargecurrent VSS=1V 4.2 6.0 7.8 μA ISSD SSdischargecurrent VSS=0.5V 0.1 0.2 mA UVLO WakeupVREG5voltage 3.75 UVLO UVLOthreshold V HysteresisVREG5voltage 0.32 (2) Notproductiontested. 4 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 DEVICE INFORMATION DDAPACKAGE (TOPVIEW) 1 VBST SS 8 TPS54229 2 VIN DDA EN 7 (HSOP8) 3 SW Power PAD VREG5 6 4 GND VFB 5 PINFUNCTIONS PIN DESCRIPTION NAME NO. Supplyinputforthehigh-sideFETgatedrivecircuit.Connect0.1µFcapacitorbetweenVBSTandSW VBST 1 pins.AninternaldiodeisconnectedbetweenVREG5andVBST. VIN 2 Inputvoltagesupplypin. SW 3 Switchnodeconnectionbetweenhigh-sideNFETandlow-sideNFET. Groundpin.Powergroundreturnforswitchingcircuit.ConnectsensitiveSSandVFBreturnstoGNDat GND 4 asinglepoint. VFB 5 Converterfeedbackinput.Connecttooutputvoltagewithfeedbackresistordivider. 5.5Vpowersupplyoutput.Acapacitor(typical0.47µF)shouldbeconnectedtoGND.VREG5isnot VREG5 6 activewhenENislow. EN 7 Enableinputcontrol.ENisactivehighandmustbepulleduptoenablethedevice. SS 8 Soft-startcontrol.AnexternalcapacitorshouldbeconnectedtoGND. ExposedThermal Thermalpadofthepackage.Mustbesolderedtoachieveappropriatedissipation.Mustbeconnectedto Backside Pad GND. Copyright©2011–2012,TexasInstrumentsIncorporated 5 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com FUNCTIONALBLOCKDIAGRAM EN 7 EN VIN Logic VIN 2 VREG5 VBST Control Logic 1 Ref + SS +PWM VFB 1 shot SW VO 5 - 3 XCON ON VREG5 VREG5 Ceramic 6 Capacitor SGND SS SS 4 8 Softstart GND PGND SGND + SW OCP - PGND VIN VREG5 UVLO Protection TSD Logic UVLO REF Ref 6 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 OVERVIEW The TPS54229 is a 2-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low ESRoutputcapacitorsincludingceramicandspecialpolymertypes. DETAILED DESCRIPTION PWMOperation The main control loop of the TPS54229 is an adaptive on-time pulse width modulation (PWM) controller that supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with bothlowESRandceramicoutputcapacitors.Itisstableevenwithvirtuallynorippleattheoutput. At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need forESRinducedoutputripplefromD-CAP2™modecontrol. PWMFrequencyandAdaptiveOn-TimeControl TPS54229 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The TPS54229 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the outputvoltage,therefore,whenthedutyratioisVOUT/VIN,thefrequencyisconstant. SoftStartandPre-BiasedSoftStart The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up. The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is 6μA. C (nF)xV ´1.1 C (nF)x0.765´1.1 SS REF SS t (ms)= = SS I (mA) 6 SS (1) The TPS54229 contains a unique circuit to prevent current from being pulled from the output during startup if the output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start becomes greater than feedback voltage V ), the controller slowly activates synchronous rectification by starting FB the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by- cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal modeoperation. CurrentProtection The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature compensated. During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin, Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current decreases linearly. The average value of the switch current is the load current I . The TPS54229 constantly OUT monitorsthelow-sideFETswitchvoltage,whichisproportionaltotheswitchcurrent,duringthelow-sideon-time. If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching Copyright©2011–2012,TexasInstrumentsIncorporated 7 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the highervalue. There are some important considerations for this type of over-current protection. The load current one half of the peak-to-peak inductor current higher than the over-current threshold. Also when the current is being limited, the output voltage tends to fall as the demanded load current may be higher than the current available from the converter. This may cause the output voltage to fall. When the over current condition is removed, the output voltagewillreturntotheregulatedvalue.Thisprotectionisnon-latching. UVLOProtection Undervoltage lock out protection (UVLO) monitors the voltage of the V pin. When the V voltage is lower REG5 REG5 thanUVLOthresholdvoltage,theTPS54229isshutoff.Thisisprotectionisnon-latching. ThermalShutdown TPS54229 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C), thedeviceisshutoff.Thisisnon-latchprotection. 8 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 TYPICAL CHARACTERISTICS VIN=12V,T =25°C(unlessotherwisenoted). A 1200 12 1000 10 VI= 12 V A m urrent -Am 800 n Current - 8 VI= 12 V C 600 w 6 I- Supply CC 400 csdn - Shutdo 4 c 200 Iv 2 0 0 -50 0 50 100 150 -50 0 50 100 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure1.VINCURRENTvsJUNCTIONTEMPERATURE Figure2.VINSHUTDOWNCURRENTvs JUNCTIONTEMPERATURE 50 1.07 45 40 1.06 VI= 5 V VI= 12 V VI= 18 V nput Current -Am 22330505 VI= 18 V Output Voltage - V 1.05 EN I 15 V- O 1.04 10 5 0 1.03 0 5 10 15 20 0 0.5 1 1.5 2 VI- Input Voltage - V IO- Output Current -A Figure3.ENCURRENTvsENVOLTAGE Figure4.1.05-VOUTPUTVOLTAGEvsOUTPUTCURRENT 1.07 Vout = 50 mV/div 1.06 IO= 0A V e - g a olt ut V 1.05 IO= 1A p Iout = 1A/div ut O - O V 1.04 1.03 0 5 10 15 20 t - Time - 100ms VI- Input Voltage - V Figure5.1.05-VOUTPUTVOLTAGEvsINPUTVOLTAGE Figure6.1.05-V,50-mAto2-ALOADTRANSIENT RESPONSE Copyright©2011–2012,TexasInstrumentsIncorporated 9 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com TYPICAL CHARACTERISTICS VIN=12V,T =25°C(unlessotherwisenoted). A 100 VO= 1.8 V VO= 2.5 V VO= 3.3 V EN = 10 V/div 90 80 VREG5 = 5 V/div % y - nc 70 e ci Effi VO= 0.5 V/div 60 50 40 t - Time - 1 ms 0 0.5 1 1.5 2 IO- Output Current -A Figure7.START-UPWAVEFORM Figure8.EFFICIENCYvsOUTPUTCURRENT 900 900 850 850 uency - kHz 778050000 VO= 2.5 V VO= 3.3 V VO= 5 V uency - kHz 778050000 VO= 3.3 V q q Fre 650 Fre 650 g g witchin 565000 VO= 1.05V VO= 1.2 V VO= 1.5 V witchin 565000 VO= 1.05 V VO= 1.8 V f - Ssw 500 VO= 1.8 V f - Ssw 500 450 450 400 400 0 5 10 15 20 0 0.5 1 1.5 2 VI- Input Voltage - V IO- Output Current -A Figure9.SWITCHINGFREQUENCYvsINPUTVOLTAGE Figure10.SWITCHINGFREQUENCYvs OUTPUTCURRENT VO= 1.05 V VO= 1.05 V VO= 10 mV/div VO= 50 mV/div SW = 5 V/div SW = 5 V/div t - Time - 400 ns t - Time - 400 ns Figure11.VOLTAGERIPPLEATOUTPUT(I =2A) Figure12.VOLTAGERIPPLEATINPUT(I =2A) O O 10 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 TYPICAL CHARACTERISTICS VIN=12V,T =25°C(unlessotherwisenoted). A 0.78 VIN = 12 V 0.775 IO = 1 A V) 0.77 e ( g a olt 0.765 V B VF 0.76 0.755 0.75 −40 −20 0 20 40 60 80 100 120 Temperature (°C) G000 Figure13. VFBVOLTAGEvsJUNCTIONTEMPERATURE Copyright©2011–2012,TexasInstrumentsIncorporated 11 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com DESIGN GUIDE StepByStepDesignProcedure Tobeginthedesignprocess,youmustknowafewapplicationparameters: • Inputvoltagerange • Outputvoltage • Outputcurrent • Outputvoltageripple • Inputvoltageripple U1 TPS54229DDA Figure14. Showstheschematicdiagramforthisdesignexample. OutputVoltageResistorsSelection The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use 1%toleranceorbetterdividerresistors.StartbyusingEquation2tocalculateV . OUT To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more susceptibletonoiseandvoltageerrorsfromtheVFBinputcurrentwillbemorenoticeable. æ R1ö VOUT =0.765x çççè1+ R2ø÷÷÷÷ (2) OutputFilterSelection TheoutputfilterusedwiththeTPS54229isanLCcircuit.ThisLCfilterhasdoublepoleat: 1 F = P 2p L xC OUT OUT (3) At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal gain of the TPS54229. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the valuesrecommendedinTable1 12 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 Table1.RecommendedComponentValues OutputVoltage(V) R1(kΩ) R2(kΩ) C4(pF) L1(µH) C8+C9+C10(µF) 1 6.81 22.1 2.2 20-68 1.05 8.25 22.1 2.2 20-68 1.2 12.7 22.1 2.2 20-68 1.5 21.5 22.1 2.2 20-68 1.8 30.1 22.1 5-22 3.3 20-68 2.5 49.9 22.1 5-22 3.3 20-68 3.3 73.2 22.1 5-22 3.3 20-68 5 124 22.1 5-22 4.7 20-68 6.5 165 22.1 5-22 4.7 20-68 Since the DC gain is dependent on the output voltage, the required inductor value will increase as the output voltage increases. For higher output voltages at or above 1.8 V, additional phase boost can be achieved by addingafeedforwardcapacitor(C4)inparallelwithR1 The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4, Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for f . SW Use 700 kHz for f . Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS SW currentofEquation6. I = VOUT x VIN(max) -VOUT IPP V L x f IN(max) O SW (4) I lpp I =I + Ipeak O 2 (5) 1 I = I 2 + I 2 Lo(RMS) O 12 IPP (6) For this design example, the calculated peak current is 2.311 A and the calculated RMS current is 2.009 A. The inductorusedisaTDKCLF7045T-2R2Mwithapeakcurrentratingof5.5AandanRMScurrentratingof4.3A. The capacitor value and ESR determines the amount of output voltage ripple. The TPS54229 is intended for use with ceramic or other low ESR capacitors. Recommended values range from 20 µF to 68 µF. Use Equation 7 to determinetherequiredRMScurrentratingfortheoutputcapacitor. V x(V -V ) I = OUT IN OUT Co(RMS) 12 xV xL x f IN O SW (7) For this design three TDK C3216X5R0J106M 10µF output capacitors are used. The typical ESR is 2 mΩ each. ThecalculatedRMScurrentis0.19Aandeachoutputcapacitorisratedfor4A. InputCapacitorSelection The TPS54229 requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor(C3)isrequiredtoprovideadditionalhighfrequencyfilteringandinsureaccuratecurrentlimitoperation. This capacitor must be placed as close to the IC pins 2 (VIN) and 4 (GND) as possible. The capacitor voltage ratingneedstobegreaterthanthemaximuminputvoltage. BootstrapCapacitorSelection A 0.1µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is recommendedtouseaceramiccapacitor. Copyright©2011–2012,TexasInstrumentsIncorporated 13 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com VREG5CapacitorSelection A 0.47µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is recommendedtouseaceramiccapacitor. THERMAL INFORMATION This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC). For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No. SLMA002andApplicationBrief,PowerPAD™MadeEasy,TexasInstrumentsLiteratureNo.SLMA004. Theexposedthermalpaddimensionsforthispackageareshowninthefollowingillustration. Figure15. ThermalPadDimensions(TopView) 14 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 LAYOUT CONSIDERATIONS 1. Keeptheinputswitchingcurrentloopassmallaspossible. 2. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the feedbackpinofthedevice. 3. Keepanalogandnon-switchingcomponentsawayfromswitchingcomponents. 4. Makeasinglepointconnectionfromthesignalgroundtopowerground. 5. Donotallowswitchingcurrenttoflowunderthedevice. 6. KeepthepatternlinesforVINandPGNDbroad. 7. ExposedpadofdevicemustbeconnectedtoPGNDwithsolder. 8. VREG5capacitorshouldbeplacednearthedevice,andconnectedPGND. 9. OutputcapacitorshouldbeconnectedtoabroadpatternofthePGND. 10. Voltagefeedbackloopshouldbeasshortaspossible,andpreferablywithgroundshield. 11. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to analog ground trace. 12. ProvidingsufficientviasforVIN,SWandPGNDconnection. 13. VIN input bypass capacitor and VIN high frequency bypass capacitor must be placed as near as possible to thedevice. 14. Performancebasedonfourlayerprintedcircuitboard. Copyright©2011–2012,TexasInstrumentsIncorporated 15 ProductFolderLink(s):TPS54229

TPS54229 SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 www.ti.com VIA to Power Ground Plane VIA to SW Copper Pour on Bottom or Internal Layer VIN ANALOG GROUND VIN VIN BOOST TRACE INPUT HIGH FREQENCY CAPACITOR BYPASS BYPASS CAPACITOR CAPACITOR VBST SS TO ENABLE VIN EN CONTROL SW VREG5 GND VFB BIAS SLOW CAP START CAP EXPOSED POWER THERMALPAD AREA GROUND FEEDBACK RESISTORS OUTPUT INDUCTOR SW node copper pour area on internal or POWER bottom layer GROUND Connection to POWER GROUND on internal or bottom layer VOUT OUTPUT FILTER CAPACITOR Figure16. PCBLayout 16 Copyright©2011–2012,TexasInstrumentsIncorporated ProductFolderLink(s):TPS54229

TPS54229 www.ti.com SLVSAZ8A–SEPTEMBER2011–REVISEDMARCH2012 REVISION HISTORY ChangesfromOriginal(September2011)toRevisionA Page • Removed(SWIFT™)fromthedatasheettitle ..................................................................................................................... 1 • DeletedfromELECTRICALCHARACTERISTICStable,V andV ,deletedV MINandMAXvalues .................. 3 LN5 LD5 VREG5 • AddedinELECTRICALCHARACTERISTICStable,I andR andR footnotereferences........................... 3 VREG5 DS(on)h DS(on)l • AddedinELECTRICALCHARACTERISTICStable,t footnotereferenceanddeleteMAXvalue ............................ 4 OFF(MIN) • DeletedfromELECTRICALCHARACTERISTICS,UVLOMINandMAXvalues ................................................................ 4 • AddedTYPICALCHARACTERISTICSCondition ................................................................................................................ 9 Copyright©2011–2012,TexasInstrumentsIncorporated 17 ProductFolderLink(s):TPS54229

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54229DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54229 & no Sb/Br) TPS54229DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS NIPDAU | SN Level-2-260C-1 YEAR -40 to 85 54229 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54229DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1 Power PAD PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jul-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54229DDAR SOPowerPAD DDA 8 2500 366.0 364.0 50.0 PackMaterials-Page2

GENERIC PACKAGE VIEW DDA 8 PowerPAD TM SOIC - 1.7 mm max height PLASTIC SMALL OUTLINE Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4202561/G

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