TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 1.5-A 60-V STEP-DOWN SWIFT™ DC-DC CONVERTER WITH Eco-mode™ CONTROL CheckforSamples:TPS54160-Q1 FEATURES 1 • QualifiedforAutomotiveApplications • AdjustableUndervoltageLockout(UVLO) 2 • 3.5-Vto60-VInputVoltageRange VoltageandHysteresis • 200-mΩHigh-SideMOSFET • 0.8-VInternalVoltageReference • HighEfficiencyatLightLoadsWithPulse- • SupportedbySwitcherPro™SoftwareTool SkippingEco-mode™ControlScheme (http://focus.ti.com/docs/toolsw/folders/print/s witcherpro.html) • 116-μAOperatingQuiescentCurrent • ForSWIFT™powerproductsdocumentation, • 1.3-μAShutdownCurrent seetheTIWebsiteathttp://www.ti.com/swift. • 100-kHzto2.5-MHzSwitchingFrequency • SynchronizestoExternalClock APPLICATIONS • AdjustableSlowStartandSequencing • 12-V,24-V,and48-VIndustrialandCommercial • UndervoltageandOvervoltagePower-Good Low-PowerSystems Output • AftermarketAutomotiveAccessories:Video, GPS,Entertainment DESCRIPTION The TPS54160-Q1 device is a 60-V 1.5-A step-down regulator with an integrated high-side MOSFET. Current- mode control provides simple external compensation and flexible component selection. A low-ripple pulse-skip mode reduces the no-load, input supply current to 116 μA. Using the enable pin reduces the shutdown supply currentto1.3μA. Undervoltage lockout is set internally at 2.5 V but can be increased using the enable pin. The slow-start pin, which is also configurable for sequencing or tracking, controls the output-voltage start-up ramp. An open-drain power-goodsignalindicatestheoutputiswithin92%to109%ofitsnominalvoltage. A wide switching-frequency range allows optimization of efficiency and external component size. Frequency foldbackandthermalshutdownprotectthepartduringanoverloadcondition. TheTPS54160-Q1isavailableina10-pinthermallyenhancedMSOP(DGQ)or10-pinSON(DRC)PowerPAD™ package. SIMPLIFIEDSCHEMATIC EFFICIENCY VIN PWRGD LOAD CvUsRRENT 90 TPS54160 85 EN BOOT 80 RSST//CTRLK PH Efficiency - % 677505 COMP 60 VI= 12 V, VSENSE VO= 3.3 V, 55 fsw= 1200 kHz GND 500 0.25 0.50 0.75 1 1.25 1.50 1.75 2 Load Current -A 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Eco-mode,SwitcherPro,SWIFT,PowerPADaretrademarksofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2013,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. PACKAGE AND ORDERING INFORMATION For the most-current package and ordering information, see the Package Option Addendum at the end of this document,orseetheTIWebsiteatwww.ti.com. Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. ABSOLUTE MAXIMUM RATINGS(1) overoperatingtemperaturerange(unlessotherwisenoted) VIN –0.3Vto65V EN(2) –0.3Vto5V BOOT 73V VSENSE –0.3Vto3V V Inputvoltage IN COMP –0.3Vto3V PWRGD –0.3Vto6V SS/TR –0.3Vto3V RT/CLK –0.3Vto3.6V BOOTtoPH 8V –0.6Vto65V V Outputvoltage 200ns –1Vto65V OUT PH 30ns –2Vto65V Maximumdcvoltage,T =–40°C –0.85V J V Differentialvoltage PADtoGND ±200mV DIFF EN 100μA BOOT 100mA I Sourcecurrent VSENSE 10μA SOURCE PH Currentlimit RT/CLK 100μA VIN Currentlimit COMP 100μA I Sinkcurrent SINK PWRGD 10mA SS/TR 200μA Human-bodymodel(HBM)(AEC-Q100-002) 500V ESD Electrostaticdischargeprotection Machinemodel(MM)(AEC-Q100-003) 50V Charged-devicemodel(CDM)(AEC-Q100-011) 1000V T Operatingjunctiontemperaturerange –40°Cto150°C J T Storagetemperaturerange –65°Cto150°C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) SeeEnableandAdjustingUndervoltageLockoutfordetails. 2 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 THERMAL INFORMATION TPS54160-Q1 THERMALMETRIC(1)(2) DGQ DRC UNIT 10PINS 10PINS θ Junction-to-ambientthermalresistance(standardboard) 62.5 56.5 °C/W JA θ Junction-to-ambientthermalresistance(customboard)(3) 57 61.5 °C/W JA θ Junction-to-case(top)thermalresistance 83 52.1 °C/W JCtop θ Junction-to-boardthermalresistance 28 20.6 °C/W JB ψ Junction-to-topcharacterizationparameter 1.7 0.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 20.1 20.8 °C/W JB θ Junction-to-case(bottom)thermalresistance 21 5.2 °C/W JCbot (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. (2) DeterminethepowerratingataspecificambienttemperatureT withajunctiontemperatureof150°C.Thisisthepointwheredistortion A startstoincreasesubstantially.Seethepower-dissipationestimateintheapplicationsectionofthisdatasheetformoreinformation. (3) Test-boardconditions: (a)3inches(7.62cm)×3inches(7.62cm),twolayers,thickness:0.062inch(1.59mm) (b) 2-oz.(0.071-mmthick)coppertraceslocatedonthetopofthePCB (c) 2-oz.(0.071-mmthick)coppergroundplane,bottomlayer (d)Sixthermalvias(13-mil),0.33-mm)locatedunderthedevicepackage ELECTRICAL CHARACTERISTICS T =–40°Cto150°C,VIN=3.5Vto60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage 3.5 60 V Internalundervoltage-lockout Novoltagehysteresis,risingandfalling 2.5 V threshold EN=0V,25°C,3.5V≤VIN≤60V 1.5 4 Shutdownsupplycurrent EN=0V,125°C,3.5V≤VIN≤60V 1.9 6.5 μA Operatingnonswitchingsupply VSENSE=0.83V,VIN=12V,T =25°C 116 136 current J ENABLEANDUVLO(ENPIN) Novoltagehysteresis,risingandfalling, Enablethresholdvoltage 0.9 1.25 1.55 V T =25°C J Enablethreshold50mV –3.8 Inputcurrent μA Enablethreshold–50mV –0.9 Hysteresiscurrent –2.9 μA VOLTAGEREFERENCE T =25°C 0.792 0.8 0.808 J Voltagereference V 0.784 0.8 0.816 HIGH-SIDEMOSFET VIN=3.5V,BOOT-PH=3V 300 On-resistance mΩ VIN=12V,BOOT-PH=6V 200 410 ERRORAMPLIFIER Inputcurrent 50 nA gm Error-amplifiertransconductance –2μA<I <2μA,V =1V 97 μS COMP COMP gm Error-amplifiertransconductance –2μA<ICOMP<2μA,VCOMP=1V, 26 μS duringslowstart V =0.4V VSENSE Error-amplifierdcgain V =0.8V 10,000 V/V VSENSE Error-amplifierbandwidth 2700 kHz Error-amplifiersource/sink V =1V,100-mVoverdrive ±7 μA (COMP) Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) T =–40°Cto150°C,VIN=3.5Vto60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT COMPtoswitchcurrent 6 A/V transconductance 4 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 ELECTRICAL CHARACTERISTICS (continued) T =–40°Cto150°C,VIN=3.5Vto60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CURRENTLIMIT Current-limitthreshold VIN=12V,T =25°C 1.8 2.7 A J THERMALSHUTDOWN Thermalshutdown 182 °C TIMINGRESISTORANDEXTERNALCLOCK(RT/CLKPIN) SwitchingfrequencyrangeusingRT VIN=12V 100 2500 kHz mode f Switchingfrequency VIN=12V,R =200kΩ 450 581 720 kHz SW T Switching-frequencyrangeusing VIN=12V 300 2200 kHz CLKmode MinimumCLKinput-pulseduration 40 ns RT/CLKhighthreshold VIN=12V 1.9 2.2 V RT/CLKlowthreshold VIN=12V 0.45 0.7 V RT/CLKfalling-edgetoPHrising- Measuredat500kHzwithRTresistorinseries 60 ns edgedelay PLLlock-intime Measuredat500kHz 100 μs SLOWSTARTANDTRACKING(SS/TR) Chargecurrent V =0.4V 2 μA SS/TR SS/TR-to-VSENSEmatching V =0.4V 45 mV SS/TR SS/TR-to-referencecrossover 98%nominal 1.0 V SS/TRdischargecurrent(overload) VSENSE=0V,V(SS/TR)=0.4V 112 μA SS/TRdischargevoltage VSENSE=0V 54 mV POWERGOOD(PWRGDPIN) VSENSEfalling(fault) 92% VSENSErising(good) 94% V VSENSEthreshold VSENSE VSENSErising(fault) 109% VSENSEfalling(good) 107% Hysteresis VSENSEfalling 2% VSENSE=VREF,V(PWRGD)=5.5V, Outputhighleakage 10 nA T =25°C J Onresistance I(PWRGD)=3mA,VSENSE<0.79V 50 Ω MinimumVINfordefinedoutput V(PWRGD)<0.5V,II(PWRGD)=100μA 0.95 1.5 V Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DEVICE INFORMATION PIN CONFIGURATION DGQ PACKAGE DRC PACKAGE (TOPVIEW) (TOPVIEW) BOOT 1 10 PH BOOT 1 10 PH VIN 2 9 GND VIN 2 9 GND Exposed Exposed EN 3 Thermal 8 COMP EN 3 Thermal 8 COMP Pad Pad SS/TR 44 7 VSENSE SS/TR 44 7 VSENSE RT/CLK 5 6 PWRGD RT/CLK 5 6 PWRGD PINFUNCTIONS PIN I/O DESCRIPTION NAME NO. ThedevicerequiresabootstrapcapacitorbetweenBOOTandPH.Avoltageonthiscapacitorthatisbelow BOOT 1 O theminimumrequiredbytheoutputdevice,forcestheoutputtoswitchoffuntilthecapacitorrecharges. Error-amplifieroutput,andinputtotheoutput-switchcurrentcomparator.Connectfrequency-compensation COMP 8 O componentstoCOMP. Enablepin,internalpullupcurrentsource.Pullbelow1.2Vtodisable.Floattoenable.Adjusttheinput EN 3 I undervoltagelockoutwithtworesistors. GND 9 – Ground PH 10 I Thesourceoftheinternalhigh-sidepowerMOSFET Open-drainoutput,assertslowifoutputvoltageislowduetothermalshutdown,dropout,overvoltage,orEN PWRGD 6 O shutdown. Resistortimingandexternalclock.Aninternalamplifierholdsthispinatafixedvoltagewhenusingan externalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLLupperthreshold, RT/CLK 5 I amodechangeoccursandthepinbecomesasynchronizationinput.Themodechangedisablestheinternal amplifierandthepinisahigh-impedanceclockinputtotheinternalPLL.Stoppageoftheclockingedgesre- enablestheinternalamplifier,andthemodereturnstoaresistor-setfunction. Slow-startandtracking.Anexternalcapacitorconnectedtothispinsetstherisetimeoftheoutput.The SS/TR 4 I voltageonthispinoverridestheinternalreference,whichallowsuseofthepinfortrackingandsequencing. VIN 2 I Inputsupplyvoltage,3.5Vto60V VSENSE 7 I Invertingnodeofthetransconductance(gm)erroramplifier Thermalpad ConnecttheGNDpinelectricallytotheexposedpadontheprintedcircuitboardforproperoperation. 6 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 FUNCTIONAL BLOCK DIAGRAM PWRGD EN VIN 6 3 2 Shutdown Thermal Shutdown UVLO Enable UO Logic Comparator Shutdown Shutdown Logic OV Enable Threshold Boot Charge Voltage Minimum Boot Reference Clamp UVLO Current Pulse Sense ERROR Skip AMPLIFIER PWM VSENSE 7 Comparator 1 BOOT SS/TR 4 Logic And PWM Latch Shutdown Slope Compensation COMP 8 10PH 11 POWERPAD Frequency Shift Overload Maximum Recovery Clamp Oscillator TPS54160Block Diagram 9 GND with PLL 5 RT/CLK Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com TYPICAL CHARACTERISTICS ON-RESISTANCEvsJUNCTIONTEMPERATURE VOLTAGEREFERENCEversusJUNCTIONTEMPERATURE W 0.816 m 500 nce - VI= 12 V VI= 12 V a c Drain-Source On-State Resist 213527055 BOOT-PH = 3 V BOOT-PH = 6 V V- Voltage Reference - Vref 000...788900208 ati St N - O 0.784 DS 0 -50 -25 0 25 50 75 100 125 150 R -50 -25 0 25 50 75 100 125 150 T - Junction Temperature - °C TJ- Junction Temperature - °C J Figure1. Figure2. SWITCH-CURRENTLIMITversusJUNCTION SWITCHINGFREQUENCYversusJUNCTION TEMPERATURE TEMPERATURE 3.5 610 V= 12 V, V= 12 V I I RT= 200 kW 600 Hz k A 3 cy - 590 witch Current - ching Frequen 580 S2.5 wit 570 S - fs 560 2 550 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure3. Figure4. SWITCHINGFREQUENCYversusRT/CLKRESISTANCE SWITCHINGFREQUENCYversusRT/CLKRESISTANCE- HIGH-FREQUENCYRANGE LOWFREQUENCYRANGE 2500 1000 VI= 12 V, VI= 12 V, TJ= 25°C TJ= 25°C Hz 2000 Hz 800 witching Frequency - k 11050000 witching Frequency - k 460000 S S f- s 500 f- s 200 0 0 0 25 50 75 100 125 150 175 200 100 200 300 400 500 600 700 800 900 1000 RT/CLK - Resistance - kW RT/CLK - Resistance - kW Figure5. Figure6. 8 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 TYPICAL CHARACTERISTICS (continued) EATRANSCONDUCTANCEDURINGSLOWSTARTversus EATRANSCONDUCTANCEversusJUNCTION JUNCTIONTEMPERATURE TEMPERATURE 40 150 V= 12 V I V= 12 V I 130 30 110 V V A/ A/ m m m - m - g g 90 20 70 10 50 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure7. Figure8. ENPINVOLTAGEversusJUNCTIONTEMPERATURE ENPINCURRENTversusJUNCTIONTEMPERATURE 1.40 -3.25 V= 12 V VI= 12 V, I VI(EN)=Threshold +50 mV -3.5 V 1.30 d - ol A h m EN - Thres 1.20 I-(EN)-3.75 -4 1.10 -4.25 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure9. Figure10. SS/TRCHARGECURRENTversusJUNCTION ENPINCURRENTversusJUNCTIONTEMPERATURE TEMPERATURE -0.8 -1 VI= 12 V, VI= 12 V VI(EN)=Threshold -50 mV -0.85 -1.5 Am Am I-(EN)-0.9 -SS/TR) -2 I( -0.95 -2.5 -1 -3 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure11. Figure12. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com TYPICAL CHARACTERISTICS (continued) SS/TRDISCHARGECURRENTversusJUNCTION TEMPERATURE SWITCHINGFREQUENCYversusVSENSE 120 100 VI= 12 V VI= 12 V, T = 25°C J 80 115 w -AmS/TR)110 Nominal fs 60 II(S % of 40 105 20 100 0 -50 -25 0 25 50 75 100 125 150 0 0.2 0.4 0.6 0.8 TJ- Junction Temperature - °C VSENSE- V Figure13. Figure14. SHUTDOWNSUPPLYCURRENTversusJUNCTION SHUTDOWNSUPPLYCURRENTversusINPUTVOLTAGE TEMPERATURE (V ) in 2 2 V= 12 V I T = 25°C J 1.5 1.5 A A m m I-(VIN) 1 I-(VIN) 1 0.5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 TJ- Junction Temperature - °C VI- Input Voltage - V Figure15. Figure16. VINSUPPLYCURRENTversusJUNCTIONTEMPERATURE VINSUPPLYCURRENTversusINPUTVOLTAGE 140 140 VI= 12 V, TJ= 25oC, VI(VSENSE)= 0.83 V VI(VSENSE)= 0.83 V 130 130 120 120 A A m m I-(VIN) 110 I-(VIN) 110 100 100 90 90 -50 -25 0 25 50 75 100 125 150 0 20 40 60 TJ- Junction Temperature - °C VI- Input Voltage - V Figure17. Figure18. 10 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 TYPICAL CHARACTERISTICS (continued) PWRGDON-RESISTANCEversusJUNCTION TEMPERATURE PWRGDTHRESHOLDversusJUNCTIONTEMPERATURE 100 115 VI= 12 V VI= 12 V 80 ef110 VSENSE Rising Vr of % 105 VSENSE Falling WN - 60 old - RDSO 40 Thresh 100 GD 95 VSENSE Rising R W P 20 90 VSENSE Falling 0 85 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 T - Junction Temperature - °C T - Junction Temperature - °C J J Figure19. Figure20. BOOT-PHUVLOversusJUNCTIONTEMPERATURE INPUTVOLTAGE(UVLO)versusJUNCTIONTEMPERATURE 3 2.3 2.75 V - 2.1 OOT-PH) - VVIN) 2.50 VI(B VI( 1.9 2.25 1.7 2 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure21. Figure22. SS/TRTOVSENSEOFFSETversusVSENSE SS/TRTOVSENSEOFFSETversusTEMPERATURE 600 60 V = 0.2 V V =12V (SS/TR) mV) 500 TIJN=25°C 55 VI= 12 V ( d hol 400 50 res mV geTh 300 Offset - 45 a olt 40 V 200 et s 35 Off 100 30 -50 -25 0 25 50 75 100 125 150 0 0 200 400 600 800 TJ- Junction Temperature - °C VoltageSense(mV) Figure23. Figure24. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com OVERVIEW The TPS54160-Q1 device is a 60-V 1.5-A step-down (buck) regulator with an integrated high-side n-channel MOSFET. To improve performance during line and load transients, the device implements a constant-frequency, current-mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. A resistor to ground on the RT/CLK pin adjusts the switching frequency. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that synchronizes the power-switch turnon to the falling edgeofanexternalsystemclock. The TPS54160-Q1 has a default start-up voltage of approximately 2.5 V. The EN pin has an internal pullup current source that one can use to adjust the input-voltage undervoltage lockout (UVLO) threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating, the device can operate. The operating current is 116 μA when not switching and under no load. When the device is disabled,thesupplycurrentis1.3μA. The integrated 200-mΩ high-side MOSFET allows for high-efficiency power-supply designs capable of delivering 1.5-A continuous current to a load. The TPS54160-Q1 reduces the external component count by integrating the boot-recharge diode. A capacitor between the BOOT and PH pins supplies the bias voltage for the integrated high-side MOSFET. A UVLO circuit monitors the boot capacitor voltage and turns off the high-side MOSFET when the boot voltage falls below a preset threshold. The TPS54160-Q1 can operate at high duty cycles becauseofthebootUVLO.Itispermissibletosteptheoutputvoltagedowntoaslowasthe0.8-Vreference. The TPS54160-Q1 has a power-good comparator (PWRGD), which asserts when the regulated output voltage is less than 92% or greater than 109% of the nominal output voltage. The PWRGD pin is an open-drain output which de-asserts when the VSENSE pin voltage is between 94% and 107% of the nominal output voltage, allowingthepintotransitionhighwhenusingapullupresistor. The TPS54160-Q1 minimizes excessive output overvoltage (OV) transients by taking advantage of the OV power-good comparator. Activation of the OV comparator turns off the high-side MOSFET and masks it from turningonuntiltheoutputvoltageislowerthan107%. One can use the SS/TR (slow start/tracking) pin to minimize inrush currents or provide power-supply sequencing during power up. Connect a small-value capacitor to the pin to adjust the slow-start time. Connect a resistor divider to the pin for critical power-supply sequencing requirements. Discharge of the SS/TR pin occurs before the output powers up. This discharging ensures a repeatable restart after an overtemperature fault, UVLO fault, oradisabledcondition. The TPS54160-Q1 also discharges the slow-start capacitor during overload conditions with an overload-recovery circuit. The overload-recovery circuit slow-starts the output from the fault voltage to the nominal regulation voltage after rmoval of a fault condition. A frequency foldback circuit reduces the switching frequency during start-upandovercurrent-faultconditionstohelpcontroltheinductorcurrent. 12 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION Fixed-Frequency PWM Control The TPS54160-Q1 uses an adjustable fixed-frequency, peak-current mode control. An internal voltage reference compares the output voltage through external resistors on the VSENSE pin to an error amplifier which drives the COMPpin.Aninternaloscillatorinitiatestheturnonofthehigh-sidepowerswitch.Thedevicecomparestheerror amplifier output to the high-side power-switch current. When the power-switch current reaches the level set by the COMP voltage, the power switch turns off. The COMP pin voltage increases and decreases as the output current increases and decreases. The device implements a current limit by clamping the COMP pin voltage to a maximumlevel.ThedeviceimplementstheEco-modecontrolschemewithaminimumclampontheCOMPpin. Slope-Compensation Output Current The TPS54160-Q1 adds a compensating ramp to the switch-current signal. This slope compensation prevents sub-harmonicoscillations.Theavailablepeakinductorcurrentremainsconstantoverthefullduty-cyclerange. Pulse-Skip Eco-Mode Control Scheme The TPS54160-Q1 operates in a pulse-skip Eco-mode control scheme at light load currents to improve efficiency by reducing switching and gate-drive losses. If the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-mode control.ThiscurrentthresholdisthecurrentlevelcorrespondingtoanominalCOMPvoltageor500mV. When in Eco-mode, a clamp holds the COMP pin voltage at 500 mV, inhibiting the high-side MOSFET. Further decreasesinloadcurrentorinoutputvoltagecannotdrivetheCOMPpinbelowthevoltagelevelofthisclamp. Because the device is not switching, the output voltage begins to decay. As the voltage-control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET turns on, initiating a switching pulse on the next switching cycle.The COMP pin voltage sets the peak current. The output voltage recharges the regulated value (see Figure 25), then the peak switch current starts to decrease, and eventually falls below the control-scheme threshold, at which time the device again enters the Eco-modecontrolscheme. ForEco-modecontrol-schemeoperation,theTPS54160-Q1sensespeakcurrent,notaverageorloadcurrent,so the load current where the device enters the Eco-mode control scheme depends on the output inductor value. For example, the circuit in Figure 51 enters the Eco-mode control scheme at about 18 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 116 μA of input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light load currents in the pulse-skip mode, the switching transitions occur synchronously with the externalclocksignal. VOUT(ac) IL PH Figure25. Pulse-SkipModeOperation Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) Low-Dropout Operation and Bootstrap Voltage (BOOT) The TPS54160-Q1 has an integrated boot regulator, and requires a small ceramic capacitor between the BOOT and PH pins to provide the gate-drive voltage for the high-side MOSFET. The BOOT capacitor recharges when the high-side MOSFET is off and the low-side diode conducts. The value of this ceramic capacitor should be 0.1 μF. TI recommends a ceramic capacitor with an X7R or X5R grade dielectric and a voltage rating of 10 V or higherbecauseofthestablecharacteristicsovertemperatureandvoltage. To improve dropout, the TPS54160-Q1 operates at 100% duty cycle as long as the BOOT-to-PH pin voltage is greater than 2.1 V. When the voltage from BOOT to PH drops below 2.1 V,a UVLO circuit turns off the high-side MOSFET, which allows the low-side diode to conduct and refresh the charge on the BOOT capacitor. Because the supply current sourced from the BOOT capacitor is low, the high-side MOSFET can remain on for more switching cycles than are required to refresh the capacitor; thus, the effective duty cycle of the switching regulatorishigh. iThe voltage drops across the power MOSFET, inductor resistance, low-side diode, and printed-circuit board resistance mainly influence the effective duty cycle during dropout of the regulator. During operating conditions in which the input voltage drops and the regulator is operating in continuous conduction mode, the high-side MOSFET can remain on for 100% of the duty cycle to maintain output regulation, until the BOOT-to-PH voltage fallsbelow2.1V. Pay attention in maximum-duty-cycle applications which experience extended time periods with light loads or no load.WhenthevoltageacrosstheBOOTcapacitorfallsbelowthe2.1-VUVLOthreshold,thehigh-sideMOSFET turns off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than2.1V.Theoutputcapacitorthendecaysuntilthedifferenceintheinputvoltageandoutputvoltageisgreater than 2.1 V, at this point exceeding the BOOT UVLO threshold, and the device starts switching again until the desired output voltage is reached. This operating condition persists until the input voltage and/or the load current increases. TI recommends adjusting the VIN stop voltage greater than the BOOT UVLO trigger condition at the minimumloadoftheapplication,usingtheadjustableVINUVLOfeaturewithresistorsontheENpin. Figure 26 and Figure 27 show the start and stop voltages for typical 3.3-V and 5-V output applications. The voltages are plotted versus load current. The start-voltage definition is the input voltage needed to regulate the output within 1%. The stop-voltage definition is the input voltage at which the output drops by 5% or stops switching. During high-duty-cycle conditions, the inductor-current ripple increases while the BOOT capacitor is being recharged, resulting in an increase in ripple voltage on the output. This is due to the recharge time of the boot capacitorbeinglongerthanthetypicalhigh-sideofftimewhenswitchingoccurseverycycle. 4 5.6 VO= 3.3 V VO= 5 V 3.8 5.4 V V Voltage - 3.6 Start Voltage - 5.2 Start V- Input I 3.4 Stop V- Input I 5 Stop 3.2 4.8 3 4.6 0 0.05 0.10 0.15 0.20 0 0.05 0.10 0.15 0.20 IO- Output Current -A IO- Output Current -A Figure26.3.3-VStartandStopVoltages Figure27.5-VStartandStopVoltages 14 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) Error Amplifier The TPS54160-Q1 has a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the SS/TR pin voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 97 μA/V during normal operation. During the slow-start operation, thetransconductanceisafractionofthenormaloperatinggm.WhenthevoltageoftheVSENSEpinisbelow0.8 VandthedeviceregulatesusingtheSS/TRvoltage,thegmis25μA/V. The frequency compensation components (capacitor, series resistor, and capacitor) are added to the COMP pin toground. Voltage Reference The voltage reference system produces a precise ±2% voltage reference over temperature by scaling the output ofatemperature-stableband-gapcircuit. Adjusting the Output Voltage A resistor divider from the output node to the VSENSE pin sets the output voltage. TI recommends using 1% tolerance or better divider resistors. Start with 10 kΩ for the R2 resistor and use Equation 1 to calculate R1. To improve efficiency at light loads, consider using larger-value resistors. If the values are too high, the regulator is moresusceptibletonoise,andvoltageerrorsfromtheVSENSEinputcurrentarenoticeable. V -0.8 V R1 = R2? OUT 0.8 V (1) Enable and Adjusting Undervoltage Lockout The VIN pin voltage falling below 2.5 V disables the TPS54160-Q1. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using two external resistors. Though it is not necessary to use the UVLO adjust resistors, for operation TI highly recommendsprovidingconsistentpower-upbehavior.TheENpinhasaninternalpullupcurrentsource,I1,of0.9 μA that provides the default condition of the TPS54160-Q1 operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, a compatrator adds an additional 2.9 μA of hysteresis, I . This additional current hys facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation3tosettheinputstartvoltage. TPS54160-Q1 VIN I HYS I1 R1 0.9mA 2.9mA + EN R2 1.25 V - Figure28. AdjustableUndervoltageLockout(UVLO) V -V R1= START STOP I HYS (2) V R2= ENA V -V START ENA +I R1 1 (3) Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) Figure 29 shows another technique to add input voltage hysteresis. One can use this method if the resistance values are high from the previous method and there is a need for wider voltage hysteresis. The resistor R3 sourcesadditionalhysteresiscurrentintotheENpin. TPS54160-Q1 VIN I HYS R1 I1 2.9mA 0.9mA + EN R2 1.25 V - VOUT R3 Figure29.AddingAdditionalHysteresis V -V R1= START STOP V I + OUT HYS R3 (4) V R2= ENA V -V V START ENA +I - ENA R1 1 R3 (5) Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if V > 5 V when using a voltage divider to adjust the start and stop voltage. EN The node voltage, (see Figure 30) must remain equal to or less than 5.8 V. The Zener diode can sink up to 100 μA. The EN pin voltage can be greater than 5 V if the V voltage source has a high impedance and does not IN sourcemorethan100μAintotheENpin. V IN I A R UVLO1 EN 10kW Node 3 I IB R C 5.8V UVLO2 UDG-10065 Figure30. NodeVoltage 16 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) Slow Start or Tracking Pin (SS/TR) The TPS54160-Q1 effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow-start time. The TPS54160-Q1 has an internal pullup current source of 2 μA that chargestheexternalslow-startcapacitor.Equation6showsthecalculationsfortheslow-starttime(10%to90%). The voltage reference (V ) is 0.8 V and the slow-start current (I ) is 2 μA. The slow-start capacitor should be REF SS lessthan0.47μFandgreaterthan0.47nF. T (ms)?I (mA) C (nF) = SS SS SS V (V)?0.8 REF (6) At power up, the TPS54160-Q1 does not start switching until the slow-start pin discharges to less than 40 mV; to ensureaproperpowerup,seeFigure31. Also, during normal operation, the TPS54160-Q1 stops switching and SS/TR must discharge to 40 mV on exceedingtheVINUVLO,pullingtheENpinbelow1.25V,orathermalshutdownevent. The VSENSE voltage follows the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference.WhentheSS/TRvoltageisgreaterthan85%ontheinternalreferencevoltage,theoffsetincreasesas the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure23).TheSS/TRvoltagerampslinearlyuntilclampedat1.7V. EN SS/TR V SENSE VOUT Figure31. OperationofSS/TRPinWhenStarting Overload Recovery Circuit The TPS54160-Q1 has an overload recovery (OLR) circuit. The OLR circuit slow-starts the output from the overload voltage to the nominal regulation voltage on removal of the fault condition. The OLR circuit discharges the SS/TR pin to a voltage slightly greater than the VSENSE pin voltage using an internal pulldown of 100 μA when the error amplifier is changed to a high voltage from a fault condition. On removal of the fault condition, the outputslow-startsfromthefaultvoltagetonominaloutputvoltage. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) Sequencing One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. One implementation of the sequential method uses the open-drain output of a power-on-reset pin of another device. Figure 32 illustrates the sequential method using two TPS54160-Q1 devices. The power-good output connects to the EN pin on the second TPS54160-Q1, which enables the second power supply once the primary supply reaches regulation. If needed, a 1-nF ceramic capacitor on the EN pin of the second power supplyprovidesa1-msstart-updelay.Figure33showstheresultsofFigure32. TPS54160-Q1 TPS54160-Q1 PWRGD EN EN PWRGD EN1 SS/TR SS/TR PWRGD1 VOUT1 VOUT2 Figure32.SchematicforSequentialStart-Up Figure33.SequentialStartupUsingENand Sequence PWRGD 18 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) TPS54160-Q1 3 EN EN1, EN2 4 SS/TR VOUT1 VOUT2 6 PWRGD TPS54160-Q1 3 EN 4 SS/TR 6 PWRGD Figure34.SchematicforRatiometricStart-Up Figure35.RatiometricStartupUsingCoupled UsingCoupledSS/TRPins SS/TRPins Figure 34 shows a method for ratiometric start-up sequence by connecting the SS/TR pins together. The regulatoroutputsrampupandreachregulationatthesametime.Whencalculatingtheslow-starttime,thepullup doublecurrentsourceinEquation6.Figure35showstheresultsofFigure34. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) TPS54160-Q1 EN VOUT1 SS/TR PWRGD TPS54160-Q1 EN VOUT2 R1 SS/TR R2 PWRGD R3 R4 Figure36. SchematicforRatiometricandSimultaneousStart-UpSequence One can implement ratiometric and simultaneous power supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 36 to the output of the power supply to track or to another voltage-reference source. Using Equation 7 and Equation 8, calculate the tracking resistors to initiate Vout2 slightly before, after, or at the same time as Vout1. Equation 9 is the voltage difference between Vout1 and Vout2 at the 95% point of nominal outputregulation. The ΔV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TR to VSENSE offset (Vssoffset) in the slow-start circuit and the offset created by the pullup current source (Iss) and trackingresistors,theequationsincludeVssoffsetandIssasvariables. To design a ratiometric start-up in which the Vout2 voltage is slightly greater than the Vout1 voltage when Vout2 reaches regulation, use a negative number in Equation 7 through Equation 9 for ΔV. Equation 9 results in a positivenumberforapplicationsinwhichVout2isslightlylowerthanVout1whenachievingVout2regulation. Because of the requirement to pull the SS/TR pin below 40 mV before starting after an EN, UVLO, or thermal- shutdown fault, careful selection of the tracking resistors is needed to ensure device restart after a fault. Make sure the calculated R1 value from Equation 7 is greater than the value calculated in Equation 10 to ensure the devicecanrecoverfromafault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, Vssoffset becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.3 V for a complete handoff to the internal voltage reference as shown in Figure23. V +DV V R1 = OUT2 ? SSOFFSET V I REF SS (7) V ? R1 R2 = REF V +DV-V OUT2 REF (8) DV = V -V OUT1 OUT2 (9) R1 > 2800?V -180?DV OUT1 (10) 20 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) EN EN VOUT1 VOUT1 VOUT2 VOUT2 Figure37.RatiometricStartupWithV Leading Figure38.RatiometricStartupWithV Leading OUT2 OUT1 V V OUT1 OUT2 EN VOUT1 VOUT2 Figure39.SimultaneousStartupWithTrackingResistor Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS54160-Q1 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 11 or the curves in Figure 40 or Figure 41. To reduce the solution size, one would typically set the switching frequency as high as possible, but consider tradeoffs of the supply efficiency, maximuminputvoltage,andminimumcontrollableon-time. Theminimumcontrollableon-timeistypically130nsandlimitsthemaximumoperatinginputvoltage. The frequency-shift circuit also limits the maximum switching frequency. More discussion on the details of the maximumswitchingfrequencyfollows. 206033 R (kW) = T f (kHz)1.0888 SW (11) SWITCHINGFREQUENCY SWITCHINGFREQUENCY versus versus RT/CLKRESISTANCE,HIGH-FREQUENCYRANGE RT/CLKRESISTANCE,LOW-FREQUENCYRANGE 2500 500 V= 12 V, I T = 25°C J V= 12 V, Hz 2000 Hz 400 TJI= 25°C witching Frequency - k 11050000 witching Frequency - k 230000 S S f- s 500 f- s 100 0 0 0 25 50 75 100 125 150 175 200 200 300 400 500 600 700 800 900 1000 1100 1200 RT/CLK - Clock Resistance - kW RT/CLK - Resistance - kW Figure40.High-RangeRT Figure41.Low-RangeRT Overcurrent Protection and Frequency Shift The TPS54160-Q1 implements current-mode control, which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle has a comparison of the switch current and COMP pin voltaged; when the peak switch current intersects the COMP voltage, the high-side switch turns off. During overcurrent conditions that pull the output voltage low, the error amplifier responds by driving the COMP pin high, increasing the switch current. There is an internal clamp on the error-amplifier output, which functions as a switch-current limit. To increase the maximum operating switching frequency at high input voltages, the TPS54160-Q1 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on theVSENSEpin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal start- up and fault conditions. Because the device can divide the switching frequency only by 8, there is a maximum input-voltagelimitatwhichthedeviceoperatesandcanmaintainfrequency-shiftprotection. Duringshort-circuitevents(particularlywithhigh-input-voltageapplications),thecontrolloophasafiniteminimum controllable on-time and the output has a low voltage. During the switch-on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on-time. During the switch-off time, the inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the ramp- upamount.Thefrequencyshifteffectivelyincreasestheoff-time,allowingthecurrenttorampdown. 22 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) Selecting the Switching Frequency The selected switching frequency should be the lower value of the two equations, Equation 12 and Equation 13. Equation 12 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switchingfrequencyabovethisvaluecausestheregulatortoskipswitchingpulses. Equation 13 is the maximum switching-frequency limit set by the frequency-shift protection. To have adequate output short-circuit protection at high input voltages, set the switching frequency to be less than the f sw(maxshift) frequency. In Equation 13, to calculate the maximum switching frequency one must take into account that as the output voltage decreases from the nominal voltage to 0 volts, the f integer increases from 1 to 8 corresponding div tothefrequencyshift. In Figure 42, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, the resistance of the inductor is 0.1 Ω, the FET on-resistance is 0.2 Ω, and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching frequency. æ ö 1 I ´R +V +V f = ´ç L dc OUT d ÷ SW(maxskip) t çV -I ´R +V ÷ ON è IN L DS(on) d ø (12) fSWshift = fDIV ´æçIL´Rdc +VOUT(sc)+Vd ö÷ tON ç VIN-IL´RDS(on)+Vd ÷ è ø (13) I Inductorcurrent L Rdc Inductorresistance V Maximuminputvoltage IN V Outputvoltage OUT V Outputvoltageduringshort OUTSC Vd Diodevoltagedrop R Switchon-resistance DS(on) t Controllableon-time ON ƒ Frequencydivide;equals(1,2,4,or8) DIV 2500 V = 3.3 V O kHz 2000 Shift y - c n ue 1500 q e Fr Skip g n hi 1000 c wit S - fs 500 0 10 20 30 40 50 60 VI- Input Voltage - V Figure42. MaximumSwitchingFrequencyversusInputVoltage Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) How to Interface to the RT/CLK Pin One can use the RT/CLK pin to synchronize the regulator to an external system clock. To implement the synchronization feature, connect a square wave to the RT/CLK pin through the circuit network shown in Figure 43. The square-wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin andhaveanon-timegreaterthan40nsandanoff-timegreaterthan40ns.Thesynchronizationfrequencyrange is 300 kHz to 2200 kHz. The rising edge of PH is synchronized to the falling edge of the RT/CLK pin signal. Design the external synchronization circuit in such a way that the device has the default-frequency-set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended to use a frequency-set resistor connected as shown in Figure 43 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. TI recommends to ac-couple the synchronization signal through a 10-pF ceramic capacitor to the RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy-load applications when synchronizing to an external clock and in applications which transition from synchronizing mode to RT mode. The first time CLK is pulled above the CLK threshold,thedeviceswitchesfromtheRTresistorfrequencytothePLLmode.Theinternal0.5-Vvoltagesource is removed and the CLK pin becomes high-impedance as the PLL starts to lock onto the external signal. Because there is a PLL on the regulator, the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreasestheswitchingfrequencyuntilthePLLlocksontotheCLKfrequencywithin100μs. When the device transitions from the PLL mode to the resistor mode, the switching frequency slows down from the CLK frequency to 150 kHz; then reapply the 0.5-V voltage and the resistor then sets the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 V to 0.8 V on the VSENSE pin. The device implements a digital-frequency shift to enable synchronizing to an external clock during normal start- up and fault conditions. Figure 44, Figure 45, and Figure 46show the device synchronized to an external system clock in continuous-conduction mode (CCM), discontinuous-conduction mode (DCM), and pulse-skip mode (PSM). TPS54160-Q1 10 pF 4 kW PLL R fset RT/CLK EXT Clock 50W Source Figure43. SynchronizingtoaSystemClock 24 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) EXT EXT VOUT IL PH PH IL Figure44.PlotofSynchronizinginCCM Figure45.PlotofSynchronizinginDCM EXT IL PH Figure46.PlotofSynchronizinginPSM Power-Good (PWRGD Pin) The PWRGD pin is an open-drain output. Once the VSENSE pin is between 94% and 107% of the internal voltage reference, de-assertion of the PWRGD pin occurs, and the pin floats. TI recommends using a pullup resistor between the values of 1 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. PWRGD is in a defined state once the VIN input voltage is greater than 1.5 V, but with reduced current-sinking capability. PWRGD achievesfullcurrent-sinkingcapabilityastheVINinputvoltageapproaches3V. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) ThePWRGDpinispulledlowwhentheVSENSEislowerthan92%orgreaterthan109%ofthenominalinternal referencevoltage.Also,PWRGDispulledlowifUVLOorthermalshutdownisassertedorENispulledlow. Overvoltage Transient Protection The TPS54160-Q1 incorporates an overvoltage-transient protection (OVTP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power-supply designs with low-value output capacitance. For example, with the power-supply output overloaded, the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier responds by clamping the error- amplifier output to a high voltage, thus requesting the maximum output current. On removal of the condition, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power-supply output voltage can respond faster than the error-amplifier output can respond; this actuality leads to the possibility of an output overshoot. The OVTP feature minimizes the output overshoot, when using a low-value output capacitor, by implementing a circuit to compare the VSENSE pin voltage to OVTP threshold, which is 109% of the internal voltage reference. The VSENSE pin voltage rising above the OVTP threshold disables the high-side MOSFET, preventing current from flowing to the output and minimizing output overshoot. The VSENSE voltage dropping below the OVTP threshold allows the high-side MOSFET to turn on at thenextclockcycle. Thermal Shutdown The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 182°C. The thermal shutdown forces the device to stop switching when the junction temperature exceeds the thermal trip threshold. Once the die temperature decreases below 182°C, the device reinitiates the power-up sequence bydischargingtheSS/TRpin. Small-Signal Model for Loop Response Figure 47 shows an equivalent model for the TPS54160-Q1 control loop, which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm of 97 μA/V. One can model the error amplifier using an ideal voltage- EA controlledcurrentsource.ResistorR andcapacitorC modeltheopen-loopgainandfrequencyresponseofthe O O amplifier. The 1-mV ac voltage source between nodes a and b effectively breaks the control loop for the frequency-response measurements. Plotting c / a shows the small-signal response of the frequency compensation. Plotting a / b shows the small-signal response of the overall loop. One can check the dynamic loop response by replacing R with a current source with the appropriate load-step amplitude and step rate in a L time-domainanalysis.Thisequivalentmodelisonlyvalidforcontinuous-conduction-modedesigns. 26 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) PH V Power Stage O gm 6A/V ps a b R1 RESR R COMP L c VSENSE C 0.8 V OUT R3 C2 CO RO gmea R2 97mA/V C1 Figure47. Small-SignalModelforLoopResponse Simple Small-Signal Model for Peak-Current-Mode Control Figure 48 describes a simple small-signal model that one can use to understand how to design the frequency compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor can approximate the TPS54160-Q1 power stage. Equation 14 shows the control-to- output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 47) is the power-stage transconductance. The gm for the TPS54160-Q1 is 6 A/V. The low-frequency gain of the power-stage PS frequencyresponseistheproductofthetransconductanceandtheloadresistanceasshowninEquation15. Astheloadcurrentincreasesanddecreases,thelow-frequencygaindecreasesandincreases,respectively.This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 16). The dashed line in the right half of Figure 48 highlights the combined effect. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequencythesameforthevaryingloadconditions,whichmakesiteasiertodesignthefrequencycompensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency- compensation design. Using high-ESR aluminum electrolytic capacitors may reduce the number of frequency- compensation components needed to stabilize the overall loop, because the phase margin increases from the ESRzeroatthelowerfrequencies(seeEquation17). V O VC Adc R ESR fp R L gm ps C OUT fz Figure48.SimpleSmall-SignalModelandFrequencyResponseforPeak-Current-ModeControl Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com DETAILED DESCRIPTION (continued) æ s ö ç1+ ÷ VOUT = Adc´è 2p´fZ ø V æ s ö C ç1+ ÷ è 2p´fP ø (14) Adc=gm ´ R ps L (15) 1 f = P C ´R ´2p OUT L (16) 1 f = Z C ?R ?2p OUT ESR (17) Small-Signal Model for Frequency Compensation The TPS54160-Q1 uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Figure 49 shows compensation circuits Type 2A, Type 2B, and Type 1. Type 2 circuit implementation is most likely in high-bandwidth power-supply designs using low-ESR outputcapacitors.TheType1circuitisforpower-supplydesignswithhigh-ESRaluminumelectrolyticortantalum capacitors.Equation18andEquation19showhowtorelatethefrequencyresponseoftheamplifiertothesmall- signal model in Figure 49. Modeling of the open-loop gain and bandwidth uses R and C , shown in Figure 49. O O SeetheapplicationsectionforadesignexampleusingaType2Anetworkwithalow-ESRoutputcapacitor. Those who prefer to compensate using the preferred methods should see Equation 18 through Equation 27 as a reference.ThosewhoprefertousetheprescribedmethodusethemethodoutlinedintheApplicationInformation sectionoruseswitchedinformation. V O R1 VSENSE gm Type 2A Type 2B Type 1 ea COMP Vref R3 C2 R3 R2 RO CO C2 C1 C1 Figure49. TypesofFrequencyCompensation 28 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 DETAILED DESCRIPTION (continued) Aol P1 A0 Z1 P2 A1 BW Figure50. FrequencyResponseoftheType2AandType2BFrequencyCompensation Aol(V/V) Ro= gm ea (18) gm C = ea OUT 2p ´ BW (Hz) (19) æ s ö ç1+ ÷ è 2p´fZ1ø EA = A0´ æ s ö æ s ö ç1+ ÷´ç1+ ÷ è 2p´fP1ø è 2p´fP2 ø (20) R2 A0=gm ´ Ro ´ ea R1+R2 (21) R2 A1=gm ´ Ro||R3 ´ ea R1+R2 (22) 1 P1= 2p´Ro´C1 (23) 1 Z1= 2p´R3´C1 (24) 1 P2= type2a 2p ´ R3||R ´ (C2+C ) OUT (25) 1 P2= type2b 2p ´ R3||R ´ C OUT (26) 1 P2= type1 2p ´ R ´ (C2+C ) OUT (27) Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com APPLICATION INFORMATION Design Guide — Step-By-Step Design Procedure This example details the design of a high-frequency switching-regulator design using ceramic output capacitors. One must know a few parameters to start the design process. Determination of these parameters is typically at thesystemlevel.Forthisexample,startwiththefollowingknownparameters: Outputvoltage 3.3V Transientresponse,0to1.5-Aloadstep ΔVout=4% Maximumoutputcurrent 1.5A Inputvoltage 12V(nom),8Vto18V Output-voltageripple <33mV pp Startinputvoltage(risingVIN) 7.25V Stopinputvoltage(fallingVIN) 6.25V Selecting the Switching Frequency The first step is to decide on a switching frequency for the regulator. Typically, the user wants to choose the highest switching frequency possible, because this produces the smallest solution size. The high switching frequency allows for lower-valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The minimum on-time of the internal power switch, the input voltage, the output voltage,andthefrequency-shiftlimitationlimittheselectableswitchingfrequency. Use Equation 12 and Equation 13 to find the maximum switching frequency for the regulator; choose the lower value of the two equations. Switching frequencies higher than these values result in pulse skipping or the lack of overcurrentprotectionduringashortcircuit. The typical minimum on-time (t ) is 130 ns for the TPS54160-Q1. For this example, the output voltage is 3.3 onmin V and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz when including the inductor resistance, on-resistance, and diode voltage in Equation 12. To ensure overcurrent runaway in your design is not a concern during short circuits, use Equation 13 or the solid curve in Figure 42 to determine the maximum switching frequency. With a maximum input voltage of 20 V, for some margin above 18 V, assuming a diode voltage of 0.5 V, inductor resistance of 100 mΩ, switch resistance of 200 mΩ, a current- limitvalueof2.7A,themaximumswitchingfrequencyisapproximately2500kHz. Choosing the lower of the two values and adding some margin, a switching frequency of 1200 kHz is used. To determinethetimingresistanceforagivenswitchingfrequency,useEquation11orthecurveinFigure40. ResistorRT,showninFigure51,setstheswitchingfrequency. L1 10mH C1 0.1mF 3.3 V at 1.5A U1 D1 + COUT TPS54160DGQ B220A 47mF/6.3 V 8 - 18 V BOOT PH VIN GND C2 C3 C4 R3 EN COMP 2.2mF 2.2mF 0.1mF 332 kW RSTS//CTLRKPwPdPWVRSGNDS 6.8 CpFF 7R6C.8 kW 3R11.6 kW CSS RT R4 0.01mF 90.9 kW CC R2 61.9 kW 2700 pF 10 kW Figure51. High-Frequency,3.3-VOutputPower-SupplyDesignWithAdjustedUVLO 30 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 Output Inductor Selection (L ) O Tocalculatetheminimumvalueoftheoutputinductor,useEquation28. K isacoefficientthatrepresentstheamountofinductorripplecurrentrelativetothemaximumoutputcurrent. IND The output capacitor filters the inductor ripple current. Therefore, choosing high inductor ripple currents impacts the selection of the output capacitor, because the output capacitor must have a ripple-current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however,thefollowingguidelinesmaybeused. For designs using low-ESR output capacitors such as ceramics, one may use a value as high as K = 0.3. IND When using higher-ESR output capacitors, K = 0.2 yields better results. Because the inductor ripple current is IND part of the PWM control system, the inductor ripple current should always be greater than 100 mA for dependable operation. In a wide-input-voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use K = 0.2 and the minimum calculated inductor value is 7.6 μH. For this design, IND the nearest standard value was chosen: 10 μH. For the output-filter inductor, it is important not to exceed the rms-current and saturation-current ratings. One can find the rms and peak inductor current from Equation 30and Equation31. For this design, the rms inductor current is 1.506 A and the peak inductor current is 1.62 A. The chosen inductor isaMSS6132-103.Ithasasaturation-currentratingof1.64Aandanrms-currentratingof1.9A. As the equation set demonstrates, lower ripple currents reduce the output-voltage ripple of the regulator but require a larger value of inductance. Selecting higher ripple currents increases the output voltage ripple of the regulatorbutallowsforalowerinductancevalue. The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults, or transient load conditions, the inductor current can increase above the calculated peak inductor-current level previously calculated. In transient conditions, the inductor current can increase up to the switch-current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current ratingequaltoorgreaterthantheswitch-currentlimitratherthanthepeakinductorcurrent. Vinmax - Vout Vout Lomin= ´ Io ´ K Vinmax ´ ƒsw IND (28) I £I ´K RIPPLE O IND (29) 2 I = (I )2 + 1 ´æçVOUT ´ (Vinmax - VOUT)ö÷ L(rms) O 12 ç Vinmax ´ L ´ f ÷ è O SW ø (30) I I = I + RIPPLE LPeak OUT 2 (31) Output Capacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output-voltage ripple, and how the regulator responds to a large change in loadcurrent.Selecttheoutputcapacitancebasedonthemost-stringentofthesethreecriteria. The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also temporarily is not able to supply sufficient output current if there is a large fast increase in the current needs of the load, such as transitioning from no load to a full load. The regulator usually requires two or more clock cycles for the control loop to see the change in load current and output voltage and then adjust the duty cycle to react to the change. The output capacitor size must be able to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for two clock cycles, while only allowing a tolerable amount of droop in the output voltage. Equation 32 shows the minimum output capacitance necessarytoaccomplishthis. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com Where ΔI is the change in output current, ƒsw is the regulator switching frequency, and ΔV is the allowable out out change in the output voltage. For this example, the specified transient-load response is a 4% change in Vout for a load step from 0 A (no load) to 1.5 A (full load). For this example, ΔI = 1.5 – 0 = 1.5 A and out ΔV =0.04× 3.3=0.132V.Usingthesenumbersgivesaminimumcapacitanceof18.9μF.Thisvaluedoesnot out take the ESR of the output capacitor into account in the output-voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESRthatshouldbetakenintoaccount. The catch diode of the regulator cannot sink current, so any stored energy in the inductor produces an output- voltage overshoot when the load current rapidly decreases (see Figure 52). The output capacitor size must be able to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that is stored in the output capacitor increases the voltage on the capacitor. The capacitor mustbesizedtomaintainthedesiredoutputvoltageduringthesetransientperiods.UseEquation33tocalculate the minimum capacitance to keep the output voltage overshoot to a desired value, where L is the value of the inductor, I is the output current under heavy load, I is the output under light load, VF is the final peak output OH OL voltage, and Vi is the initial capacitor voltage. For this example, the worst-case load step us from 1.5 A to 0 A. The output voltage increases during this load transition, and the stated maximum in our specification is 4% of the output voltage. This makes Vf = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage, which is the nominal output voltageof3.3V.UsingthesenumbersinEquation33yieldsaminimumcapacitanceof25.3 μF. Equation 34 calculates the minimum output capacitance needed to meet the output-voltage ripple specification, where f is the switching frequency, V is the maximum allowable output-voltage ripple, and I is the sw oripple ripple inductorripplecurrent.Equation35yields0.7 μF. Equation 35 calculates the maximum ESR an output capacitor can have to meet the output-voltage ripple specification.Equation35indicatestheESRshouldbelessthan147mΩ. The most stringent criterion for the output capacitor is 25.3 μF of capacitance to keep the output voltage in regulationduringanunloadtransient. Additional capacitance de-ratings for aging, temperature, and dc bias should be factored in, which increases this minimumvalue.Forthisexample,a47-μF6.3-VX7Rceramiccapacitorwith5-mΩ ESRisused. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. Select an output capacitor that can support the inductor ripple current. Some capacitor data sheets specify the root-mean-square (rms) value of the maximum ripple current. Use Equation 36 to calculate the rms ripplecurrentthattheoutputcapacitormustsupport.Forthisapplication,Equation36yields64.8mA. 2´DI C > OUT OUT fSW ´DVOUT (32) ( 2 2) (IOH) -(IOL) COUT >LO´ ( 2 2) (Vf) -(Vi) (33) 1 1 C > ´ OUT 8´ fSW æVOUT(ripple)ö ç ÷ ç I ÷ è RIPPLE ø (34) 32 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 V OUT(ripple) R = ESR I RIPPLE (35) ( ) V ´ V -V OUT IN(max) OUT I = COUT(rms) 12´V ´L ´ f IN(max) O SW (36) Catch Diode The TPS54160-Q1 requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than V . The peak-current rating of the diode must be inmax greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of thediode,thehighertheefficiencyoftheregulator. Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage. Because the designexamplehasaninputvoltageupto18V,adiodewithaminimumof20-Vreversevoltageisselected. For the example design, the B220A Schottky diode is selected for its lower forward voltage, and it comes in a larger package size, which has good thermal characteristics compared with smaller devices. The typical forward voltageoftheB220Ais0.5V. The diode selection must also be based on an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode, which equals the conduction losses of the diode. At higher switch frequencies, one must take into account the ac losses of the diode. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Use Equation 37 to calculate the totalpowerdissipation,conductionlossesplusaclosses,ofthediode. The B220A has a junction capacitance of 120 pF. Using Equation 37, the selected diode dissipates 0.632 W. This power dissipation, depending on mounting techniques, should produce a 16°C temperature rise in the diode whentheinputvoltageis18Vandtheloadcurrentis1.5A. If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diodewhichhasalowleakagecurrentandslightlyhigherforwardvoltagedrop. ( ) VIN(max)-VOUT ´ IOUT´Vfd Cj´ fSW ´(VIN+Vfd)2 P = + D V 2 IN(max) (37) Input Capacitor The TPS54160-Q1 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3-μF effective capacitance and, in some applications, a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS54160- Q1.OnecancalculatetheinputripplecurrentusingEquation38. The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. One can minimize the capacitance variations due to temperature by selecting a dielectric material that is stable over temperature. Designers usually select X5R and X7R ceramic dielectrics for power-regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. Also select the output capacitor with the dc bias taken into account. The capacitance value of a capacitor decreases asthedcbiasacrossacapacitorincreases. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com This example design requires a ceramic capacitor with at least a 20-V voltage rating to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, and 100 V, so select a 25-V capacitor. The selection for this example is two 2.2-μF 25-V capacitors in parallel. Table 1 shows a selection of high-voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. One can calculate the input voltage ripple using Equation 39. Using the design example values, I = 1.5 A, C = 4.4 μF, ƒ = 1200 kHz, yields an input voltage ripple of 71 mV and an rms input outmax in sw ripplecurrentof0.701A. Vout (Vinmin - Vout) Icirms=Iout ´ ´ Vinmin Vinmin (38) Ioutmax ´ 0.25 ΔVin= Cin ´ ¦sw (39) Table1.CapacitorTypes VENDOR VALUE(μF) EIASIZE VOLTAGE DIELECTRIC COMMENTS 1to2.2 100V 1210 GRM32series 1to4.7 50V Murata 1 100V 1206 GRM31series 1to2.2 50V 1101.8 50V 2220 1to1.2 100V Vishay VJX7Rseries 1to3.9 50V 2225 1to1.8 100V X7R 1to2.2 100V 1812 CseriesC4532 1.5to6.8 50V TDK 1to2.2 100V 1210 CseriesC3225 1to3.3 50V 1to4.7 50V 1210 1 100V AVX X7Rdielectricseries 1to4.7 50V 1812 1to2.2 100V Slow-Start Capacitor The slow-start capacitor determines the minimum amount of time required for the output voltage to reach its nominal programmed value during power up. A slow-start capacitor is useful if a load requires a controlled voltage slew rate. A slow-start capacitor is also used if the output capacitance is large and would require large amounts of current to charge the capacitor quickly to the output-voltage level. The large currents necessary to charge the capacitor may make the TPS54160-Q1 reach the current limit, or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output-voltage slew rate solves both of theseproblems. The slow-start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. On can use Equation 40 to find the minimum slow-start time, t , ss necessary to charge the output capacitor, C , from 10% to 90% of the output voltage, Vout, with an average out slow-start current of I . In the example, to charge the 47-μF output capacitor up to 3.3 V while only allowing ssavg theaverageinputcurrenttobe0.125Arequiresa1-msslow-starttime. Once the slow-start time is known, one can calculate the slow-start capacitor value using Equation 6. For the examplecircuit,theslow-starttimeisnottoocritical,becausetheoutputcapacitorvalueis47μF,whichdoesnot require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of 1 ms,whichrequiresa3.3-nFcapacitor. C ?V ?0.8 T > OUT OUT SS I SSAVG (40) 34 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 Bootstrap Capacitor Selection Proper operation requires a 0.1-μF ceramic capacitor connected between the BOOT and PH pins. TI recommends using a ceramic capacitor with X5R or better-grade dielectric. The capacitor should have a 10-V or highervoltagerating. Undervoltage Lockout (UVLO) Set Point One can adjust the UVLO using an external voltage divider on the EN pin of the TPS54160-Q1. The UVLO has twothresholds,oneforpowerupwhentheinputvoltageisrisingandoneforpowerdownorbrownoutswhenthe input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.25 V (enabled). After the regulator starts switching, it should continue to do so until theinputvoltagefallsbelow6.25V(UVLOstop). TheprogrammableUVLOandenablevoltagesaresetusingaresistordividerbetweenVinandgroundtotheEN pin. Use Equation 2 through Equation 3 to calculate the resistance values necessary. The example application requires 332 kΩ between Vin and EN and 61.9 kΩ between EN and ground to produce the 7.25-V and 6.25-V startandstopvoltages. Output Voltage and Feedback Resistors Selection Fortheexampledesign,theR2selectionwas10.0kΩ.UsingEquation1,thecalculatedvalueofR1is31.25kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values decreases quiescentcurrentandimprovesefficiencyatlowoutputcurrents,butmayintroducenoiseimmunityproblems. Compensation There are several industry techniques used to compensate dc-dc regulators. The method presented here yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54160-Q1. Ignoring the slope compensation results in an actual crossover frequency that is usually lower than the crossover frequencyusedinthecalculations. UseSwitcherProsoftwareforamoreaccuratedesign. The uncompensated regulator has a dominant pole, typically located between 300 Hz and 3 kHz due to the output capacitor and load resistance, and a pole due to the error amplifier. One zero exists due to the output capacitorandtheESR.Thezero-frequencyishigherthaneitherofthetwopoles. Ifleftuncompensated,thedoublepolecreatedbytheerroramplifierandthemodulatorwouldleadtoanunstable regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a compensating zero at the modulator pole. Then select a crossover frequency that is higher than the modulator pole. One can calculate the gain of the error amplifier to achieve the desired crossover frequency. The capacitor used to create the compensation zero, along with the output impedance of the error amplifier, form a low- frequency pole to provide a –1 slope through the crossover frequency. Then the addition of a compensating pole cancels the zero due to the output-capacitor ESR. Ignore an ESR zero that resides at a frequency higher than theswitchingfrequency. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com To compensate the TPS54160-Q1 using this method, first calculate the modulator pole and zero using the followingequations: I OUT(max) f = P(mod) 2´p´VOUT´COUT (41) where I isthemaximumoutputcurrent. OUT(max) C istheoutputcapacitance. OUT V isthenominaloutputvoltage. OUT 1 f = Z(mod) 2´p´RESR´COUT (42) Fortheexampledesign,themodulatorpolelocationis1.5kHzandtheESRzerolocationis338kHz. Next, the designer selects a crossover frequency which determines the bandwidth of the control loop. The crossover-frequency location must be at a frequency at least five times higher than the modulator pole. The crossover frequency selection must also be such that the available gain of the error amplifier at the crossover frequencyishighenoughtoallowforpropercompensation. Use Equation 47 to calculate the maximum crossover frequency when the ESR-zero location is at a frequency that is higher than the desired crossover frequency. This usually is the case for ceramic or low-ESR tantalum capacitors. Aluminum electrolytic and tantalum capacitors typically produce a modulator zero at a low frequency duetotheirhighESR. Theexampleapplicationusesalow-ESRceramiccapacitorwith10mΩ ofESR,makingthezeroat338kHz. This value is much higher than typical crossover frequencies, so the maximum crossover frequency is calculated usingbothEquation43andEquation46. Using Equation 46 gives a minimum crossover frequency of 7.6 kHz and Equation 43 gives a maximum crossoverfrequencyof45.3kHz. Anarbitrarycrossover-frequencyselectionfromthisrangeis45kHz. ForceramiccapacitorsuseEquation43: f P(mod) f £2100 C(max) V OUT (43) FortantalumoraluminumcapacitorsuseEquation44: 51442 f £ C(max) V OUT (44) ForallcasesuseEquation45andEquation46: fSW f £ C(max) 5 (45) f ³5´ f C(min) P(mod) (46) After selecting a crossover frequency, f , one can calculate the gain of the modulator at the crossover frequency C usingEquation47. gm ´R ´(2p´ f ´C ´R +1) (PS) LOAD C OUT ESR G = MOD(fc) 2p´ f ´C ´(R +R )+1 C OUT LOAD ESR (47) 36 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 For the example problem, the gain of the modulator at the crossover frequency is 0.542. Next, calculate the compensation components. Use of a resistor in series with a capacitor creates a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on whether the ESR-zero location is above or below the crossover frequency. For ceramic or low-ESR tantalum output capacitors, the zero location is usually above the crossover frequency. For aluminum electrolytic and tantalum capacitors, the modulator zero location is usually lower in frequency than the crossover frequency. For cases where the modulator zero is higher than the crossover frequency (ceramic capacitors),theequationsare: V R = OUT C G ´gm ´V MOD(fc) (EA) REF (48) 1 CC = 2p´RC´ fP(mod) (49) C ´R Cf = OUT ESR R C (50) For cases where the modulator zero is less than the crossover frequency (aluminum or tantalum capacitors), the equationsare: V R = OUT C G ´ f ´gm ´V MOD(fc) Z(mod) (EA) REF (51) 1 CC = 2p´RC´ fP(mod) (52) 1 Cf = 2p´RC´ fZ(mod) (53) For the example problem, the ESR zero is located at a higher frequency compared to the crossover frequency, so Equation 50 through Equation 53 are used to calculate the compensation components. In this example, the calculatedcomponentsvaluesare: • R =76.2kΩ C • C =2710pF C • Cf=6.17pF The calculated value of the Cf capacitor is not a standard value, so use a value of 2700 pF. Use 6.8 pF for C . C The R resistor sets the gain of the error amplifier, which determines the crossover frequency. The calculated R C C resistorisnotastandardvalue,souse76.8kΩ. APPLICATION CURVES Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com VIN VO VOUT IO EN IL Figure52.LoadTransmit Figure53.StartupWithEN VOUT VOUT IL PH VIN IL Figure54.VINPowerUp Figure55.OutputRipple,CCM VOUT VOUT IL IL PH PH Figure56.OutputRipple,DCM Figure57.OutputRipple,PSM 38 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 VIN VIN IL IL PH PH Figure58.InputRipple,CCM Figure59.InputRipple,DCM 95 VI= 8 V VO= 3.3 V, 90 fsw= 1200 kHz VIN 85 80 IL cy - % 75 VI= 12 V VI= 16 V n e ci 70 Effi 65 PH 60 55 50 0 0.25 0.50 0.75 1 1.25 1.5 1.75 2 IL- Load Current -A Figure60.InputRipple,PSM Figure61.EfficiencyversusLoadCurrent 60 1.015 150 V= 12 V I 1.010 40 100 Phase 1.005 50 20 %) Gain - dB 0 Gain 0 oPhase - gulation ( 1.000 -50 Re 0.995 -20 -100 0.990 -150 -40 0.985 100 1-103 1-104 1-105 1-106 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 f - Frequency - Hz Load Current -A Figure62.OverallLoopFrequencyResponse Figure63.RegulationversusLoadCurrent Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com 1.015 I = 0.5A O 1.010 1.005 %) n ( atio 1.000 ul g e R 0.995 0.990 0.985 5 10 15 20 VI- Input Voltage - V Figure64.RegulationversusInputVoltage 40 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 Power Dissipation The following formulas show how to estimate power dissipation under continuous-conduction mode (CCM) operation.Donotusetheseequationsifthedeviceisworkingindiscontinuous-conductionmode(DCM). The power dissipation of the device includes conduction loss (P ), switching loss (P ), gate-drive loss (P ), con sw gd andsupply-currentloss(P ). q P = I 2× R × (V / V ) con O DS(on) OUT IN (54) P = V 2× f × I × 0.25×10–9sec/V SW IN SW O (55) P = V × 3×10–9Asec × f gd IN SW (56) P = 116µA× V q IN (57) where: I istheoutputcurrent(A). OUT r istheon-resistanceofthehigh-sideMOSFET(Ω). DS(on) V istheoutputvoltage(V). OUT V istheinputvoltage(V). IN f istheswitchingfrequency(Hz). sw So P = P + P + P + P tot con SW gd q (58) ForagivenT , A T =T +q × P J A JA tot (59) ForagivenT =150°C J(MAX) T =T –q × P A(MAX) J(MAX) JA tot (60) where: P isthetotaldevicepowerdissipation(W). tot T istheambienttemperature(°C). A T isthejunctiontemperature(°C). J θ isthethermalresistanceofthepackage(°C/W). JA T ismaximumjunctiontemperature(°C). J(MAX) T ismaximumambienttemperature(°C). A(MAX) There are additional power losses in the regulator circuit due to the inductor ac and dc losses, the catch diode, andtraceresistancethatimpacttheoverallefficiencyoftheregulator. Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 SLVS922F–JULY2009–REVISEDMARCH2013 www.ti.com Layout Layout is a critical portion of good power-supply design. There are several signals paths that conduct fast- changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, bypass the VIN pin to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by thebypass-capacitorconnections,theVINpin,andtheanodeofthecatchdiode.SeeFigure65foraPCBlayout example.TietheGNDpindirectlytothethermalpadandtheIC. Connect the thermal pad to any internal PCB ground planes using multiple vias directly under the IC. Route the PH pin to the cathode of the catch diode and to the output inductor. Because the PH connection is the switching node, locate the catch diode and output inductor close to the PH pins, and minimize the area of the PCB conductor to prevent excessive capacitive coupling. For operation at full-rated load, the top-side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise, so locate the RT resistor as close as possible to the IC, and route the traces to minimize their lengths. Place the additional external components approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layout.However,thislayout,providedforuseasaguideline,producesgoodresults. Vout Output Capacitor Output Topside Inductor Ground Route Boot Capacitor Catch Area Trace on another layer to Diode provide wide path for topside ground Input Bypass Capacitor BOOT PH Vin VIN GND EN COMP UVLO Adjust SS/TR VSENSE Compensation Resistor Resistors Network RT/CLK PWRGD Divider Slow Start Frequency Thermal VIA Capacitor Set Resistor Signal VIA Figure65. PCBLayoutExample 42 SubmitDocumentationFeedback Copyright©2009–2013,TexasInstrumentsIncorporated ProductFolderLinks:TPS54160-Q1

TPS54160-Q1 www.ti.com SLVS922F–JULY2009–REVISEDMARCH2013 Figure66. WideInputVoltageDesign Copyright©2009–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:TPS54160-Q1

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