Product Sample & Technical Tools & Support & Folder Buy Documents Software Community TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 TPS54061 Wide Input 60-V, 200-mA Synchronous Step-Down DC-DC Converter With Low IQ 1 Features 3 Description • IntegratedHigh-SideandLow-SideMOSFET The TPS54061 device is a 60-V, 200-mA, 1 synchronous step-down DC-DC converter with • DiodeEmulationforImprovedLightLoad integrated high-side and low-side MOSFETs. Current Efficiency mode control provides simple external compensation • PeakCurrentModeControl and flexible component selection. The non-switching • 90-µAOperatingQuiescentCurrent supply current is 90 µA. Using the enable pin, shutdownsupplycurrentisreducedto1.4 µA. • 1.4-µAShutdownSupplyCurrent To increase light load efficiency the low-side • 50-kHzto1100-kHzAdjustableSwitching MOSFET emulates a diode when the inductor current Frequency reacheszero. • SynchronizestoExternalClock Under voltage lockout is internally set at 4.5 V, but • InternalSlow-Start can be increased using two resistors on the enable • 0.8V±1%VoltageReference pin. The output voltage startup ramp is controlled by • StableWithCeramicOutputCapacitorsorLow- theinternalslow-starttime. CostAluminumElectrolytic The adjustable switching frequency range allows • Cycle-by-CycleCurrentLimit,Thermal,OVPand efficiency and external component size to be FrequencyFoldbackProtection optimized. Frequency foldback and thermal shutdown • VSON-8Package,3mm ×3mmWithThermal protectsthepartduringanoverloadcondition. Pad The TPS54061 enables small designs by integrating • –40°Cto150°COperatingJunctionTemperature the MOSFETs, boot recharge diode, and minimizing the IC footprint with a small 3.00 mm x 3.00 mm 2 Applications thermallyenhancedVSONpackage • 4to20-mACurrent-LoopPoweredSensors The TPS54061 is supported in the WEBENCH™ Designeratwww.ti.com. • LowPowerStandbyorBiasVoltageSupplies • IndustrialProcessControl,Metering,andSecurity DeviceInformation(1) Systems PARTNUMBER PACKAGE BODYSIZE(NOM) • HighEfficiencyReplacementforHighVoltage TPS54061 VSON(8) 3.00mmx3.00mm LinearRegulators (1) For all available packages, see the orderable addendum at theendofthedatasheet. SimplifiedSchematic EfficiencyvsLoadCurrent 100 VIN VVVIIINNN BOOT VIN= 12 V 90 TPS54061 80 EN PH VOUT 70 %) 60 RT /CLK ncy ( 50 e VSNS Effici 40 COMP 30 GND PowerPAD 20 VOUT= 5 V,fSW= 50 kHz V = 5 V,f = 400 kHz 10 OUT SW V = 3.3 V,f = 400 kHz OUT SW 0 0.001 0.010 0.100 Load Current (A) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com Table of Contents 1 Features.................................................................. 1 7.3 FeatureDescription.................................................11 2 Applications........................................................... 1 7.4 DeviceFunctionalModes........................................15 3 Description............................................................. 1 8 ApplicationandImplementation........................ 16 4 RevisionHistory..................................................... 2 8.1 ApplicationInformation............................................16 8.2 TypicalApplications................................................16 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 30 6 Specifications......................................................... 4 10 Layout................................................................... 30 6.1 AbsoluteMaximumRatings......................................4 6.2 ESDRatings..............................................................4 10.1 LayoutGuidelines.................................................30 6.3 RecommendedOperatingConditions.......................4 10.2 LayoutExample....................................................30 6.4 ThermalInformation..................................................4 11 DeviceandDocumentationSupport................. 31 6.5 ElectricalCharacteristics..........................................5 11.1 Trademarks...........................................................31 6.6 TypicalCharacteristics..............................................7 11.2 ElectrostaticDischargeCaution............................31 7 DetailedDescription............................................ 10 11.3 Glossary................................................................31 7.1 Overview.................................................................10 12 Mechanical,Packaging,andOrderable Information........................................................... 31 7.2 FunctionalBlockDiagram.......................................11 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionD(December2014)toRevisionE Page • ChangedPH,10nsTransientMINvalueintheAbsoluteMaximumRatingsFrom:–2VTo:–4V....................................... 4 • MovedStoragetemperature,T From:ESDRatingsTo:AbsoluteMaximumRatings........................................................ 4 stg • ChangedHandlingRatingstableTo:ESDRatingstable....................................................................................................... 4 ChangesfromRevisionC(September2013)toRevisionD Page • AddedPinConfigurationandFunctionssection,HandlingRatingtable,FeatureDescriptionsection,Device FunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layout section,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation section ................................................................................................................................................................................... 1 • ChangedY-axisvalueµA/VtoµS.......................................................................................................................................... 8 ChangesfromRevisionB(January2013)toRevisionC Page • ChangedRT/CLKfallingedgetoPHrisingedgedelayFrom:130nsTo:60ns................................................................... 5 ChangesfromRevisionA(May2012)toRevisionB Page • ChangedtheEfficiencyvsLoadCurrentgraph...................................................................................................................... 1 • ChangedPinConfigurationgraphicforclarificationofthermalpad....................................................................................... 3 ChangesfromOriginal(May2012)toRevisionA Page • Changedtitlefrom"4.7Vto60VInput....."to"WideInput...."andremoved"ProductPreview"banner................................ 1 2 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 5 Pin Configuration and Functions VSONPACKAGE 8PINS BOTTOMVIEW PH 8 1 BOOT Thermal Pad (9) GND 7 2 VIN COMP 6 See appended 3 EN Mechanical Data for VSENSE 5 size and shape 4 RT/CLK PinFunctions PIN I/O DESCRIPTION NAME NUMBER AbootstrapcapacitorisrequiredbetweenBOOTandPH.Ifthevoltageonthiscapacitorisbelow BOOT 1 O theminimumrequiredbytheoutputdevice,theoutputisforcedtoswitchoffuntilthecapacitoris refreshed. VIN 2 I Inputsupplyvoltage,4.7Vto60V. Enablepinwithinternalpull-upcurrentsource.Pullbelow1.18Vtodisable.Floattoenable.Adjust EN 3 I theinputundervoltagelockout(UVLO)withtworesistors,seetheEnableandAdjusting UndervoltageLockoutsection. ResistorTimingandExternalClock.Aninternalamplifierholdsthispinatafixedvoltagewhen usinganexternalresistortogroundtosettheswitchingfrequency.IfthepinispulledabovethePLL upperthreshold,amodechangeoccursandthepinbecomesasynchronizationinput.Theinternal RT/CLK 4 I amplifierisdisabledandthepinisahighimpedanceclockinputtotheinternalPLL.Ifclocking edgesstop,theinternalamplifierisre-enabledandthemodereturnstoaresistorfrequency programming. VSENSE 5 I Invertinginputofthetransconductance(gm)erroramplifier. Erroramplifieroutputandinputtotheoutputswitchcurrentcomparator.Connectfrequency COMP 6 O compensationcomponentstothispin. GND 7 – Ground PH 8 O Thesourceoftheinternalhigh-sidepowerMOSFETanddrainoftheinternallow-sideMOSFET Thermal GNDpinmustbeelectricallyconnectedtotheexposedpadontheprintedcircuitboardforproper 9 – Pad operation. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperature(unlessotherwisenoted)(1) MIN MAX UNIT VIN –0.3 62 V EN(2) –0.3 8 V BOOT-PH –0.3 8 V VSENSE –0.3 6 V Voltage COMP –0.3 3 V PH –0.6 62 V PH,10nsTransient –4 62 V RT/CLK –0.3 6 V VIN InternallyLimited A Current BOOT 100 mA PH InternallyLimited A Operatingjunctiontemperature –40 150 ºC Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) SeeEnableandAdjustingUVLOsection 6.2 ESD Ratings VALUE UNIT Humanbodymodel(HBM),perANSI/ESDA/JEDECJS-001,allpins(1) ±2000 V(ESD) Electrostaticdischarge Chargeddevicemodel(CDM),perJEDECspecificationJESD22-C101, V allpins(2) ±500 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT Inputcoltage 4.7 60 V Outputcurrent 200 mA SwitchingfrequencysetbyRT/CLKresistor 50 1100 kHz Switchingfrequencysynchronizedtoexternalclock 300 1100 kHz 6.4 Thermal Information TPS54061 THERMALMETRIC(1) DRB UNIT 8PINS R Junction-to-ambientthermalresistance 42.9 θJA R Junction-to-case(top)thermalresistance 46.0 θJC(top) R Junction-to-boardthermalresistance 18.1 θJB °C/W ψ Junction-to-topcharacterizationparameter 0.5 JT ψ Junction-to-boardcharacterizationparameter 18.3 JB R Junction-to-case(bottom)thermalresistance 3.0 θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheICPackageThermalMetricsapplicationreport,SPRA953. 4 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 6.5 Electrical Characteristics(1) T =–40°Cto150°C,VIN=4.7to60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SUPPLYVOLTAGE(VINPIN) Operatinginputvoltage VIN 4.7 60 V Shutdownsupplycurrent EN=0V 1.4 µA IqOperating–Nonswitching VSENSE=0.9V,VIN=12V 90 110 µA ENABLEANDUVLO(ENPIN) Rising 1.23 1.4 V Enablethreshold Falling 1 1.18 V Enablethreshold+50mV –4.7 µA Inputcurrent Enablethreshold–50mV –1.2 µA Hysteresis –3.5 µA Enablehightostartswitchingtime 450 µs VIN VINstartvoltage VINrising 4.5 V VOLTAGEREFERENCE T =25°C,VIN=12V 0.792 0.8 0.808 J Voltagereference V 1mA<I <MinimumCurrentLimit 0.784 0.8 0.816 OUT HIGH-SIDEMOSFET Switchresistance BOOT-PH=5.7V 1.5 3.0 Ω LOW-SIDEMOSFET Switchresistance VIN=12V 0.8 1.5 Ω ERRORAMPLIFIER InputCurrent VSENSEpin 20 nA Errorampgm –2µA<I <2µA,V =1V 108 µS (COMP) (COMP) EAgmduringslowstart –2µA<I <2µA,V =1V,VSENSE=0.4V 27 µS (COMP) (COMP) ErrorampDCgain VSENSE=0.8V 1000 V/V Minunitygainbandwidth 0.5 MHz Errorampsource/sink V =1V,100mVOverdrive ±8 µA (COMP) Start-SwitchingThreshold 0.57 V COMPtoIswitchgm 1.0 A/V CURRENTLIMIT High-sidesourcingcurrentlimit BOOT-PH=5.7V 250 350 500 mA threshold Zerocrossdetectcurrent –1.1 mA THERMALSHUTDOWN Thermalshutdown 176 C RT/CLK OperatingfrequencyusingRTmode 50 1100 kHz Switchingfrequency R =120kΩ 425 472 520 kHz (RT/CLK) MinimumCLKpulsewidth 40 ns RT/CLKvoltage R =120kΩ 0.53 V (RT/CLK) RT/CLKhighthreshold 1.8 V RT/CLKlowthreshold 0.5 V RT/CLKfallingedgetoPHrising Measureat500kHzwithRTresistor 60 ns edgedelay PLLlockintime Measureat500kHz 100 µs PLLfrequencyrange 300 1100 kHz (1) TheElectricalCharacteristicsspecifiedinthissectionwillapplytoallspecificationsinthisdocumentunlessotherwisenoted. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com Electrical Characteristics(1) (continued) T =–40°Cto150°C,VIN=4.7to60V(unlessotherwisenoted) J PARAMETER TESTCONDITIONS MIN TYP MAX UNIT PH MinimumOn-time Measuredat50%to50%,I =200mA 120 ns OUT Deadtime VIN=12V,I =200mA,Onetransition 30 ns OUT BOOT BOOTtoPHregulationvoltage VIN=12V 6.0 V BOOT-PHUVLO 2.9 V INTERNALSLOW-STARTTIME Slow-Starttime f =472kHz,RT=120kΩ,10%to90% 2.36 ms SW 6 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 6.6 Typical Characteristics 3 1.4 VIN = 12 V VIN = 12 V 1.2 2.5 W W 1 R- On Resistance -dson1.152 R- On Resistance -dson000...468 0.5 0.2 0 0 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure1.High-SideRDS(on)vsTemperature Figure2.Low-SideRDS(on)vsTemperature 0.803 120 VIN= 12 V, 0.801 RT= 120 kW 100 TJ= 25°C 0.799 V Rising – ce 0.797 w 80 e Referen 0.795 ormal - fs 60 g N Falling Volta 0.793 % of – 40 REF 0.791 V 0.789 20 0.787 –50 –25 0 25 50 75 100 125 150 0 0 100 200 300 400 500 600 700 800 TJ–Junction Temperature–Deg VSENSE- Feedback Voltage - mV Figure3.VREFVoltagevsTemperature Figure4.FrequencyvsVsenseVoltage 540 1100 520 VRITN== 11220 V k,W 1000 VTJIN = = 2 152°C V Hz Hz) 900 quency - k 458000 uency (k 678000000 f- Oscillator Fresw 444600 Oscillator Freq 234500000000 420 100 0 400 25 100 1000 2500 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C Timing Resistance (kW ) G001 Figure5.FrequencyvsTemperature Figure6.FrequencyvsRT/CLKResistance Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com Typical Characteristics (continued) 140 1.26 VIN= 12 V VIN= 12 V VENRising 120 1.24 1.22 Sm100 ge - V ce - 80 olta 1.20 VENFalling n V Transconducta 4600 VENA- Enable 111...111468 20 1.12 0 -50 -25 0 25 50 75 100 125 150 1.10 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure7.ErrorAmpTransconductancevsTemperature Figure8.EnablePinVoltagevsTemperature -3.35 4.6 VIN= 12 V 4.55 -3.40 4.5 Aμ -3.45 4.45 e Hysteresis Current - ---333...655050 V- Input Voltage - VI 44..44423...55234 UUVVLLOO SSttaorpt abl -3.65 4.15 n E 4.1 -3.70 4.05 -3.75 4 -50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150 TJ- Junction Temperature - °C TJ- Junction Temperature - °C Figure9.EnablePinHysteresisCurrent Figure10.InputVoltage(UVLO)vsTemperature vsTemperature -1 3 -1.05 VIN= 12 V EN = 0 V TJ=25°C -1.1 A) 2.5 µ -1.15 nt ( A e 2 nt -m -1.2 Curr urre-1.25 wn 1.5 C o Enable -1-1.3.35 Shutd 1 T = 150°C - J -1.4 Isd 0.5 TTJJ== −254°0C°C -1.45 0 -1.5 0 5 10 15 20 25 30 35 40 45 50 55 60 0 5 10 15 20 25 30 35 40 45 50 55 60 - VI- Input Voltage - V VI Input Voltage (V) G002 Figure11.EnablePinPullupCurrentvsInputVoltage Figure12.ShutdownSupplyCurrent(VIN)vsInputVoltage 8 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 Typical Characteristics (continued) 98 2 EN = Open EN = 0 V 96 VSENSE = 0.83 V 1.75 94 TJ = 150°C nt (µA) 92 nt (µA) 1.12.55 TTJJ == −254°0C°C e 90 e urr urr 1 C 88 C y y pl pl 0.75 p 86 p u u S TJ = 150°C S 0.5 84 TJ = −40°C 82 TJ = 25°C 0.25 80 0 0 5 10 15 20 25 30 35 40 45 50 55 60 0 1 2 3 4 5 Input Voltage (V) Input Voltage (V) G003 G004 Figure13. SupplyCurrent(VINPin)vsInputVoltage Figure14.SupplyCurrent(VINPin) vsInputVoltage(0VtoV )EnPinLow START 160 2.48 EN = Open VIN= 12 V, 140 TJ= 150°C 2.46 fsw= 472 kHz 120 TJ= -40°C 2.44 urrent -Am 10800 TJ= 25°C Time - ms 22..4402 y C SS uppl 60 - SS 2.38 S t 40 2.36 20 2.34 0 2.32 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150 VI- Input Voltage - V TJ- Junction Temperature - °C Figure15.SupplyCurrent(VINPin)vs Figure16.Slow-StartTimevsTemperature InputVoltage(0VtoV )EnPinOpen START 0.45 TJ= -40°C TJ= 25°C 0.4 A d - ol sh 0.35 e hr T mit nt Li 0.3 TJ= 150°C e urr C 0.25 0.2 0 5 10 15 20 25 30 35 40 45 50 55 60 VI- Input Voltage - V Figure17.CurrentLimitvsInputVoltage Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 7 Detailed Description 7.1 Overview The TPS54061 device is a 60-V, 200-mA, step-down (buck) regulator with an integrated high-side and low-side n-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, current mode control which reduces output capacitance and simplifies external frequency compensationdesign. The switching frequency of 50 kHz to 1100 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor-to-ground on the RT/CLK pin. The device has an internal phase-lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turnontoafallingedgeofanexternalsystemclock. The TPS54061 has a default startup voltage of approximately 4.5 V. The EN pin has an internal pullup current source that can be used to adjust the input voltage UVLO threshold with two external resistors. In addition, the pullup current provides a default condition. When the EN pin is floating the device will operate. The operating current is 90 µA when not switching and under no load. When the device is disabled, the supply current is 1.4 µA. The integrated 1.5-Ω high-side MOSFET and 0.8-Ω low-side MOSFET allows for high-efficiency power supply designscapableofdelivering200milliamperesofcontinuouscurrenttoaload. The TPS54061 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS54061 can operate at high duty cycles because of the boot UVLO. The output voltagecanbeadjusteddowntoaslowasthe0.8-Vreference. The TPS54061 has an internal output OV protection that disables the high-side MOSFET if the output voltage is 109%ofthenominaloutputvoltage. The TPS54061 reduces external component count by integrating the slow-start time using a reference DAC system. The TPS54061 resets the slow-start times during overload conditions with an overload recovery circuit. The overload recovery circuit will slow start the output from the fault voltage to the nominal regulation voltage once a fault condition is removed. A frequency foldback circuit reduces the switching frequency during startup and overcurrentfaultconditionstohelpcontroltheinductorcurrent. 10 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 7.2 Functional Block Diagram EN VIN Thermal Shutdown UVLO Enable Comparator Shutdown Shutdown Logic Enable Threshold Boot Charge VSENSE OV Regulator Boot Minimum UVLO Current Clamp Sense ERROR AMPLIFIER PWM Comparator BOOT Deadtime Control Logic Shutdown Reference DAC With Slow Start Slope Compensation COMP PH Frequency DRV Shift REG Maximum Clamp ZX detect Oscillator with PLL GND RT/CLK THERMALPAD 7.3 Feature Description 7.3.1 FixedFrequencyPWMControl The TPS54061 uses adjustable fixed-frequency, peak-current mode control. The output voltage is sensed through external resistors on the VSENSE pin and compared to an internal voltage reference by an error amplifierwhichdrivestheCOMPpin.Aninternaloscillatorinitiatestheturnonofthehigh-sidepowerswitch.The error amplifier output is compared to the high-side power switch current. When the power switch current reaches the level set by the COMP voltage, the power switch is turned off. The COMP pin voltage will increase and decrease as the output current increases and decreases. The device implements current limiting by clamping the COMPpinvoltagetoamaximumlevel. 7.3.2 SlopeCompensationOutputCurrent The TPS54061 adds a compensating ramp to the switch current signal. This slope compensation prevents sub- harmonicoscillations. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) 7.3.3 ErrorAmplifier The TPS54061 uses a transconductance amplifier for the error amplifier. The error amplifier compares the VSENSE voltage to the lower of the internal slow-start voltage or the internal 0.8-V voltage reference. The transconductance (gm) of the error amplifier is 108 µA/V during normal operation. During the slow-start operation, the transconductance is a fraction of the normal operating gm. The frequency compensation components(capacitor,seriesresistorandcapacitor)areaddedtotheCOMPpin-to-ground. 7.3.4 VoltageReference The voltage reference system produces a precise voltage reference over temperature by scaling the output of a temperaturestableband-gapcircuit 7.3.5 AdjustingtheOutputVoltage The output voltage is set with a resistor divider from the output node to the VSENSE pin. TI recommends using 1% tolerance or better divider resistors. Start with a 10-kΩ for the R resistor and use the Equation 1 to LS calculateR . HS æV - 0.8Vö OUT R =R ´ ç ÷ HS LS ç 0.8V ÷ è ø (1) 7.3.6 EnableandAdjustingUVLO The TPS54061 is enabled when the VIN pin voltage rises above 4.5 V and the EN pin voltage exceeds the EN rising threshold of 1.23 V. The EN pin has an internal pullup current source, I1, of 1.2 µA that provides the defaultenabledconditionwhentheENpinfloats. If an application requires a higher input UVLO threshold, use the circuit shown in Figure 18 to adjust the input voltage UVLO with two external resistors. When the EN pin voltage exceeds 1.23 V, an additional 3.5 µA of hysteresis current, Ihys, is sourced out of the EN pin. When the EN pin is pulled below 1.18 V, the 3.5-µA Ihys current is removed. This additional current facilitates adjustable input voltage hysteresis. Use Equation 2 to calculateR forthedesiredinputstartandstopvoltages.UseEquation3tosimilarlycalculateR . UVLO1 UVLO2 In applications designed to start at relatively low input voltages (for example, from 4.7 V to 10 V) and withstand high input voltages (for example, from 40 V to 60 V), the EN pin may experience a voltage greater than the absolute maximum voltage of 8 V during the high input voltage condition. TI recommends using a zener diode to clampthepinvoltagebelowtheabsolutemaximumrating. VIN TPS54061 i1 ihys Ruvlo1 EN Optional V EN Ruvlo2 Figure18. AdjustableUndervoltageLock-Out æV ö V ç ENAFALLING ÷- V START V STOP R 1= è ENARISING ø UVLO æ V ö I1× ç1- ENAFALLING ÷+I V HYS è ENARISING ø (2) 12 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 Feature Description (continued) R 1 ´ V R 2= UVLO ENAFALLING UVLO V - V +R 1 ´ (I +I ) STOP ENAFALLING UVLO 1 HYS (3) 7.3.7 InternalSlow-Start The TPS54061 has an internal digital slow-start that ramps the reference voltage from zero volts to its final value in1114switchingcycles.Theinternalslow-starttimeiscalculatedbythefollowingexpression: 1114 tss(ms)= f (kHz) SW (4) If the EN pin is pulled below the stop threshold of 1.18 V, switching stops and the internal slow-start resets. The slow-startalsoresetsinthermalshutdown. 7.3.8 ConstantSwitchingFrequencyandTimingResistor(RT/CLKPin) The switching frequency of the TPS54061 is adjustable over a wide range from 50 kHz to 1100 kHz by varying the resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.53 V and must have a resistor-to-ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 5. To reduce the solution size, one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on-time should be considered. The minimum controllable on-time is typically 120 ns and limits the operating frequency for high input voltages. The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of the maximumswitchingfrequencyislocatedbelow. 71657 R (kW)= T f (kHz)1.039 SW (5) 7.3.9 SelectingtheSwitchingFrequency The TPS54061 implements current-mode control which uses the COMP pin voltage to turn off the high-side MOSFET on a cycle-by-cycle basis. Each cycle the switch current and COMP pin voltage are compared, when the peak switch current intersects the COMP voltage, the high-side switch is turned off. During overcurrent conditions that pull the output voltage low, the error amplifier will respond by driving the COMP pin high, increasing the switch current. The error amplifier output is clamped internally, which functions as a switch current limit. To enable higher switching frequency at high input voltages, the TPS54061 implements a frequency shift. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Because the device can only divide the switching frequency by 8, there is a maximum input voltage limit in which the device operates and still have frequency shift protection. During short-circuit events (particularly with high input voltage applications), the control loop has a finite minimum controllable on-time and the output has a low voltage. During the switch-on time, the inductor current ramps to the peak current limit because of the high input voltage and minimum on-time. During the switch-off time, the inductor would normally not have enough off-time and output voltage for the inductor to ramp down by the ramp up amount. The frequencyshifteffectivelyincreasestheoff-timeallowingthecurrenttorampdown. æ 1 ö æV +R ´ I +R ´ I ö f (maxskip)= ç ÷ ´ ç OUT LS O DC O÷ SW èt ø è V - I ´ R +I ´ R ø ON IN O HS O LS (6) æ fdivö æV +R ×I +R ´ I ö f (shift)= ç ÷ × ç OUTSC LS CL DC CL ÷ SW è t ø è V - I ´ R +I ´ R ø ON IN CL HS CL LS Where • I =Outputcurrent O • I =CurrentLimit CL • V =InputVoltage IN • V =OutputVoltage OUT Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com Feature Description (continued) • V OutputVoltageduringshort OUTSC • R =Inductorresistance DC • R =High-sideMOSFETresistance HS • R =Low-sideMOSFETresistance LS • t =Controllableon-time on • fdiv=Frequencydivide(equals1,2,4,or8) (7) 7.3.10 SynchronizationtoRT/CLKPin The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through one of the circuit networks shown in Figure 19. The square-wave amplitude must extend lower than 0.5 V and higher than 1.8 V on the RT/CLK pin and have high and low states greater than 40 ns. The synchronization frequency range is 300 kHz to 1100 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin-to-ground should the synchronization signal turn off. TI recommends using a frequency set resistor connected as shown in Figure 19 through another resistor-to-ground (e.g., 50 Ω) for clock signal that are not Hi-Z or tristate during the off state. The sum of the resistance should set the switching frequency close to the external CLK frequency. TI recommends to AC couple the synchronization signal through a 10-pF ceramic capacitor to RT/CLK pin. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5 V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. The switching frequency can be higher or lower than the frequency set with the RT/CLK resistor. The device transitions from the resistor mode to the PLL mode and lock onto the CLK frequency within 100 microseconds. When the device transitions from the PLL mode to the resistor mode, the switching frequency will reduce from the external CLK frequency to 150 kHz, then reapply the 0.5-V voltage source and the resistor will then set the switchingfrequency.Theswitchingfrequencyisdividedby8,4,2,and1asthevoltagerampsfrom0to0.8volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock duringnormalstartupandfaultconditions. TPS54061 TPS54061 RT/CLK RT/CLK PLL PLL RT Hi-Z Clock Clock RT Source Source Figure19. SynchronizingtoaSystemClock 7.3.11 OvervoltageProtection The TPS54061 incorporates an output overvoltage transient protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions or strong unload transients on power supply designs with low-value output capacitance. For example, when the power supply output is overloaded the error amplifier compares the actual output voltage to the internal reference voltage. If the VSENSE pin voltage is lower than the internal reference voltage for a considerable time, the output of the error amplifier will respond by clamping the error amplifier output to a high voltage. Thus, requesting the maximum output current. Once the condition is removed, the regulator output rises and the error amplifier output transitions to the steady-state duty cycle. In some applications, the power supply output voltage can respond faster than the error amplifier output can respond,thisactualityleadstothepossibilityofanoutputovershoot. The OVP feature minimizes the output overshoot when using a low-value output capacitor by comparing the VSENSE pin voltage to OVP threshold which is 109% of the internal voltage reference. If the VSENSE pin voltage is greater than the OVP threshold, the high-side MOSFET is disabled to minimize output overshoot. When the VSENSE voltage drops lower than the OVP threshold, the high-side MOSFET resumes normal operation. 14 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 Feature Description (continued) 7.3.12 ThermalShutdown The device implements an internal thermal shutdown until the junction temperature exceeds 176°C. The thermal shutdown forces the device to stop switching until the junction temperature falls below the thermal trip threshold. Oncethedietemperaturedecreasesbelow176°C,thedevicereinitiatesthepower-upsequencebyrestartingthe internalslow-start. 7.4 Device Functional Modes 7.4.1 OperationNearMinimimumInputVoltage The TPS54061 is recommended to operate with input voltages above 4.7 V. The typical VIN UVLO threshold is 4.5VandthedevicemayoperateatinputvoltagesdowntotheUVLOvoltage.Atinputvoltagesbelowtheactual UVLO voltage the device will not switch. If EN is floating or externally pulled up to greater up than the typical 1.23 V rising threshold, when V passes the UVLO threshold the TPS54061 will become active. Switching is (VIN) enabled and the slow-start sequence is initiated. The TPS54061 starts linearly ramping up the internal reference DACfrom0Vtothereferencevoltageovertheinternalslow-starttimeperiodsetbytheswitchingfrequency. 7.4.2 OperationWithEnableControl The enable start threshold voltage is 1.23 V typical. With EN held below the 1.23 V typical rising threshold voltage the TPS54061 is disabled and switching is inhibited even if VIN is above its UVLO threshold. The quiescent current is reduced in this state. If the EN voltage is increased above the rising threshold voltage while V is above the UVLO threshold, the device becomes active. Switching is enabled and the slow-start (VIN) sequence is initiated. The TPS54061 starts linearly ramping up the internal reference DAC from 0 V to the referencevoltageovertheinternalslow-starttimeperiodsetbytheswitchingfrequency.IfENispulledbelowthe 1.18VtypicalfallingthresholdtheTPS54061willenterthereducedquiescentcurrentstateagain. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information The TPS54061 is a 60-V, 200-mA step-down regulator with an integrated high-side and low-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 200 mA. Example applications are: Low-Power Standby or Bias Voltage Supplies, 4-20 mA Current Loop Powered Sensors, Industrial Process Control, Metering, and Security Systems or an efficient high voltage linear regulator replacement. Use the following design procedure to select component values for the TPS54061. This procedure illustrates the design of a high-frequency switching regulator. These calculations can be done with the aid of the excel spreadsheet tool SLVC431. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive databaseofcomponentswhengeneratingadesign. 8.2 Typical Applications 8.2.1 CCMApplication CBOOT 0.01μF L O U1 TPS54061 100μH 3.3 V 200 mA 1 8 1 2 8 V to 60 V 2 7 R 3 6 COMP R R HS UVLO1 C O 31.6 kΩ C 196 kΩ 4 5 26.1 kΩ IN CPOLE CCOMP 10μF 2.2μF RUVLO2 * RT 33 pF 4700 pF 143 kΩ RLS 36.5 kΩ 10 kΩ *SeeEnableandAdjustingUndervoltageLockoutsection Figure20. CCMApplicationSchematic 8.2.1.1 DesignRequirements This example details the design of a continuous conduction mode (CCM) switching regulator design using ceramic output capacitors. If a low-output current design is needed, see DCM Application. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level.Forthisexample,wewillstartwiththefollowingknownparameters: Table1.DesignParameters PARAMETERS VALUES OutputVoltage 5.0V TransientResponse50to150mAloadstep ΔV =4% OUT MaximumOutputCurrent 200mA InputVoltage 24Vnom.8Vto60V OutputVoltageRipple 0.5%ofV OUT 16 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 Typical Applications (continued) Table1.DesignParameters(continued) PARAMETERS VALUES StartInputVoltage(risingVIN) 7.50V StopInputVoltage(fallingVIN) 6.50V 8.2.1.2 DetailedDesignProcedure 8.2.1.2.1 SelectingtheSwitchingFrequency The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible because this will produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency is limited by the minimum on-time of the internal power switch,themaximuminputvoltage,theoutputvoltageandthefrequencyshiftlimitation. Equation 6 and Equation 7 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two results. Switching frequencies higher than these values will result in pulse skipping or a lack of overcurrent protection during short circuit conditions. The typical minimum on-time, t min, is 120 ns for on the TPS54061. To ensure overcurrent runaway does not occur during short circuits in your design, use Equation 7 to determine the maximum switching frequency. With a maximum input voltage of 60 V, inductor resistance of 0.77 Ω, high-side switch resistance of 3.0 Ω, low-side switch resistance of 1.5 Ω, a current limit value of 350 mA and a short circuit output voltage of 0.1 V, the maximum switching frequency is 524 kHz and 1003 kHz in each case respectively. A switching frequency of 400 kHz is used. To determine the timing resistance for a given switching frequency, use Equation 5. The switching frequency is set by resistor R shown T inFigure20.R iscalculatedtobe142kΩ.Astandardvalueof143kΩisused. T 8.2.1.2.2 OutputInductorSelection(L ) O To calculate the minimum value of the output inductor, use Equation 8. KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used. Typically it is recommended to use KIND values in the range of 0.2 to 0.4; however, for designs using low-ESR output capacitors such as ceramics and low output currents, a KIND value as high as 1 may be used. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum. For this design example, use KIND of 0.4 and the minimum inductor value is calculated to be 97 µH. For this design, a standard 100 µH value was chosen. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. The RMS and peak inductor current can be found from Equation 10 and Equation11. For this design, the RMS inductor current is 200 mA and the peak inductor current is 239 mA. The chosen inductor is a Würth 74408943101. It has a saturation current rating of 680 mA and an RMS current rating of 520 mA. As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator butwillrequirealargervalueofinductance.Selectinghigherripplecurrentswillincreasetheoutputvoltageripple of the regulator but allow for a lower inductance value. The current flowing through the inductor is the inductor ripple current plus the average output current. During power-up, faults or transient load conditions, the inductor current can increase above the peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather thanthecalculatedpeakinductorcurrent. V max - V V LOmin ³ IN OUT ´ OUT Kind ´ IO VINmax ´ ¦sw (8) V ´ (V max - V ) I ³ OUT IN OUT RIPPLE V max ´ L ´ f IN O SW (9) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 2 1 æV ´ (V max - V )ö ILrms= IO2 + 12 ´ çç OUVT max I´N L ´ f OUT ÷÷ è IN O SW ø (10) I I peak=I + RIPPLE L OUT 2 (11) 8.2.1.2.3 OutputCapacitor There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance needs to be selected based on the most stringent of these three criteria. The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current until the regulator increases the inductor current. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change.Theoutputcapacitormustbesizedtosupplytheextracurrenttotheloaduntilthecontrolloopresponds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 15 shows the minimum output capacitance necessary to accomplish this, where ΔIout is the change in output current, ƒ is the sw regulatorsswitchingfrequencyandΔVoutistheallowablechangeintheoutputvoltage. For this example, the transient load response is specified as a 4% change in Vout for a load step from 50 mA to 150mA.Forthisexample,ΔI =0.150 –0.05=0.10and ΔV =0.04 ×3.3=0.132. OUT OUT Using these values gives a minimum capacitance of 3.79 µF. This does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account. The low side FET of the regulator emulates a diode so it can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, as in Figure 28. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 14 is used to calculate the minimum capacitance input the output voltage overshoot to a desired value, where is the value of the inductor, I is the output current under heavy load, I is the LO OH OL output under light load, V +ΔV is the final peak output voltage, and Vi is the initial capacitor voltage. For this O O example, the worst case load step will be from 150 mA to 50 mA. The output voltage will increase during this load transition and must be limited to 4% of the output voltage to satisy the design goal. This will make V +ΔV O O = 1.04 × 3.3 = 3.432 V. V is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using O thesenumbersinEquation14yieldsaminimumcapacitanceof2.25 µF. Equation 13 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where f is the switching frequency, Vripple is the maximum allowable output voltage ripple, and Iripple is the SW inductor ripple current. Equation 13 yields 1.48 µF. Equation 16 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 16 indicates the ESR should be less than0.160Ω. The most stringent criteria for the output capacitor is 3.79 µF of capacitance to maintain the output voltage regulationduringanloadtransient. Additional capacitance de-ratings for aging, temperature and DC bias will increase this minimum value. For this example,a10-µF,10-VX5Rceramiccapacitorwith0.003 Ω ofESRina1206packageisused. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor datasheetsspecifytheRootMeanSquare(RMS)valueofthemaximumripplecurrent. Equation 12 can be used to calculate the RMS ripple current the output capacitor needs to support. For this example,Equation12yields10.23mA. 18 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 1 æV ´ (V max - V )ö ICOrms= 12 ´ çç OUVT max I´N L ´ f OUT ÷÷ è IN O SW ø (12) I æ 1 ö C 1 ³ RIPPLE ´ ç ÷ O VRIPPLE è8 ´ fSW ø (13) I 2 - I 2 C 2 ³ L ´ OH OL O O (V +DV )2 - V 2 OUT OUT OUT (14) DI 2 C 3 ³ OUT ´ O DV fsw OUT (15) V R £ RIPPLE C I RIPPLE (16) 8.2.1.2.4 InputCapacitor The TPS54061 requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor of at least 1 µF of effective capacitance. The effective capacitance includes any deration for DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have an RMS current rating greater than the maximum RMS input current. The input RMS current can be calculated using Equation17.Thevalueofaceramiccapacitorvariessignificantlyovertemperatureandthedcbiasappliedtothe capacitor. The capacitance variations with temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The effective value of a capacitor decreases as the DC bias across a capacitor increases. For this example design, a ceramic capacitor with at least a 60-V voltage rating is required to support the maximum input voltage. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated byrearrangingEquation18. Using the design example values, Ioutmax = 200 mA, C = 2.2 µF, ƒ = 400 kHz, yields an input voltage ripple IN SW of56.8mVandanRMSinputripplecurrentof98.5mA. V (V - V ) IC rms = I ´ OUT ´ INmin OUT IN OUT V V INmin INmin (17) I æ0.25ö C ³ O ´ ç ÷ IN V ripple è f ø IN SW (18) 8.2.1.2.5 BootstrapCapacitorSelection A 0.01-µF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. TI recommends using a ceramic capacitor with X5R or better grade dielectric. The capacitor should have 10 V or highervoltagerating. 8.2.1.2.6 UVLOSetPoint TheUVLOcanbeadjustedusinganexternalvoltagedividerontheENpinoftheTPS54061.TheUVLOhastwo thresholds, one for power-up when the input voltage is rising and one for power-down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.50 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.50 V (UVLO stop). The programmable UVLO and enable voltages are set by connecting resistor divider between Vin and ground to the EN pin. Equation 2 and Equation 3 can be used to calculate the resistance values necessary. For example, a 196-kΩ resistor between Vin and EN and a 36.5-kΩ resistor between EN and ground are required to produce the 7.50 and 6.50 volt start and stop voltages. See the Enable and Adjusting Undervoltage Lockout section for additional considerations in high input voltage applications. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 8.2.1.2.7 OutputVoltageandFeedbackResistorsSelection For the example design, 10 kΩ was selected for R . Using Equation 1, R is calculated as 31.46 kΩ. The LS HS neareststandard1%resistoris31.6kΩ. 8.2.1.2.8 ClosingtheLoop There are several methods used to compensate DC-DC regulators. The method presented here is easy to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency will usually be lower than the crossover frequency used in the calculations. This method assume the crossover frequency is between the modulator pole and the ESR zeroandtheESRzeroisatleast10timesgreaterthemodulatorpole. To get started, the modulator pole, fpole, and the ESR zero, fzero must be calculated using Equation 19 and Equation 20. For Cout, use a derated value of 6.0 µF. Use Equation 21 and Equation 22, to estimate a starting pointforthecrossoverfrequency,fco,todesignthecompensation.Fortheexampledesign,fpoleis1015Hzand fzerois5584kHz. Equation 21 is the geometric mean of the modulator pole and the ESR zero and Equation 22 is the mean of modulator pole and the switching frequency. Equation 21 yields 119.2 kHz and Equation 22 gives 17.9 kHz. Use afrequencynearthelowervalueofEquation21orEquation22foraninitialcrossoverfrequency. For this example, fco of 17.9 kHz is used. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components formsthecompensatingpole. To determine the compensation resistor, R , use Equation 23. Assume the power stage transconductance, COMP gmps, is 1.00 A/V. The output voltage, Vo, reference voltage, V , and amplifier transconductance, gmea, are REF 3.3V,0.8Vand108µA/V,respectively. R is calculated to be 25.9 kΩ, use the nearest standard value of 26.1 kΩ. Use Equation 24 to set the COMP compensation zero equal to the modulator pole frequency. Equation 24 yields a 3790 pF for capacitor C and COMP a 4700 pF is chosen. Use the larger value of Equation 25 and Equation 26 to calculate the C value, to set POLE thecompensationpole.Equation26yields30.5pFsotheneareststandardof33pFisselected. 1 fpole(Hz)= Vout ´ Co ´ 2 ´ p Io (19) 1 fzero(Hz)= R ´ C ´ 2 ´ p C O (20) fco1(Hz)= (fzero ´ fpole)0.5 (21) æ fsw ö0.5 fco2(Hz)= ç ´ fpole÷ è 2 ø (22) 2 ´ p ´ ¦ ´C V R = CO O ´ OUT COMP gmps V ´ gmea REF (23) 1 C5= 2 ´ p ´ R4 ´ f POLE (24) R ´ C C6= C O R4 (25) 1 C6= R4 ´ f ´ p SW (26) 20 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 8.2.1.3 ApplicationCurves 100 100 90 90 VOUT= 3.3 V, FSW= 400 kHz 80 80 70 70 %) 60 %) 60 ncy ( 50 ncy ( 50 Efficie 40 Efficie 40 30 30 VIN= 8 V VIN= 8 V 20 VIN= 12 V 20 VIN= 12 V 10 VFSOWUT== 4 30.03 kVH,z VVVIIINNN=== 236460 VVV 10 VVVIIINNN=== 236460 VVV 0 0 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.001 0.01 0.1 1 Load Current (A) Load Current (A) Figure21.EfficiencyvsOutputCurrent Figure22.EfficiencyvsOutputCurrent 100 100 90 90 VOUT= 5 V, FSW= 400 kHz 80 80 70 70 ncy (%) 5600 ncy (%) 5600 Efficie 40 Efficie 40 30 30 VIN= 8 V VIN= 8 V 20 VIN= 12 V 20 VIN= 12 V 10 VFSOWUT== 4 50 0V ,kHz VVVIIINNN=== 236460 VVV 10 VVVIIINNN=== 236460 VVV 0 0 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.001 0.01 0.1 1 Load Current (A) Load Current (A) Figure23.EfficiencyvsOutputCurrent Figure24.EfficiencyvsOutputCurrent 60 180 0.25 0.2 IOUT= 200 mA, 40 120 FSW= 400 kHz %) 0.15 20 60 alized ( 0.1 Gain (dB) 0 0 Phase (º) age Norm 0.050 olt –0.05 –20 –60 put V –0.1 ut O –0.15 –40 –120 Gain –0.2 Phase –60 –180 –0.25 10 100 1K 10K 100K 0 10 20 30 40 50 60 Frequency (Hz) Input Voltage (V) Figure25.GainvsPhase Figure26.OutputVoltagevsInputVoltage Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 0.50 0.40 VIN= 24 V, VOUT= 3.3 V, I =100mA/div %) 0.30 FSW= 400 kHz OUT ed ( 0.20 maliz 0.10 or e N 0 g a olt–0.10 V ut –0.20 p ut O–0.30 –0.40 VOUT= 50 mV /div ac coupled –0.50 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 Load Current (A) 500μs /div Figure27.OutputVoltagevsOutputCurrent Figure28. LoadTransient VIN= 10 V /div VIN= 10 V /div V = 5 V /div EN V = 20 mV /div ac coupled OUT V = 2 V /div OUT 1 ms /div 5 ms /div Figure29.LineTransient Figure30.Start-UpWithENA PH= 20 V /div V = 10 V /div IN Inductor Current= 200 mA/div V = 2 V /div EN VOUT= 2 V /div VIN= 10 mV /div ac coupled 2 ms /div 2μs /div Figure31.Start-UpWithV Figure32.InputRippleinDCM IN 22 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 PH= 20 V /div PH= 20 V /div Inductor Current= 200 mA/div Inductor Current= 200 mA/div VIN= 50 mV /div ac coupled VIN= 10 mV /div ac coupled 2μs /div 2μs /div Figure33.InputRippleinCCM Figure34.InputRippleSkip PH= 20 V /div PH= 20 V /div Inductor Current= 200 mA/div Inductor Current= 200 mA/div VOUT= 10 mV /div VOUT= 10 mV /div ac coupled 2μs /div 2μs /div Figure36.OutputRippleinCCM Figure35.OutputRippleinDCM PH= 20 V /div Inductor Current= 200 mA/div ac coupled VOUT= 20 mV /div ac coupled 2μs /div Figure37.OutputRippleSkip Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 8.2.2 DCMApplication It is most desirable to have a power supply that is efficient and has a fixed switching frequency at low output currents. A fixed frequency power supply will have a predictable output voltage ripple and noise. Using a traditional continuous conduction mode (CCM) design method to calculate the output inductor will yield a large inductance for a low output current supply. Using a CCM inductor will result in a large sized supply or will affect efficiency from the large dc resistance an alternative is to operate in discontinuous conduction mode (DCM). Use the procedure below to calculate the components values for designing a power supply operating in discontinuous conduction mode. The advantage of operating a power supply in DCM for low output current is the fixed switching frequency, lower output inductance, and lower DC resistance on the inductor. Use the frequency shift andskipequationstoestimatethemaximumswitchingfrequency. CBOOT 0.01 µF L U1 O 220µH TPS54061 5.0 V 1 8 1 2 8 V to 40 V 2 7 744 053 221 R 3 6 COMP R R HS UVLO1 CC 255 kΩ 4 5 35.7 kΩ OO 52.3 kΩ CIN CPOLE CCOMP 22 µF 2.2 µF RUVLO2 RT 220 pF 0.33 µF 45.3 kΩ 1240 kΩ RLS 10 kΩ Figure38. DCMApplicationSchematic 8.2.2.1 DesignRequirements This example details the design of a low-output current, fixed-switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determinedatthesystemlevel.Forthisexample,wewillstartwiththefollowingknownparameters: Table2.DesignParameters DESIGNPARAMETERS VALUES OutputVoltage 5.0V TransientResponse37.5to75-mAloadstep ΔV =4% OUT MaximumOutputCurrent 75mA MinimumOutputCurrert 1mA InputVoltage 24Vnom.8Vto40V OutputVoltageRipple 1%ofV OUT SwitchingFrequency 50kHz StartInputVoltage(risingVIN) 8V StopInputVoltage(fallingVIN) 6.8V 8.2.2.2 DetailedDesignProcedure 8.2.2.2.1 DesigninganEfficient,Low-OutputCurrentPowerSupplyataFixedSwitchingFrequency The TPS54061 is designed for applications which require a fixed operating frequency and low output voltage ripple at low-output currents, thus, the TPS54061 does not have a pulse skip mode at light loads. Because the device has a minimum controllable on time, there is an output current at which the power supply will pulse skip. To ensure that the supply does not pulse skip at output current of the application the inductor value will be need to be selected greater than a minimum value. The minimum inductance needed to maintain a fixed switching 24 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 frequency at the minimum load is calculated to be 227 µH using Equation 27. Because the equation is ideal and was derived without losses, assume the minimum controllable light load on time, t , is 180 ns. To maintain onminll DCM operation the inductor value and output current need to stay below a maximum value. The maximum inductance is calculated to be 250 µH using Equation 28. A 744053221 inductor from Würth Elektronik is selected.IfCCMoperationisnecessary,usethepreviousdesignprocedure. Use Equation 29, to make sure the minimum current limit on the high-side power switch is not exceeded at the maximum output current. The peak current is calculated as 244 mA and is lower than the 350 mA current limit. To determine the RMS current for the inductor and output capacitor, it is necessary to calculate the duty cycle. The duty cycle, D1, for a step down regulator in DCM is calculated in Equation 30. D1 is the portion of the switchingcyclethehighsidepowerswitchison,andiscalculatedtobe0.1345.D2istheportionoftheswitching cyclethelow-sidepowerswitchison,andiscalculatedtobe0.5111. Using the Equation 32 and Equation 33, the RMS current of the inductor and output capacitor are calculated, to be 0.1078 A and 0.0774 A respectively. Select components that ratings exceed the calculated RMS values. Calculate the output capacitance using the Equation 34 to Equation 36 and use the largest value, Vripple is the steady-state voltage ripple and deltaV is voltage change during a transient. A minimum of 7.5-µF capacitance is calculated. Additional capacitance de-ratings for aging, temperature and DC bias should be factored in which increases this minimum value. For this example, a 22-µF 10-V X7R ceramic capacitor with 5-mΩ ESR is used. To have a low-output ripple power supply use a low ESR capacitor. Use Equation 37 to estimate the maximum ESR for the output capacitor. Equation 38 and Equation 39 estimate the RMS current and capacitance for the input capacitor. An RMS current of 38.7 mA and capacitance of 1.56 µF is calculated. A 2.2-µF 100-V/X7R ceramicisusedforthisexample. æV max - V ö æV maxö t nmin2 Lomin ³ çè IN VOUT OUT ÷ø ´ çè IN2 ÷ø ´ OIOmin x fsw (27) æV min - V ö æ V ö 1 LOmax £ çè IN 2 OUT ÷ø ´ çèVINOmUTin÷ø ´ fsw ´ IO (28) æ2 ´ V ´ Iomax ´ (V max - V )ö0.5 I peak= ç OUT IN OUT ÷ L ç V max ´ L ´ f ÷ è IN O sw ø (29) 0.5 æ2 ´ V ´ I ´ L ´ f ö D1= ç OUT O O sw ÷ ç V ´ (V - V ) ÷ è IN IN OUT ø (30) æV - V ö D2= ç IN OUT ÷ ´ D1 V è OUT ø (31) æD1+D2ö0.5 I rms=I peak ´ ç ÷ L L è 3 ø (32) ææD1+D2ö æD1+D2ö2ö0.5 I rms=I peak ´ çç ÷ - ç ÷ ÷ CO L çè 3 ø è 4 ø ÷ è ø (33) I peak æD1+D2ö C 1 £ L ´ ç ÷ O V è8 ´ f ø RIPPLE SW (34) Io2 - 02 C 2 ³ L ´ O O (V +DV)2 - V 2 OUT OUT (35) I 1 Co3 ³ OUT ´ DV f OUT co (36) V R £ RIPPLE C I peak L (37) Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com ææD1ö æD1ö2ö0.5 I rms=I peak ´ çç ÷ - ç ÷ ÷ CIN L çè 3 ø è 4 ø ÷ è ø (38) I æ0.25ö C ³ O ´ ç ÷ IN VINRIPPLE è fSW ø (39) 8.2.2.2.2 ClosingtheFeedbackLoop The method presented here is easy to calculate and includes the effect of the slope compensation that is internal to the TPS54061. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least 10 times greater than the modulator pole. Once the output components are determined, use the equations below to close the feedback loop. A current mode controlled power supply operating in DCM has a transfer function which includes an ESR zero and pole as shown in Equation 40. To calculate the current mode power stage gain, first calculate, Kdcm, the DCM gain, and Fm, the modulator gain, using Equation 41 and Equation 42. Kdcm and Fm are 32.4 and 0.475 respectively. The location of the pole and ESR zero are calculated using Equation 43 and Equation 44 . The pole and zero are 491 Hz and 2.8 MHz, respectively. Use the lower value of Equation 45and Equation 46 as a starting point for the crossover frequency. Equation 45 is the geometric mean of the power stage pole and the ESR zero and Equation 46 is the mean of powerstagepoleandtheswitchingfrequency.Thecrossoverfrequencyischosenas5kHzfromEquation46. To determine the compensation resistor, R , use Equation 47. Assume the power stage transconductance, COMP gmps, is 1.0 A/V. The output voltage, V , reference voltage, V , and amplifier transconductance, gmea, are O REF 5.0 V, 0.8 V and 108 µA/V, respectively. R is calculated to be 38.3 kΩ; use the nearest standard value of COMP 35.7 kΩ. Use Equation 48 to set the compensation zero to equalthe modulator pole frequency. Equation 48 yields 290 nF for compensating capacitor C , and a 330 nF is used. Use the larger value of Equation 49 or COMP Equation 50 to calculate the C , which sets the compensation pole. Equation 50 yields 178 pF standard value POLE of220pFisselected. s 1+ 2 ´ p ´ f Gdcm(s) » Fm ´ Kdcm ´ ZERO s 1+ 2 ´ p ´ f POLE (40) 2 V ´ (V - V ) Kdcm = ´ OUT IN OUT D1 æ ö ç Rdc ÷ V ´ ç2+ ÷ - V IN V OUT ç OUT ÷ ç I ÷ è O ø (41) gmps Fm = æV - V ö ç IN OUT ÷+0.380 è LO ´ fsw ø (42) æ V ö ç2 - OUT ÷ 1 V f (Hz)= ´ ç IN ÷ POLE V ç V ÷ OIUT ´ CO ´ 2 ´ p çè1 - VOUT ÷ø O IN (43) 1 f (Hz)= ZERO R ´ C ´ 2 ´ p C O (44) f (Hz)= (f ´ f )0.5 CO1 ZERO POLE (45) f (Hz)= (f ´ f )0.5 CO2 SW POLE (46) R = ¦co x VOUT COMP Kdcm´Fm´¦ V ´gmea POLE REF (47) 26 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 1 C = COMP 2 ´ p ´ R ´ Kdcm ´ Fm COMP (48) R ´ C C = C O POLE1 R COMP (49) 1 C = POLE2 R ´ f ´ p COMP SW (50) 8.2.2.3 ApplicationCurves 100 100 90 90 VOUT= 5 V, FSW= 50 kHz 80 80 70 70 %) 60 %) 60 Efficiency ( 4500 Efficiency ( 4500 30 VIN= 8 V 30 20 VIN= 12 V VIN= 8 V VOUT= 5 V, VIN= 24 V 20 VIN= 12 V 10 FSW= 50 kHz VIN= 36 V 10 VVIINN== 2346 VV 0 0 0.025 0.05 0.075 0.1 0 0.001 0.01 0.1 Load Current (A) Load Current (A) Figure39.EfficiencyvsLoadCurrent Figure40.EfficiencyvsLoadCurrent 100 100 90 90 VFSOWUT== 5 30. 3k HVz, 80 80 70 70 ncy (%) 5600 ency (%) 5600 Efficie 40 Effici 40 30 30 1200 VFSOWUT== 5 30. 3k HVz, VVVVIIIINNNN==== 8123 246V VVV 1200 VVVVIIIINNNN==== 8123 246V VVV 0 00 0.025 0.05 0.075 0.1 0.001 0.01 0.1 Load Current (A) Load Current (A) Figure41.EfficiencyvsLoadCurrent Figure42.EfficiencyvsLoadCurrent Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 40 180 0.50 30 GPhaainse 135 0.40 VIN= 24 V, 20 90 %) 0.30 VFSOWUT== 5 50 VkH,z d ( 0.20 Gain (dB)–11000 04–545Phase (º) Voltage Normalize–000...101000 –20 –90 Output –0.20 –0.30 –30 –135 –0.40 –40 –180 –0.50 10 100 1K 10K 100K 0 0.025 0.05 0.075 0.1 Frequency (Hz) Load Current (A) Figure43.FrequencyResponse Figure44.OutputVoltageNormalizedvsLoadCurrent 0.25 0.2 IFOSUWT== 5307 .k5H mzA, VVOOUUTT== 110000 mmVV //ddiivv aacc ccoouupplleedd 0.15 %) 0.1 malized ( 0.05 Voltage Nor –0.005 Output –0.1 –0.15 –0.2 IIOOUUTT==2200mmAA//ddiivv –0.25 0 10 20 30 40 50 60 Input Voltage (V) 22 mmss //ddiivv Figure45.OutputVoltageNormalizedvsInputVoltage Figure46.LoadTransient VOUT= 100 mV /div ac coupled V = 10 V /div IN V = 2 V /div OUT EN= 5 V /div IOUT=20mA/div IOUT=50mA/div 4 ms /div 10 ms /div Figure47.UnloadTransient Figure48.Start-UpWithENA 28 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 VIN= 10 V /div VIN= 10 V /div VOUT= 2 V /div VOUT= 2 V /div EN= 5 V /div EN= 5 V /div I =50mA/div OUT I =50mA/div OUT 10 ms /div 10 ms /div Figure49.Start-UpWithV Figure50.PrebiasStart-UpWithENA IN PH= 20 V /div V = 10 V /div IN VOUT= 2 V /div VIN= 100 nV /div ac coupled VOUT= 50 mV /div ac coupled EN= 5 V /div I =50mA/div OUT Inductor current= 100 mA/div 10 ms /div 4µs /div Figure51.PrebiasStart-UpWithVIN Figure52.InputandOutputRippleinDCM PH= 20 V /div VIN= 20 mV /div ac coupled VOUT= 20 mV /div ac coupled Inductor current= 20 mA/div 4µs /div Figure53.InputandOutputRippleinPSM Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:TPS54061

TPS54061 SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 www.ti.com 9 Power Supply Recommendations TheTPS54061isdesignedtooperatefromaninputvoltagesupplyrangebetween4.7Vand60V.Thisinput supplyshouldremainwithintheinputvoltagesupplyrange.Iftheinputsupplyislocatedmorethanafewinches fromtheTPS54061converterbulkcapacitancemayberequiredinadditiontotheceramicbypasscapacitors. 10 Layout 10.1 Layout Guidelines Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed to ground with a low-ESR ceramic bypass capacitor with X5R or X7R dielectric. Take care to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the GND pin. See Figure 54 for a PCB layout example. Because the PH connection is the switching node and output inductor should be located close to the PH pins, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The RT/CLK pin is sensitive to noise. so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts; however; this layout has been shown to producegoodresultsandismeantasaguideline. 10.2 Layout Example VOUT Output Output Capacitor Route Boot Capacitor Inductor Trace on another layer to GND provide wide path for topside ground Input Capacitor Boot Capacitor BOOT PH Compensation Network VIN VIN GND EN COMP Feedback UVLO Resistors Adjust RT/CLK VSENSE Resistor Signal VIA Frequency Set Resistor Figure54. PCBLayoutExample 30 SubmitDocumentationFeedback Copyright©2012–2015,TexasInstrumentsIncorporated ProductFolderLinks:TPS54061

TPS54061 www.ti.com SLVSBB7E–MAY2012–REVISEDNOVEMBER2015 11 Device and Documentation Support 11.1 Trademarks WEBENCHisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.2 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.3 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. Copyright©2012–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:TPS54061

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TPS54061DRBR ACTIVE SON DRB 8 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 150 61 & no Sb/Br) TPS54061DRBT ACTIVE SON DRB 8 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 150 61 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF TPS54061 : •Automotive: TPS54061-Q1 NOTE: Qualified Version Definitions: •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Mar-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TPS54061DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS54061DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Mar-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TPS54061DRBR SON DRB 8 3000 367.0 367.0 35.0 TPS54061DRBT SON DRB 8 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE DRB0008B VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 B A 2.9 PIN 1 INDEX AREA 3.1 2.9 C 1 MAX SEATING PLANE 0.05 0.08 C 0.00 EXPOSED 1.65 0.05 (0.2) TYP THERMAL PAD 4 5 2X 1.95 2.4 0.05 8 1 6X 0.65 0.35 8X 0.25 PIN 1 ID 0.5 0.1 C A B (OPTIONAL) 8X 0.3 0.05 C 4218876/A 12/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT DRB0008B VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) 8X (0.6) SYMM 1 8 8X (0.3) (2.4) (0.95) 6X (0.65) 4 5 (R0.05) TYP (0.575) ( 0.2) VIA (2.8) TYP LAND PATTERN EXAMPLE SCALE:20X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218876/A 12/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN DRB0008B VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD SYMM 8X (0.6) METAL TYP 1 8X (0.3) 8 (0.63) SYMM 6X (0.65) (1.06) 5 4 (R0.05) TYP (1.47) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 81% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218876/A 12/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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