(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 (cid:1) Extremely Low Offset Voltage...1 µV Max D008, JG, OR P PACKAGE (cid:1) (TOP VIEW) Extremely Low Change on Offset Voltage With Temperature...0.003 µV/°C Typ (cid:1) CXA 1 8 CXB Low Input Offset Current IN− 2 7 VDD+ 500 pA Max at T = − 55°C to 125°C A IN+ 3 6 OUT (cid:1) AVD...135 dB Min VDD− 4 5 CLAMP (cid:1) CMRR...120 dB Min (cid:1) k ...110 dB Min D014, J, OR N PACKAGE SVR (TOP VIEW) (cid:1) Single-Supply Operation (cid:1) Common-Mode Input Voltage Range CXB 1 14 INT/EXT Includes the Negative Rail CXA 2 13 CLK IN (cid:1) No Noise Degradation With External NC 3 12 CLK OUT Capacitors Connected to VDD− IN− 4 11 VDD+ IN+ 5 10 OUT description NC 6 9 CLAMP The TLC2652 and TLC2652A are high-precision VDD− 7 8 C RETURN chopper-stabilized operational amplifiers using Texas Instruments Advanced LinCMOS pro- FK PACKAGE cess. This process, in conjunction with unique (TOP VIEW) T chopper-stabilization circuitry, produces opera- X N teioxcneael dasm tphlaifite orsf swimhoilasre dpeevrifcoersm aavnaciela mblea ttcohdeasy .or VXAVXBNCNT/E CLK I I Chopper-stabilization techniques make possible 3 2 1 20 19 extremely high dc precision by continuously NC 4 18 CLK OUT nulling input offset voltage even during variations NC 5 17 NC in temperature, time, common-mode voltage, and IN− 6 16 VDD+ power supply voltage. In addition, low-frequency NC 7 15 NC noise voltage is significantly reduced. This high IN+ 8 14 OUT 9 10 11 12 13 precision, coupled with the extremely high input impedance of the CMOS input stage, makes the C D− CN P TLC2652 and TLC2652A an ideal choice for N D NR M V U A low-level signal processing applications such as T L E C strain gauges, thermocouples, and other R C transducer amplifiers. For applications that NC − No internal connection require extremely low noise and higher usable bandwidth, use the TLC2654 or TLC2654A device, which has a chopping frequency of 10 kHz. The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior performance in either single-supply or split-supply applications, even at power supply voltage levels as low as ±1.9 V. Two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply configuration with a normal CMOS or TTL clock input. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Advanced LinCMOSis a trademark of Texas Instruments. (cid:20)(cid:21)(cid:18)(cid:29)(cid:31)(cid:3)(cid:1)(cid:23)(cid:18)(cid:24) (cid:29)(cid:8)(cid:1)(cid:8) (cid:16)(cid:13)!"#$(cid:12)%(cid:16)"(cid:13) (cid:16)& (cid:14)’##(cid:15)(cid:13)% (cid:12)& "! (’)*(cid:16)(cid:14)(cid:12)%(cid:16)"(cid:13) (cid:10)(cid:12)%(cid:15)+ Copyright  1988−2005, Texas Instruments Incorporated (cid:20)#"(cid:10)’(cid:14)%& (cid:14)"(cid:13)!"#$ %" &((cid:15)(cid:14)(cid:16)!(cid:16)(cid:14)(cid:12)%(cid:16)"(cid:13)& ((cid:15)# %,(cid:15) %(cid:15)#$& "! (cid:1)(cid:15)-(cid:12)& (cid:23)(cid:13)&%#’$(cid:15)(cid:13)%& &%(cid:12)(cid:13)(cid:10)(cid:12)#(cid:10) .(cid:12)##(cid:12)(cid:13)%/+ (cid:20)#"(cid:10)’(cid:14)%(cid:16)"(cid:13) (#"(cid:14)(cid:15)&&(cid:16)(cid:13)0 (cid:10)"(cid:15)& (cid:13)"% (cid:13)(cid:15)(cid:14)(cid:15)&&(cid:12)#(cid:16)*/ (cid:16)(cid:13)(cid:14)*’(cid:10)(cid:15) (cid:18)(cid:13) (#"(cid:10)’(cid:14)%& (cid:14)"$(*(cid:16)(cid:12)(cid:13)% %" (cid:17)(cid:23)(cid:2)(cid:26)(cid:20)(cid:21)(cid:30)(cid:26)12(cid:6)1(cid:6)(cid:7) (cid:12)** ((cid:12)#(cid:12)$(cid:15)%(cid:15)#& (cid:12)#(cid:15) %(cid:15)&%(cid:15)(cid:10) %(cid:15)&%(cid:16)(cid:13)0 "! (cid:12)** ((cid:12)#(cid:12)$(cid:15)%(cid:15)#&+ ’(cid:13)*(cid:15)&& "%,(cid:15)#.(cid:16)&(cid:15) (cid:13)"%(cid:15)(cid:10)+ (cid:18)(cid:13) (cid:12)** "%,(cid:15)# (#"(cid:10)’(cid:14)%&(cid:7) (#"(cid:10)’(cid:14)%(cid:16)"(cid:13) (#"(cid:14)(cid:15)&&(cid:16)(cid:13)0 (cid:10)"(cid:15)& (cid:13)"% (cid:13)(cid:15)(cid:14)(cid:15)&&(cid:12)#(cid:16)*/ (cid:16)(cid:13)(cid:14)*’(cid:10)(cid:15) %(cid:15)&%(cid:16)(cid:13)0 "! (cid:12)** ((cid:12)#(cid:12)$(cid:15)%(cid:15)#&+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 description (continued) Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload recovery time. If desired, an output clamp pin is available to reduce the recovery time even further. The device inputs and output are designed to withstand ±100-mA surge currents without sustaining latch-up. Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance. The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized for operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from −40°C to125°C. The M-suffix devices are characterized for operation over the full military temperature range of −55°C to125°C. AVAILABLE OPTIONS(1) PACKAGED DEVICES 8 PIN 14 PIN 20 PIN CCHHIIPP VVIIOOmmaaxx TA AT 25°C SMALL CERAMIC PLASTIC SMALL CERAMIC PLASTIC CHIP FFOORRMM OUTLINE DIP DIP OUTLINE DIP DIP CARRIER (Y) (D008) (JG) (P) (D014) (J) (N) (FK) 00°CC 11 µµVV TTLLCC22665522AACC--88DD —— TTLLCC22665522AACCPP TTLLCC22665522AACC--1144DD —— TTLLCC22665522AACCNN —— 7700ttoo°CC 33 µµVV TTLLCC22665522CC--88DD —— TTLLCC22665522CCPP TTLLCC22665522CC--1144DD —— TTLLCC22665522CCNN —— TTLLCC22665522YY −−4400°CC 11 µµVV TTLLCC22665522AAII--88DD —— TTLLCC22665522AAIIPP TTLLCC22665522AAII--1144DD —— TTLLCC22665522AAIINN —— 8855ttoo°CC 33 µµVV TTLLCC22665522AA--88DD —— TTLLCC22665522IIPP TTLLCC22665522II--1144DD —— TTLLCC22665522IINN —— —— −−4400°CC ttoo 33..55 µµVV TTLLCC22665522QQ--88DD —— —— —— —— —— —— —— 112255°CC −55°C 33 µµVV TTLLCC22665522AAMM--88DD TTLLCC22665522AAMMJJGG TTLLCC22665522AAMMPP TTLLCC22665522AAMM--1144DD TTLLCC22665522AAMMJJ TTLLCC22665522AAMMNN TTLLCC22665522AAMMFFKK 12tt5oo°C 3.5 µV TLC2652M-8D TLC2652MJG TLC2652MP TLC2652M-14D TLC2652MJ TLC2652MN TLC2652MFK —— The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25°C. NOTE (1):For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. functional block diagram DISTRIBUTION OF TLC2652 INPUT OFFSET VOLTAGE VDD+ 7 36 150 Units Tested From 1 Wafer Lot Clamp 5 CLAMP 32 VDD± = ±5 V Circuit TA = 25°C 3 IN+ + 6 OUT 28 N Package IN− − % 2 B B Main CICA s − 24 A Unit 20 −+ Compensation- of Biasing e 16 Null A B Circuit g a nt 12 External Components e CXA CXB rc e P 8 4 4 8 0 VDD− C RETURN −3 −2 −1 0 1 2 3 Pin numbers shown are for the D (14 pin), JG, and N packages. VIO − Input Offset Voltage − µV 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TLC2652Y chip information This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform. BONDING PAD ASSIGNMENTS (13) (12) (11) (10) (9) (14) (8) CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJmax = 150°C 80 TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. (1) PIN (7) IS INTERNALLY CONNECTED TO BACK SIDE OF CHIP. FOR THE PINOUT, SEE THE FUNCTIONAL BLOCK DIAGRAM. (2) (4) (5) (7) 90 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V DD+ Supply voltage V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V DD− Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±16 V ID Input voltage, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8 V I Voltage range on CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V − to V + 5.2 V DD DD− Input current, II (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited Current into CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, T :C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C A I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package . . . . . . . . . . . . . . . . 300°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VDD+ and VDD−. 2. Differential voltages are at IN+ with respect to IN−. 3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. DISSIPATION RATING TABLE TTAA ≤≤ 2255°CC DDEERRAATTIINNGG FFAACCTTOORR TTAA == 7700°CC TTAA == 8855°CC TTAA == 112255°CC PPAACCKKAAGGEE POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING D008 725 mV 5.8 mW/°C 464 mW 377 mW 145 mW D014 950 mV 7.6 mW/°C 608 mW 494 mW 190 mW FK 1375 mV 11.0 mW/°C 880 mW 715 mW 275 mW J 1375 mV 11.0 mW/°C 880 mW 715 mW 275 mW JG 1050 mV 8.4 mW/°C 672 mW 546 mW 210 mW N 1575 mV 12.6 mW/°C 1008 mW 819 mW 315 mW P 1000 mV 8.0 mW/°C 640 mW 520 mW 200 mW recommended operating conditions C SUFFIX I SUFFIX Q SUFFIX M SUFFIX UUNNIITT MIN MAX MIN MAX MIN MAX MIN MAX Supply voltage, VDD± ±1.9 ±8 ±1.9 ±8 ±1.9 ±8 ±1.9 ±8 V Common-mode input voltage, VIC VDD− VDD+ −1.9 VDD− VDD+ −1.9 VDD− VDD+ −1.9 VDD− VDD+ −1.9 V Clock input voltage VDD− VDD− +5 VDD− VDD− +5 VDD− VDD− +5 VDD− VDD− +5 V Operating free-air temperature, TA 0 70 −40 85 −40 125 −55 125 °C 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, V ± = ±5 V (unless otherwise noted) DD TLC2652C TLC2652AC PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† UUNNIITT MIN TYP MAX MIN TYP MAX 25°C 0.6 3 0.5 1 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee µVV Full range 4.35 2.35 TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff αVVIIOO input offset voltage FFuullll rraannggee 00..000033 00..0033 00..000033 00..0033 µVV//°°CC Input offset voltage long-term drift (see Note 4) VIC = 0, RS = 50 Ω 25°C 0.003 0.06 0.003 0.02 µV/mo 25°C 2 60 2 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ppAA Full range 100 100 25°C 4 60 4 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ppAA Full range 100 100 −−55 −−55 CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee VVIICCRR rraannggee RRSS == 5500 ΩΩ FFuullll rraannggee ttoo ttoo VV 3.1 3.1 MMaaxxiimmuumm ppoossiittiivvee ppeeaakk 25°C 4.7 4.8 4.7 4.8 VVOOMM++ output voltage swing RRLL == 1100 kkΩΩ, SSeeee NNoottee 55 Full range 4.7 4.7 VV MMaaxxiimmuumm nneeggaattiivvee ppeeaakk 25°C −4.7 −4.9 −4.7 −4.9 VVOOMM−− output voltage swing RRLL == 1100 kkΩΩ, SSeeee NNoottee 55 Full range −4.7 −4.7 VV LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall 25°C 120 150 135 150 AAVVDD voltage amplification VVOO == ±±44 VV,, RRLL == 1100 kkΩΩ Full range 120 130 ddBB fch Internal chopping frequency 25°C 450 450 Hz 25°C 25 25 CCllaammpp oonn--ssttaattee ccuurrrreenntt RRLL == 110000 kkΩΩ µAA Full range 25 25 25°C 100 100 CCllaammpp ooffff--ssttaattee ccuurrrreenntt VVOO == −−44 VV ttoo 44 VV ppAA Full range 100 100 CCoommmmoonn--mmooddee rreejjeeccttiioonn VVOO == 00,, VVIICC == VVIICCRRmmiinn,, 25°C 120 140 120 140 CCMMRRRR ratio RS = 50 Ω Full range 120 120 ddBB SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo VDD± = ±1.9 V to ±8 V, 25°C 110 135 110 135 kkSSVVRR (∆VDD±/∆VIO) VO = 0, RS = 50 Ω Full range 110 110 ddBB 25°C 1.5 2.4 1.5 2.4 IIDDDD SSuuppppllyy ccuurrrreenntt mmAA Full range 2.5 2.5 †Full range is 0° to 70°C. NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 operating characteristics specified free-air temperature, VDD± = ±5 V TTEESSTT TLC2652C TLC2652AC PPAARRAAMMEETTEERR CONDITIONS TTAA†† MIN TYP MAX MIN TYP MAX UUNNIITT 25°C 2 2.8 2 2.8 SSRR++ PPoossiittiivvee sslleeww rraattee aatt uunniittyy ggaaiinn VVOO == ±22..33 VV,, Full range 1.5 1.5 VV//µss RRLL == 1100 kkΩΩ,, 25°C 2.3 3.1 2.3 3.1 SSRR−− NNeeggaattiivvee sslleeww rraattee aatt uunniittyy ggaaiinn CCLL == 110000 ppFF VV//µss Full range 1.8 1.8 EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 10 Hz 25°C 94 94 140 VVnn (see Note 6) f = 1 kHz 25°C 23 23 35 nnVV//√√HHzz PPeeaakk--ttoo--ppeeaakk eeqquuiivvaalleenntt iinnppuutt f = 0 to 1 Hz 25°C 0.8 0.8 VVNN((PPPP)) noise voltage f = 0 to 10 Hz 25°C 2.8 2.8 µVV In Equivalent input noise current f = 10 kHz 25°C 0.004 0.004 fA/√Hz ff == 1100 kkHHzz,, GGaaiinn--bbaannddwwiiddtthh pprroodduucctt RRLL == 1100 kkΩΩ,, 2255°CC 11..99 11..99 MMHHzz CL = 100 pF φm Phase margin at unity gain RCLL == 11000 k ΩpF, 25°C 48° 48° †Full range is 0° to 70°C. NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, V ± = ±5 V (unless otherwise noted) DD TLC2652I TLC2652AI PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† UUNNIITT MIN TYP MAX MIN TYP MAX 25°C 0.6 3 0.5 1 VVIIOO IInnppuutt ooffffsseett vvoollttaaggee µVV Full range 4.95 2.95 TTeemmppeerraattuurree ccooeeffffiicciieenntt ooff αVVIIOO input offset voltage FFuullll rraannggee 00..000033 00..0033 00..000033 00..0033 µVV//°°CC Input offset voltage long-term drift (see Note 4) VIC = 0, RS = 50 Ω 25°C 0.003 0.06 0.003 0.02 µV/mo 25°C 2 60 2 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ppAA Full range 150 150 25°C 4 60 4 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ppAA Full range 150 150 −−55 −−55 CCoommmmoonn--mmooddee iinnppuutt VVIICCRR vvoollttaaggee rraannggee RRSS == 5500 ΩΩ FFuullll rraannggee ttoo ttoo VV 3.1 3.1 MMaaxxiimmuumm ppoossiittiivvee ppeeaakk 25°C 4.7 4.8 4.7 4.8 VVOOMM++ output voltage swing RRLL == 1100 kkΩΩ, SSeeee NNoottee 55 Full range 4.7 4.7 VV MMaaxxiimmuumm nneeggaattiivvee ppeeaakk 25°C −4.7 −4.9 −4.7 −4.9 VVOOMM−− output voltage swing RRLL == 1100 kkΩΩ, SSeeee NNoottee 55 Full range −4.7 −4.7 VV LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall 25°C 120 150 135 150 AAVVDD voltage amplification VVOO == ±±44 VV,, RRLL == 1100 kkΩΩ Full range 120 125 ddBB Internal chopping frequency 25°C 450 450 Hz 25°C 25 25 CCllaammpp oonn--ssttaattee ccuurrrreenntt RRLL == 110000 kkΩΩ µAA Full range 25 25 25°C 100 100 CCllaammpp ooffff--ssttaattee ccuurrrreenntt VVOO == −−44 VV ttoo 44 VV ppAA Full range 100 100 CCoommmmoonn--mmooddee rreejjeeccttiioonn VVOO == 00,, VVIICC == VVIICCRRmmiinn,, 25°C 120 140 120 140 CCMMRRRR ratio RS = 50 Ω Full range 120 120 ddBB SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn VDD± = ±1.9 V to ±8 V, 25°C 110 135 110 135 kkSSVVRR ratio (∆VDD±/∆VIO) VO = 0, RS = 50 Ω Full range 110 110 ddBB 25°C 1.5 2.4 1.5 2.4 IIDDDD SSuuppppllyy ccuurrrreenntt VVOO == 00,, NNoo llooaadd mmAA Full range 2.5 2.5 †Full range is −40° to 85°C. NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 operating characteristics at specified free-air temperature, VDD± = ±5 V TTEESSTT TLC2652I TLC2652AI PPAARRAAMMEETTEERR CONDITIONS TTAA†† MIN TYP MAX MIN TYP MAX UUNNIITT 25°C 2 2.8 2 2.8 SSRR++ PPoossiittiivvee sslleeww rraattee aatt uunniittyy ggaaiinn VVOO == ±22..33 VV,, Full range 1.4 1.4 VV//µss RRLL == 1100 kkΩΩ,, 25°C 2.3 3.1 2.3 3.1 SSRR−− NNeeggaattiivvee sslleeww rraattee aatt uunniittyy ggaaiinn CCLL == 110000 ppFF VV//µss Full range 1.7 1.7 EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 10 Hz 25°C 94 94 140 VVnn (see Note 6) f = 1 kHz 25°C 23 23 35 nnVV//√√HHzz PPeeaakk--ttoo--ppeeaakk eeqquuiivvaalleenntt iinnppuutt f = 0 to 1 Hz 25°C 0.8 0.8 VVNN((PPPP)) noise voltage f = 0 to 10 Hz 25°C 2.8 2.8 µVV In Equivalent input noise current f = 1 kHz 25°C 0.004 0.004 pA/√Hz ff == 1100 kkHHzz,, GGaaiinn--bbaannddwwiiddtthh pprroodduucctt RRLL == 1100 kkΩΩ,, 2255°CC 11..99 11..99 MMHHzz CL = 100 pF φm Phase margin at unity gain RCLL == 11000 k ΩpF, 25°C 48° 48° †Full range is −40° to 85°C. NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement has no bearing on testing or nontesting of other parameters. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at specified free-air temperature, V ± = ±5 V (unless otherwise noted) DD TLC2652Q TLC2652AM PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS TTAA†† TLC2652M UUNNIITT MIN TYP MAX MIN TYP MAX IInnppuutt ooffffsseett vvoollttaaggee 25°C 0.6 3.5 0.5 3 VVIIOO (see Note 7) Full range 10 8 µVV αVVIIOO TTineepmmuppt oeefrrfaastteuutrr eev occlootaeegffffeiicciieenntt ooff FFuullll rraannggee 00..000033 00..0033∗∗ 00..000033 00..0033∗∗ µVV//°°CC Ilonnpgu-tt eorffmse dt rvifot l(tasegee Note 4) VIC = 0, RS = 50 Ω 25°C 0.003 0.06∗ 0.003 0.02∗ µV/mo 25°C 2 60 2 60 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt ppAA Full range 500 500 25°C 4 60 4 60 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt ppAA Full range 500 500 −−55 −−55 CCoommmmoonn--mmooddee iinnppuutt VVIICCRR vvoollttaaggee rraannggee RRSS == 5500 ΩΩ FFuullll rraannggee ttoo ttoo VV 3.1 3.1 MMaaxxiimmuumm ppoossiittiivvee ppeeaakk 25°C 4.7 4.8 4.7 4.8 VVOOMM++ output voltage swing RRLL == 1100 kkΩΩ, SSeeee NNoottee 55 Full range 4.7 4.7 VV MMaaxxiimmuumm nneeggaattiivvee ppeeaakk 25°C −4.7 −4.9 −4.7 −4.9 VVOOMM−− output voltage swing RRLL == 1100 kkΩΩ, SSeeee NNoottee 55 Full range −4.7 −4.7 VV LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall 25°C 120 150 135 150 AAVVDD voltage amplification VVOO == ±±44 VV,, RRLL == 1100 kkΩΩ Full range 120 120 ddBB fch Internal chopping frequency 25°C 450 450 Hz 25°C 25 25 CCllaammpp oonn--ssttaattee ccuurrrreenntt VVOO == −−55 VV ttoo 55 VV µAA Full range 25 25 25°C 100 100 CCllaammpp ooffff--ssttaattee ccuurrrreenntt RRLL == 110000 kkΩΩ ppAA Full range 500 500 CCoommmmoonn--mmooddee rreejjeeccttiioonn VVOO == 00,, VVIICC == VVIICCRRmmiinn,, 25°C 120 140 120 140 CCMMRRRR ratio RS = 50 Ω Full range 120 120 ddBB SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn VDD± = ±1.9 V to ±8 V, 25°C 110 135 110 135 kkSSVVRR ratio (∆VDD±/∆VIO) VO = 0, RS = 50 Ω Full range 110 110 ddBB 25°C 1.5 2.4 1.5 2.4 IIDDDD SSuuppppllyy ccuurrrreenntt VVOO == 00,, NNoo llooaadd mmAA Full range 2.5 2.5 ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. †Full range is −40° to 125°C for Q suffix, −55° to 125°C for M suffix. NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. 7. This parameter is not production tested. Thermocouple effects preclude measurement of the actual VIO of these devices in high speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes. The test ensures that the stabilization circuitry is performing properly. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 operating characteristics at specified free-air temperature, VDD± = ±5 V TLC2652Q TLC2652M PARAMETER TEST CONDITIONS TAA† TLC2652AM UNIT MIN TYP MAX 25°C 2 2.8 SSRR++ PPoossiittiivvee sslleeww rraattee aatt uunniittyy ggaaiinn VVOO == ±22..33 VV,, Full range 1.3 VV//µss RRLL == 1100 kkΩΩ,, 25°C 2.3 3.1 SSRR−− NNeeggaattiivvee sslleeww rraattee aatt uunniittyy ggaaiinn CCLL == 110000 ppFF VV//µss Full range 1.6 f = 10 Hz 25°C 94 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 1 kHz 25°C 23 nnVV//√√HHzz f = 0 to 1 Hz 25°C 0.8 VVNN((PPPP)) PPeeaakk--ttoo--ppeeaakk eeqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee f = 0 to 10 Hz 25°C 2.8 µVV In Equivalent input noise current f = 1 kHz 25°C 0.004 pA/√Hz f = 10 kHz, Gain-bandwidth product RL = 10 kΩ, 25°C 1.9 MHz CL = 100 pF φm Phase margin at unity gain RCLL == 11000 k ΩpF, 25°C 48° †Full range is −40° to 125°C for the Q suffix, −55° to 125°C for the M suffix. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 electrical characteristics at VDD± = ±5 V, TA = 25°C (unless otherwise noted) TLC2652Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX VIO Input offset voltage 0.6 3 µV Input offset voltage long-term drift (see Note 4) 0.003 0.006 µV/mo VVIICC == 00,, RRSS == 5500 ΩΩ IIO Input offset current 2 60 pA IIB Input bias current 4 60 pA −−55 VVIICCRR CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee rraannggee RRSS == 5500 ΩΩ ttoo VV 3.1 VOM+ Maximum positive peak output voltage swing RL = 10 kΩ, See Note 5 4.7 4.8 V VOM− Maximum negative peak output voltage swing RL = 10 kΩ, See Note 5 −4.7 −4.9 V AVD Large-signal differential voltage amplification VO = ±4 V, RL = 10 kΩ 120 150 dB fch Internal chopping frequency 450 Hz Clamp on-state current RL = 100 kΩ 25 µA Clamp off-state current VO = −4 V to 4 V 100 pA VO = 0, VIC = VICRmin, CMRR Common-mode rejection ratio 120 140 dB RS = 50 Ω VDD± = ±1.9 V to ±8 V, kkSSVVRR SSuuppppllyy--vvoollttaaggee rreejjeeccttiioonn rraattiioo ((∆∆VVDDDD±//∆∆VVIIOO)) RS = 50 Ω VO = 0, 111100 113355 ddBB IDD Supply current VO = 0, No load 1.5 2.4 mA NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV. 5. Output clamp is not connected. operating characteristics at VDD± = ±5 V, TA = 25°C TLC2652Y PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP MAX SR+ Positive slew rate at unity gain VVOO == ±±22..33 VV,, RRLL == 1100 kkΩΩ,, 2 2.8 V/µs SR− Negative slew rate at unity gain CL = 100 pF 2.3 3.1 V/µs f = 10 Hz 94 VVnn EEqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee nnVV//√√HHzz f = 1 kHz 23 f = 0 to 1 Hz 0.8 VVNN((PPPP)) PPeeaakk--ttoo--ppeeaakk eeqquuiivvaalleenntt iinnppuutt nnooiissee vvoollttaaggee µVV f = 0 to 10 Hz 2.8 In Equivalent input noise current f = 1 kHz pA/√Hz f = 10 kHz, RL = 10 kΩ, Gain-bandwidth product 1.9 MHz CL = 100 pF φm Phase margin at unity gain RL = 10 kΩ, CL = 100 pF 48° POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS Table of Graphs FIGURE VIO Normalized input offset voltage vs Chopping frequency 1 vvss CCoommmmoonn--mmooddee iinnppuutt vvoollttaaggee 22 IIIIBB IInnppuutt bbiiaass ccuurrrreenntt vvss CChhooppppiinngg ffrreeqquueennccyy 33 vs Free-air temperature 4 vvss CChhooppppiinngg ffrreeqquueennccyy 55 IIIIOO IInnppuutt ooffffsseett ccuurrrreenntt vs Free-air temperature 6 Clamp current vs Output voltage 7 V(OPP) Maximum peak-to-peak output voltage vs Frequency 8 vvss OOuuttppuutt ccuurrrreenntt 99,, 1100 VVOOMM MMaaxxiimmuumm ppeeaakk oouuttppuutt vvoollttaaggee vs Free-air temperature 11, 12 vvss FFrreeqquueennccyy 1133 AAVVDD LLaarrggee--ssiiggnnaall ddiiffffeerreennttiiaall vvoollttaaggee aammpplliiffiiccaattiioonn vs Free-air temperature 14 vvss SSuuppppllyy vvoollttaaggee 1155 CChhooppppiinngg ffrreeqquueennccyy vs Free-air temperature 16 vvss SSuuppppllyy vvoollttaaggee 1177 IIDDDD SSuuppppllyy ccuurrrreenntt vs Free-air temperature 18 vvss SSuuppppllyy vvoollttaaggee 1199 IIOOSS SShhoorrtt--cciirrccuuiitt oouuttppuutt ccuurrrreenntt vs Free-air temperature 20 vvss SSuuppppllyy vvoollttaaggee 2211 SSRR SSlleeww rraattee vs Free-air temperature 22 SSmmaallll--ssiiggnnaall 2233 VVoollttaaggee--ffoolllloowweerr ppuullssee rreessppoonnssee Large-signal 24 VN(PP) Peak-to-peak equivalent input noise voltage vs Chopping frequency 25, 26 Vn Equivalent input noise voltage vs Frequency 27 vvss SSuuppppllyy vvoollttaaggee 2288 GGaaiinn--bbaannddwwiiddtthh pprroodduucctt vs Free-air temperature 29 vvss SSuuppppllyy vvoollttaaggee 3300 φφmm PPhhaassee mmaarrggiinn vvss FFrreeee--aaiirr tteemmppeerraattuurree 3311 vs Load capacitance 32 Phase shift vs Frequency 13 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† NORMALIZED INPUT OFFSET VOLTAGE INPUT BIAS CURRENT vs vs CHOPPING FREQUENCY COMMON-MODE INPUT VOLTAGE 70 25 VDD± = ±5 V VDD± = ±5 V 60 VIC = 0 TA = 25°C VV TA = 25°C µu 20 et − 50 − pA Offs 40 ent ut urr 15 p C d In 30 as e Bi maliz 20 put 10 Nor − In O − O 10 IIIB IB 5 VVI I 0 −10 0 100 1 k 10 k 100 k −5 −4 −3 −2 −1 0 1 2 3 4 5 Chopping Frequency − Hz VIC − Common-Mode Input Voltage − V Figure 1 Figure 2 INPUT BIAS CURRENT INPUT BIAS CURRENT vs vs CHOPPING FREQUENCY FREE-AIR TEMPERATURE 70 100 VDD± = ±5 V VVDOD =± 0 = ±5 V 60 TVAIC = = 2 05°C VIC = 0 A A Current − p 5400 Current − p IIB − Input Bias IIB 2300 IIB − Input Bias IIB 10 10 0 1 100 1 k 10 k 100 k 25 45 65 85 105 125 Chopping Frequency − Hz TA − Free-Air Temperature − °C Figure 3 Figure 4 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† INPUT OFFSET CURRENT INPUT OFFSET CURRENT vs vs CHOPPING FREQUENCY FREE-AIR TEMPERATURE 25 10 VDD± = ±5 V VDD± = ±5 V VIC = 0 VIC = 0 TA = 25°C A 20 A 8 p p − − nt nt e e urr 15 urr 6 C C et et s s Off Off ut 10 ut 4 p p n n − I − I O O O O IIII 5 IIII 2 0 0 100 1 k 10 k 100 k 25 45 65 85 105 125 Chopping Frequency − Hz TA − Free-Air Temperature − °C Figure 5 Figure 6 MAXIMUM PEAK-TO-PEAK OUTPUT CLAMP CURRENT VOLTAGE vs vs OUTPUT VOLTAGE FREQUENCY 100 µA V 10 − VDD± = ±5 V e 10 µA TA = 25°C oltag V 8 1 µA ut Positive Clamp Current utp TA = −55°C O rrent| 100 nA Peak 6 Cu 10 nA o- p k-t TA = 125°C m a |Cla 1 nA m Pe 4 u m 100 pA xi Ma 2 Negative Clamp Current 10 pA P) − P) VDD± = ±5 V 1 pA VO(PVO(P 0 RL = 10 kΩ 4 4.2 4.4 4.6 4.8 5 100 1 k 10 k 1 M |VO| − Output Voltage − V f − Frequency − Hz Figure 7 Figure 8 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE vs vs OUTPUT CURRENT OUTPUT CURRENT 5 7.5 − V VTAD D= ±2 5=° C±5 V − V TVAD D= ±2 5=° C±7.5 V e e ag 4.8 ag Volt VOM+ Volt 7.3 put VOM− put VOM+ VOM− ut 4.6 ut O O k k ea ea 7.1 P P m 4.4 m u u m m xi xi a a M M M| − M 4.2 M| − M 6.9 OO OO VV VV || || 4 6.7 0 0.4 0.8 1.2 1.6 2 0 0.4 0.8 1.2 1.6 2 |IO| − Output Current − mA |IO| − Output Current − mA Figure 9 Figure 10 MAXIMUM PEAK OUTPUT VOLTAGE MAXIMUM PEAK OUTPUT VOLTAGE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 5 8 V V − − e e g g olta 2.5 olta 4 V V ut ut p p Out VDD± = ±5 V Out VDD± = ±7.5 V ak 0 RL = 10 kΩ ak 0 RL = 10 kΩ e e P P m m u u m m Maxi −2.5 Maxi −4 − − M M M M OO OO VV VV −5 −8 −75 −50 −25 0 25 50 75 100 125 −75 −50 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C Figure 11 Figure 12 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION AND PHASE SHIFT vs FREQUENCY 120 60° 100 Phase Shift 80° al nti dB 80 100° re − AVD al Diffe cation 60 120° hift Sign mplifi 40 140° se S arge- ge A 20 160° Pha L a ÁÁVD − VDÁÁVolt 0 180° AA VDD± = ±5 V ÁÁ−20 RL = 10 kΩ 200° CL = 100 pF TA = 25°C −40 220° 10 100 1 k 10 k 100 k 1 M 10 M f − Frequency − Hz Figure 13 LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE 155 VDD± = ±7.5 V RL = 10 kΩ VO = ±4 V al nti dB 150 re − al Diffe cation Sign mplifi 145 e- A rg e a g ÁÁVD − LÁÁVDVolta 140 AA ÁÁ 135 −75 −50 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C Figure 14 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† CHOPPING FREQUENCY CHOPPING FREQUENCY vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 540 460 TA = 25°C VDD± = ±5 V 520 450 Hz Hz Chopping Frequency − k 445860000 Chopping Frequency − k 444324000 440 410 420 400 0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125 |VDD±| − Supply Voltage − V TA − Free-Air Temperature − °C Figure 15 Figure 16 SUPPLY CURRENT SUPPLY CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 2 2 VO = 0 VDD± = ±7.5 V No Load 1.6 1.6 VDD± = ±5 V A A m m − − ent 1.2 TA = 25°C ent 1.2 VDD± = ±2.5 V urr urr C C ply TA = −55°C ply p 0.8 p 0.8 u u S S − − D D TA = 125°C D D DD DD II 0.4 II 0.4 VO = 0 No Load 0 0 0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125 |VDD ±| − Supply Voltage − V TA − Free-Air Temperature − °C Figure 17 Figure 18 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† SHORT-CIRCUIT OUTPUT CURRENT SHORT-CIRCUIT OUTPUT CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 12 15 VO = 0 VDD± = ±5 V A TA = 25°C A VO = 0 m m − 8 − 10 nt nt e e urr 4 urr 5 ut C ut C VID = −100 mV utp VID = −100 mV utp O 0 O 0 uit uit c c Cir −4 Cir −5 ort- ort- VID = 100 mV h h S S OS − OS −8 VID = 100 mV OS − OS −10 II II −12 −15 0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125 |VDD ±| − Supply Voltage − V TA − Free-Air Temperature − °C Figure 19 Figure 20 SLEW RATE SLEW RATE vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 4 4 VDD± = ±5 V SR− RL = 10 kΩ SR− CL = 100 pF 3 3 µsV?usV/ SR+ µsV?usV/ SR+ − − e e Rat 2 Rat 2 w w e e Sl Sl − − R R S S 1 1 RL = 10 kΩ CL = 100 pF TA = 25°C 0 0 0 1 2 3 4 5 6 7 8 −75 −50 −25 0 25 50 75 100 125 |VDD±| − Supply Voltage − V TA − Free-Air Temperature − °C Figure 21 Figure 22 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS VOLTAGE-FOLLOWER VOLTAGE-FOLLOWER SMALL-SIGNAL LARGE-SIGNAL PULSE RESPONSE PULSE RESPONSE 100 4 VDD± = ±5 V RL = 10 kΩ 75 3 CL = 100 pF TA = 25°C 50 2 V m V e − 25 VDD± = ±5 V ge − 1 oltag RCLL == 1100 0k ΩpF Volta ut V 0 TA = 25°C put 0 VO − OutpVO −−5205 VO − OutVO −−12 −75 −3 −100 −4 0 1 2 3 4 5 6 7 0 5 10 15 20 25 30 35 40 t − Time − µs t − Time − µs Figure 23 Figure 24 PEAK-TO-PEAK INPUT NOISE VOLTAGE PEAK-TO-PEAK INPUT NOISE VOLTAGE vs vs CHOPPING FREQUENCY CHOPPING FREQUENCY 1.8 5 µe −uVV 1.6 VRDSD =± 2 =0 Ω±5 V µVe − uV VRDSD =± 2 =0 Ω±5 V ag f = 0 to 1 Hz ag f = 0 to 10 Hz olt 1.4 TA = 25°C olt 4 TA = 25°C V V e e s 1.2 s oi oi N N ut 1 ut 3 p p n n ak I 0.8 ak I e e P P 2 k-to- 0.6 k-to- a a e e P 0.4 P − − 1 P) P) P) P) PP 0.2 PP VN(V N( V VN(N( 0 0 0 2 4 6 8 10 0 2 4 6 8 10 fch − Chopping Frequency − kHz fch − Chopping Frequency − kHz Figure 25 Figure 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† EQUIVALENT INPUT NOISE VOLTAGE GAIN-BANDWIDTH PRODUCT vs vs FREQUENCY SUPPLY VOLTAGE 100 2.1 z Hz RL = 10 kΩ H nV/e − nV/ 80 Hz TCAL == 2150°0C pF g M Volta ct − 2 oise 60 rodu N P put dth n 40 wi ent I and 1.9 al B − Equiv 20 VDD± = ±5 V Gain- n n RS = 20 Ω VV TA = 25°C 0 1.8 1 10 100 1 k 0 1 2 3 4 5 6 7 8 f − Frequency − Hz |VCC±| − Supply Voltage − V Figure 27 Figure 28 GAIN-BANDWIDTH PRODUCT PHASE MARGIN vs vs FREE-AIR TEMPERATURE SUPPLY VOLTAGE 2.6 50° VDD± = ±5 V RL = 10 kΩ RL = 10 kΩ CL = 100 pF z 2.4 CL = 100 pF 48° TA = 25°C H M − duct 2.2 argin 46° o M h Pr 2 se dt ha dwi − P 44° an 1.8 m m B φo n- Gai 42° 1.4 1.2 40° −75 −50 −25 0 25 50 75 100 125 0 1 2 3 4 5 6 7 8 TA − Free-Air Temperature − °C |VCC±| − Supply Voltage − V Figure 29 Figure 30 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 TYPICAL CHARACTERISTICS† PHASE MARGIN PHASE MARGIN vs vs FREE-AIR TEMPERATURE LOAD CAPACITANCE 50° 60° VDD± = ±5 V RL = 10 kΩ 50° TA = 25°C 48° n n 40° argi 46° argi M M se se 30° a a h h − P 44° − P m m m m 20° φo φo 42° VDD± = ±5 V 10° RL = 10 kΩ CL = 100 pF 40° 0° −75 −50 −25 0 25 50 75 100 125 0 200 400 600 800 1000 TA − Free-Air Temperature − °C CL − Load Capacitance − pF Figure 31 Figure 32 †Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. APPLICATION INFORMATION capacitor selection and placement The two important factors to consider when selecting external capacitors C and C are leakage and XA XB dielectric absorption. Both factors can cause system degradation, negating the performance advantages realized by using the TLC2652. Degradation from capacitor leakage becomes more apparent with the increasing temperatures. Low-leakage capacitors and standoffs are recommended for operation at T = 125°C. In addition, guard bands are A recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems caused by surface leakage on circuit boards. Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which directly affects input offset voltage. In applications where fast settling of input offset voltage is needed, it is recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. In other applications, however, a ceramic or other low-grade capacitor can suffice. Unlike many choppers available today, the TLC2652 is designed to function with values of CXA and CXB in the range of 0.1 µF to 1 µF without degradation to input offset voltage or input noise voltage. These capacitors should be located as close as possible to the CXA and CXB pins and returned to either VDD− or C RETURN. On many choppers, connecting these capacitors to VDD− causes degradation in noise performance. This problem is eliminated on the TLC2652. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 APPLICATION INFORMATION internal/external clock The TLC2652 has an internal clock that sets the chopping frequency to a nominal value of 450 Hz. On 8-pin packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages and the 20-pin FK package, the device chopping frequency can be set by the internal clock or controlled externally by use of the INT/EXT and CLK IN pins. To use the internal 450-Hz clock, no connection is necessary. If external clocking is desired, connect INT/EXT to VDD− and the external clock to CLK IN. The external clock trip point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above the negative rail. If this level is exceeded, damage could occur to the device unless the current into CLK IN is limited to ±5 mA. When operating in the single-supply configuration, this feature allows the TLC2652 to be driven directly by 5-V TTL and CMOS logic. A divide-by- two frequency divider interfaces with CLK IN and V 0 soef ttsh eth eex ctleorcnka cl hcolopcpki nisg fnroetq ucerinticcay.l Tbhuet sdhuotyu lcdy cblee age − VTAD D= ±2 5=° ±C5 V kept between 30% and 60%. Volt ut p overload recovery/output clamp ut O When large differential input voltage conditions O − O −5 VV aatrtee mapptpsl iteod p rteov ethnet thTeL Cou2t6p5u2t ,f rothme snautullrinagti nlgo obpy V m 0 lderviveinlsg. OCXnAce a nthde C oXvBe trod riinvtee rcnoanlldy-itciolanm ipse rde mvooltvaegde, ge − a a period of time is required to allow the built-up olt charge to dissipate. This time period is defined as ut V overload recovery time (see Figure 33). Typical p n overload recovery time for the TLC2652 is − I significantly faster than competitive products; VI VI −50 0 10 20 30 40 50 60 70 80 however, if required, this time can be reduced t − Time − ms further by use of internal clamp circuitry accessible through CLAMP if required. Figure 33. Overload Recovery The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop gain is reduced, and the TLC2652 output is prevented from going into saturation. Since the output must source or sink current through the switch (see Figure 7), the maximum output voltage swing is slightly reduced. thermoelectric effects To take advantage of the extremely low offset voltage drift of the TLC2652, care must be taken to compensate for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such as device leads being soldered to a printed circuit board). Dissimilar metal junctions can produce thermoelectric voltages in the range of several microvolts per degree Celsius (orders of magnitude greater than the 0.01-µV/°C typical of the TLC2652). To help minimize thermoelectric effects, careful attention should be paid to component selection and circuit-board layout. Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the input signal path. Cancel thermoelectric effects by duplicating the number of components and junctions in each device input. The use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also beneficial. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 APPLICATION INFORMATION latch-up avoidance Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close to the device as possible. The current path established if latch-up occurs is usually between the supply rails and is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up occurring increases with increasing temperature and supply voltage. electrostatic discharge protection The TLC2652 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric performance. theory of operation Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier. This superior performance is the result of using two operational amplifiers, a main amplifier and a nulling amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single amplifier. With this approach, the TLC2652 achieves submicrovolt input offset voltage, submicrovolt noise voltage, and offset voltage variations with temperature in the nV/°C range. The TLC2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying phase. The term chopper-stabilized derives from the process of switching between these two clock phases. Figure 34 shows a simplified block diagram of the TLC2652. Switches A and B are make-before-break types. During the nulling phase, switch A is closed shorting the nulling amplifier inputs together and allowing the nulling amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node. Simultaneously, external capacitor CXA stores the nulling potential to allow the offset voltage of the amplifier to remain nulled during the amplifying phase. Main Amplifier IN+ + VO IN− − B CXB B A + VDD− − Null A Amplifier CXA Figure 34. TLC2652 Simplified Block Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

(cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:8)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4)(cid:5)(cid:6)(cid:4)(cid:9) (cid:8)(cid:10)(cid:11)(cid:12)(cid:13)(cid:14)(cid:15)(cid:10) (cid:2)(cid:16)(cid:13)(cid:3)(cid:17)(cid:18)(cid:19) (cid:20)(cid:21)(cid:22)(cid:3)(cid:23)(cid:19)(cid:23)(cid:18)(cid:24) (cid:3)(cid:25)(cid:18)(cid:20)(cid:20)(cid:22)(cid:21)(cid:26)(cid:19)(cid:1)(cid:8)(cid:27)(cid:23)(cid:2)(cid:23)(cid:28)(cid:22)(cid:29) (cid:18)(cid:20)(cid:22)(cid:21)(cid:8)(cid:1)(cid:23)(cid:18)(cid:24)(cid:8)(cid:2) (cid:8)(cid:17)(cid:20)(cid:2)(cid:23)(cid:30)(cid:23)(cid:22)(cid:21)(cid:19) SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005 APPLICATION INFORMATION theory of operation (continued) During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also, external capacitor C stores the nulling potential to allow the offset voltage of the main amplifier to remain XB nulled during the next nulling phase. This continuous chopping process allows offset voltage nulling during variations in time and temperature over the common-mode input voltage range and power supply range. In addition, because the low-frequency signal path is through both the null and main amplifiers, extremely high gain is achieved. The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces the input noise voltage. The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing chopping frequency. This problem has been significantly reduced in the TLC2652 by use of a patent-pending compensation circuit and the Advanced LinCMOS process. The TLC2652 incorporates a feed-forward design that ensures continuous frequency response. Essentially, the gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the main amplifier. As a result, the high-frequency response of the system is the same as the frequency response of the main amplifier. This approach also ensures that the slewing characteristics remain the same during both the nulling and amplifying phases. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9089501MPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9089501MPA TLC2652M 5962-9089503MCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9089503MC A TLC2652AMJB 5962-9089503MPA ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9089503MPA TLC2652AM TLC2652AC-14D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652AC & no Sb/Br) TLC2652AC-8D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652AC & no Sb/Br) TLC2652ACN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type TLC2652ACN & no Sb/Br) TLC2652ACP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TLC2652AC & no Sb/Br) TLC2652AI-14D ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652AI & no Sb/Br) TLC2652AI-8D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652AI & no Sb/Br) TLC2652AI-8DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652AI & no Sb/Br) TLC2652AIN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type TLC2652AIN & no Sb/Br) TLC2652AIP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TLC2652AI & no Sb/Br) TLC2652AMJB ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9089503MC A TLC2652AMJB TLC2652AMJG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 TLC2652 AMJG TLC2652AMJGB ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9089503MPA TLC2652AM TLC2652C-8D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652C & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) TLC2652C-8DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652C & no Sb/Br) TLC2652C-8DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652C & no Sb/Br) TLC2652CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type TLC2652CN & no Sb/Br) TLC2652CP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TLC2652CP & no Sb/Br) TLC2652I-8D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652I & no Sb/Br) TLC2652I-8DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 2652I & no Sb/Br) TLC2652IP ACTIVE PDIP P 8 50 Green (RoHS NIPDAU N / A for Pkg Type TLC2652IP & no Sb/Br) TLC2652M-8DG4 ACTIVE SOIC D 8 1000 Green (RoHS NIPDAU Level-1-260C-UNLIM T2652M & no Sb/Br) TLC2652MJG ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 TLC2652MJG TLC2652MJGB ACTIVE CDIP JG 8 1 TBD Call TI N / A for Pkg Type -55 to 125 9089501MPA TLC2652M TLC2652Q-8D ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 T2652Q & no Sb/Br) TLC2652Q-8DG4 ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM T2652Q & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLC2652, TLC2652A, TLC2652AM, TLC2652M : •Catalog: TLC2652A, TLC2652 •Military: TLC2652M, TLC2652AM NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2010 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) TLC2652AI-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC2652C-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 TLC2652I-8DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Oct-2010 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) TLC2652AI-8DR SOIC D 8 2500 340.5 338.1 20.6 TLC2652C-8DR SOIC D 8 2500 340.5 338.1 20.6 TLC2652I-8DR SOIC D 8 2500 340.5 338.1 20.6 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (10,16) 0.355 (9,00) 8 5 0.280 (7,11) 0.245 (6,22) 1 4 0.065 (1,65) 0.045 (1,14) 0.063 (1,60) 0.020 (0,51) MIN 0.310 (7,87) 0.015 (0,38) 0.290 (7,37) 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0°–15° 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 4040107/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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