THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS FEATURES 1 THS4021 THS4022 • Ultralow1.5-nV/√HzVoltageNoise D and DGN Package D and DGN Package 23 • HighSpeed: (Top View) (Top View) – 350-MHzBandwidth(G=10,–3dB) NULL 1 8 NULL 1OUT 1 8 V CC+ – 470-V/μsSlewRate IN– 2 7 V 1IN– 2 7 2OUT CC+ – 40-nsSettlingTime(0.1%) IN+ 3 6 OUT 1IN+ 3 6 2IN– • StableataGainof10(–9)orGreater VCC– 4 5 NC –VCC 4 5 2IN+ • HighOutputDrive,I =100mA(typ) O NC - No internal connection • ExcellentVideoPerformance: – 17-MHzBandwidth(0.1dB,G=10) – 0.02%DifferentialGain Cross Section View Showing PowerPAD Option (DGN) – 0.08(cid:176) DifferentialPhase • VeryLowDistortion: VOLTAGEANDCURRENTNOISE vs – THD=–68dBc(f=1MHz,R =150Ω) L FREQUENCY • WideRangeofPowerSupplies: 100 VCC = ± 15 V and ± 5 V – VCC=±5Vto±15V TA = 25°C • AvailableinStandardSOICorMSOP PowerPAD™Package Hz Hz • EvaluationModuleAvailable (cid:1)V/ (cid:1)A/ n p − − DTnohEiesSe,TCHhRSigI4Ph0-T2sp1IOeeaNdndvoTltHaSge40f2e2edabraeckulatrmalpolwifievrsoltathgaet age Noise ent Noise 10 are ideal for applications requiring low voltage noise, olt urr isninclguldei-nagmplifcieormmTuHnSic4a0t2io1n anadndtheimdaugainl-ga.mplTifiheer V − Vn I − Cn Vn THS4022 offer very good ac performance with 350-MHz bandwidth, 470-V/μs slew rate, and 40-ns In settling time (0.1%). The THS4021 and THS4022 are stable at gains of 10 (–9) or greater. These amplifiers 1 10 100 1k 10k 100k have a high drive capability of 100 mA and draw only 7.8-mA supply current per channel. With total f − Frequency − Hz G001 harmonic distortion (THD) of –68 dBc at f = 1 MHz, Figure1. the THS4021 and THS4022 are ideally suited for applicationsrequiringlowdistortion. RELATEDDEVICES DEVICE DESCRIPTION THS4011/4012 290-MHzLow-DistortionHigh-SpeedAmplifiers THS4031/4032 100-MHzLow-NoiseHigh-SpeedAmplifiers THS4061/4062 180-MHzHigh-SpeedAmplifiers 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PowerPADisatrademarkofTexasInstruments. 2 Allothertrademarksarethepropertyoftheirrespectiveowners. 3 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©1999–2007,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 CAUTION:TheTHS4021andTHS4022provideESDprotectioncircuitry.However,permanentdamagecanstilloccurifthisdevice is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradationorlossoffunctionality. AVAILABLEOPTIONS(1) PACKAGEDDEVICES TA NCUHMABNENRELOSF SMALPLLAOSUTTILCINE(2) PLASTICMSOP(2) MSOPSYMBOL EVMAOLUDAUTLIEON (DGN) (D) 1 THS4021CD THS4021CDGN ACK THS4021EVM 0(cid:176) Cto70(cid:176) C 2 THS4022CD THS4022CDGN ACA THS4022EVM 1 THS4021ID THS4021CIDGN ACL – –40(cid:176) Cto85(cid:176) C 2 THS4022ID THS4022CIDGN ACB – (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI Websiteatwww.ti.com. (2) TheDandDGNpackagesareavailabletapedandreeled.AddanRsuffixtothedevicetype(forexample,THS4021CDGN). FUNCTIONAL BLOCK DIAGRAMS Null 1 2 IN– 8 6 OUT 3 IN+ S0273-01 Figure2.THS4021—SingleChannel V CC 1IN– 1OUT 1IN+ 2IN– 2OUT 2IN+ –V CC S0274-01 Figure3.THS4022—DualChannel 2 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 ABSOLUTE MAXIMUM RATINGS(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT V Supplyvoltage ±16.5 V CC V Inputvoltage ±V V I CC I Outputcurrent 150 mA O V Differentialinputvoltage ±4 V IO Continuoustotalpowerdissipation SeeDissipationRatingstable T Maximumjunctiontemperature 150 (cid:176) C J Operatingfree-airtemperature:C-suffix 0to70 T (cid:176) C A I-suffix –40to85 T Storagetemperature –65to150 (cid:176) C stg Leadtemperature1,6mm(1/16inch)fromcasefor10seconds 300 (cid:176) C (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. DISSIPATION RATINGS θ θ T =25(cid:176) C PACKAGE ((cid:176) CJ/AW) ((cid:176) CJ/CW) POWAERRATING D(1) 167 38.3 740mW DGN(2) 58.4 4.7 2.14W (1) ThisdatawastakenusingtheJEDECstandardlow-KtestPCB.FortheJEDECproposedhigh-KtestPCB,theθ is95(cid:176) C/Wwitha JA powerratingatT =25(cid:176) Cof1.32W. A (2) Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadona3-in.· 3-in.(7.62-cm· 7.62-cm)PCB,withthedevice soldereddirectlytotheboard.Forfurtherinformation,seetheApplicationInformationsectionofthisdatasheet. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Dualsupply ±4.5 ±16 V andV Supplyvoltage V CC+ CC– Singlesupply 9 32 C-suffix 0 70 T Operatingfree-airtemperature (cid:176) C A I-suffix –40 85 ELECTRICAL CHARACTERISTICS atT =25(cid:176) C,V =±15V,R =150Ω(unlessotherwisenoted) A CC L PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DynamicPerformance V =±15V 350 CC Gain=10 Small-signalbandwidth VCC=±5V 280 (–3dB) V =±15V 80 CC Gain=20 V =±5V 70 CC BW MHz V =±15V 17 CC Bandwidthfor01-dBflatness Gain=10 V =±5V 17 CC V =20V,V =±15V 3.7 Fullpowerbandwidth(1) O(pp) CC V =5V,V =±5V 11.8 O(pp) CC V =±15V,10-Vstep 470 SR Slewrate(2) CC Gain=10 V/μs V =±5V,5-Vstep 370 CC (1) Full-powerbandwidth=slewrate/2πV . O(Peak) (2) Slewrateismeasuredfromanoutputlevelrangeof25%to75%. Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS (continued) atT =25(cid:176) C,V =±15V,R =150Ω(unlessotherwisenoted) A CC L PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =±15V,5-Vstep 40 CC Settlingtimeto0.1% Gain=–10 V =±5V,2-Vstep 50 CC t ns s V =±15V,5-Vstep 145 CC Settlingtimeto0.01% Gain=–10 V =±5V,2-Vstep 150 CC Noise/DistortionPerformance VO(pp)=2V,f=1MHz, RL=150Ω –68 gain=2,VCC=±15V RL=1kΩ –77 THD Totalharmonicdistortion dBc VO(pp)=2V,f=1MHz, RL=150Ω –69 gain=2,VCC=±5V RL=1kΩ –78 V Inputvoltagenoise V =±5Vor±15V,f>10kHz 1.5 nV/√Hz n CC I Inputcurrentnoise V =±5Vor±15V,f>10kHz 2 pA/√Hz n CC Gain=2,NTSC,40IRE VCC=±15 0.02% Differentialgainerror modulation,±100IREramp V =±5V 0.02% CC Differentialphaseerror Gain=2,NTSC,40IRE VCC=±15 0.08 (cid:176) modulation,±100IREramp V =±5V 0.06 CC Channel-to-channelcrosstalk X V =±5Vor±15V,f=1MHz –60 dB T (THS4022only) CC DCPerformance VCC=±15V,VO=±10V, TA=25(cid:176) C 40 60 RL=1kΩ TA=fullrange 35 Open-loopgain V/mV VCC=±5V,VO=±2.5V, TA=25(cid:176) C 20 35 RL=250Ω TA=fullrange 15 T =25(cid:176) C 0.5 2 A V Inputoffsetvoltage mV OS T =fullrange 3 A Offsetvoltagedrift T =fullrange 15 μV/(cid:176) C A V =±5Vor±15V T =25(cid:176) C 3 6 CC A I Inputbiascurrent μA IB T =fullrange 6 A T =25(cid:176) C 30 250 A I Inputoffsetcurrent nA OS T =fullrange 400 A Offsetcurrentdrift T =fullrange 0.3 nA/(cid:176) C A InputCharacteristics Common-modeinputvoltage VCC=±15V ±13.8 ±14.3 V V ICR range V =±5V ±3.8 ±4.3 CC CMRR Common-moderejectionratio V =±15V,V =±12V,T =fullrange 74 95 dB CC ICR A r Inputresistance 1 MΩ i C Inputcapacitance 1.5 pF i OutputCharacteristics V =±15V R =250Ω ±12 ±12.5 CC L V =±5V R =150Ω ±3 ±3.3 CC L V Outputvoltageswing V O V =±15V ±13 ±13.5 CC R =1kΩ L V =±5V ±3.4 ±3.8 CC V =±15V 80 100 CC I Outputcurrent R =20Ω mA O L V =±5V 50 75 CC I Short-circuitcurrent(3) V =±15V 150 mA SC CC R Outputresistance(3) Openloop 13 Ω O (3) Observepowerdissipationratingstokeepthejunctiontemperaturebelowtheabsolutemaximumratingwhentheoutputisheavily loadedorshorted.SeetheAbsoluteMaximumRatingstableofthisdatasheetformoreinformation. 4 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 ELECTRICAL CHARACTERISTICS (continued) atT =25(cid:176) C,V =±15V,R =150Ω(unlessotherwisenoted) A CC L PARAMETER TESTCONDITIONS MIN TYP MAX UNIT PowerSupply Supplyvoltageoperating Dualsupply ±4.5 ±16.5 V V CC range Singlesupply 9 33 T =25(cid:176) C 7.8 10 A V =±15V CC T =fullrange 11 A I Supplycurrent(peramplifier) mA CC T =25(cid:176) C 6.7 9 A V =±5V CC T =fullrange 10.5 A PSRR Power-supplyrejectionratio V =±5Vor±15V,T =fullrange 80 95 dB CC A TYPICAL CHARACTERISTICS CROSSTALK OPENLOOPGAINANDPHASERESPONSE vs vs FREQUENCY FREQUENCY 10 120 30 0 VCC = ± 15 V VCC = ± 5 V & ±15 V Gain = 10 100 0 −10 RF = 220 W Gain B −20 RL = 150 W − dB 80 −30 osstalk − d −−4300 Loop Gain 4600 Phase −−9600 (cid:1)Phase − Cr −50 en Op 20 −120 −60 −70 0 −150 −80 −20 −180 1M 10M 100M 1G 1k 10k 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz G002 G003 Figure4. Figure5. TOTALHARMONICDISTORTION DISTORTION DISTORTION vs vs vs FREQUENCY OUTPUTVOLTAGE OUTPUTVOLTAGE −40 −10 −10 n − dBc −50 VGVCOaC(inP P==) ±1= 0 125 VV −30 VRGf =CL = C1= 1 =M10 ±Hk Wz15 V −30 VRGf =CL = C1= 1 =M10 5±H0 z1 W5 V o nic Distorti −−7600 RL = 150 W on − dBc −50 2nd Harmonic on − dBc −50 2nd Harmonic otal Harmo −80 RL = 1 kW Distorti −70 Distorti −70 3rd Harmonic T −90 −90 − −90 HD 3rd Harmonic T −100 −110 −110 100k 1M 10M 0 5 10 15 20 0 5 10 15 20 f − Frequency − Hz VO − Output Voltage − V VO − Output Voltage − V G004 G005 G006 Figure6. Figure7. Figure8. Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) DISTORTION DISTORTION DISTORTION vs vs vs FREQUENCY FREQUENCY FREQUENCY −50 −50 −50 VRCL C= =1 ±k W15 V VRCL C= =1 ±k W5 V VRCL C= =1 5±0 1 W5 V −60 G = 10 −60 G = 10 −60 G = 10 VO(PP) = 2 V VO(PP) = 2 V 2nd Harmonic VO(PP) = 2 V Bc Bc Bc 2nd Harmonic d −70 d −70 d −70 − − − on 2nd Harmonic on on storti −80 storti −80 storti −80 Di Di Di 3rd Harmonic 3rd Harmonic −90 −90 −90 3rd Harmonic −100 −100 −100 100k 1M 10M 100k 1M 10M 100k 1M 10M f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz G007 G008 G009 Figure9. Figure10. Figure11. DISTORTION OUTPUTAMPLITUDE OUTPUTAMPLITUDE vs vs vs FREQUENCY FREQUENCY FREQUENCY −40 25 25 VCC = ± 5 V RL = 150 W −50 G = 10 2nd Harmonic VO(PP) = 2 V dB RF = 220 W dB RF = 220 W − dBc −60 ude − 20 ude − 20 ortion −70 Amplit RF = 150 W Amplit RF = 150 W Dist −80 3rd Harmonic put 15 put 15 Out VCC = ± 15 V Out VCC = ± 5 V Gain = 10 Gain = 10 −90 RL = 150 W RL = 150 W VO(PP) = 400 mV VO(PP) = 400 mV −100 10 10 100k 1M 10M 10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz G010 G011 G012 Figure12. Figure13. Figure14. OUTPUTAMPLITUDE OUTPUTAMPLITUDE vs vs FREQUENCY FREQUENCY 1-VSTEPRESPONSE 30 30 0.8 RF = 6.2 kW RF = 6.2 kW 0.6 ut Amplitude − dB 2205 RF = 220 W ut Amplitude − dB 2205 RF = 220 W Output Voltage − V 000...024 Outp 1105 VGRVCOLa C(i=nP P=1=) 5 ±2=010 54W 0V0 mV RF = 1 kW Outp 1105 VGRVCOLa C(i=nP P=1=) 5 ±2=050 4WV00 mV RF = 1 kW V − O −−−000...642 VGRRCFLa Ci==n =12= 52 ±100 05 WW V 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G 0 50 100 150 200 250 300 350 400 f − Frequency − Hz f − Frequency − Hz t − Time − ns G013 G014 G015 Figure15. Figure16. Figure17. 6 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) 5-VSTEPRESPONSE 1-VSTEPRESPONSE 10-VSTEPRESPONSE 3 0.8 6 0.6 2 4 V V V V − Output Voltage − O −−0121 VGRRCFLa Ci==n =1=2 52 ±−00 15 WW0 V V − Output Voltage − O −−00000.....02442 VGRRCFLa Ci==n =12= 52 ±100 01 WW5 V V − Output Voltage − O −−0242 VGRRCFLa Ci==n =12= 52 ±100 01 W5 V −3 −0.6 −6 0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400 0 100 200 300 400 500 t − Time − ns t − Time − ns t − Time − ns G016 G017 G018 Figure18. Figure19. Figure20. INPUTOFFSETVOLTAGE INPUTBIASCURRENT OUTPUTVOLTAGE vs vs vs FREE-AIRTEMPERATURE FREE-AIRTEMPERATURE SUPPLYVOLTAGE −0.05 3.30 14 VCC = ± 5 V & ±15 V TA = 25°C V 3.25 12 V − Input Offset Voltage − mIO−−−−0000....22115050 VCC = ± 15 VVCC = ± 5 V mI − Input Bias Current − AIB 3333....01125050 |V| − Output Voltage − |V|O 10468 RL = 1R Lk W= 150 W −0.30 3.00 2 −40 −20 0 20 40 60 80 100 −40 −20 0 20 40 60 80 100 5 7 9 11 13 15 TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C (cid:1)VCC − Supply Voltage − V G019 G020 G021 Figure21. Figure22. Figure23. COMMON-MODEINPUTVOLTAGE OUTPUTVOLTAGE SUPPLYCURRENT vs vs vs SUPPLYVOLTAGE FREE-AIRTEMPERATURE SUPPLYVOLTAGE 15 14 11 V (cid:1) − Common−Mode Input Voltage − R 1113579 TA = 25°C |V| − Output Voltage − |V|O 11022468 VRCL CVR= C=L1 C =±k =W11 5±k WV5 V VRVRCL CLC= C = =2 = 51± 05± 1 0 W55 W VV I − Supply Current − mACC 106789 TTTAAA===82−554°°0CC°C C VI 3 0 5 5 7 9 11 13 15 −40 −20 0 20 40 60 80 100 5 7 9 11 13 15 (cid:1)VCC − Supply Voltage − V TA − Free-Air Temperature − °C (cid:1)VCC − Supply Voltage − V G022 G023 G024 Figure24. Figure25. Figure26. Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 TYPICAL CHARACTERISTICS (continued) VOLTAGEANDCURRENTNOISE POWERSUPPLYREJECTIONRATIO COMMONMODEREJECTIONRATIO vs vs vs FREQUENCY FREQUENCY FREQUENCY (cid:1)V − Voltage Noise − nV/Hzn(cid:1)I − Current Noise − pA/Hzn101010 VTACI nC= =2 5±° C1V5n V and ± 5 V PSRR − Power Supply Rejection Ratio − dB −−−−−−−−87654321000000000 VCC = ±15 V &−V ±C5C V +VCC CMRR − Common-Mode Rejection Ratio − dB −−−−−−6543210000000 VRVCIF(P C=P =)2 =0± 12k5 WV V or ±5 V 10 100 1k 10k 100k 100k 1M 10M 100M 1G 100k 1M 10M 100M 1G f − Frequency − Hz f − Frequency − Hz f − Frequency − Hz G025 G026 G027 Figure27. Figure28. Figure29. 8 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 APPLICATION INFORMATION Theory of Operation The THS402x is a high-speed operational amplifier configured in a voltage feedback architecture. It is built using a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f of T several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew rate,fastsettlingtime,andlowdistortion.AsimplifiedschematicisshowninFigure30. (7) V CC+ (6) OUT IN–(2) IN+ (3) (4) V CC– NULL(1) NULL(8) S0276-01 Figure30.THS4021SimplifiedSchematic Noise Calculations and Noise Figure Noise can cause errors on very small signals. This is especially true when amplifying small signals, where signal-to-noise ratio (SNR) is very important. The noise model for the THS402x is shown in Figure 31. This modelincludesallofthenoisesourcesasfollows: • e =Amplifierinternalvoltagenoise(nV/√Hz) n • IN+=Noninvertingcurrentnoise(pA/√Hz) • IN–=Invertingcurrentnoise(pA/√Hz) • e =Thermalvoltagenoiseassociatedwitheachresistor(e =4kTR ) Rx Rx x Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 e e R Rs n Noiseless S eni + e _ no IN+ e Rf R F e IN– Rg R G S0277-01 Figure31.NoiseModel Thetotalequivalentinputnoisedensity(e )iscalculatedbyusingthefollowingequation: ni (cid:7) 2 2 2 eni(cid:3) (cid:5)en(cid:6) (cid:2)(cid:5)IN+(cid:1)RS(cid:6) (cid:2)(cid:5)IN−(cid:1)(cid:5)RF(cid:4) RG(cid:6)(cid:6) (cid:2)4kTRs(cid:2)4kT(cid:5)RF (cid:4) RG(cid:6) where: k=Boltzmann’sconstant=1.380658· 10–23 T=TemperatureindegreesKelvin(273+(cid:176) C) R ||R =ParallelresistanceofR andR F G F G To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the ni overallamplifiergain(A ). V (cid:3) R (cid:4) eno(cid:2)eniAV (cid:2) eni 1(cid:1)RF (noninvertingcase) G As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel G resistance term. This leads to the general conclusion that the most dominant noise sources are the source resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares S n method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly simplifytheformulaandmakenoisecalculationsmucheasiertocalculate. For more information on noise analysis, see the Noise Analysis in Operational Amplifier Circuits application report(SLVA043). This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be definedandistypically50ΩinRFapplications. (cid:5) (cid:7) e 2 NF (cid:1) 10log(cid:4)(cid:4) ni 2(cid:4)(cid:4) (cid:6)(cid:2)eRs(cid:3) (cid:8) 10 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 Because the dominant noise components are generally the source resistance and the internal amplifier noise voltage,wecanapproximatenoisefigureas: (cid:7) (cid:4) 2 2(cid:5)(cid:9) (cid:6)(cid:6) (cid:4)en(cid:5) (cid:2)(cid:4)IN+(cid:1)RS(cid:5) (cid:6)(cid:6) (cid:6) (cid:6) NF (cid:3)10log(cid:6)1(cid:2) 4kTR (cid:6) S (cid:6) (cid:6) (cid:8) (cid:10) Figure32showsthenoisefiguregraphfortheTHS402x. NOISEFIGURE vs SOURCERESISTANCE 16 f = 10 kHz 14 TA = 25°C 12 B d 10 − e r gu 8 Fi e ois 6 N 4 2 0 10 100 1k 10k Source Resistance − W G028 Figure32.NoiseFigurevsSourceResistance Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 Driving a Capacitive Load Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are taken. The first is to realize that the THS402x has been internally compensated to maximize its bandwidth and slew-rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the output decreases the device phase margin, leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of the amplifier, as shown in Figure 33. A minimum value of 20 Ω should work well for most applications. For example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance loadingandprovidestheproperlineimpedancematchingatthesourceend. 1 kW 50W Input _ 20W THS402x Output C + LOAD S0278-01 Figure33.DrivingaCapacitiveLoad Offset Nulling The THS402x has very low input offset voltage for a high-speed amplifier. However, if additional correction is required, an offset nulling function has been provided on the THS4021. The input offset can be adjusted by placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply. This isshowninFigure34. V CC+ 0.1mF + THS402x _ 10 kW 0.1mF V CC– S0279-01 Figure34.OffsetNullingSchematic 12 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 Offset Voltage The output offset voltage (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times OO IO IB the corresponding gains. The schematic and formula of Figure 35 can be used to calculate the output offset voltage. R R G F I IB– – V OS R + S + – IIB+ VIO VOS=(±VIO±IIB+´RS)æççè1+RRGF ö÷÷ø±IIB-´RF S0280-01 Figure35.OutputOffsetVoltageModel General Configurations When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see Figure36). R R G F – V O V + I R1 C1 1 f = -3dB 2pR1C1 V æ R öæ 1 ö VOI =ççè1+RGF ÷÷øçè1+sR1C1÷ø S0281-01 Figure36.Single-PoleLow-PassFilter Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 Circuit Layout Considerations To achieve the levels of high-frequency performance of the THS402x, follow proper printed-circuit board high-frequency design techniques. A general set of guidelines is given as follows. In addition, a THS402x evaluationboardisavailabletouseasaguideforlayoutorforevaluatingthedeviceperformance. • Ground planes—It is highly recommended that a ground plane be used on the board to provide all components with a low-inducance ground connection. However, in the areas of the amplifier inputs and output,thegroundplanecanberemovedtominimizethestraycapacitance. • Proper power-supply decoupling—Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier. Inaddition,the0.1-μFcapacitorshouldbeplacedascloseaspossibletothesupplyterminal.Asthis distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer should strive for distances of less than 0.1 inch (2.54 mm) between the device power terminals and the ceramic capacitors. • Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead inductance in the socket pins often produces stability problems. Surface-mount packages soldered directly to thePCBisthebestimplementation. • Short trace runs/compact part placements—Optimum high-frequency performance is achieved when stray series inductance has been minimized. To realize this, the circuit layout should be made as compact as possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance attheinputoftheamplifier. • Surface-mount passive components—Using surface-mount passive components is recommended for high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept asshortaspossible. 14 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 General Thermal Pad Design Considerations The THS402x is available packaged in a thermally-enhanced DGN package, which is a member of the PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is mounted [see Figure 37(a) and Figure 37(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 37(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from thethermalpad. The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heatcanbeconductedawayfromthepackageintoeitheragroundplaneorotherheatdissipatingdevice. The PowerPAD package represents a design breakthrough, combining the small area and ease of the surface mountassemblymethodtoeliminatethepreviouslydifficultmechanicalmethodsofheatsinking. DIE Thermal Side View (a) Pad DIE End View (b) Bottom View (c) M0031-01 NOTE: Thethermalpadiselectricallyisolatedfromallterminalsinthepackage. Figure37.ViewsofThermallyEnhancedDGNPackage Although there are many ways to heatsink this device properly, the following steps illustrate the recommended approach. Thermal pad area = 68 mils´70 mils (1.73 mm´1.78 mm) with 5 vias. Via diameter = 13 mils (0.33 mm). M0032-02 Figure38.ThermalPadPCBEtchandViaPattern 1. Prepare the PCB with a top side etch pattern as shown in Figure 38. There should be etch for the leads as wellasetchforthethermalpad. 2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0.33 mm) in diameter. Keep themsmallsothatsolderwickingthroughtheholesisnotaproblemduringreflow. 3. Additionalviasmaybe placed anywhere along the thermal plane outside of the thermal pad area. These vias help dissipate the heat generated by the THS402xDGN IC. These additional vias may be larger than the 13-mil (0.33-mm) diameter vias directly under the thermal pad. They can be larger because they are not in thethermalpadareatobesoldered,sowickingisnotaproblem. 4. Connectallholestotheinternalgroundplane. 5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS402xDGN package should connect to the internal ground plane with a complete connectionaroundtheentirecircumferenceoftheplated-throughhole. 6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This preventssolderfrombeingpulledawayfromthethermalpadareaduringthereflowprocess. Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 7. ApplysolderpastetotheexposedthermalpadareaandalloftheICterminals. 8. With these preparatory steps in place, the THS402xDGN IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. The actual thermal performance achieved with the THS402xDGN in its PowerPAD package depends on the application. In the example above, if the size of the internal ground plane is approximately 3 inches · 3 inches (7.62 cm · 7.62 cm), then the expected thermal coefficient, θ , is about 58.4(cid:176) C/W. For comparison, the JA non-PowerPAD version of the THS402x IC (SOIC) is shown. For a given θ , the maximum power dissipation is JA showninFigure39andiscalculatedbythefollowingformula: (cid:2)T –T (cid:3) MAX A PD(cid:1) (cid:1) JA where: P =MaximumpowerdissipationofTHS402xIC(watts) D T =Absolutemaximumjunctiontemperature(150(cid:176) C) MAX T =Free-ambientairtemperature((cid:176) C) A θ =θ +θ JA JC CA θ =Thermalcoefficientfromjunctiontocase JC θ =Thermalcoefficientfromcasetoambientair((cid:176) C/W) CA MAXIMUMPOWERDISSIPATION vs FREE-AIRTEMPERATURE 3.5 Dq JGAN = P5a8c.4k°aCg/eW TJ = 150°C 3.0 2 oz. Trace And Copper Pad With Solder W − DGN Package on 2.5 q JA = 158°C/W ati SOIC Package 2 oz. Trace And ssip 2.0 Hq JiAg h=- K98 T°eCs/Wt PCB CWoitphpoeurt PSaodlder Di r e w 1.5 o P m u m 1.0 xi a M 0.5 SOIC Package Low-K Test PCB q JA = 167°C/W 0.0 −40 −20 0 20 40 60 80 100 TA − Free-Air Temperature − °C G029 NOTE: ResultsarewithnoairflowandPCBsize=3in.· 3in.(7.62cm· 7.62cm). Figure39.MaximumPowerDissipationvsFree-AirTemperature More-complete details of the thermal pad installation process and thermal management techniques can be found inthePowerPADThermallyEnhancedPackageapplicationreport(SLMA002). 16 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent powerandoutputpower. The designer should never forget about the quiescent heat generated within the device, especially with multiamplifier devices. Because these devices have linear output stages (Class A-B), most of the heat dissipation is at low output voltages with high output currents. Figure 40 through Figure 43 show this effect, along with the quiescent heat, with an ambient air temperature of 50(cid:176) C. Obviously, as the ambient temperature increases,thelimitlinesshowndropaccordingly.Theareaundereachrespective limit line is considered the safe operating area. Any condition above this line exceeds the amplifier limits and failure may result. When using V CC =±5V,thereisgenerallynotaheatproblem,evenwith SOIC packages. But, when using V = ±15 V, the SOIC CC package is severely limited in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But the device should always be soldered to a copper plane to use fully the heat dissipation properties of the thermal pad. The SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ decreases and the heat dissipation JA capability increases. The currents and voltages shown in these graphs are for the total package. For the dual-amplifier package (THS4022), the sum of the RMS output currents and voltages should be used to choose theproperpackage.Thegraphsshownassumethatbothamplifieroutputsareidentical. THS4021 THS4021 MAXIMUMRMSOUTPUTCURRENT MAXIMUMRMSOUTPUTCURRENT vs vs RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS 200 1k VCC = ± 5 V Maximum Output TJ = 150°C VCC = ± 15 V A 180 Tj = 150°C Current Limit Line A TA = 50°C m TA = 50°C m nt − 160 nt − CMuarxreimntu Lmim Oiut tLpiunte e e DGN Package Curr 140 Curr q JA = 58.4°C/W ut 120 Package With ut utp q JA < = 120°C/W utp O 100 O 100 S S M M SO-8 Package R 80 R m q JA = 167°C/W m SO-8 Package u u xim 60 Low-K Test PCB xim q JA = 98°C/W a a High-K Test PCB M 40 M − − SO-8 Package |I| O 20 Safe Operating |I| O q JA = 167°C/W Safe Operating Area Low-K Test PCB Area 0 10 0 1 2 3 4 5 0 3 6 9 12 15 |VO| − RMS Output Voltage − V |VO| − RMS Output Voltage − V G030 G031 Figure40. Figure41. Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 THS4022 THS4022 MAXIMUMRMSOUTPUTCURRENT MAXIMUMRMSOUTPUTCURRENT vs vs RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS RMSOUTPUTVOLTAGEDUETOTHERMALLIMITS 200 1k A 180 Pq aJAc k≤a 6g0e° WC/iWth MCuarxriemnut mLi mOuitt Lpiunte A VTJC C= =1 5±0 1°C5 V CMuarxreimntu Lmim Oiut tLpiunte nt − m 160 nt − m TBAo t=h 5 C0h°Cannels e e Curr 140 Curr 100 ut 120 ut p p ut ut O 100 O S SO-8 Package S M M um R 80 LqoJwA- K= 1T6e7s°tC P/WCB um R 10 Sq OJA-8 = P 9a8c°kCa/Wge m 60 m High-K Test PCB xi Safe Operating Area xi a a |I| − MO 2400 HSiqgOJhA--8 K= P T9ae8cs°kCt a/PWgCeB VTTAJC C == = 51 0±5° 0C5° CV |I| − MO qDJAG N= P58a.c4k°aCg/We LSqoJOwA-- 8K= P1T6ae7cs°ktC aP/gWCeB Both Channels Safe Operating Area 0 1 0 1 2 3 4 5 0 3 6 9 12 15 |VO| − RMS Output Voltage − V |VO| − RMS Output Voltage − V G032 G033 Figure42. Figure43. 18 SubmitDocumentationFeedback Copyright©1999–2007,TexasInstrumentsIncorporated ProductFolderLink(s):THS4021THS4022

THS4021 THS4022 www.ti.com SLOS265C–SEPTEMBER1999–REVISEDJULY2007 Evaluation Board Evaluation boards are available for the THS4021 (literature number SLOP129) and THS4022 (literature number SLOP231). These boards have been configured for very low parasitic capacitance in order to realize the full performance of the amplifier. A schematic of the THS4021 evaluation board is shown in Figure 44. The circuitry has been designed so that the amplifier may be used in either an inverting or noninverting configuration. For more information, see the THS4021 High-Speed Operational Amplifier Evaluation Module user’s guide (SLOU063) or the THS4022 Dual High-Speed Operational Amplifier Evaluation Module user’s guide (SLOU064). To order the evaluation board, contact your local TI sales office or distributor or visit the Texas Instruments Web siteatwww.ti.com. V CC+ + C2 C3 6.8mF 0.1mF R4 1 kW NULL IN+ + R5 49.9W R3 THS4021 OUT 49.9W _ NULL R2 C1 49.9W C4 + 6.8mF 0.1mF IN– V CC– S0282-01 Figure44.THS4021EvaluationBoard Copyright©1999–2007,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):THS4021THS4022

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) THS4021CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4021C & no Sb/Br) THS4021CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACK & no Sb/Br) THS4021CDGNG4 ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACK & no Sb/Br) THS4021CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACK & no Sb/Br) THS4021ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4021I & no Sb/Br) THS4021IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACL & no Sb/Br) THS4021IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ACL & no Sb/Br) THS4021IDR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4021I & no Sb/Br) THS4022CD ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 4022C & no Sb/Br) THS4022CDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACA & no Sb/Br) THS4022CDGNG4 ACTIVE HVSSOP DGN 8 80 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACA & no Sb/Br) THS4022CDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ACA & no Sb/Br) THS4022ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 4022I & no Sb/Br) THS4022IDGN ACTIVE HVSSOP DGN 8 80 Green (RoHS Call TI | NIPDAU Level-1-260C-UNLIM -40 to 85 ACB & no Sb/Br) THS4022IDGNR ACTIVE HVSSOP DGN 8 2500 Green (RoHS Call TI | NIPDAU Level-1-260C-UNLIM -40 to 85 ACB & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) THS4021CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4021IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4021IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS4022CDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4022IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-Sep-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) THS4021CDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4021IDGNR HVSSOP DGN 8 2500 358.0 335.0 35.0 THS4021IDR SOIC D 8 2500 350.0 350.0 43.0 THS4022CDGNR HVSSOP DGN 8 2500 350.0 350.0 43.0 THS4022IDGNR HVSSOP DGN 8 2500 350.0 350.0 43.0 PackMaterials-Page2

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE C 5.05 A 4.75 TYP 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1 2X 3.1 1.95 2.9 NOTE 3 4 5 0.38 8X 0.25 B 3.1 0.13 C A B 2.9 NOTE 4 0.23 0.13 SEE DETAIL A EXPOSED THERMAL PAD 4 5 0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX 8 1 0.7 0.15 0 -8 0.05 0.4 DETA 20AIL A 1.57 TYPICAL 1.28 4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187. www.ti.com

EXAMPLE BOARD LAYOUT DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (3) 9 SYMM NOTE 9 (1.89) 6X (0.65) (1.22) 5 4 ( 0.2) TYP VIA (0.55) SEE DETAILS (4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4225481/A 11/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. www.ti.com

EXAMPLE STENCIL DESIGN DGN0008D PowerPAD TM VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE (1.57) BASED ON 0.125 THICK STENCIL SYMM 8X (1.4) (R0.05) TYP 8 8X (0.45) 1 (1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65) 4 5 METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60 4225481/A 11/2019 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design. www.ti.com

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