STGIPS35K60L1 SLLIMM™ (small low-loss intelligent molded module) IPM, single phase - 35 A, 600 V short-circuit rugged IGBT − Datasheet production data Features ■ IPM 35 A, 600 V single phase IGBT including control ICs for gate driving and free-wheeling diodes ) s ( ■ Short-circuit rugged IGBTs t c ■ V negative temperature coefficient u CE(sat) d ■ 3.3 V, 5 V, 15 V CMOS/TTL inputs o comparators with hysteresis and pull down / r P pull up resistors e ■ Undervoltage lockout t e ■ Internal bootstrap diode l o SDIP-22L ■ Dead time and interlocking function s b ■ Smart shutdown function O ■ Comparator for fault protection against over - Description temperature and overcurrent ) s ■ Op amp for advanced current sensin(g This intelligent power module provides a compact, t c high performance AC motor drive for a simple and ■ DBC substrate leading to low thermal u rugged design. It targets power inverters for air resistance d o conditioners. It combines ST proprietary control ■ Isolation rating of 2500 V /min r rms ICs with the most advanced short-circuit rugged P ■ 4.7 kΩ NTC for temperature control IGBT system technology. SLLIMM™ is a e trademark of STMicroelectronics. ■ UL Recognized : UL1557 file E81734 t e l o Applications s b O ■ Power inverters for compressors Table 1. Device summary Order code Marking Package Packaging STGIPS35K60L1 GIPS35K60L1 SDIP-22L Tube August 2012 Doc ID 018864 Rev 3 1/21 This is information on a product in full production. www.st.com 21

Contents STGIPS35K60L1 Contents 1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ). . . 7 s ( 3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c. .t . . . . . . . 9 u 3.1.1 NTC thermistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d. . . . . . . . . . . . . . 12 o 3.1.2 Dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 r P 3.2 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 e t e 4 Smart shutdown function . . . . . . . . . . . l. . . . . . . . . . . . . . . . . . . . . . . . . 15 o s b 5 Package mechanical data . . . . O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 - 6 Revision history . . . . . ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 s ( t c u d o r P e t e l o s b O 2/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Internal schematic diagram and pin configuration 1 Internal schematic diagram and pin configuration Figure 1. Internal schematic diagram E E S S P P A A N N n22: n21: 0: PH 9: PH n18: n17: Pi Pi 2 1 Pi Pi n n Pi Pi ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o P r Vboot HVG OUT LVG CP+ OP+ t e LIN SD/OD HIN VCC DT OP- OPOUT GND e l o s b O T T U Pin1: OUT Pin2: VBOO Pin3: NC Pin4: T1 Pin5: T2 Pin6: /LIN Pin7: /SD Pin8: HIN Pin9: DT Pin10: OP- Pin11: OPO Pin12: OP+ Pin13: VCC Pin14: CIN Pin15: GND Pin16: GND AM09386v2 Doc ID 018864 Rev 3 3/21

Internal schematic diagram and pin configuration STGIPS35K60L1 Table 2. Pin description Pin Symbol Description 1 OUT PHASE reference output PHASE 2 V Bootstrap voltage boot 3 NC Not connected 4 T NTC thermistor terminal 1 1 5 T NTC thermistor terminal 2 2 6 LIN Low side logic input ) 7 SD/OD Shutdown logic input (active low) / open drain (comparator soutput) ( 8 HIN High side logic input t c u 9 DT Dead time setting d o 10 OP- Op amp inverting input r P 11 OP Op amp output OUT e 12 OP+ Op amp non inverting input t e 13 VCC Low voltage power soulpply 14 CIN Comparator inpust b 15 GND Ground O 16 GND Gro-und ) 17 N s Negative DC input ( t 18 Nc Negative DC input u 19 d PHASE Phase output o 20 PHASE Phase output r P 21 P Positive DC input e t 22 P Positive DC input e l o s Figure 2. Pin layout (bottom view) b O Marking area AM06017v1 4/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Electrical ratings 2 Electrical ratings 2.1 Absolute maximum ratings T able 3. Inverter part Symbol Parameter Value Unit V Each IGBT collector emitter voltage (V = 0) 600 V CES IN Each IGBT continuous collector current ± I (1) 35 A C at T = 25°C C ) ± I (2) Each IGBT pulsed collector current 70 s A CP ( PTOT Each IGBT total dissipation at TC = 25°C 100 ct W u Short circuit withstand time, V = 0.5 V t CE (BR)CES 5d µs scw TJ = 125 °C, VCC = Vboot= 15 V, VI= 1 "logic state" o r 1. Calculated according to the iterative formula: P I (T ) = -------------------------------------T---j--(--m----a---x---)---–----T----C-----------e---- ----------------------- C C R ×V (Tt ,I (T )) thj–c CE(sat)(max) e j(max) C C l 2. Pulse width limited by max junction temperature o s b O Table 4. Control part - Symbol )Parameter Min. Max. Unit s ( Output voltagte applied between V c V - 21 V + 0.3 V OUT OUTU, OuUTV, OUTW - GND boot boot d V Low voltage power supply - 0.3 21 V CC o r VCINP Comparator input voltage - 0.3 VCC + 0.3 V eVop+ OPAMP non-inverting input - 0.3 VCC + 0.3 V t e V OPAMP inverting input - 0.3 V + 0.3 V op- CC l o V Bootstrap voltage - 0.3 620 V s boot b Logic input voltage applied between HIN, LIN and O V - 0.3 15 V IN GND VSD/OD Open drain voltage - 0.3 15 V dV /dt Allowed output slew rate 50 V/ns OUT T able 5. Total system Symbol Parameter Value Unit Isolation withstand voltage applied between each V 2500 V ISO pin and heatsink plate (AC voltage, t = 60 sec.) T Power chips operating junction temperature -40 to 150 °C J T Module case operation temperature -40 to 125 °C C Doc ID 018864 Rev 3 5/21

Electrical ratings STGIPS35K60L1 2.2 Thermal data T able 6. Thermal data Symbol Parameter Value Unit Thermal resistance junction-case single IGBT 1.25 °C/W R thJC Thermal resistance junction-case single diode 2.5 °C/W Figure 3. Transient thermal impedance IGBT/diode - inverter 10 AM09385v1) s ( t c u d o 1 r P W] e [K/ Diode e t hj-c ol Zt IGBT s 0.1 b O - ) s ( t 0.01 c 1.E-04 u1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 1.E+02 d o time [s] r P e t e l o s b O 6/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Electrical characteristics 3 Electrical characteristics T = 25 °C unless otherwise specified. J Table 7. Inverter part Value Symbol Parameter Test conditions Unit Min. Typ. Max. V = V = 15 V, V = 1 "logic CC boot IN - 2.1 2.7 Collector-emitter state", IC = 30 A ) VCE(sat) saturation voltage VstCaCte =", VICb o=o t3 =0 1A5, TV,J V=I N1 2=5 1 ° C"logic - 1.9 ct( s V u Collector-cut off current I V = 550 V, V = V = 15 V - d 500 µA CES (VIN(1)= 0 “logic state”) CE CC Boot o r VF Diode forward voltage VIN = 0 "logic state", IF = 30A - P 2.5 V Switching on/off (inductive load) (1) e t e t Turn-on time l - 440 - on o t Crossover time (on) s - 87 - c(on) b toff Turn-off time VDD = 410 V, O - 280 - ns t Crossover time (off) VCC = Vboot =- 1 5 V, - 130 - c(off) V = 1 "log ic state" (see Table13) IN ) trr Reverse recovery time IC = 3(0 sA (see Figure4 and 5) - 60 - t Eon Turn-on switching losses c - 680 - u µJ Eoff Turn-off switching losdses - 760 - o V = 410 V, V = V = 15 V, r DD CC boot Rate of rise Pof on-state di/dt V = 1 "logic state" (see Table13), - 2000 - A/µs (on) current IN e I = 70 A (see Figure4 and 5) C t t Teurn-on time - 550 - on l o t Crossover time (on) - 110 - cs(on) V = 410 V, b DD t Turn-off time - 410 - ns O off V = V = 15 V, CC boot tc(off) Crossover time (off) VIN = 1 "logic state" (see Table13) - 200 - trr Reverse recovery time IC = 30 A, TJ = 125 °C - 85 - (see Figure4 and 5) E Turn-on switching losses - 1025 - on µJ E Turn-off switching losses - 1400 - off V = 410 V, DD V = V = 15 V, CC boot Rate of rise of on-state di/dt V = 1 "logic state" (see Table13) - 1750 - A/µs (on) current IN I = 70 A, T = 125 °C C J (see Figure4 and 5) 1. t and t include the propagation delay time of the internal drive. t and t are the switching time of IGBT itself ON OFF C(ON) C(OFF) under the internally given gate driving condition. Parameter values take into account a 20 nH stray inductance. Doc ID 018864 Rev 3 7/21

Electrical characteristics STGIPS35K60L1 Figure 4. Switching time test circuit ) s ( t c u d o r P e t e l o Figure 5. Switching time definition (1) s b O 100% IC 100% IC t - rr ) s ( t c VCuE IC IC VCE d o r P e t e l o s b O VIN VIN t t ON OFF t t C(ON) C(OFF) VIN(ON) 10% IC 90% IC 10% VCE VIN(OFF) 10% VCE 10% IC (a) turn-on (b) turn-off AM09223V1 1. “Switching time definition" refers to HIN inputs (active high). For LIN inputs (active low), V polarity must IN be inverted for turn-on and turn-off. 8/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Electrical characteristics 3.1 Control part Table 8. L ow voltage power supply (V = 15 V unless otherwise specified) CC Symbol Parameter Test conditions Min. Typ. Max. Unit V V UV hysteresis 1.2 1.5 1.8 V CC_hys CC V V UV turn ON threshold 11.5 12 12.5 V CC_thON CC V V UV turn OFF threshold 10 10.5 11 V CC_thOFF CC V = 10 V Undervoltage quiescent CC Iqccu supply current SD/OD = 5 V; LIN = 5 V; 200 µA HIN = 0, CIN = 0 ) s VCC = 15 V ( t Iqcc Quiescent current SD/OD = 5 V; LIN = 5 V c 1 mA u HIN = 0, CIN = 0 d V Internal reference voltage 0.5 o 0.54 0.58 V ref r P e t Table 9. Bootstrapped voltage (V = 15 V unless otherwisee specified) CC l o Symbol Parameter Test conditions Min. Typ. Max. Unit s b VBS_hys VBS UV hysteresis O 1.2 1.5 1.8 V VBS_thON VBS UV turn ON threshold - 10.6 11.5 12.4 V VBS_thOFF VBS UV turn OFF threshold s ) 9.1 10 10.9 V ( IQBSU Ucunrdreenrvtoltage VBS quiuesccetnt VSBDS/O <D 9 =V 5 V; LIN and 70 110 µA d HIN = 5 V; CIN = 0 o V = 15 V r BS IQBS VBS quiesPcent current SD/OD = 5 V; LIN and 150 210 µA e HIN = 5 V; CIN = 0 t R e Bootstrap driver on resistance LVG ON 120 Ω DS(on) l o s b Table 10. Logic inputs (V = 15 V unless otherwise specified) O CC Symbol Parameter Test conditions Min. Typ. Max. Unit Vil Low logic level voltage 0.8 V V High logic level voltage 2.25 V ih I HIN logic “1” input bias current HIN = 15 V 110 175 260 µA HINh I HIN logic “0” input bias current HIN = 0 V 1 µA HINl I LIN logic “1” input bias current LIN = 0 V 3 6 20 µA LINl I LIN logic “0” input bias current LIN = 15 V 1 µA LINh I SD logic “0” input bias current SD = 15 V 10 40 100 µA SDh I SD logic “1” input bias current SD = 0 V 1 µA SDl Doc ID 018864 Rev 3 9/21

Electrical characteristics STGIPS35K60L1 Table 11. Op amp characteristics (V = 15 V unless otherwise specified) CC Symbol Parameter Test condition Min. Typ. Max. Unit V Input offset voltage V = 0 V, V = 7.5 V 6 mV io ic o I Input offset current 4 40 nA io V = 0 V, V = 7.5 V I Input bias current (1) ic o 100 200 nA ib Input common mode voltage V 0 V icm range V Low level output voltage R = 10 kΩ to V 75 150 mV OL L CC V High level output voltage R = 10 kΩ to GND 14 14.7 )V OH L s ( Source, Vid = +1; Vo = 0 V 16 30 t mA I Output short circuit current c o Sink, V = -1; V = V 50 80 u mA id o CC d SR Slew rate Vi = 1 - 4 V; CL = 100 pF; 2.5 o3.8 V/µs unity gain r P GBWP Gain bandwidth product V = 7.5 V 8 12 MHz o e Avd Large signal voltage gain RL = 2 kΩ e t 70 85 dB l SVR Supply voltage rejection ratio vs. V o 60 75 dB CC s CMRR Common mode rejection ratio b 55 70 dB O 1. The direction of input current is out of the IC. - ) s Table 12. Sense comparator characteristics (V = 15 V unless otherwise specified) ( CC t c Symbol Parameter Test conditions Min. Typ. Max. Unit u d I Input bias current V = 1 V - 1 µA ib o CP+ Open-drainr low-level output V P I = 3 mA - 0.5 V ol voltage od e t SD/OD pulled to 5 V through td_comp e Comparator delay 100 kΩ resistor - 90 130 ns l o sSR Slew rate CL = 180 pF; Rpu = 5 kΩ - 60 V/µsec b O t Shutdown to high / low side VOUT = 0, Vboot = VCC, 50 125 200 sd driver propagation delay VIN = 0 to 3.3 V Comparator triggering to high / Measured applying a voltage ns tisd low side driver turn-off step from 0 V to 3.3 V to pin 50 200 250 propagation delay CINi 10/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Electrical characteristics Table 13. Truth table Logic input (V) Output I Condition SD/OD LIN HIN LVG HVG Shutdown enable L X X L L half-bridge tri-state Interlocking H L H L L half-bridge tri-state 0 ‘’logic state” H H L L L half-bridge tri-state ) s 1 “logic state” ( H L L H ct L low side direct driving u 1 “logic state” d H H H Lo H high side direct driving r P e Note: X: don’t care t e l o s b O - ) s ( t c u d o r P e t e l o s b O Doc ID 018864 Rev 3 11/21

Electrical characteristics STGIPS35K60L1 3.1.1 NTC thermistor Table 14. NTC thermistor Symbol Parameter Test conditions Min. Typ. Max. Unit. R25 Resistance TC = 25°C 4.7 kΩ R125 Resistance TC = 125°C 160 Ω B B-constant T = 25°C 3950 K C T Operating temperature -40 150 °C ) Equation 1: resistance variation vs. temperature s ( t c B⎛-1--–----1------⎞ u R(T) = R ⋅e ⎝T 298⎠ d 25 o r P Where T are temperatures in Kelvins e t e l Figure 6. NTC resistance vs. temperature o s b RR ((kkΩΩ)) O AAMM0077884433vv11 - ) 110000 s ( t c u d 1100 o r P e 11 t e l o s b 00..11 O 00..0011 --5500 00 5500 110000 TT ((°°CC)) 12/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Electrical characteristics 3.1.2 Dead time Figure 7. Dead time and interlocking waveforms definitions LIN COINOVTENERTRRLLAOOPLCP KSEIIDGN:GN A +L D EEDAGDE TSIME LHVING IINNTTEERRLLOOCCKKIINNGG IINNTTEERRLLOOCCKKIINNGGG DTLH DTHL HVG gate driver outputs OFF gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE) LIN ) s CONTROL SIGNALS EDGES HIN ( SYNCHRONOUS (*): t c DEAD TIME LVG u DTLH d DTHL HVG o gate driver outputs OFF gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (HALF-BRIDGE rTRI-STATE) P e LIN t e CONTROL SIGNALS EDGES HIN NOT OVERLAPPED, ol BUT INSIDE THE DEAD TIME: DEAD TIME LVG s bDTLH DTHL HVG O gate driver outputs OFF gate driver outputs OFF (HALF-BRIDG-E TRI-STATE) (HALF-BRIDGE TRI-STATE) ) s LIN ( CONTROL SIGNALS EDGES t NOT OVERLAPPED, c HIN OUTSIDE THE DEAD TIMEu: DIRECT DRIVING d LVG o DTLH DTHL HVG r P gate driver outputs OFF gate driver outputs OFF (HALF-BRIDGE TRI-STATE) (HALF-BRIDGE TRI-STATE) e t (*) HIN and LIN can be connected together and driven by just one control signal e l o Figure 8. Typical dead time vs. DT resistor value s b 3.5 O 3 2.5 2 DT (µs)1.5 1 0.5 0 0 50 100 150 200 250 300 Rdt (kOhm) AM06020v1 Doc ID 018864 Rev 3 13/21

Electrical characteristics STGIPS35K60L1 3.2 Recommendations ● Input signal HIN is active high logic. A 85 kΩ (typ.) pull down resistor is built-in for each high side input. If an external RC filter is used, for noise immunity, pay attention to the variation of the input signal level. ● Input signal LIN is active low logic. A 720 kΩ (typ.) pull-up resistor, connected to an internal 5 V regulator through a diode, is built-in for each low side input. ● To prevent the input signals oscillation, the wiring of each input should be as short as possible. ● By integrating an application specific type HVIC inside the module, direct coupling to MCU terminals without any opto-coupler is possible. ● Each capacitor should be located as nearby the pins of IPM as possible. ) s ● Low inductance shunt resistors should be used for phase leg current sensin(g. t c ● Electrolytic bus capacitors should be mounted as close to the module bus terminals as u possible. Additional high frequency ceramic capacitor mounted closde to the module pins will further improve performance. o r ● The SD/OD signal should be pulled up to 5 V / 3.3 V with aPn external resistor (see Section4: Smart shutdown function for detailed info). e ● When setting the maximum voltage to be applied btetween P-N, the internal stray e inductance and the maximum di/dt should be lconsidered. Due to both internal and o layout stray inductances, the di/dt results sin a voltage surges between the DC-link capacitor and the switches during combmutations. O ● Suggested control supply voltage (V ): from 13.5 V to 18 V CC ● Suggested high side bias vo lt-age (VBS between VBOOT and PHASE): from 13 V to 18 V ) s ( Table 15. Recommentded operating conditions c u Value d Symbol Parameter Conditions Unit o r Min. Typ. Max. P VeP N Supply voltage Applied between P-Nu, Nv, Nw 300 400 V e tVCC Control supply voltage Applied between VCC-GND 13.5 15 18 V l o Applied between V -OUT for V High side bias voltage BOOTi i 13 18 V s BS i = U, V, W b O Blanking time to t For each input signal 1 µs dead prevent Arm-short -40°C < T < 100°C fPWM PWM input signal -40°C < Tc < 125°C 20 kHz j Case operation T 100 °C C temperature For further details refer to AN3338. 14/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Smart shutdown function 4 Smart shutdown function The STGIPS35K60L1 integrates a comparator for fault sensing purposes. The comparator non-inverting input (C ) can be connected to an external shunt resistor in order to IN implement a simple overcurrent protection function. When the comparator triggers, the device is set in shutdown state and both its outputs are set to low-level leading the half- bridge in tri-state. In the common overcurrent protection architectures the comparator output is usually connected to the shutdown input through a RC network, in order to provide a mono-stable circuit, which implements a protection time that follows the fault condition. Our smart shutdown architecture allows to immediately turn-off the output gate driver in case of overcurrent, the fault signal has a preferential path which directly switches off the ) outputs. The time delay between the fault and the outputs turn-off is no more depensdent on the RC values of the external network connected to the shutdown pin. At the sam(e time the t internal logic turns on the open-drain output and holds it on until the shutdownc voltage goes u below the logic input lower threshold. Finally the smart shutdown function provides the d possibility to increase the real disable time without increasing the conostant time of the external RC network. r P e Figure 9. Smart shutdown timing waveforms t comp e Vref ol s b CP+O - PROTECTION ) s ( t HIN/LIN c u d HVG/LVG o r P SD/OD e upper t threshold e lower l threshold o 1 s 2 b open drain gate O (internal) real disable time Fast shut down: the driver outputs are set in SD state TIME CONSTANTS imtrmigegdeiraintegly e avfetenr i ft hthee c SomD psaigrantaolr 1= (RON_OD// RSD) CSD has not yet reach 2= RSD CSD the lower input threshold SHUT DOWN CIRCUIT VBIAS R SD FROM/TO SD/OD CONTROLLER SMART CSD RON_OD LOSGDIC Pls refer to Table12 for internal propagation delay time details. Doc ID 018864 Rev 3 15/21

Package mechanical data STGIPS35K60L1 5 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Please refer to dedicated technical note TN0107 for mounting instructions. Table 16. SDIP-22L package mechanical data mm. ) Dim. s Min. Typ. Ma(x. t c A 43.90 44.40 u 44.90 d A1 1.15 1.35 o 1.55 r A2 1.40 1.60 P 1.80 A3 38.90 39e.40 39.90 t e B 21.50 22.00 22.50 l o B1 11.25 s 11.85 12.45 b B2 24.83O 25.23 25.63 C 5. 00 5.40 6.00 - ) C1 s 6.50 7.00 7.50 ( C2 t 11.20 11.70 12.20 c u e 2.15 2.35 2.55 d e1o 3.40 3.60 3.80 r P e2 4.50 4.70 4.90 e e3 15.70 15.90 16.10 t e l e4 6.30 6.50 6.70 o s e5 9.20 9.40 9.60 b O D 33.20 D1 5.60 E 10.20 E1 0.40 F 0.85 1.00 1.15 F1 0.35 0.50 0.65 R 1.55 1.75 1.95 T 0.45 0.55 0.65 V 0° 6° 16/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Package mechanical data Figure 10. SDIP-22L package drawing (dimensions are in mm.) ) s ( t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e 8229874_D l o s b O Doc ID 018864 Rev 3 17/21

Package mechanical data STGIPS35K60L1 Figure 11. SDIP-22L shipping tube (dimensions are in mm.) M10488v1 A ) s ( t c u d o r P e t e l o s b O E _ 7 2 - 1 23 ) 1 s 8 ( t c u d o r P e t e l o s b O ase quantity: 11 pcsulk quantity: 132 pcs BB 18/21 Doc ID 018864 Rev 3

STGIPS35K60L1 Package mechanical data Figure 12. SDIP-22L shipping tube type B (dimensions are in mm.) M10487v1 A C V P 3 0 S C ) TI s A ( T t S c TI u N A d o r P e t e l o s b O - ) s ( t c u d o E _ r 27 P 1 3 2 1 e 8 t e l o s b O ase quantity: 11 pcsulk quantity: 132 pcs BB Doc ID 018864 Rev 3 19/21

Revision history STGIPS35K60L1 6 Revision history T able 17. Document revision history Date Revision Changes 15-Jun-2011 1 Initial release. Added: Figure11 on page18. 24-Jan-2012 2 Updated: Figure10 on page17. Document status promoted from preliminary data to production data. Added: feature Comparator for fault protection against over 28-Aug-2012 3 ) temperature and overcurrent on page1. s ( Modified: Min. and Max. value Table4 on page5. t c u d o r P e t e l o s b O - ) s ( t c u d o r P e t e l o s b O 20/21 Doc ID 018864 Rev 3

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