Product Order Technical Tools & Support & Folder Now Documents Software Community SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 SN74CBTLV3383 Low-Voltage 10-Bit FET Bus-Exchange Switch 1 Features 3 Description • 5-Ω SwitchConnectionBetweenTwoPorts TheSN74CBTLV3383providestenbitsofhigh-speed 1 bus switching or exchanging. The low on-state • Rail-to-RailSwitchingonDataI/OPorts resistance of the switch allows connections to be • IoffSupportsPartial-Power-DownModeOperation madewithminimalpropagationdelay. • Latch-UpPerformanceExceeds250mAPer The device operates as a 10-bit bus switch or as a 5- JESD17 bit bus exchanger, which provides swapping of the A • ESDProtectionExceedsJESD22 and B pairs of signals. The bus-exchange function is selectedwhenBXishigh,andBEislow. – 2000-VHuman-BodyModel(A114-A – 200-VMachineModel(A115-A) This device is fully specified for partial-power-down applications using I . The I feature ensures that off off 2 Applications damagingcurrentwillnotbackflowthroughthedevice when it is powered down. The device has isolation • Gaming duringpoweroff. • RackServer DeviceInformation(1) • CommunicationBoard PARTNUMBER PACKAGE BODYSIZE(NOM) QSOP−DBQ 8.65mmx3.90mm SOIC−DW 15.4mmx7.50mm SN74CBTLV3383 TSSOP−PW 7.80mmx4.40mm TVSOP−DGV 5.00mmx4.40mm (1) For all available packages, see the orderable addendum at theendofthedatasheet. spacer spacer spacer SimplifiedSchematic,EachFETSwitch 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 www.ti.com Table of Contents 1 Features.................................................................. 1 8.4 DeviceFunctionalModes..........................................8 2 Applications........................................................... 1 9 ApplicationandImplementation.......................... 9 3 Description............................................................. 1 9.1 ApplicationInformation..............................................9 4 RevisionHistory..................................................... 2 9.2 TypicalApplication ...................................................9 5 PinConfigurationandFunctions......................... 3 10 PowerSupplyRecommendations..................... 10 6 Specifications......................................................... 4 11 Layout................................................................... 11 6.1 AbsoluteMaximumRatings......................................4 11.1 LayoutGuidelines.................................................11 6.2 ESDRatings..............................................................4 11.2 LayoutExample....................................................11 6.3 RecommendedOperatingConditions.......................4 12 DeviceandDocumentationSupport................. 12 6.4 ThermalInformation..................................................4 12.1 DocumentationSupport........................................12 6.5 ElectricalCharacteristics...........................................5 12.2 ReceivingNotificationofDocumentationUpdates12 6.6 SwitchingCharacteristics..........................................5 12.3 CommunityResources..........................................12 7 ParameterMeasurementInformation..................6 12.4 Trademarks...........................................................12 12.5 ElectrostaticDischargeCaution............................12 8 DetailedDescription.............................................. 7 12.6 Glossary................................................................12 8.1 Overview...................................................................7 13 Mechanical,Packaging,andOrderable 8.2 FunctionalBlockDiagram.........................................7 Information........................................................... 12 8.3 FeatureDescription...................................................7 4 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionG(October2003)toRevisionH Page • AddedDeviceInformationtable,ESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes, ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanical,Packaging,andOrderableInformationsection. .................................... 1 2 SubmitDocumentationFeedback Copyright©1998–2018,TexasInstrumentsIncorporated ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 www.ti.com SCDS047H–MARCH1998–REVISEDDECEMBER2018 5 Pin Configuration and Functions DBQ,DGV,DW,ORPWPackage 24-Pin TopView BE 1 24 VCC 1B1 2 23 5B2 1A1 3 22 5A2 1A2 4 21 5A1 1B2 5 20 5B1 2B1 6 19 4B2 2A1 7 18 4A2 2A2 8 17 4A1 2B2 9 16 4B1 3B1 10 15 3B2 3A1 11 14 3A2 GND 12 13 BX Not to scale PinFunctions PIN I/O DESCRIPTION NAME NO. Activelowenable:Whenthispinishigh,allswitchesareturnedoff.Whenthispinislow,BXpincontrols BE 1 I thesignalpathselection. 1B1 2 I/O Signalpath.Canbeaninputoroutput 1A1 3 I/O Signalpath.Canbeaninputoroutput 1A2 4 I/O Signalpath.Canbeaninputoroutput 1B2 5 I/O Signalpath.Canbeaninputoroutput 2B1 6 I/O Signalpath.Canbeaninputoroutput 2A1 7 I/O Signalpath.Canbeaninputoroutput 2A2 8 I/O Signalpath.Canbeaninputoroutput 2B2 9 I/O Signalpath.Canbeaninputoroutput 3B1 10 I/O Signalpath.Canbeaninputoroutput 3A1 11 I/O Signalpath.Canbeaninputoroutput GND 12 P Ground(0V)reference BX 13 I Controlsstateofswitches 3A2 14 I/O Signalpath.Canbeaninputoroutput 3B2 15 I/O Signalpath.Canbeaninputoroutput 4B1 16 I/O Signalpath.Canbeaninputoroutput 4A1 17 I/O Signalpath.Canbeaninputoroutput 4A2 18 I/O Signalpath.Canbeaninputoroutput 4B2 19 I/O Signalpath.Canbeaninputoroutput 5B1 20 I/O Signalpath.Canbeaninputoroutput 5A1 21 I/O Signalpath.Canbeaninputoroutput 5A2 22 I/O Signalpath.Canbeaninputoroutput 5B2 23 I/O Signalpath.Canbeaninputoroutput VCC 24 P Positivepowersupply. Copyright©1998–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT V Supplyvoltagerange –0.5 4.6 V CC V Inputvoltagerange –0.5 4.6 V I Continuouschannelcurrent. 128 mA I Inputclampcurrent,V <0 –50 mA IK I/O T Storagetemperature –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V(ESD) Electrostaticdischarge Charged-devicemodel(CDM),perJEDECspecificationJESD22- V C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT V Supplyvoltage 2.3 3.6 V CC V =2.3Vto2.7V 1.7 V CC V High-levelcontrolinputvoltage IH V =2.7Vto3.6V 2 V CC V =2.3Vto2.7V 0.7 V CC V Low-levelcontrolinputvoltage IL V =2.7Vto3.6V 0.8 V CC T Operatingfree-airtemperature –40 85 °C A (1) AllunusedcontrolinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs. 6.4 Thermal Information SN74CBTLV3383 THERMALMETRIC(1) DBQ DVG DW PW UNIT (QSOP) (TVSOP) (SPIC) (TSSOP) 24PINS 24PINS 24PINS 24PINS R Junction-to-ambientthermalresistance 86.6 105.6 66.6 90.1 °C/W θJA R Junction-to-case(top)thermalresistance 40.5 36.9 36.7 34.12 °C/W θJC(top) R Junction-to-boardthermalresistance 40.8 51.1 36.6 45.2 °C/W θJB ψ Junction-to-topcharacterizationparameter 7.8 2.6 13.1 2.8 °C/W JT ψ Junction-to-boardcharacterizationparameter 40.4 50.6 36.4 44.8 °C/W JB R Junction-to-case(bottom)thermalresistance n/a n/a n/a n/a °C/W θJC(bot) (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 4 SubmitDocumentationFeedback Copyright©1998–2018,TexasInstrumentsIncorporated ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 www.ti.com SCDS047H–MARCH1998–REVISEDDECEMBER2018 6.5 Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP(1) MAX UNIT V Clampcurrent V =3V I =–18mA –1.2 V IK CC I I Inputcurrent V =3.6V V =V orGND –1 1 µA I CC I CC Partialpowerdownmode I V =0V V orV =0to3.6V 10 µA off operation CC I IO I Supplycurrent V =3.6 I =0,V =V orGND 10 µA CC CC O I CC ΔI (2) Supplycurrent-Controlinputs V =3.6V Oneinputat Otherinputsat 300 µA CC CC 3V VCCorGND InputCapacitance-Control C V =3Vor0 3.5 pF I inputs I C Inputtooutputcapacitance V =3Vor0 BE=V 13.5 pF IO(OFF) O CC I =64mA 5 8 Ω VCC=2.3V VI=0 I TYPatVCC= I =24mA 5 8 Ω I 2.5V V =1.7V I =15mA 27 40 Ω r (3) On-stateresistance I I (on) I =64mA 5 7 Ω I V =0 I V =3V I =24mA 5 7 Ω CC I V =2.4V I =15mA 10 15 Ω I I (1) AlltypicalvaluesareatV =3.3V(unlessotherwisenoted),T =25°C CC A (2) Thisistheincreaseinsupplycurrentforeachinputthatisatthespecifiedvoltagelevel,ratherthanV orGND. CC (3) MeasuredbythevoltagedropbetweentheAandBterminalsattheindicatedcurrentthroughtheswitch.On-stateresistanceis determinedbythelowerofthevoltagesofthetwo(AorB)terminals. 6.6 Switching Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) TESTCONDITIONS V =2.5V±0.2V V =3.3V±0.3V CC CC PARAMETER UNIT FROM(INPUT) TO(OUTPUT) MIN MAX MIN MAX t (1) Propagationdelaytime AorB BoorA 0.15 0.25 ns pd t Propagationdelaytime BX AorB 1.5 5.8 1.5 4.7 ns pd t Enabletime BE AorB 1.5 5.3 1.5 4.7 ns en t Disabletime BE AorB 1 6 1 6 ns dis (1) ThepropagationdelayisthecalculatedRCtimeconstantofthetypicalon-stateresistanceoftheswitchandthespecifiedload capacitance,whendrivenbyanidealvoltagesource(zerooutputimpedance). Copyright©1998–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 www.ti.com 7 Parameter Measurement Information Figure1. LoadCurrent Figure2. VoltageWaveformsPulseDuration Figure3. VoltageWaveformsSetupandHold xx Times Figure4. VoltageWaveformsPropagationDelay Figure5. VoltageWaveformsEnableAndDisable TimesInvertingandNoninvertingOutputs TimesLow-andHigh-LevelEnabling Notes: A. C includesprobeandjigcapacitance. L B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabledbytheoutputcontrol C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t O r ≤2ns,t ≤ 2ns. f D. Theoutputsaremeasuredoneatatimewithonetransitionpermeasurement. E. t andt arethesameast . PLZ PHZ dis F. t andt arethesameast . PZL PZH en G. t andt arethesameast . PLH PHL pd H. H.Allparametersandwaveformsarenotapplicabletoalldevices. 6 SubmitDocumentationFeedback Copyright©1998–2018,TexasInstrumentsIncorporated ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 www.ti.com SCDS047H–MARCH1998–REVISEDDECEMBER2018 8 Detailed Description 8.1 Overview The SN74CBTLV3383 device is a 10-bit high-speed bus exchange FET switch. The low ONstate resistance of theswitchallowsconnectionstobemadewithminimalpropagationdelay.Theselect(BX)inputcontrolsthedata flow. The FET multiplexers and demultiplexers are disabled when the output-enable (BE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor;theminimumvalueoftheresistorisdeterminedbythecurrent-sinkingcapabilityofthedriver. 8.2 Functional Block Diagram 8.3 Feature Description BidirectionalOperation The SN74CBTLV3383 conducts equally well from source (xA1, xA2) to drain (xB1,xB2). Each channel has very similarcharacteristicsinbothdirectionsandsupportsbothanaloganddigitalsignals. Rail-to-railswitching TheSN74CBTLV3383willsupportsignalsontheI/Opathacrossthefullsupplyrange0toV CC Copyright©1998–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 www.ti.com 8.4 Device Functional Modes ShowsthefunctionalmodesoftheSN74CBTLV3383. Table1.FunctionTable INPUTS INPUTS–OUTPUTS BE BX 1A1–5A1 1A2-5A2 L L 1B1–5B1 1B2–5B2 L H 1B2–5B2 1B1–5B1 H X Z Z 8 SubmitDocumentationFeedback Copyright©1998–2018,TexasInstrumentsIncorporated ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 www.ti.com SCDS047H–MARCH1998–REVISEDDECEMBER2018 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 9.1 Application Information The SN74CBTLV3383 device operates as a 10-bit bus switch or as a 5-bit bus exchanger, which provides swappingoftheAandBpairsofsignals.Thebus-exchangefunctionisselectedwhenBXishigh,andBEislow. The application shown here is a 5-bit bus being multiplexed between two devices. The BE and BX pins are used tocontrolthechipfromthebuscontroller.Thisisagenericexample,andcouldapplytomanysituations. 9.2 Typical Application Figure6. SimpleSchematic 9.2.1 DesignRequirements 1. RecommendedInputConditions: – Forspecifiedhighandlowlevels,seeV andV inRecommendedOperatingConditions. IH IL – Inputsandoutputsareovervoltagetolerantslowingthemtogoashighas4.6VatanyvalidVCC. 2. RecommendedOutputConditions: – Loadcurrentsshouldnotexceed ±128mAperchannel. 3. FrequencySelectionCriterion: – Maximumfrequencytestedis200MHz. 9.2.2 DetailedDesignProcedure The SN74CBTLV3383 can be operated without any external components. All inputs signals passing through the switch must fall within the recommend operating conditions of the SN74CBTLV3383 including signal range and continuous current. For this design example, with a supply of 3.3 V, the signals can range from 0 V to 3.3 V whenthedeviceispowered.Themaxcontinuouscurrentcanbe128mA. Copyright©1998–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 www.ti.com 10 Power Supply Recommendations TheSN74CBTLV3383operatesacrossawidesupplyrangeof2.3Vto3.6V.Donotexceedtheabsolute maximumratingsbecausestressesbeyondthelistedratingscancausepermanentdamagetothedevices. Power-supplybypassingimprovesnoisemarginandpreventsswitchingnoisepropagationfromtheVDDsupply toothercomponents.Goodpower-supplydecouplingisimportanttoachieveoptimumperformance.For improvedsupplynoiseimmunity,useasupplydecouplingcapacitorrangingfrom0.1μFto10μFfromVDDto ground.Placethebypasscapacitorsasclosetothepowersupplypinsofthedeviceaspossibleusinglow- impedanceconnections.TIrecommendsusingmulti-layerceramicchipcapacitors(MLCCs)thatofferlow equivalentseriesresistance(ESR)andinductance(ESL)characteristicsforpower-supplydecouplingpurposes. Forverysensitivesystems,orforsystemsinharshnoiseenvironments,avoidingtheuseofviasforconnecting thecapacitorstothedevicepinsmayoffersuperiornoiseimmunity.Theuseofmultipleviasinparallellowers theoverallinductanceandisbeneficialforconnectionstogroundplanes. 10 SubmitDocumentationFeedback Copyright©1998–2018,TexasInstrumentsIncorporated ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 www.ti.com SCDS047H–MARCH1998–REVISEDDECEMBER2018 11 Layout 11.1 Layout Guidelines Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore some traces must turn corners. Figure 4 shows progressively better techniques of rounding corners.Onlythelastexample(BEST)maintainsconstanttracewidthandminimizesreflections. 11.2 Layout Example WORST BETTER BEST W 2 1W min. W Figure7. ExampleLayout Copyright©1998–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:SN74CBTLV3383

SN74CBTLV3383 SCDS047H–MARCH1998–REVISEDDECEMBER2018 www.ti.com 12 Device and Documentation Support 12.1 Documentation Support 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 12.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 12.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 12.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 12 SubmitDocumentationFeedback Copyright©1998–2018,TexasInstrumentsIncorporated ProductFolderLinks:SN74CBTLV3383

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74CBTLV3383DBQR ACTIVE SSOP DBQ 24 2500 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 85 CBTLV3383 & no Sb/Br) SN74CBTLV3383DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CL383 & no Sb/Br) SN74CBTLV3383DW ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3383 & no Sb/Br) SN74CBTLV3383DWE4 ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3383 & no Sb/Br) SN74CBTLV3383DWR ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3383 & no Sb/Br) SN74CBTLV3383PW ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CL383 & no Sb/Br) SN74CBTLV3383PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CL383 & no Sb/Br) SN74CBTLV3383PWR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 CL383 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74CBTLV3383DBQR SSOP DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBTLV3383DGVR TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74CBTLV3383DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74CBTLV3383PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74CBTLV3383DBQR SSOP DBQ 24 2500 367.0 367.0 38.0 SN74CBTLV3383DGVR TVSOP DGV 24 2000 367.0 367.0 35.0 SN74CBTLV3383DWR SOIC DW 24 2000 350.0 350.0 43.0 SN74CBTLV3383PWR TSSOP PW 24 2000 367.0 367.0 38.0 PackMaterials-Page2

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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