SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 • 3-State Buffer-Type Noninverting Outputs SN54ALS574B, SN54AS574...J OR W PACKAGE Drive Bus Lines Directly SN74ALS574B, SN74AS574...DW OR N PACKAGE • (TOP VIEW) Bus-Structured Pinout • Buffered Control Inputs OE 1 20 VCC • 1D 2 19 1Q SN74ALS575A and ′AS575 Have 2D 3 18 2Q Synchronous Clear 3D 4 17 3Q • 4D 5 16 4Q Package Options Include Plastic 5D 6 15 5Q Small-Outline (DW) Packages, Ceramic 6D 7 14 6Q Chip Carriers (FK), Standard Plastic (N, NT) 7D 8 13 7Q 8D 9 12 8Q and Ceramic (J, JT) 300-mil DIPs, and GND 10 11 CLK Ceramic Flat (W) Packages SN54ALS574B, SN54AS574...FK PACKAGE description (TOP VIEW) C These octal D-type edge-triggered flip-flops DDECQ 21OV1 feature 3-state outputs designed specifically for 3 2 1 2019 bus driving. They are particularly suitable for 3D 4 18 2Q implementing buffer registers, I/O ports, 4D 5 17 3Q 5D 6 16 4Q bidirectional bus drivers, and working registers. 6D 7 15 5Q The eight flip-flops enter data on the low-to-high 7D 8 14 6Q 910111213 transition of the clock (CLK) input. The DDKQQ SN74ALS575A, SN54AS575, and SN74AS575 8NL87 GC may be synchronously cleared by taking the clear SN54AS575...JT OR W PACKAGE (CLR) input low. SN74ALS575A, SN74AS575...DW OR NT PACKAGE (TOP VIEW) The output-enable (OE) input does not affect internal operations of the flip-flops. Old data can CLR 1 24 VCC be retained or new data can be entered while the OE 2 23 NC outputs are in the high-impedance state. 1D 3 22 1Q 2D 4 21 2Q The SN54ALS574B, SN54AS574, and 3D 5 20 3Q SN54AS575 are characterized for operation over 4D 6 19 4Q 5D 7 18 5Q the full military temperature range of –55°C to 6D 8 17 6Q 125°C. The SN74ALS574B, SN74ALS575A, 7D 9 16 7Q SN74AS574, and SN74AS575 are characterized 8D 10 15 8Q for operation from 0°C to 70°C. NC 11 14 CLK GND 12 13 NC SN54AS575...FK PACKAGE (TOP VIEW) R C DELCCCQ 1OCNVN1 4 3 2 1 282726 2D 5 25 2Q 3D 6 24 3Q 4D 7 23 4Q NC 8 22 NC 5D 9 21 5Q 6D 10 20 6Q 7D 11 19 7Q 12131415161718 DCDCCKQ 8NNNNL8 G C NC – No internal connection PRODUCTION DATA information is current as of publication date. Copyright  1995, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 Function Tables SN54ALS574B, SN74ALS574B, SN54AS574, SN74AS574 (each flip-flop) INPUTS OUTPUT OE CLK D Q L ↑ H H L ↑ L L L L X Q0 H X X Z SN74ALS575A, SN54AS575, SN74AS575 (each flip-flop) INPUTS OUTPUT OE CLR CLK D Q L L ↑ X L L H ↑ H H L H ↑ L L L H L X Q0 H X H X Z logic symbols† SN54ALS574B, SN74ALS574B, SN74ALS575A, SN54AS575, SN54AS574, SN74AS574 SN74AS575 1 2 OE EN OE EN 11 14 CLK C1 CLK C1 1 2 19 CLR 1R 1D 1D 1Q 3 18 3 22 2D 2Q 1D 1D 1Q 4 17 4 21 3D 3Q 2D 2Q 5 16 5 20 4D 4Q 3D 3Q 6 15 6 19 5D 5Q 4D 4Q 7 14 7 18 6D 6Q 5D 5Q 8 13 8 17 7D 7Q 6D 6Q 9 12 9 16 8D 8Q 7D 7Q 10 15 8D 8Q †These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DW, J, JT, N, and NT packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 logic diagrams (positive logic) SN54ALS574B, SN74ALS574B, SN74ALS575A, SN54AS575, SN54AS574, SN74AS574 SN74AS575 1 2 OE OE 11 14 CLK CLK 1 C1 CLR 19 1Q 2 1D 1D C1 22 1Q 3 1D 1D To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DW, J, JT, N, and NT packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, T : SN54ALS574B . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C A SN74ALS574B, SN74ALS575A . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN74ALS574B SN54ALS574B SN74ALS575A UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.7 0.8 V IOH High-level output current –1 –2.6 mA IOL Low-level output current 12 24 mA ′ALS574B 0 28 0 35 ffcllockk CClloocckk ffrreeqquueennccyy MMHHzz SN74ALS575A 0 30 ′ALS574B, CLK high or low 16.5 14 ttw PPuullssee dduurraattiioonn nnss SN74ALS575A, CLK high or low 16.5 Data 15 15 ttsu SSeettupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss SN74ALS575A, CLR 15 Data 4 0 tthh HHoolldd ttiimmee aafftteerr CCLLKK↑↑ nnss SN74ALS575A, CLR 0 TA Operating free-air temperature –55 125 0 70 °C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN74ALS574B SN54ALS574B PARAMETER TEST CONDITIONS SN74ALS575A UNIT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC –2 VCC –2 VOH IOH = –1 mA 2.4 3.3 V VVCCCC == 44.55 VV IOH = –2.6 mA 2.4 3.2 IOL = 12 mA 0.25 0.4 0.25 0.4 VVOOLL VVCCCC == 44.55 VV VV IOL = 24 mA 0.35 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 20 20 m A IOZL VCC = 5.5 V, VO = 0.4 V –20 –20 m A II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A IIL VCC = 5.5 V, VI = 0.4 V –0.2 –0.2 mA IO‡ VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA Outputs high 11 18 11 18 ′ALS574B VCC = 5.5 V Outputs low 17 27 17 27 Outputs disabled 17 28 17 28 IICCCC mmAA Outputs high 10 17 10 17 SN74ALS575A VCC = 5.5 V Outputs low 15 24 15 24 Outputs disabled 16 30 16 30 †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 W , FROM TO R2 = 500 W , PARAMETER UNIT (INPUT) (OUTPUT) TA = MIN to MAX§ SN54ALS574B SN74ALS574B SN74ALS575A MIN MAX MIN MAX MIN MAX fmax 28 35 30 MHz tPLH 4 22 3 14 4 14 CCLLKK QQ nnss tPHL 4 17 4 14 4 14 tPZH 4 21 3 18 4 18 OOEE QQ nnss tPZL 4 26 4 18 4 18 tPHZ 2 16 1 10 2 10 OOEE QQ nnss tPLZ 2 25 2 12 3 13 §For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V CC Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, T : SN54AS574, SN54AS575 . . . . . . . . . . . . . . . . . . –55°C to 125°C A SN74AS574, SN74AS575 . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS574 SN74AS574 SN54AS575 SN74AS575 UNIT MIN NOM MAX MIN NOM MAX VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V IOH High-level output current –12 –15 mA IOL Low-level output current 32 48 mA fclock* Clock frequency 0 100 0 90 MHz CLK high 5 5.5 ttw** PPuullssee dduurraattiioonn nnss CLK low 4 5.5 Data 3 5.5 ttsu** SSeettupp ttiimmee bbeeffoorree CCLLKK↑↑ nnss ′AS575, CLR high or low 6.5 6.5 Data 3 3 tthh** HHoolldd ttiimmee aafftteerr CCLLKK↑↑ nnss ′AS575, CLR 0 0 TA Operating free-air temperature –55 125 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54AS574 SN74AS574 PARAMETER TEST CONDITIONS SN54AS575 SN74AS575 UNIT MIN TYP† MAX MIN TYP† MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 V VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC –2 VCC –2 VOH IOH = –12 mA 2.4 3.2 V VVCCCC == 44.55 VV IOH = –15 mA 2.4 3.3 IOL = 32 mA 0.29 0.5 VVOOLL VVCCCC == 44.55 VV VV IOL = 48 mA 0.34 0.5 IOZH VCC = 5.5 V, VO = 2.7 V 50 50 m A IOZL VCC = 5.5 V, VO = 0.4 V –50 –50 m A II VCC = 5.5 V, VI = 7 V 0.1 0.1 mA IIH VCC = 5.5 V, VI = 2.7 V 20 20 m A OE, CLK, CLR –0.5 –0.5 IIIILL VVCCCC == 55.55 VV, VVII == 00.44 VV mmAA D –3 –2 IO‡ VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA Outputs high 73 116 73 116 ′AS574 VCC = 5.5 V Outputs low 85 134 85 134 Outputs disabled 84 134 84 134 IICCCC mmAA Outputs high 78 126 78 126 ′AS575 VCC = 5.5 V Outputs low 89 142 89 142 Outputs disabled 88 142 88 142 †All typical values are at VCC = 5 V, TA = 25°C. ‡The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 W , R2 = 500 W , FROM TO PARAMETER ((IINNPPUUTT)) ((OOUUTTPPUUTT)) TA = MIN to MAX§ UNIT SN54AS574 SN74AS574 SN54AS575 SN74AS575 MIN MAX MIN MAX fmax* 100 90 MHz tPLH 3 11 3 8 CCLLKK AAnny QQ nnss tPHL 4 11 4 9 tPZH 2 7 2 6 OOEE AAnny QQ nnss tPZL 3 11 3 10 tPHZ 2 7 2 6 OOEE AAnnyy QQ nnss tPLZ 2 7 2 6 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. §For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ALS574B, SN54AS574, SN54AS575 SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS165B – JUNE 1982 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7 V VCC RL = R1 = R2 S1 RL R1 From Output Test From Output Test From Output Test Under Test Point Under Test Point Under Test Point (see NoteC AL) RL CL (see NoteC AL) R2 (see Note A) LOAD CIRCUIT FOR BI-STATE LOAD CIRCUIT LOAD CIRCUIT TOTEM-POLE OUTPUTS FOR OPEN-COLLECTOR OUTPUTS FOR 3-STATE OUTPUTS 3.5 V 3.5 V Timing High-Level Input 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V tsu th tw 3.5 V 3.5 V Data Low-Level Input 1.3 V 1.3 V Pulse 1.3 V 1.3 V 0.3 V 0.3 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES PULSE DURATIONS 3.5 V Output Control 1.3 V 1.3 V (low-level enabling) 0.3 V 3.5 V tPZL Input 1.3 V 1.3 V tPLZ (cid:1)3.5 V 0.3 V Waveform 1 tPLH tPHL S1 Closed 1.3 V In-Phase VOH (see Note B) VOL Output 1.3 V 1.3 V tPHZ 0.3 V VOL tPZH tPLH VOH tPHL Waveform 2 Out-of-Phase VOH S1 Open 1.3 V 0.3 V Output 1.3 V 1.3 V (see Note B) (cid:1)0 V (see Note C) VOL VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 84001012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84001012A SNJ54ALS 574BFK 8400101RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8400101RA SNJ54ALS574BJ 8400101SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8400101SA SNJ54ALS574BW JM38510/37104B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37104B2A JM38510/37104BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 37104BRA M38510/37104B2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 JM38510/ 37104B2A M38510/37104BRA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 37104BRA SN54ALS574BJ ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54ALS574BJ SN54AS574J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SN54AS574J SN74ALS574BDW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B & no Sb/Br) SN74ALS574BDWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B & no Sb/Br) SN74ALS574BDWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B & no Sb/Br) SN74ALS574BN ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74ALS574BN (RoHS) SN74ALS574BNE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74ALS574BN (RoHS) SN74ALS574BNSR ACTIVE SO NS 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS574B & no Sb/Br) SN74ALS575ADW ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 ALS575A & no Sb/Br) SN74AS574DW ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AS574DWR ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 AS574 & no Sb/Br) SN74AS574N ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 SN74AS574N (RoHS) SNJ54ALS574BFK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 84001012A SNJ54ALS 574BFK SNJ54ALS574BJ ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8400101RA SNJ54ALS574BJ SNJ54ALS574BW ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8400101SA SNJ54ALS574BW SNJ54AS574J ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 SNJ54AS574J (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ALS574B, SN54AS574, SN74ALS574B, SN74AS574 : •Catalog: SN74ALS574B, SN74AS574 •Military: SN54ALS574B, SN54AS574 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ALS574BDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN74ALS574BNSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1 SN74AS574DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2017 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ALS574BDWR SOIC DW 20 2000 367.0 367.0 45.0 SN74ALS574BNSR SO NS 20 2000 367.0 367.0 45.0 SN74AS574DWR SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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