SN54AHCT139, SN74AHCT139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS267M – DECEMBER 1995 – REVISED MARCH 2003 (cid:0) Inputs Are TTL-Voltage Compatible SN54AHCT139...J OR W PACKAGE (cid:0) SN74AHCT139...D, DB, DGV, N, NS, OR PW PACKAGE Designed Specifically for High-Speed (TOP VIEW) Memory Decoders and Data-Transmission Systems 1G 1 16 VCC (cid:0) Incorporate Two Enable Inputs to Simplify 1A 2 15 2G Cascading and/or Data Reception 1B 3 14 2A (cid:0) Latch-Up Performance Exceeds 250 mA Per 1Y0 4 13 2B JESD 17 1Y1 5 12 2Y0 (cid:0) 1Y2 6 11 2Y1 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) 1Y3 7 10 2Y2 – 200-V Machine Model (A115-A) GND 8 9 2Y3 – 1000-V Charged-Device Model (C101) SN54AHCT139...FK PACKAGE description/ordering information (TOP VIEW) The ’AHCT139 devices are dual 2-line to 4-line A G C CC G decoders/demultiplexers designed for 4.5-V to 1 1 NV 2 5.5-V V operation. These devices are CC 3 2 1 20 19 designed to be used in high-performance 1B 4 18 2A memory-decoding or data-routing applications 1Y0 5 17 2B requiring very short propagation delay times. In NC 6 16 NC high-performance memory systems, these 1Y1 7 15 2Y0 decoders can be used to minimize the effects of 1Y2 8 14 2Y1 9 10 1112 13 system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay 3 DC 32 times of these decoders and the enable time of the 1Y GNN 2Y2Y memory usually are less than the typical access NC – No internal connection time of the memory. This means that the effective system delay introduced by the decoders is negligible. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP – N Tube SN74AHCT139N SN74AHCT139N Tube SN74AHCT139D SSOOIICC –– DD AAHHCCTT113399 Tape and reel SN74AHCT139DR SOP – NS Tape and reel SN74AHCT139NSR AHCT139 ––4400°°CC ttoo 8855°°CC SSOP – DB Tape and reel SN74AHCT139DBR HB139 Tube SN74AHCT139PW TTSSSSOOPP – PPWW HHBB113399 Tape and reel SN74AHCT139PWR TVSOP – DGV Tape and reel SN74AHCT139DGVR HB139 CDIP – J Tube SNJ54AHCT139J SNJ54AHCT139J –55°C to 125°C CFP – W Tube SNJ54AHCT139W SNJ54AHCT139W LCCC – FK Tube SNJ54AHCT13FK SNJ54AHCT139FK †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION Copyright  2003, Texas Instruments Incorporated DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54AHCT139, SN74AHCT139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS267M – DECEMBER 1995 – REVISED MARCH 2003 description/ordering information (continued) The active-low enable (G) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. FUNCTION TABLE (each decoder/demultiplexer) INPUTS OOUUTTPPUUTTSS SELECT GG B A Y0 Y1 Y2 Y3 H X X H H H H L L L L H H H L L H H L H H L H L H H L H L H H H H H L logic diagram (positive logic) 4 1Y0 1 1G 5 1Y1 6 1Y2 2 1A Select 7 Inputs 3 1Y3 1B Data Outputs 12 2Y0 15 2G 11 2Y1 10 2Y2 14 2A Select 9 Inputs 13 2Y3 2B Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHCT139, SN74AHCT139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS267M – DECEMBER 1995 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V O CC Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA CC Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W JA DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54AHCT139 SN74AHCT139 UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 5.5 0 5.5 V VO Output voltage 0 VCC 0 VCC V IOH High-level output current –8 –8 mA IOL Low-level output current 8 8 mA ∆t/∆v Input transition rise or fall rate 20 20 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54AHCT139, SN74AHCT139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS267M – DECEMBER 1995 – REVISED MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54AHCT139 SN74AHCT139 PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC UUNNIITT MIN TYP MAX MIN MAX MIN MAX IOH = –50 (cid:0)A 4.4 4.5 4.4 4.4 VVOOHH 44.55 VV VV IOH = –8 mA 3.94 3.8 3.8 IOL = 50 (cid:0)A 0.1 0.1 0.1 VVOOLL 44.55 VV VV IOL = 8 mA 0.36 0.44 0.44 II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1 (cid:0)A ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 (cid:0)A One input at 3.4 V, ∆ICC† Other inputs at VCC or GND 5.5 V 1.35 1.5 1.5 mA Ci VI = VCC or GND 5 V 2 10 10 pF * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. †This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, VCC = 5 V±0.5 V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 25°C SN54AHCT139 SN74AHCT139 PPAARRAAMMEETTEERR UUNNIITT (INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX tPLH 5** 7.2** 1** 8.5** 1 8.5 AA oorr BB YY CCLL == 1155 ppFF nnss tPHL 5** 7.2** 1** 8.5** 1 8.5 tPLH 4.4** 6.3** 1** 7.5** 1 7.5 GG YY CCLL == 1155 ppFF nnss tPHL 4.4** 6.3** 1** 7.5** 1 7.5 tPLH 6.5 9.2 1 10.5 1 10.5 AA oorr BB YY CCLL == 5500 ppFF nnss tPHL 6.5 9.2 1 10.5 1 10.5 tPLH 5.9 8.3 1 9.5 1 9.5 GG YY CCLL == 5500 ppFF nnss tPHL 5.9 8.3 1 9.5 1 9.5 ** On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 13 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54AHCT139, SN74AHCT139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCLS267M – DECEMBER 1995 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Test From Output RL = 1 kΩ S1 Open TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL CL tPLZ/tPZL VCC (see Note A) (see Note A) tPHZ/tPZH GND Open Drain VCC LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS 3 V Timing Input 1.5 V tw 0 V th 3 V tsu 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPLH tPHL tPZL tPLZ Output VOH Waveform 1 ≈VCC InO-Puhtapsuet 50% VCC 50% VCC S1 at VCC 50% VCC VOL + 0.3 V VOL (see Note B) VOL tPHL tPLH tPZH tPHZ Output Out-ofO-Puhtapsuet 50% VCC 50% VCVVCOOHL (WseSae1v eNaftoo GtremN B D2) 50% VCC VOH – 0.3 VV≈0O VH VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) SN74AHCT139D ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT139 & no Sb/Br) SN74AHCT139DBR ACTIVE SSOP DB 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB139 & no Sb/Br) SN74AHCT139DG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT139 & no Sb/Br) SN74AHCT139DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB139 & no Sb/Br) SN74AHCT139DR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AHCT139 & no Sb/Br) SN74AHCT139N ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 SN74AHCT139N & no Sb/Br) SN74AHCT139PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB139 & no Sb/Br) SN74AHCT139PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB139 & no Sb/Br) SN74AHCT139PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 HB139 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74AHCT139DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74AHCT139DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74AHCT139PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 20-Dec-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74AHCT139DGVR TVSOP DGV 16 2000 367.0 367.0 35.0 SN74AHCT139DR SOIC D 16 2500 333.2 345.9 28.6 SN74AHCT139PWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

None

None

PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,23 0,40 0,07 M 0,13 24 13 0,16 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 0°–(cid:1)8° 0,75 1 12 0,50 A Seating Plane 0,15 1,20 MAX 0,08 0,05 PINS ** 14 16 20 24 38 48 56 DIM A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 4073251/E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated