SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 (cid:1) State-of-the-Art EPIC-II B BiCMOS Design SN54ABT543A...JT OR W PACKAGE Significantly Reduces Power Dissipation SN74ABT543A...DB, DW, NT, OR PW PACKAGE (cid:1) (TOP VIEW) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V LEBA 1 24 VCC Using Machine Model (C = 200 pF, R = 0) OEBA 2 23 CEBA (cid:1) Typical VOLP (Output Ground Bounce) < 1 V A1 3 22 B1 at VCC = 5 V, TA = 25°C A2 4 21 B2 (cid:1) High-Drive Outputs (–32-mA I , 64-mA I ) A3 5 20 B3 OH OL (cid:1) A4 6 19 B4 Package Options Include Plastic A5 7 18 B5 Small-Outline (DW), Shrink Small-Outline A6 8 17 B6 (DB), and Thin Shrink Small-Outline (PW) A7 9 16 B7 Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) A8 10 15 B 8 and Ceramic (JT) DIPs CEAB 11 14 LEAB GND 12 13 OEAB description SN54ABT543A...FK PACKAGE The ’ABT543A octal transceivers contain two sets (TOP VIEW) of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable AA A BB C B (LEAB or LEBA) and output-enable (OEAB or 1 EE C C E 1 A OL NV C B OEBA) inputs are provided for each register to permit independent control in either direction of 4 3 2 1 28 27 26 A2 5 25 B2 data flow. A3 6 24 B3 The A-to-B enable (CEAB) input must be low to A4 7 23 B4 enter data from A or to output data from B. If CEAB NC 8 22 NC is low and LEAB is low, the A-to-B latches are A5 9 21 B5 transparent; a subsequent low-to-high transition A6 10 20 B6 of LEAB puts the A latches in the storage mode. A7 11 19 B7 With CEAB and OEAB both low, the 3-state 12 13 14 15 16 1718 B outputs are active and reflect the data present 8 B DC B B8 at the output of the A latches. Data flow from B to A A NN A AB E G E E A is similar, but requires using the CEBA, LEBA, C O L and OEBA inputs. NC – No internal connection To ensure the high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT543A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT543A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-II B is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 FUNCTION TABLE† INPUTS OUTPUT CEAB LEAB OEAB A B H X X X Z X X H X Z L H L X B0‡ L L L L L L L L H H †A-to-B data flow is shown; B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA. ‡Output level before the indicated steady-state input conditions were established logic symbol§ 2 OEBA 1EN3 23 CEBA G1 1 LEBA 1C5 13 OEAB 2EN4 11 CEAB G2 14 LEAB 2C6 3 22 A1 3 1 5D B1 6D 1 4 4 21 A2 B2 5 20 A3 B3 6 19 A4 B4 7 18 A5 B5 8 17 A6 B6 9 16 A7 B7 10 15 A8 B8 §This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 logic diagram (positive logic) 2 OEBA 23 CEBA 1 LEBA 13 OEAB 11 CEAB 14 LEAB C1 3 A1 22 1D B1 C1 1D To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V I Voltage range applied to any output in the high or power-off state, V . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V O Current into any output in the low state, I : SN54ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA O SN74ABT543A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, q JA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 recommended operating conditions (see Note 3) SN54ABT543A SN74ABT543A UUNNIITT MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 V VIL Low-level input voltage 0.8 0.8 V VI Input voltage 0 VCC 0 VCC V IOH High-level output current –24 –32 mA IOL Low-level output current 48 64 mA D t/D v Input transition rise or fall rate Outputs enabled 5 5 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C SN54ABT543A SN74ABT543A PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS UUNNIITT MIN TYP† MAX MIN MAX MIN MAX VIK VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = –3 mA 3 3 3 VVOOHH VV IOH = –24 mA 2 2 VVCCCC == 44.55 VV IOH = –32 mA 2* 2 IOL = 48 mA 0.55 0.55 VVOOLL VVCCCC == 44.55 VV VV IOL = 64 mA 0.55* 0.55 Vhys 100 mV Control inputs ±1 ±1 ±1 IIII VVCCCC == 55.55 VV, VVII == VVCCCC oorr GGNNDD mm AA A or B ports ±100 ±100 ±100 IOZH‡ VCC = 5.5 V, VO = 2.7 V 10§ 10§ 10§ m A IOZL‡ VCC = 5.5 V, VO = 0.5 V –10§ –10§ –10§ m A Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 m A ICEX VVCOC = =5 .55. 5V V, Outputs high 50 50 50 m A IO¶ VCC = 5.5 V, VO = 2.5 V –50* –100 –180* –50 –200 –50 –180 mA Outputs high 1 250* 350 250 m A VVCCCC == 55..55 VV,, ICC A or B ports IO = 0, Outputs low 24 30* 34 30 mA VI = VCC or GND Outputs disabled 0.5 250* 350 250 m A D ICC# VOCthCe r= i n5p.5u tVs ,a Ot nVeC iCn pourt GaNt 3D.4 V, 1.5 1.5 1.5 mA Ci Control inputs VI = 2.5 V or 0.5 V 4 pF Cio A or B ports VO = 2.5 V or 0.5 V 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. †All typical values are at VCC = 5 V. ‡The parameters IOZH and IOZL include the input leakage current. §This data sheet limit may vary among suppliers. ¶Not more than one output should be tested at a time, and the duration of the test should not exceed one second. #This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ABT543A VCC = 5 V, TA = 25°C MIN MAX UNIT MIN MAX tw Pulse duration, LEAB or LEBA low 3.5 3.5 ns High 2.5 2.5 DDaattaa bbeeffoorree LLEEAABB oorr LLEEBBAA↑↑ Low 3 3 ttsu SSeettuupp ttiimmee nnss High 2.5 2.5 DDaattaa bbeeffoorree CCEEAABB oorr CCEEBBAA↑↑ Low 3 3 Data after LEAB or LEBA↑ 1 1 tthh HHoolldd ttiimmee Data after CEAB or CEBA↑ 1 1 nnss timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN74ABT543A VCC = 5 V, TA = 25°C MIN MAX UNIT MIN MAX tw Pulse duration, LEAB or LEBA low 3.5 3.5 ns High 3.5 3.5 DDaattaa bbeeffoorree LLEEAABB oorr LLEEBBAA↑↑ Low 3 3 ttsu SSeettuupp ttiimmee nnss High 3.5 3.5 DDaattaa bbeeffoorree CCEEAABB oorr CCEEBBAA↑↑ Low 3 3 Data after LEAB or LEBA↑ 0.5 0.5 tthh HHoolldd ttiimmee Data after CEAB or CEBA↑ 0.5 0.5 nnss POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN54ABT543A FROM TO VCC = 5 V, PARAMETER (INPUT) (OUTPUT) TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH 1.6† 4.4 4.4 1.6† 5.5 AA oorr BB BB oorr AA nnss tPHL 1.6 4.4 5.1 1.6 6.2 tPLH 1.6† 4.1 5.1 1.6† 6.6 LLEEBBAA oorr LLEEAABB AA oorr BB nnss tPHL 1.6 4.6 5.4 1.6 6.4 tPZH 1.4 3.9 4.1 1.4 5.1 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPZL 2 5 4.9 2 5.8 tPHZ 2.5† 5.9 5.8 2.5† 6.9 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPLZ 2.5† 5.5 6.1 2.5† 7.6 tPZH 1.4 3.9 4.7 1.4 5.6 CCEEBBAA oorr CCEEAABB AA oorr BB nnss tPZL 2 5 5.7 2 6.2 tPHZ 3.2† 5.9 6.5 3.2† 7.3 CCEEBBAA oorr CCEEAABB AA oorr BB nnss tPLZ 2.5† 5.5 6.7 2.5† 7.8 †This data sheet limit may vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C = 50 pF (unless otherwise noted) (see Figure 1) L SN74ABT543A FROM TO VCC = 5 V, PARAMETER (INPUT) (OUTPUT) TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH 1.8† 4.4 5.9 1.8† 6.9 AA oorr BB BB oorr AA nnss tPHL 1.9 4.4 5.9 1.9 6.9 tPLH 1.5† 4.1 5.6 1.5† 6.6 LLEEBBAA oorr LLEEAABB AA oorr BB nnss tPHL 2.1 4.6 6.1 2.1 7.1 tPZH 1.4 3.9 5.4 1.4 6.4 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPZL 2.5 5 6.5 2.5 7.5 tPHZ 2.5† 5.9 7.4 2.5† 8.4 OOEEBBAA oorr OOEEAABB AA oorr BB nnss tPLZ 2.5† 5.5 7 2.5† 8 tPZH 1.4 3.9 5.4 1.4 6.4 CCEEBBAA oorr CCEEAABB AA oorr BB nnss tPZL 2.5 5 6.5 2.5 7.5 tPHZ 2.9† 5.9 7.4 2.9† 8.4 CCEEBBAA oorr CCEEAABB AA oorr BB nnss tPLZ 2.4† 5.5 7 2.4† 8 †This data sheet limit may vary among suppliers. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT543A, SN74ABT543A OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS157F – JANUARY 1991 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 7 V 500 W S1 Open From Output TEST S1 Under Test GND tPLH/tPHL Open (sCeeL N= o5t0e pAF) 500 W tPLZ/tPZL 7 V tPHZ/tPZH Open LOAD CIRCUIT 3 V Timing Input 1.5 V 0 V tw tsu th 3 V 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V 1.5 V 1.5 V Control 0 V 0 V tPZL tPLH tPHL tPLZ Output VOH 3.5 V Waveform 1 Output 1.5 V 1.5 V S1 at 7 V 1.5 V VOL + 0.3 V VOL VOL (see Note B) tPHZ tPHL tPLH tPZH Output VOH VOH Output 1.5 V 1.5 V WSa1v aetf oOrpme n2 1.5 V VOH – 0.3 V VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 W , tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9231402Q3A ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9231402Q3A SNJ54 ABT543AFK SN74ABT543ADBR ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB543A & no Sb/Br) SN74ABT543ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB543A & no Sb/Br) SN74ABT543ADW ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT543A & no Sb/Br) SN74ABT543ADWR ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 ABT543A & no Sb/Br) SN74ABT543APW ACTIVE TSSOP PW 24 60 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB543A & no Sb/Br) SN74ABT543APWR ACTIVE TSSOP PW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 85 AB543A & no Sb/Br) SNJ54ABT543AFK ACTIVE LCCC FK 28 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 5962- 9231402Q3A SNJ54 ABT543AFK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT543A, SN74ABT543A : •Catalog: SN74ABT543A •Military: SN54ABT543A NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) SN74ABT543ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74ABT543ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74ABT543APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) SN74ABT543ADBR SSOP DB 24 2000 367.0 367.0 38.0 SN74ABT543ADWR SOIC DW 24 2000 350.0 350.0 43.0 SN74ABT543APWR TSSOP PW 24 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0024A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 22X 0.65 24 1 2X 7.9 7.15 7.7 NOTE 3 12 13 0.30 24X B 4.5 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 0.25 GAGE PLANE 0.15 0.05 (0.15) TYP SEE DETAIL A 0.75 0 -8 0.50 DETA 20AIL A TYPICAL 4220208/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0024A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 24X (1.5) SYMM (R0.05) TYP 1 24X (0.45) 24 22X (0.65) SYMM 12 13 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–(cid:1)8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38 DIM A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065/E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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